Amplifier circuit

Abstract

This amplifier circuit (10) comprises: a 90° hybrid circuit (50) having an input terminal (50a) and output terminals (50b and 50c); a power amplifier (11) having a first input end and a first output end, the first input end being connected to the output terminal (50b); a power amplifier (12) having a second input end and a second output end, the second input end being connected to the output terminal (50c); a synthesis circuit having a third input end, a fourth input end, and a third output end; a high-pass filter (21) connected between the first output end and the third input end; a low-pass filter (22) connected between the second output end and the fourth input end; inductors (51 and 52) connected to each other in series between the first output end and a power supply terminal (120); and a switch (43) connected in parallel to the inductor (52).

Description

Amplification circuit

[0001] The present invention relates to an amplifier circuit.

[0002] Patent Document 1 discloses a multi-band amplifier including an output stage amplifier and multiple bias power supply lines of different lengths connected in parallel between the output terminal of the amplifier and a bias power supply terminal. One of the multiple bias power supply lines is selected by a switch, and the distortion characteristics of the fundamental wave are optimized by switching the inductance of the bias power supply line.

[0003] JP 2011-155357 A

[0004] However, in the multi-band amplifier disclosed in Patent Document 1, although the baseband impedance on the high frequency side can be reduced, the fundamental wave leaks to the bias power supply terminal side, causing a problem that the transmission loss of the fundamental wave cannot be suppressed.

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an amplifier circuit in which the transmission loss of the fundamental wave is suppressed while deterioration of distortion characteristics is suppressed.

[0006] In order to achieve the above object, an amplifier circuit according to one aspect of the present invention includes: a 90° hybrid circuit having a first input terminal, a first output terminal, and a second output terminal; a first power amplifier having a first input terminal and a first output terminal, the first input terminal being connected to the first output terminal; a second power amplifier having a second input terminal and a second output terminal, the second input terminal being connected to the second output terminal; a combiner circuit having a third input terminal, a fourth input terminal, and a third output terminal; a high-pass filter connected between the first output terminal and the third input terminal; a low-pass filter connected between the second output terminal and the fourth input terminal; a first inductor and a second inductor connected in series to each other, and a first switch connected in parallel to the second inductor, between the first output terminal and a power supply terminal.

[0007] According to the present invention, it is possible to provide an amplifier circuit in which the transmission loss of the fundamental wave is suppressed while deterioration of distortion characteristics is suppressed.

[0008] FIG. 1 is a circuit configuration diagram of an amplifier circuit, a high-frequency circuit, and a communication device according to an embodiment. FIG. 2A is a circuit state diagram of a high-frequency circuit according to an embodiment in Band A transmission mode (modulation bandwidth 20 MHz). FIG. 2B is a circuit state diagram of a high-frequency circuit according to an embodiment in Band A transmission mode (modulation bandwidth 100 MHz). FIG. 3 is a graph showing baseband impedance characteristics of an amplifier circuit according to an embodiment. FIG. 4 is a circuit configuration diagram of an amplifier circuit according to a comparative example. FIG. 5A is a diagram showing baseband impedance in Band A transmission mode (modulation bandwidth 20 MHz) of a power amplifier according to an embodiment. FIG. 5B is a diagram showing baseband impedance in Band A transmission mode (modulation bandwidth 100 MHz) of a power amplifier according to an embodiment. FIG. 6A is a diagram explaining the principle of suppressing fundamental distortion in Band A transmission mode (modulation bandwidth 20 MHz) of an amplifier circuit according to an embodiment. FIG. 6B is a diagram explaining the principle of suppressing fundamental distortion in Band A transmission mode (modulation bandwidth 100 MHz) of an amplifier circuit according to an embodiment. FIG. 7A is a graph showing signal strength of the fundamental frequency band in Band A transmission mode (modulation bandwidth 100 MHz) of an amplifier circuit according to an embodiment. FIG. 7B is a graph showing signal strength of the fundamental frequency band in Band A transmission mode (modulation bandwidth 100 MHz) of an amplifier circuit according to a comparative example. FIG. 8A is a plan view and a cross-sectional view of an amplifier circuit according to an embodiment. FIG. 8B is a plan view and a cross-sectional view of an amplifier circuit according to a first modification of the embodiment. FIG. 9 is a circuit configuration diagram of an amplifier circuit according to a second modification of the embodiment. FIG. 10A is a graph showing baseband impedance characteristics of an amplifier circuit according to a second modification of the embodiment. FIG. 10B is a graph showing power-added efficiency characteristics of an amplifier circuit according to a second modification of the embodiment. FIG. 11 is a circuit configuration diagram of an amplifier circuit according to a third modification of the embodiment. FIG. 12 is a circuit configuration diagram of an amplifier circuit according to a fourth modification of the embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0010] It should be noted that the drawings are schematic diagrams in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present invention, and are not necessarily strictly illustrated, and may differ from the actual shapes, positional relationships, and proportions. In the drawings, the same reference numerals are used to denote substantially the same components, and redundant explanations may be omitted or simplified.

[0011] In the following figures, the x-axis and y-axis are axes that are orthogonal to each other on a plane parallel to the main surface of the mounting substrate. Specifically, when the mounting substrate has a rectangular shape in a plan view, the x-axis is parallel to a first side of the mounting substrate, and the y-axis is parallel to a second side that is orthogonal to the first side of the mounting substrate. The z-axis is an axis perpendicular to the main surface of the mounting substrate, with its positive direction indicating the upward direction and its negative direction indicating the downward direction.

[0012] In the component placement of the present disclosure, "a component is placed on a substrate" includes a component being placed on the main surface of the substrate and a component being placed within the substrate. "A component is placed on the main surface of the substrate" includes a component being placed in contact with the main surface of the substrate, as well as a component being placed above the main surface without contacting the main surface (for example, a component being stacked on another component placed in contact with the main surface). "A component is placed on the main surface of the substrate" may also include a component being placed in a recess formed in the main surface. "A component is placed within the substrate" includes a component being encapsulated within a module substrate, as well as a component being entirely placed between both main surfaces of the substrate but partially not covered by the substrate, and a component being only partially placed within the substrate.

[0013] In the component placement of the present invention, "planar view of the main surface" means viewing an object by orthogonally projecting it onto the xy plane from the positive side of the z axis. "A overlaps with B in planar view" means that at least a portion of the area of ​​A orthogonally projected onto the xy plane overlaps with at least a portion of the area of ​​B orthogonally projected onto the xy plane. "A is placed between B and C" means that at least one of multiple line segments connecting any point in B and any point in C passes through A.

[0014] In the circuit configuration of the present disclosure, "connected" includes not only direct connection by connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Connected between A and B" means connected to both A and B between A and B.

[0015] In addition, in this disclosure, a "path" means a transmission line composed of a wiring through which a high-frequency signal propagates, an electrode directly connected to the wiring, and a terminal directly connected to the wiring or the electrode.

[0016] In addition, in this disclosure, "component A is arranged in series on path B" means that both the signal input terminal and the signal output terminal of component A are connected to wiring, electrodes, or terminals that make up path B.

[0017] In the present invention, the terms "terminal," "input end," and "output end" refer to the points at which conductors within elements terminate. However, if the impedance of the conductor between elements is sufficiently low, a terminal is interpreted as any point on the conductor between elements or the entire conductor, not just a single point.

[0018] Furthermore, terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "rectangle," and numerical ranges do not only represent the strict meaning, but also include a substantially equivalent range, for example, an error of a few percent.

[0019] The "passband of a filter" is defined as the portion of the frequency spectrum transmitted by the filter over which the output power is not attenuated by more than 3 dB below the maximum output power. The upper and lower ends of the passband of a bandpass filter are therefore identified as the higher and lower frequencies of the two points at which the output power is attenuated by 3 dB below the maximum output power.

[0020] The term "transmission band" refers to a frequency band used for transmission in a communication device. The term "reception band" refers to a frequency band used for reception in a communication device. For example, in frequency division duplex (FDD), different frequency bands are used as the transmission band and the reception band, while in time division duplex (TDD), the same frequency band is used as the transmission band and the reception band. In particular, in FDD, when a communication device is implemented in a user equipment (UE) of a cellular network, an uplink operation band is used as the transmission band, and a downlink operation band is used as the reception band. Conversely, when a communication device is implemented as a base station (BS) of a cellular network, the downlink band is used as the transmission band, and the uplink band is used as the reception band.

[0021] The "pass phase" of a high-frequency signal between two terminals can be obtained by applying a measurement RF probe to the two terminals and measuring the pass characteristic (S21) with a network analyzer. The "reflection phase" of a high-frequency signal at one terminal can be obtained by applying a measurement RF probe to the one terminal and measuring the pass characteristic (S11) with a network analyzer.

[0022] (Embodiment) [1. Circuit Configuration of Amplifier Circuit 10, High-Frequency Circuit 1, and Communication Device 4] The circuit configuration of an amplifier circuit 10, a high-frequency circuit 1, and a communication device 4 according to the present embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit configuration diagram of an amplifier circuit 10, a high-frequency circuit 1, and a communication device 4 according to the embodiment.

[0023] [1.1 Circuit Configuration of Communication Device 4] First, a description will be given of the circuit configuration of the communication device 4. As shown in Fig. 1 , the communication device 4 according to this embodiment includes a high-frequency circuit 1, an antenna 2, and an RF signal processing circuit (RFIC: Radio Frequency Integrated Circuit) 3.

[0024] The high-frequency circuit 1 transmits high-frequency signals between the antenna 2 and the RFIC 3. The detailed circuit configuration of the high-frequency circuit 1 will be described later.

[0025] The antenna 2 is connected to an antenna connection terminal 100 of the high frequency circuit 1 , and transmits high frequency signals output from the high frequency circuit 1 , and also receives high frequency signals from the outside and outputs them to the high frequency circuit 1 .

[0026] The RFIC 3 is an example of a signal processing circuit that processes high-frequency signals. Specifically, the RFIC 3 performs signal processing on a transmission signal input from a baseband signal processing circuit (BBIC, not shown) by up-conversion or the like, and outputs the transmission signal generated by the signal processing to the transmission path of the high-frequency circuit 1. The RFIC 3 also performs signal processing on a reception signal input via the reception path of the high-frequency circuit 1 by down-conversion or the like, and outputs the reception signal generated by the signal processing to the BBIC. The RFIC 3 also has a control unit that controls the high-frequency circuit 1. Note that part or all of the functions of the RFIC 3 as a control unit may be implemented outside the RFIC 3, for example, in the BBIC or the high-frequency circuit 1.

[0027] The RFIC 3 also functions as a control unit that controls the power supply voltage Vcc and bias current supplied to each amplifier in the amplifier circuit 10. Specifically, the RFIC 3 outputs control signals to a power supply circuit (not shown) and a bias circuit (not shown). The power supply circuit and the bias circuit may be disposed in the high-frequency circuit 1 or the amplifier circuit 10. Each amplifier in the amplifier circuit 10 is supplied with the power supply voltage Vcc controlled by the control signal from the power supply circuit, and with the bias current controlled by the control signal from the bias circuit.

[0028] The RFIC 3 also functions as a control unit that controls the connections of the switches 41, 42, 43, 215, and 225 of the high frequency circuit 1 based on the frequency band to be used, etc.

[0029] In the communication device 4 according to this embodiment, the antenna 2 is not an essential component.

[0030] 1.2 Circuit Configuration of High-Frequency Circuit 1 Next, a description will be given of the circuit configuration of the high-frequency circuit 1. As shown in FIG. 1 , the high-frequency circuit 1 includes an amplifier circuit 10, filters 61, 62, 63, 64, 65, and 66, a switch 42, inductors 71, 72, 73, 74, 75, 76, 77, and 78, and an antenna connection terminal 100.

[0031] The amplifier circuit 10 amplifies the transmission signals of bands A and B input from the signal input terminal 110, and also amplifies the reception signals of bands A, B, and C input from the antenna connection terminal 100.

[0032] In the present embodiment, each of band A, band B, and band C refers to a frequency band defined in advance by a standardization organization (for example, 3GPP (registered trademark: 3rd Generation Partnership Project), IEEE (Institute of Electrical and Electronics Engineers), etc.) for a communication system constructed using radio access technology (RAT). In the present embodiment, the communication system may be, for example, a 4G (4th Generation)-LTE (Long Term Evolution) system, a 5G (5th Generation)-NR (New Radio) system, and a WLAN (Wireless Local Area Network) system, but is not limited to these.

[0033] The filter 61 is connected between the switch 41 and the antenna connection terminal 100, and has a pass band that includes the transmission band of band A (first band). Specifically, one end of the filter 61 is connected to the terminal 41a of the switch 41, and the other end of the filter 61 is connected to the antenna connection terminal 100 via the inductors 71 and 77 and the switch 42.

[0034] The filter 62 is connected between the switch 41 and the antenna connection terminal 100, and has a pass band that includes the transmission band of band A (first band). Specifically, one end of the filter 62 is connected to the terminal 41b of the switch 41, and the other end of the filter 62 is connected to the antenna connection terminal 100 via the inductors 72 and 77 and the switch 42.

[0035] The filter 63 is connected between the switch 41 and the antenna connection terminal 100, and has a pass band that includes the transmission band of band B (second band). Specifically, one end of the filter 63 is connected to the terminal 41c of the switch 41, and the other end of the filter 63 is connected to the antenna connection terminal 100 via the inductors 73 and 77 and the switch 42.

[0036] The filter 64 has a pass band that includes the reception band of band B (second band). One end of the filter 64 is connected to the path connecting the antenna connection terminal 100 and the filter 61, and the other end is connected to the input terminal of the low-noise amplifier 14.

[0037] The filter 65 has a pass band that includes the reception band of band A (first band). One end of the filter 65 is connected to a path that connects the antenna connection terminal 100 and the filter 63, and the other end is connected to the input terminal of the low-noise amplifier 15.

[0038] The filter 66 has a pass band that includes the receive band of band C. One end of the filter 66 is connected to the terminal 42 e of the switch 42 , and the other end is connected to the input terminal of the low noise amplifier 16 .

[0039] The low noise amplifiers 14 to 16 connected to the filters 64 to 66 may be included in the amplifier circuit 10 .

[0040] Band A (first band) and band B (second band) are a band combination that allows simultaneous transmission. Note that each of band A (first band) and band B (second band) may be a band that uses time division duplex. In this case, the passbands of filters 61, 62, and 65 may be the same, and the passbands of filters 63 and 64 may be the same.

[0041] Band A is, for example, band B41 for 4G-LTE or band n41 for 5G-NR, and band B is, for example, band B40 for 4G-LTE or band n40 for 5G-NR.

[0042] The switch 42 is an example of an antenna switch and has terminals 42a, 42b, 42c, 42d, and 42e. The terminal 42a is connected to the antenna connection terminal 100 via an inductor 77, the terminal 42b is connected to the filters 61 and 64 via an inductor 71, the terminal 42c is connected to the filter 62 via an inductor 72, the terminal 42d is connected to the filters 63 and 65 via an inductor 73, and the terminal 42e is connected to the filter 66.

[0043] With the above configuration, switch 42 switches between connection and disconnection between antenna connection terminal 100 and filters 61 and 64, between connection and disconnection between antenna connection terminal 100 and filter 62, between connection and disconnection between antenna connection terminal 100 and filters 63 and 65, and between connection and disconnection between antenna connection terminal 100 and filter 66.

[0044] Inductor 71 is arranged in series in a path connecting terminal 42b and filters 61 and 64. Inductor 74 is connected between this path and ground. Inductors 71 and 74 match the impedance between switch 42 and filters 61 and 64. Inductor 72 is arranged in series in a path connecting terminal 42c and filter 62. Inductor 75 is connected between this path and ground. Inductors 72 and 75 match the impedance between switch 42 and filter 62. Inductor 73 is arranged in series in a path connecting terminal 42d and filters 63 and 65. Inductor 76 is connected between this path and ground. Inductors 73 and 76 match the impedance between switch 42 and filters 63 and 65. Inductor 77 is arranged in series in a path connecting terminal 42a and antenna connection terminal 100. Inductor 78 is connected between this path and ground. Inductors 77 and 78 match the impedance between switch 42 and antenna 2. At least one of the inductors 71 to 78 may be omitted.

[0045] According to the above circuit configuration, the high-frequency circuit 1 can simultaneously transmit a transmit signal in band A and a receive signal in band B, and simultaneously transmit a transmit signal in band B and a receive signal in band A.

[0046] The high-frequency circuit 1 according to the present invention may include at least the amplifier circuit 10 and the filters 61 and 64 of the circuit configuration shown in FIG.

[0047] [1.3 Circuit Configuration of Amplifier Circuit 10] Next, the circuit configuration of the amplifier circuit 10 will be described in detail.

[0048] As shown in FIG. 1, the amplifier circuit 10 includes power amplifiers 11 and 12, a high-pass filter 21, a low-pass filter 22, switches 41 and 43, a 90° hybrid circuit 50, inductors 51, 52, and 53, a capacitor 54, and a signal input terminal 110.

[0049] The signal input terminal 110 is connected to the RFIC 3. Each of the signal input terminal 110 and the antenna connection terminal 100 may be a metal conductor such as a metal electrode or a metal bump, or may be a point (node) on a metal wiring.

[0050] The 90° hybrid circuit 50 is an example of a branching filter and has an input terminal 50a (first input terminal), an output terminal 50b (first output terminal), and an output terminal 50c (second output terminal). The input terminal 50a is connected to the signal input terminal 110, the output terminal 50b is connected to a first input terminal of the power amplifier 11, and the output terminal 50c is connected to a second input terminal of the power amplifier 12. The 90° hybrid circuit 50 is configured to branch a high-frequency signal in the transmission band of Band A or Band B input to the input terminal 50a, output a branched signal RF1 from the output terminal 50b, and output a branched signal RF2, whose fundamental wave has a phase difference of +90° relative to that of the branched signal RF1, from the output terminal 50c.

[0051] It should be noted that instead of the 90° hybrid circuit 50, a 90° hybrid circuit (phase shift circuit) having another circuit configuration may be arranged.

[0052] The power amplifier 11 is an example of a first power amplifier and has a first input terminal and a first output terminal, the first input terminal being connected to the output terminal 50b. The power amplifier 12 is an example of a second power amplifier and has a second input terminal and a second output terminal, the second input terminal being connected to the output terminal 50c. The power amplifiers 11 and 12 are capable of amplifying the high-frequency signal of band A or band B output from the 90° hybrid circuit 50.

[0053] Each of the power amplifiers 11 and 12 includes an amplifying transistor. The amplifying transistor may be, for example, a bipolar transistor such as a heterojunction bipolar transistor (HBT) or a field-effect transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET). If the amplifying transistor is a bipolar transistor, the input terminals of the power amplifiers 11 and 12 are, for example, the base terminals of the bipolar transistors, and the output terminals of the power amplifiers 11 and 12 are, for example, the collector terminals of the bipolar transistors. If the amplifying transistors are field-effect transistors, the input terminals of the power amplifiers 11 and 12 are, for example, the gate terminals of the field-effect transistors, and the output terminals of the power amplifiers 11 and 12 are, for example, the drain terminals of the field-effect transistors.

[0054] The high-pass filter 21 is connected between the first output terminal of the power amplifier 11 and a terminal 41d of the switch 41. The high-pass filter 21 includes, for example, capacitors 211, 212, and 214, an inductor 213, and a switch 215. The capacitor 211 is an example of a first capacitor and is connected between the first output terminal and the terminal 41d. The inductor 213 is an example of a fourth inductor and is connected between a first path connecting the capacitor 211 and the terminal 41d and ground. The capacitor 212 is arranged in series in the path connecting the capacitor 211 and the terminal 41d. The capacitor 214 is an example of a second capacitor and is connected between the first output terminal and the terminal 41d. The switch 215 is an example of a second switch and is connected between the first output terminal and the terminal 41d. The capacitor 214 and the switch 215 are connected in series to each other and constitute a first variable capacitor circuit. The switch 215 performs a switching operation in conjunction with the on / off of the switch 43 to finely adjust the passing phase of the high-pass filter 21 .

[0055] With the above configuration, high-pass filter 21 sets the passing phase of the fundamental waves of band A and band B to, for example, +45° (advances by 45°). Note that capacitor 212 is a DC-cut capacitor and does not contribute to phase shift, and may not be included in high-pass filter 21. Furthermore, high-pass filter 21 does not need to have a phase-varying function, and capacitor 214 and switch 215 may not be included in high-pass filter 21.

[0056] The low-pass filter 22 is connected between the second output terminal of the power amplifier 12 and the terminal 41e of the switch 41. The low-pass filter 22 includes, for example, an inductor 221, capacitors 222, 223, and 224, and a switch 225. The inductor 221 is an example of a fifth inductor and is connected between the second output terminal and the terminal 41e. The capacitor 223 is an example of a third capacitor and is connected between a second path connecting the inductor 221 and the terminal 41e and ground. The capacitor 222 is arranged in series with the second path. The capacitor 224 is an example of a fourth capacitor and is connected between the second path and ground. The switch 225 is an example of a third switch and is connected between the second path and ground. The capacitor 224 and the switch 225 are connected in series with each other and form a second variable capacitor circuit. The switch 225 performs a switching operation in conjunction with the on / off of the switch 43 to finely adjust the passing phase of the low-pass filter 22.

[0057] With the above configuration, low-pass filter 22 sets the passing phase of the fundamental waves of band A and band B to, for example, −45° (delays by 45°). Note that capacitor 222 is a DC-cut capacitor and does not contribute to phase shift, and may not be included in low-pass filter 22. Furthermore, low-pass filter 22 does not need to have a phase-varying function, and capacitor 224 and switch 225 may not be included in low-pass filter 22.

[0058] The switch 41 is an example of a combining circuit and an example of a fourth switch, and has terminals 41a (third output terminal), 41b, 41c (fourth output terminal), 41d (third input terminal), and 41e (fourth input terminal). The switch 41 switches between a connection between the terminal 41d and the terminal 41a and a connection between the terminal 41e and the terminal 41a (Band A transmission mode), a connection between the terminal 41d and the terminal 41a and a connection between the terminal 41e and the terminal 41b (second Band A transmission mode), and a connection between the terminal 41d and the terminal 41c and a connection between the terminal 41e and the terminal 41c (Band B transmission mode).

[0059] As a result, in the band A transmission mode, the switch 41 is configured to output from the terminal 41a the band A output signal generated by in-phase synthesis at the terminal 41a of the first demultiplexed signal of band A input from the terminal 41d and the second demultiplexed signal of band A input from the terminal 41e.

[0060] In addition, in the band B transmission mode, the switch 41 is configured to output from the terminal 41c an output signal generated by in-phase combining at the terminal 41c the third demultiplexed signal of band B input from the terminal 41d and the fourth demultiplexed signal of band B input from the terminal 41e. The terminal 41a is a signal combining point where the first demultiplexed signal of band A and the second demultiplexed signal of band A are combined in phase, and the terminal 41c is a signal combining point where the third demultiplexed signal of band B and the fourth demultiplexed signal of band B are combined in phase.

[0061] In the second band A transmission mode, the switch 41 outputs from the terminal 41a the band A transmission signal input from the terminal 41d, and outputs from the terminal 41b the band A transmission signal input from the terminal 41e. The band A signal output from the terminal 41a and the band A signal output from the terminal 41b are combined in phase at the terminal 42a of the switch 42. In the second band A transmission mode, the terminal 42a is the signal combining point.

[0062] It should be noted that the amplifier circuit 10 does not necessarily have to operate in the second band A transmission mode, and in this case, the terminal 41b may be omitted.

[0063] Inductor 51 is an example of a first inductor and is connected between the first output terminal of power amplifier 11 and power supply terminal 120. Inductor 52 is an example of a second inductor and is connected between the first output terminal of power amplifier 11 and power supply terminal 120. Switch 43 is an example of a first switch and is connected in parallel to inductor 52. Inductor 51 and the parallel-connected inductor 52 and switch 43 are connected in series between the first output terminal and power supply terminal 120.

[0064] The inductor 53 is an example of a third inductor, and is connected between the second output terminal of the power amplifier 12 and the power supply terminal 120 .

[0065] The capacitor 54 is connected between the power supply terminal 120 and ground.

[0066] The provision of inductors 51 to 53 and capacitor 54 prevents high frequency signals output from power amplifiers 11 and 12 from leaking to power supply terminal 120 and ground.

[0067] Each of the inductors 51 to 53 may be a planar coil or wiring formed on a substrate on which the components constituting the amplifier circuit 10 are mounted, or may be a surface-mounted component.

[0068] 2A is a circuit diagram of the high-frequency circuit 1 according to the embodiment in Band A transmission mode (modulation bandwidth 20 MHz). Also, FIG. 2B is a circuit diagram of the high-frequency circuit 1 according to the embodiment in Band A transmission mode (modulation bandwidth 100 MHz).

[0069] As shown in FIGS. 2A and 2B, in the band A transmission mode in which a band A transmission signal and a band B reception signal are simultaneously transmitted, the circuit state differs depending on the size of the modulation bandwidth of the band A transmission signal.

[0070] 2A , when the modulation bandwidth is 20 MHz (first modulation bandwidth) in Band A transmission mode, terminals 41a and 41d are connected, and terminals 41a and 41e are connected in switch 41. Furthermore, terminals 42a and 42b are connected in switch 42. Furthermore, switch 43 is in a non-connected (off) state, and switches 215 and 225 are in a non-connected (off) state.

[0071] On the other hand, when the modulation bandwidth is 100 MHz (second modulation bandwidth) in Band A transmission mode, as shown in Fig. 2B, in switch 41, terminals 41a and 41d are connected, and terminals 41a and 41e are connected. In switch 42, terminals 42a and 42b are connected. In addition, switch 43 is connected (ON), and switches 215 and 225 are connected (ON).

[0072] In this case, for both modulation bandwidths of 20 MHz and 100 MHz, the transmit signal of Band A is demultiplexed into demultiplexed signals RF1 and RF2 by 90° hybrid circuit 50, which are then input to and amplified by power amplifiers 11 and 12, respectively, to become a first demultiplexed signal and a second demultiplexed signal. The phase of the first demultiplexed signal is 0° at the first output terminal of power amplifier 11, and the phase of the second demultiplexed signal is +90° at the second output terminal of power amplifier 12.

[0073] The phase of the first demultiplexed signal at terminal 41a after passing through high-pass filter 21 (the transmission signal of band A has a passing phase of +45°) is approximately +45°, and the phase of the second demultiplexed signal at terminal 41a after passing through low-pass filter 22 (the transmission signal of band A has a passing phase of -45°) is approximately +45°. As a result, the first and second demultiplexed signals of band A are combined in phase at terminal 41a, enabling highly efficient power combining in the face of load fluctuations.

[0074] 3 is a graph showing the baseband impedance characteristics of the amplifier circuit 10 according to the embodiment. The horizontal axis of the graph represents the baseband frequency (modulation bandwidth or envelope frequency) of the high-frequency signal transmitted through the amplifier circuit 10, and the vertical axis represents the impedance of the baseband band at the output terminal of the power amplifier 11 or 12 (hereinafter referred to as baseband impedance). The baseband impedance of the power amplifier 11 varies depending on the inductance of the power supply line. Specifically, when the switch 43 is in the off state, the inductance value of the power supply line is the series addition of the inductance values ​​of the inductors 51 and 52. In contrast, when the switch 43 is in the on state, the inductance value of the power supply line is the inductance value of the inductor 51 because the inductor 52 is bypassed, resulting in a smaller inductance value. Therefore, when the switch 43 is in the on state, the baseband impedance can be reduced at higher baseband frequencies (e.g., 100 MHz to 300 MHz). This makes it possible to suppress intermodulation distortion (so-called memory effect) that occurs due to mixing of the baseband and the fundamental wave when the baseband frequency is on the higher side. However, simply reducing the inductance value of the power supply line can cause the problem of high-frequency signals leaking to the power supply terminal 120 side, especially when the modulation bandwidth is large.

[0075] 4 is a circuit diagram of an amplifier circuit 510 according to a comparative example. The amplifier circuit 510 according to the comparative example differs from the amplifier circuit 10 according to the embodiment only in that only an inductor 551 is connected between the first output terminal of the power amplifier 11 and the power supply terminal 120, and the inductance value cannot be changed. In the amplifier circuit 510 according to the comparative example, the inductance value of the power supply line cannot be changed depending on the magnitude of the modulation bandwidth, and therefore, when the baseband frequency is on the higher frequency side, intermodulation distortion due to the memory effect cannot be suppressed.

[0076] Fig. 5A is a diagram illustrating the baseband impedance of the power amplifiers 11 and 12 according to the embodiment in the Band A transmission mode (modulation bandwidth 20 MHz). Fig. 5B is a diagram illustrating the baseband impedance of the power amplifiers 11 and 12 according to the embodiment in the Band A transmission mode (modulation bandwidth 100 MHz). Fig. 6A is a diagram illustrating the principle of suppressing fundamental distortion in the Band A transmission mode (modulation bandwidth 20 MHz) of the amplifier circuit 10 according to the embodiment. Fig. 6B is a diagram illustrating the principle of suppressing fundamental distortion in the Band A transmission mode (modulation bandwidth 100 MHz) of the amplifier circuit 10 according to the embodiment.

[0077] As shown in (a) of Figures 5A and 6A, in Band A transmission mode (modulation bandwidth 20 MHz), the baseband (near 20 MHz) impedances of both power amplifiers 11 and 12 are low. As a result, as shown in (c) of Figure 6A, the signal strength at the baseband frequency of power amplifiers 11 and 12 is reduced, and as shown in (d) of Figure 6A, even if a memory effect occurs, intermodulation distortion in a band adjacent to the fundamental wave band can be reduced.

[0078] On the other hand, as shown in (a) of Figures 5B and 6B, in Band A transmission mode (modulation bandwidth 100 MHz), the baseband (near 100 MHz) impedances of both power amplifiers 11 and 12 are low. Furthermore, as shown in (c) of Figures 5B and 6B, the baseband impedance (capacitive) of power amplifier 11 and the baseband impedance (inductive) of power amplifier 12 are in an inverse relationship (complex conjugate). In other words, the difference between the first reflection phase of the baseband frequency when viewed from the first output end of power amplifier 11 toward the signal combining point (terminal 41a) and the second reflection phase of the baseband frequency when viewed from the second output end of power amplifier 12 toward the signal combining point (terminal 41a) is 45° to 180°. This allows the signal strengths in the basebands of power amplifiers 11 and 12 to be canceled out, and as shown in (d) of Figure 6B, intermodulation distortion in a band adjacent to the fundamental wave band can be reduced. At this time, the baseband impedance of power amplifier 11 and the baseband impedance of power amplifier 12 are inverted, so that the combined baseband impedance of power amplifiers 11 and 12 is prevented from decreasing, and high-frequency signals are prevented from leaking to the power supply terminal 120 side.

[0079] Furthermore, since the power amplifier 11 in which the high-pass filter 21 is disposed is provided with a circuit that varies the inductance of the power supply line, the phase rotation direction of this circuit is the same as the phase rotation direction of the high-pass filter 21. This prevents the passing phase of the high-pass filter 21 from being significantly shifted due to the circuit of the power supply line, making it easy to adjust the passing phase of the high-pass filter 21. This makes it possible to suppress transmission loss of the fundamental wave of the high-frequency signal.

[0080] 7A is a graph showing the signal strength of the fundamental frequency band in Band A transmission mode (modulation bandwidth 100 MHz) of the amplifier circuit 10 according to the embodiment. Fig. 7B is a graph showing the signal strength of the fundamental frequency band in Band A transmission mode (modulation bandwidth 100 MHz) of the amplifier circuit 510 according to the comparative example.

[0081] In the amplifier circuit 510 according to the comparative example, as shown in FIG. 7B, when the modulation bandwidth is 100 MHz, even if DPD (Digital Pre-Distortion) is activated, the ACLR (Adjacent Channel Leakage Ratio) is not improved.

[0082] In contrast, in the amplifier circuit 10 according to the embodiment, turning on the switch 43 reduces the inductance of the power supply line and inverts the baseband impedance of the power amplifiers 11 and 12. Therefore, as shown in FIG. 7A, activating the DPD can improve the ACLR.

[0083] [1.5 Component Arrangement of Amplifier Circuit 10] Next, the component arrangement of the amplifier circuit 10 according to the embodiment will be described. FIG. 8A is a plan view and a cross-sectional view of the amplifier circuit 10 according to the embodiment. FIG. 8A (a) shows the arrangement of circuit components when the main surface 90a of the mounting board 90 is viewed from the positive side of the z-axis. FIG. 8A (b) shows a cross section taken along line p-p in FIG. 8A (a). Note that FIG. 8A omits some of the wiring connecting the mounting board 90 and the circuit components.

[0084] The amplifier circuit 10 shown in FIG. 8A further includes a mounting substrate 90 in addition to the amplifier circuit 10 shown in FIG.

[0085] The mounting substrate 90 has opposing main surfaces 90a (first main surface) and 90b (second main surface), and is a substrate on which circuit components constituting the amplifier circuit 10 are mounted. Examples of the mounting substrate 90 that can be used include a low temperature co-fired ceramics (LTCC) substrate having a laminated structure of multiple dielectric layers, a high temperature co-fired ceramics (HTCC) substrate, a component-embedded substrate, a substrate having a redistribution layer (RDL), a printed circuit board, and the like.

[0086] 8A, the 90° hybrid circuit 50, the power amplifiers 11 and 12, the inductors 51, 52, 53, 213 and 221, and the capacitors 211, 212, 222, 223 and 54 are arranged on the main surface 90a, while the switch 43 is arranged on the main surface 90b.

[0087] Note that Figure 8A does not show the arrangement of switches 41, 215, and 225, capacitors 214 and 224, low-noise amplifiers 14 to 16, and power supply terminal 120 that constitute amplifier circuit 10, but these may be arranged on either main surface 90a or 90b, or may be arranged inside mounting substrate 90.

[0088] Inductor 51 is a first planar coil formed on main surface 90a of mounting substrate 90, and inductor 52 is a second planar coil formed on main surface 90a of mounting substrate 90. Inductor 53 is a third planar coil formed on main surface 90a of mounting substrate 90. Node n1, which is one end of first planar coil (inductor 51), is connected to a first output terminal of power amplifier 11. Node n2, which is the other end of first planar coil (inductor 51) and one end of second planar coil (inductor 52), is connected to one end of switch 43 via via conductor 92 (first via conductor) arranged on mounting substrate 90. Node n3, which is the other end of second planar coil (inductor 52), is connected to the other end of switch 43 via via conductor 93 (second via conductor) arranged on mounting substrate 90. First planar coil (inductor 51) is a part of one planar coil, and second planar coil (inductor 52) is the other part of the one planar coil.

[0089] The first planar coil, the second planar coil, and the third planar coil may be formed on an inner layer of mounting substrate 90 rather than on a surface layer. The first planar coil and the second planar coil do not have to be formed as a single planar coil, but may be formed as separate planar coils. The first planar coil and the second planar coil may each be formed across multiple layers. The first planar coil and the second planar coil may also be formed on different layers of mounting substrate 90.

[0090] Power amplifiers 11 and 12 are included in semiconductor IC 81 (first semiconductor IC), and switch 43 is included in semiconductor IC 82 (second semiconductor IC). Switches 41, 215, and 225 may also be included in semiconductor IC 82. 90° hybrid circuit 50 may also be included in semiconductor IC 81.

[0091] According to the above-described arrangement of amplifier circuit 10, the circuit components constituting amplifier circuit 10 are distributed and arranged on both main surfaces of mounting substrate 90, thereby enabling a reduction in the size of amplifier circuit 10. Furthermore, since inductors 51 to 53 are formed by planar coils on mounting substrate 90, amplifier circuit 10 can be further reduced in size. Furthermore, since power amplifiers 11 and 12 are included in semiconductor IC 81 and switch 43 is included in semiconductor IC 82, amplifier circuit 10 can be further reduced in size.

[0092] When mounting substrate 90 is viewed from above, it is desirable that power amplifiers 11 and 12 do not overlap switch 43. This improves heat dissipation from power amplifiers 11 and 12 to main surface 90b, and also prevents the switching characteristics of switch 43 from deteriorating due to heat dissipation from power amplifiers 11 and 12.

[0093] [1.6 Component Arrangement of Amplifier Circuit 10A According to Modification 1] Next, the component arrangement of the amplifier circuit 10A according to Modification 1 will be described. FIG. 8B is a plan view and a cross-sectional view of the amplifier circuit 10A according to Modification 1 of the embodiment. FIG. 8B (a) shows the arrangement of circuit components when the main surface 90a of the mounting board 90 is viewed from the positive side of the z-axis. FIG. 8B (b) shows a cross section taken along line q-q in FIG. 8B (a). Note that FIG. 8B omits some of the wiring connecting the mounting board 90 and the circuit components.

[0094] The amplifier circuit 10A according to this modification differs from the amplifier circuit 10 according to the embodiment only in that an inductor 52A is provided instead of the inductor 52. Therefore, in the following, the description of the arrangement of the amplifier circuit 10A according to this modification, which is the same as that of the amplifier circuit 10 according to the embodiment, will be omitted and the description will focus on the different arrangement.

[0095] The amplifier circuit 10A shown in FIG. 8B differs from the amplifier circuit 10 shown in FIG. 1 in that an inductor 52A is provided instead of the inductor 52, and further includes a mounting substrate 90.

[0096] 8B, the 90° hybrid circuit 50, the power amplifiers 11 and 12, the inductors 51, 52A, 53, 213 and 221, and the capacitors 211, 212, 222, 223 and 54 are arranged on the main surface 90a, while the switch 43 is arranged on the main surface 90b.

[0097] Inductor 51 is a first planar coil formed on main surface 90a of mounting substrate 90, and inductor 52A is a surface-mounted component disposed on main surface 90a of mounting substrate 90. Inductor 53 is a third planar coil formed on main surface 90a of mounting substrate 90. Node n1, which is one end of first planar coil (inductor 51), is connected to a first output terminal of power amplifier 11. Node n2, which is the other end of first planar coil (inductor 51) and one end of surface-mounted component (inductor 52A), is connected to one end of switch 43 via via conductor 92 (first via conductor) disposed on mounting substrate 90. Node n3, which is the other end of surface-mounted component (inductor 52A), is connected to the other end of switch 43 via via conductor 93 (second via conductor) disposed on mounting substrate 90.

[0098] The first planar coil and the third planar coil may be formed on an inner layer of mounting substrate 90 instead of on a surface layer.

[0099] According to the above-described layout configuration of the amplifier circuit 10A, the circuit components constituting the amplifier circuit 10A are distributed and arranged on both main surfaces of the mounting substrate 90, thereby enabling the miniaturization of the amplifier circuit 10A. Furthermore, because the inductor 52A is configured as a surface-mounted component, the inductance value of the power supply line can be easily adjusted.

[0100] 9 is a circuit diagram of an amplifier circuit 10B according to Modification 2 of the embodiment. As shown in the figure, the amplifier circuit 10B includes power amplifiers 11 and 12, a high-pass filter 21, a low-pass filter 22, switches 41, 43, and 44, a 90° hybrid circuit 50, inductors 51, 52, 55, and 56, a capacitor 54, and a signal input terminal 110. The amplifier circuit 10B according to this modification differs from the amplifier circuit 10 according to the embodiment in the circuit configuration of the power supply line connected to the power amplifier 12. Therefore, the following description of the amplifier circuit 10B according to this modification will focus on the different configuration and omit the description of the same configuration as the amplifier circuit 10 according to the embodiment.

[0101] The switch 41 is an example of a combining circuit and an example of a fourth switch, and has terminals 41a (third output terminal), 41b, 41c (fourth output terminal), 41d (third input terminal), and 41e (fourth input terminal). The switch 41 switches between a connection between the terminal 41d and the terminal 41a and a connection between the terminal 41e and the terminal 41a (band A transmission high-power mode), a connection between the terminal 41d and the terminal 41a and a connection between the terminal 41e and the terminal 41b (second band A transmission high-power mode), a connection between the terminal 41d and the terminal 41c and a connection between the terminal 41e and the terminal 41c (band B transmission high-power mode), and a connection between the terminal 41e and the terminal 41a (band A transmission low-power mode).

[0102] As a result, in the band A transmission high power mode, the switch 41 is configured to output from the terminal 41a the band A output signal generated by in-phase synthesis at the terminal 41a of the first demultiplexed signal of band A input from the terminal 41d and the second demultiplexed signal of band A input from the terminal 41e.

[0103] In addition, in the band B transmission high power mode, the switch 41 is configured to output from the terminal 41c an output signal generated by in-phase combining at the terminal 41c the third demultiplexed signal of band B input from the terminal 41d and the fourth demultiplexed signal of band B input from the terminal 41e. The terminal 41a is a signal combining point where the first demultiplexed signal of band A and the second demultiplexed signal of band A are combined in phase, and the terminal 41c is a signal combining point where the third demultiplexed signal of band B and the fourth demultiplexed signal of band B are combined in phase.

[0104] In the second band A transmission high power mode, the switch 41 outputs from terminal 41a the band A transmission signal input from terminal 41d, and outputs from terminal 41b the band A transmission signal input from terminal 41e. The band A signal output from terminal 41a and the band A signal output from terminal 41b are in-phase combined at terminal 42a of the switch 42. In the second band A transmission mode, terminal 42a is the signal combining point.

[0105] In the band A transmission low power mode, the switch 41 outputs the band A transmission signal input from the terminal 41e from the terminal 41a, and the power amplifier 11 is turned off at this time.

[0106] In addition, the amplifier circuit 10B does not necessarily have to execute the second band A transmission high power mode, and in this case, the terminal 41b may be omitted.

[0107] The low power mode is a mode in which the maximum output power of the amplifier circuit 10B is relatively small, for example, a mode in which the maximum output power is smaller than the maximum output power allowed in power class 3. The high power mode is a mode in which the maximum output power of the amplifier circuit 10B is relatively large, for example, a mode in which the maximum output power is equal to or greater than the maximum output power allowed in power class 3.

[0108] The power class is a classification of the output power of a UE, defined by the maximum output power, etc., and the smaller the power class value, the higher the power output allowed. For example, in 3GPP (registered trademark), the maximum output power allowed for power class 1 is 31 dBm, the maximum output power allowed for power class 1.5 is 29 dBm, the maximum output power allowed for power class 2 is 26 dBm, and the maximum output power allowed for power class 3 is 23 dBm.

[0109] The inductor 55 is an example of a sixth inductor, and is connected between the second output terminal of the power amplifier 12 and the power supply terminal 120. The inductor 56 is an example of a seventh inductor, and is connected between the second output terminal of the power amplifier 12 and the power supply terminal 120. The switch 44 is an example of a second switch, and is connected in parallel to the inductor 56. The inductor 55 and the inductor 56 and switch 44 connected in parallel are connected in series between the second output terminal and the power supply terminal 120.

[0110] The capacitor 54 is connected between the power supply terminal 120 and ground.

[0111] In the case of band A transmission low power mode in which the band A transmission signal is transmitted in low power mode, the circuit state differs depending on the size of the modulation bandwidth of the band A transmission signal.

[0112] When the modulation bandwidth is 20 MHz (first modulation bandwidth) in the Band A transmission low power mode, the power amplifier 11 is turned off, and the terminals 41e and 41a of the switch 41 are connected to each other. Also, the switch 44 is turned off.

[0113] When the modulation bandwidth is 100 MHz (second modulation bandwidth) in the Band A transmission low power mode, the terminal 41e is connected to the terminal 41a of the switch 41. Also, as shown in FIG. 9, the switch 44 is in the connected (ON) state.

[0114] 10A and 10B are graphs showing baseband impedance characteristics and power-added efficiency (PAE) characteristics of the amplifier circuit 10B according to the second modification of the embodiment.

[0115] In low power mode (modulation bandwidth: 100 MHz), by turning off the power amplifier 11 connected to the high-pass filter 21 and turning on the switch 44, only the power amplifier 12 connected to the low-pass filter 22 operates at high impedance. As a result, the power amplifier 12 operates at a low current, and as shown in FIG. 10B, the PAE of the amplifier circuit 10B in the low power mode (LPM) is higher than the PAE of the amplifier circuit 10B in the high power mode (HPM). Furthermore, as shown in FIG. 10A, the inductance of the power supply line of the power amplifier 12 is reduced, thereby reducing the baseband impedance and reducing the ACLR.

[0116] 11 is a circuit diagram of an amplifier circuit 10C according to Modification 3 of the embodiment. As shown in the figure, the amplifier circuit 10C includes power amplifiers 11 and 12, a high-pass filter 21, a low-pass filter 22, switches 43 and 45, a 90° hybrid circuit 50, inductors 51, 52, and 53, a capacitor 54, a combining circuit 25, and a signal input terminal 110. The amplifier circuit 10C according to this modification has a different combining circuit configuration from the amplifier circuit 10 according to the embodiment. Therefore, the following description of the amplifier circuit 10C according to this modification will focus on the different configuration and omit a description of the same configuration as the amplifier circuit 10 according to the embodiment.

[0117] The switch 45 has terminals 45a, 45b, 45c, and 45d, and switches between a connection between the terminal 45d and the terminal 45a, a connection between the terminal 45d and the terminal 45b, and a connection between the terminal 45d and the terminal 45c.

[0118] The combining circuit 25 is disposed between the high-pass filter 21, the low-pass filter 22, and the switch 45, and has a third input terminal, a fourth input terminal, and a third output terminal. The third input terminal is connected to the third output terminal via a matching inductor, and the fourth input terminal is connected to the third output terminal via a matching inductor. The third input terminal is connected to the high-pass filter 21, and the fourth input terminal is connected to the low-pass filter 22. The third output terminal is a signal combining point and is connected to terminal 45d of the switch 45 via a matching capacitor. With the above configuration, the first demultiplexed signal of Band A input from the third input terminal and the second demultiplexed signal of Band A input from the fourth input terminal are in-phase combined to generate a Band A output signal, which can be output from the third output terminal. Therefore, the first demultiplexed signal of Band A and the second demultiplexed signal of Band A are in-phase combined at the third output terminal, enabling the amplifier circuit 10C to perform highly efficient power combining even with load fluctuations. Furthermore, since an inductor and a capacitor for impedance matching can be added before and after the third output terminal, the loss of the high frequency signal transmitted through the amplifier circuit 10C can be reduced.

[0119] 1.9 Configuration of Amplifier Circuit 10D According to Modification 4 FIG. 12 is a circuit configuration diagram of an amplifier circuit 10D according to Modification 4 of the embodiment. As shown in the figure, the amplifier circuit 10D includes power amplifiers 11 and 12, a high-pass filter 21, a low-pass filter 22, switches 44 and 45, a 90° hybrid circuit 50, inductors 51, 55, and 56, a capacitor 54, a transformer 58, and a signal input terminal 110. The amplifier circuit 10D according to this modification differs from the amplifier circuit 10 according to the embodiment in that it has a voltage-combining circuit configuration, whereas the amplifier circuit 10 according to the embodiment has a current-combining circuit configuration. Therefore, the following description of the amplifier circuit 10D according to this modification will omit a description of the same configuration as the amplifier circuit 10 according to the embodiment, and will focus on the different configuration.

[0120] In this modification, power amplifier 11 is an example of a second power amplifier, and has a second input terminal and a second output terminal, with the second input terminal being connected to output terminal 50b (not shown in FIG. 12 ) of 90° hybrid circuit 50. Power amplifier 12 is an example of a first power amplifier in this modification, and has a first input terminal and a first output terminal, with the first input terminal being connected to output terminal 50c (not shown in FIG. 12 ) of 90° hybrid circuit 50. Power amplifiers 11 and 12 are capable of amplifying the high-frequency signal of band A or band B output from 90° hybrid circuit 50.

[0121] The high-pass filter 21 is connected between the first output terminal of the power amplifier 12 and the transformer 58 .

[0122] The low-pass filter 22 is connected between the second output terminal of the power amplifier 11 and the transformer 58 .

[0123] The switch 45 has terminals 45a, 45b, 45c, and 45d, and switches between a connection between the terminal 45d and the terminal 45a, a connection between the terminal 45d and the terminal 45b, and a connection between the terminal 45d and the terminal 45c.

[0124] The transformer 58 has an input coil and an output coil and is included in a composite circuit. The composite circuit has a third input terminal, a fourth input terminal, and a third output terminal. One end of the input coil is connected to the third input terminal, the other end of the input coil is connected to the fourth input terminal, one end of the output coil is connected to the third output terminal, and the other end of the output coil is connected to ground.

[0125] The inductor 55 is an example of a first inductor and is connected between the first output terminal of the power amplifier 12 and the power supply terminal 120. The inductor 56 is an example of a second inductor and is connected between the first output terminal of the power amplifier 12 and the power supply terminal 120. The switch 44 is an example of a first switch and is connected in parallel to the inductor 56. The inductor 55 and the inductor 56 and switch 44 connected in parallel are connected in series between the first output terminal and the power supply terminal 120.

[0126] The inductor 51 is an example of a third inductor, and is connected between the second output terminal of the power amplifier 11 and the power supply terminal 120 .

[0127] The capacitor 54 is connected between the power supply terminal 120 and ground.

[0128] When transmitting a transmission signal of Band A, the circuit state differs depending on the modulation bandwidth of the transmission signal of Band A. When the modulation bandwidth is 20 MHz (first modulation bandwidth), terminals 45a and 45d of switch 45 are connected, and switch 44 is in the non-connected (off) state. On the other hand, when the modulation bandwidth is 100 MHz (second modulation bandwidth), terminals 45a and 45d of switch 45 are connected, and switch 44 is in the connected (on) state.

[0129] In this case, for both modulation bandwidths of 20 MHz and 100 MHz, the transmit signal of Band A is demultiplexed into demultiplexed signals RF1 and RF2 by 90° hybrid circuit 50, which are then input to and amplified by power amplifiers 11 and 12, respectively, to become a first demultiplexed signal and a second demultiplexed signal. The phase of the second demultiplexed signal is 0° at the second output terminal of power amplifier 11, and the phase of the first demultiplexed signal is 90° at the first output terminal of power amplifier 12.

[0130] The phase of the first demultiplexed signal at the other end of the input coil after passing through high-pass filter 21 (the transmission signal of band A has a passing phase of +45°) is approximately +135°, and the phase of the second demultiplexed signal at one end of the input coil after passing through low-pass filter 22 (the transmission signal of band A has a passing phase of -45°) is approximately -45°. As a result, the first and second demultiplexed signals of band A are combined in opposite phases by transformer 58, enabling highly efficient power combining in response to load fluctuations.

[0131] According to this, by turning on switch 44, the inductance of the power supply line is reduced and the baseband impedance of power amplifiers 11 and 12 is inverted, thereby suppressing an increase in transmission loss of the fundamental wave and deterioration of distortion characteristics.

[0132] [2. Effects, etc.] As described above, amplifier circuit 10 according to this embodiment includes: 90° hybrid circuit 50 having input terminal 50 a and output terminals 50 b and 50 c; power amplifier 11 having a first input terminal and a first output terminal, with the first input terminal connected to output terminal 50 b; power amplifier 12 having a second input terminal and a second output terminal, with the second input terminal connected to output terminal 50 c; a combiner circuit having a third input terminal, a fourth input terminal, and a third output terminal; high-pass filter 21 connected between the first output terminal and the third input terminal; low-pass filter 22 connected between the second output terminal and the fourth input terminal; inductors 51 and 52 connected in series to each other, and switch 43 connected in parallel to inductor 52, which are connected between the first output terminal and power supply terminal 120.

[0133] According to this, by turning on switch 43, the inductance of the power supply line can be reduced and the baseband impedance of power amplifiers 11 and 12 can be inverted. Furthermore, since a circuit that varies the inductance of the power supply line is provided in the path in which high-pass filter 21 is arranged, the phase rotation direction of this circuit is the same as the phase rotation direction of high-pass filter 21. Therefore, it is possible to prevent the passing phase of high-pass filter 21 from being significantly shifted due to the circuit in the power supply line. Therefore, it is possible to provide amplifier circuit 10 in which the transmission loss of the fundamental wave of the high-frequency signal is suppressed while deterioration of distortion characteristics (ACLR) is suppressed.

[0134] For example, in the amplifier circuit 10, when a high-frequency signal modulated with a first modulation bandwidth is input to the 90° hybrid circuit 50, the switch 43 is turned off, and when a high-frequency signal modulated with a second modulation bandwidth wider than the first modulation bandwidth is input to the 90° hybrid circuit 50, the switch 43 is turned on.

[0135] According to this, when the modulation bandwidth is 20 MHz, for example, the baseband impedances of the power amplifiers 11 and 12 are both low. As a result, the signal strength at the baseband frequency of the power amplifiers 11 and 12 is reduced, and even if a memory effect occurs, the intermodulation distortion (ACLR) in a band adjacent to the fundamental wave band can be reduced. Also, when the modulation bandwidth is 100 MHz, for example, the baseband impedances of the power amplifiers 11 and 12 are both low. Furthermore, the baseband impedances of the power amplifiers 11 and 12 are in an inverted relationship. This allows the signal strengths at the basebands of the power amplifiers 11 and 12 to be canceled out, thereby reducing the intermodulation distortion (ACLR) in a band adjacent to the fundamental wave band. Furthermore, since the baseband impedances of the power amplifiers 11 and 12 are inverted, the combined baseband impedance of the power amplifiers 11 and 12 is prevented from decreasing, and high-frequency signals are prevented from leaking to the power supply terminal 120.

[0136] For example, the amplifier circuit 10 further includes an inductor 53 connected between the second output terminal and the power supply terminal 120 .

[0137] This makes it possible to balance the baseband impedance of the power amplifier 11 and the baseband impedance of the power amplifier 12.

[0138] Also, for example, in the amplifier circuit 10, the high-pass filter 21 includes a capacitor 211 connected between the first output terminal and the third input terminal, an inductor 213 connected between a first path connecting the capacitor 211 and the third input terminal and ground, and a first variable capacitor circuit connected between the first output terminal and the third input terminal, the first variable capacitor circuit being composed of a capacitor 214 connected in series with each other and a switch 215. The low-pass filter 22 includes an inductor 221 connected between the second output terminal and the fourth input terminal, a capacitor 223 connected between a second path connecting the inductor 221 and the fourth input terminal and ground, and a second variable capacitor circuit connected between the second path and ground, the second variable capacitor circuit being composed of a capacitor 224 connected in series with each other and a switch 225.

[0139] With this configuration, the high-pass filter 21 can set the passing phase of the fundamental wave to +45°, and the first variable capacitor circuit can finely adjust the passing phase. The low-pass filter 22 can set the passing phase of the fundamental wave to -45°, and the second variable capacitor circuit can finely adjust the passing phase.

[0140] Also, for example, in the amplifier circuit 10C according to the third modification, the combining circuit 25 is configured to output from the third output terminal an output signal of band A generated by in-phase combining the first demultiplexed signal of band A input from the third input terminal and the second demultiplexed signal of band A input from the fourth input terminal.

[0141] In this way, the first and second demultiplexed signals of Band A are combined in phase at the third output terminal, enabling the amplifier circuit 10C to perform highly efficient power combining despite load fluctuations. Furthermore, since an inductor and a capacitor for impedance matching can be added before and after the second output terminal, loss in the high-frequency signal transmitted through the amplifier circuit 10C can be reduced.

[0142] Furthermore, for example, in the amplifier circuit 10 according to the embodiment, the combining circuit is a switch 41 having terminals 41d, 41e, 41a, and 41c, and the switch 41 is configured to output from the terminal 41a an output signal of band A generated by in-phase combining the first demultiplexed signal of band A input from the terminal 41d and the second demultiplexed signal of band A input from the terminal 41e, and to output from the terminal 41c an output signal of band B generated by in-phase combining the third demultiplexed signal of band B input from the terminal 41d and the fourth demultiplexed signal of band B input from the terminal 41e.

[0143] In this way, the switch 41 has the function of switching between transmission of band A and band B, and the function of acting as a signal combining point that combines currents of the branched signals output from the power amplifier 11 and the branched signals output from the power amplifier 12, thereby enabling the amplifier circuit 10 to be made smaller.

[0144] For example, in the amplifier circuit 10D according to the fourth modification, the composite circuit includes a transformer 58 having an input coil and an output coil, one end of the input coil is connected to the third input terminal, the other end of the input coil is connected to the fourth input terminal, one end of the output coil is connected to the third output terminal, and the other end of the output coil is connected to ground.

[0145] As a result, the phase of the first demultiplexed signal at the other end of the input coil after passing through high-pass filter 21 is approximately +135°, and the phase of the second demultiplexed signal at one end of the input coil after passing through low-pass filter 22 is approximately −45°. As a result, the first and second demultiplexed signals of Band A are combined in opposite phases by transformer 58, enabling highly efficient power combining in response to load fluctuations.

[0146] For example, the amplifier circuit 10B according to variant example 2 further includes inductors 55 and 56 connected in series to each other between the second output terminal and the power supply terminal 120, and a switch 44 connected in parallel to the inductor 56.

[0147] This makes it possible to vary not only the inductance of the power supply line in which the high-pass filter 21 is arranged, but also the inductance of the power supply line in which the low-pass filter 22 is arranged.

[0148] Furthermore, for example, in the amplifier circuit 10B according to the second modification, in the high power mode, when a radio frequency signal modulated with a first modulation bandwidth is input to the 90° hybrid circuit 50, the switch 43 is in the off state, and when a radio frequency signal modulated with a second modulation bandwidth wider than the first modulation bandwidth is input to the 90° hybrid circuit 50, the switch 43 is in the on state. In the low power mode, the power amplifier 11 is in the off state, and when a radio frequency signal modulated with the first modulation bandwidth is input to the 90° hybrid circuit 50, the switch 44 is in the off state, and when a radio frequency signal modulated with the second modulation bandwidth is input to the 90° hybrid circuit 50, the switch 44 is in the on state.

[0149] According to this, in low power mode (modulation bandwidth: 100 MHz), by turning off the power amplifier 11 connected to the high-pass filter 21 and turning on the switch 44, only the power amplifier 12 connected to the low-pass filter 22 operates at high impedance. As a result, the power amplifier 12 operates at a low current, and the PAE of the amplifier circuit 10B in the low power mode is higher than the PAE of the amplifier circuit 10B in the high power mode. Furthermore, the inductance of the power supply line of the power amplifier 12 is reduced, thereby reducing the baseband impedance and reducing the ACLR.

[0150] For example, amplifier circuit 10 further includes a mounting substrate 90 having principal surfaces 90a and 90b facing each other, power amplifiers 11 and 12 are arranged on principal surface 90a, switch 43 is arranged on principal surface 90b, inductor 51 is made of a first planar coil formed on mounting substrate 90, inductor 52 is made of a second planar coil formed on mounting substrate 90, one end of the first planar coil is connected to the first output terminal, the other end of the first planar coil and one end of the second planar coil are connected to one end of switch 43 via via conductor 92 arranged on mounting substrate 90, and the other end of the second planar coil is connected to the other end of switch 43 via via conductor 93 arranged on mounting substrate 90.

[0151] This allows the circuit components that make up the amplifier circuit 10 to be distributed and arranged on both main surfaces of the mounting substrate 90, thereby reducing the size of the amplifier circuit 10. Furthermore, since the inductors 51 to 53 are formed by planar coils on the mounting substrate 90, the amplifier circuit 10 can be further reduced in size.

[0152] For example, amplifier circuit 10A according to variant example 1 further includes mounting substrate 90 having principal surfaces 90a and 90b facing each other, power amplifiers 11 and 12 are arranged on principal surface 90a, switch 43 is arranged on principal surface 90b, inductor 51 consists of a first planar coil formed on mounting substrate 90, inductor 52A is a surface-mounted component arranged on principal surface 90a, one end of the first planar coil is connected to the first output terminal, the other end of the first planar coil and one end of the surface-mounted component are connected to one end of switch 43 via via conductor 92 arranged on mounting substrate 90, and the other end of the surface-mounted component is connected to the other end of switch 43 via via conductor 93 arranged on mounting substrate 90.

[0153] This allows the amplifier circuit 10A to be miniaturized, since the circuit components constituting the amplifier circuit 10A are distributed and arranged on both main surfaces of the mounting substrate 90. Furthermore, since the inductor 52A is configured as a surface-mounted component, the inductance value of the power supply line can be easily adjusted.

[0154] Further, for example, in the amplifier circuits 10 and 10A, the power amplifiers 11 and 12 are included in a semiconductor IC 81, and the switch 43 is included in a semiconductor IC .

[0155] This allows the amplifier circuits 10 and 10A to be further miniaturized.

[0156] Furthermore, for example, in the amplifier circuits 10 and 10A, when the mounting substrate 90 is viewed from above, the power amplifiers 11 and 12 do not overlap the switch 43 .

[0157] This improves heat dissipation toward the main surface 90 b of the power amplifiers 11 and 12 , and also prevents the switching characteristics of the switch 43 from deteriorating due to heat dissipation from the power amplifiers 11 and 12 .

[0158] (Other Embodiments, etc.) While the amplifier circuit according to the embodiment of the present invention has been described above with reference to the embodiment and modifications thereof, the amplifier circuit according to the present invention is not limited to the above-described embodiment and modifications. The present invention also includes other embodiments realized by combining any of the components in the above-described embodiment and modifications, modifications obtained by applying various modifications to the above-described embodiment and modifications that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above-described amplifier circuit.

[0159] For example, in the amplifier circuits, high-frequency circuits, and communication devices according to the above-described embodiments and modifications, other circuit elements, wiring, etc. may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings.

[0160] The features of the amplifier circuits described based on the above-described embodiment and modifications will be described below.

[0161] <1> An amplifier circuit comprising: a 90° hybrid circuit having a first input terminal, a first output terminal, and a second output terminal; a first power amplifier having a first input terminal and a first output terminal, the first input terminal being connected to the first output terminal; a second power amplifier having a second input terminal and a second output terminal, the second input terminal being connected to the second output terminal; a combiner circuit having a third input terminal, a fourth input terminal, and a third output terminal; a high-pass filter connected between the first output terminal and the third input terminal; a low-pass filter connected between the second output terminal and the fourth input terminal; a first inductor and a second inductor connected in series to each other between the first output terminal and a power supply terminal; and a first switch connected in parallel to the second inductor.

[0162] <2> The amplifier circuit according to <1>, wherein when a high-frequency signal modulated with a first modulation bandwidth is input to the 90° hybrid circuit, the first switch is turned off, and when a high-frequency signal modulated with a second modulation bandwidth wider than the first modulation bandwidth is input to the 90° hybrid circuit, the first switch is turned on.

[0163] <3> The amplifier circuit according to <1> or <2>, further comprising a third inductor connected between the second output terminal and a power supply terminal.

[0164] <4> The amplifier circuit according to any one of <1> to <3>, wherein the high-pass filter includes: a first capacitor connected between the first output terminal and the third input terminal; a fourth inductor connected between a first path connecting the first capacitor and the third input terminal and ground; and a first variable capacitor circuit connected between the first output terminal and the third input terminal, the first variable capacitor circuit being made up of a second capacitor and a second switch connected in series with each other; and the low-pass filter includes: a fifth inductor connected between the second output terminal and the fourth input terminal; a third capacitor connected between a second path connecting the fifth inductor and the fourth input terminal and ground; and a second variable capacitor circuit connected between the second path and ground, the second variable capacitor circuit being made up of a fourth capacitor and a third switch connected in series with each other.

[0165] <5> The amplifier circuit according to any one of <1> to <4>, wherein the combining circuit is configured to output from the third output terminal the output signal of the first band generated by in-phase combining the first demultiplexed signal of the first band input from the third input terminal and the second demultiplexed signal of the first band input from the fourth input terminal.

[0166] <6> The amplifier circuit according to any one of <1> to <4>, wherein the combining circuit is a fourth switch having the third input terminal, the fourth input terminal, the third output terminal, and a fourth output terminal, and the combining circuit is configured to: output from the third output terminal the output signal of the first band generated by in-phase combining the first demultiplexed signal of the first band inputted from the third input terminal and the second demultiplexed signal of the first band inputted from the fourth input terminal; and output from the fourth output terminal the output signal of the second band generated by in-phase combining the third demultiplexed signal of the second band inputted from the third input terminal and the fourth demultiplexed signal of the second band inputted from the fourth input terminal.

[0167] <7> The amplifier circuit according to any one of <1> to <4>, wherein the combining circuit includes a transformer having an input coil and an output coil, one end of the input coil is connected to the third input terminal, the other end of the input coil is connected to the fourth input terminal, one end of the output coil is connected to the third output terminal, and the other end of the output coil is connected to ground.

[0168] <8> The amplifier circuit according to <1>, further comprising: a sixth inductor and a seventh inductor connected in series to each other between the second output terminal and a power supply terminal; and a second switch connected in parallel to the seventh inductor.

[0169] <9> The amplifier circuit according to <8>, wherein in a high power mode, when a high frequency signal modulated with a first modulation bandwidth is input to the 90° hybrid circuit, the first switch is in an off state, and when a high frequency signal modulated with a second modulation bandwidth wider than the first modulation bandwidth is input to the 90° hybrid circuit, the first switch is in an on state; and in a low power mode, the first power amplifier is in an off state, when a high frequency signal modulated with the first modulation bandwidth is input to the 90° hybrid circuit, the second switch is in an off state, and when a high frequency signal modulated with the second modulation bandwidth is input to the 90° hybrid circuit, the second switch is in an on state.

[0170] <10> The amplifier circuit according to any one of <1> to <9>, further comprising a mounting substrate having first and second main surfaces opposing each other, wherein the first power amplifier and the second power amplifier are arranged on the first main surface, the first switch is arranged on the second main surface, the first inductor is made of a first planar coil formed on the mounting substrate, the second inductor is made of a second planar coil formed on the mounting substrate, one end of the first planar coil is connected to the first output terminal, the other end of the first planar coil and one end of the second planar coil are connected to one end of the first switch via a first via conductor arranged on the mounting substrate, and the other end of the second planar coil is connected to the other end of the first switch via a second via conductor arranged on the mounting substrate.

[0171] <11> The amplifier circuit according to any one of <1> to <9>, further comprising a mounting substrate having first and second main surfaces opposing each other, wherein the first power amplifier and the second power amplifier are arranged on the first main surface, the first switch is arranged on the second main surface, the first inductor is made of a first planar coil formed on the mounting substrate, the second inductor is a surface-mounted component arranged on the first main surface, one end of the first planar coil is connected to the first output terminal, the other end of the first planar coil and one end of the surface-mounted component are connected to one end of the first switch via a first via conductor arranged on the mounting substrate, and the other end of the surface-mounted component is connected to the other end of the first switch via a second via conductor arranged on the mounting substrate.

[0172] <12> The amplifier circuit according to <10> or <11>, wherein the first power amplifier and the second power amplifier are included in a first semiconductor IC, and the first switch is included in a second semiconductor IC.

[0173] <13> The amplifier circuit according to any one of <10> to <12>, wherein the first power amplifier and the second power amplifier do not overlap the first switch when the mounting board is viewed from above.

[0174] The present invention can be widely used as an amplifier circuit disposed in a front end portion of communication devices such as mobile phones.

[0175] REFERENCE SIGNS LIST 1 High frequency circuit 2 Antenna 3 RFIC 4 Communication device 10, 10A, 10B, 10C, 10D, 510 Amplification circuit 11, 12 Power amplifier 14, 15, 16 Low noise amplifier 21 High pass filter 22 Low pass filter 25 Combiner circuit 41, 42, 43, 44, 45, 215, 225 Switch 41a, 41b, 41c, 41d, 41e, 42a, 42b, 42c, 42d, 42e, 45a, 45b, 45c, 45d Terminal 50 90° hybrid circuit 50a Input terminal 50b, 50c Output terminal 51, 52, 52A, 53, 55, 56, 71, 72, 73, 74, 75, 76, 77, 78, 213, 221, 551, 552 inductor 54, 211, 212, 214, 222, 223, 224 capacitor 58 transformer 61, 62, 63, 64, 65, 66 filter 81, 82 semiconductor IC 90 mounting substrate 90a, 90b principal surface 92, 93 via conductor 100 antenna connection terminal 110 signal input terminal 120 power supply terminal

Claims

1. An amplifier circuit comprising: a 90° hybrid circuit having a first input terminal, a first output terminal, and a second output terminal; a first power amplifier having a first input terminal and a first output terminal, the first input terminal being connected to the first output terminal; a second power amplifier having a second input terminal and a second output terminal, the second input terminal being connected to the second output terminal; a combiner circuit having a third input terminal, a fourth input terminal, and a third output terminal; a high-pass filter connected between the first output terminal and the third input terminal; a low-pass filter connected between the second output terminal and the fourth input terminal; a first inductor and a second inductor connected in series with each other between the first output terminal and a power supply terminal; and a first switch connected in parallel with the second inductor.

2. The amplifier circuit according to claim 1, wherein when a high frequency signal modulated with a first modulation bandwidth is input to the 90° hybrid circuit, the first switch is turned off, and when a high frequency signal modulated with a second modulation bandwidth wider than the first modulation bandwidth is input to the 90° hybrid circuit, the first switch is turned on.

3. The amplifier circuit according to claim 1 or 2, further comprising a third inductor connected between the second output terminal and a power supply terminal.

4. The amplifier circuit according to any one of claims 1 to 3, wherein the high-pass filter includes: a first capacitor connected between the first output terminal and the third input terminal; a fourth inductor connected between a first path connecting the first capacitor and the third input terminal and ground; and a first variable capacitor circuit connected between the first output terminal and the third input terminal, the first variable capacitor circuit consisting of a second capacitor and a second switch connected in series to each other; and the low-pass filter includes: a fifth inductor connected between the second output terminal and the fourth input terminal; a third capacitor connected between a second path connecting the fifth inductor and the fourth input terminal and ground; and a second variable capacitor circuit connected between the second path and ground, and the second variable capacitor circuit consisting of a fourth capacitor and a third switch connected in series to each other.

5. An amplifier circuit according to any one of claims 1 to 4, wherein the combining circuit is configured to output from the third output terminal the output signal of the first band generated by in-phase combining the first demultiplexed signal of the first band inputted from the third input terminal and the second demultiplexed signal of the first band inputted from the fourth input terminal.

6. The amplifier circuit according to any one of claims 1 to 4, wherein the combining circuit is a fourth switch having the third input terminal, the fourth input terminal, the third output terminal, and a fourth output terminal, and the combining circuit is configured to: output from the third output terminal the output signal of the first band generated by in-phase combining the first demultiplexed signal of the first band inputted from the third input terminal and the second demultiplexed signal of the first band inputted from the fourth input terminal; and output from the fourth output terminal the output signal of the second band generated by in-phase combining the third demultiplexed signal of the second band inputted from the third input terminal and the fourth demultiplexed signal of the second band inputted from the fourth input terminal.

7. An amplifier circuit according to any one of claims 1 to 4, wherein the combining circuit includes a transformer having an input coil and an output coil, one end of the input coil being connected to the third input terminal, the other end of the input coil being connected to the fourth input terminal, one end of the output coil being connected to the third output terminal, and the other end of the output coil being connected to ground.

8. The amplifier circuit according to claim 1, further comprising: a sixth inductor and a seventh inductor connected in series to each other between the second output terminal and the power supply terminal; and a second switch connected in parallel to the seventh inductor.

9. The amplifier circuit according to claim 8, wherein in a high power mode, when a high frequency signal modulated with a first modulation bandwidth is input to the 90° hybrid circuit, the first switch is in an off state, and when a high frequency signal modulated with a second modulation bandwidth wider than the first modulation bandwidth is input to the 90° hybrid circuit, the first switch is in an on state; and in a low power mode, the first power amplifier is in an off state, when a high frequency signal modulated with the first modulation bandwidth is input to the 90° hybrid circuit, the second switch is in an off state, and when a high frequency signal modulated with the second modulation bandwidth is input to the 90° hybrid circuit, the second switch is in an on state.

10. The amplifier circuit according to any one of claims 1 to 9, further comprising a mounting board having first and second main surfaces opposing each other, wherein the first power amplifier and the second power amplifier are arranged on the first main surface, the first switch is arranged on the second main surface, the first inductor is made of a first planar coil formed on the mounting board, the second inductor is made of a second planar coil formed on the mounting board, one end of the first planar coil is connected to the first output terminal, the other end of the first planar coil and one end of the second planar coil are connected to one end of the first switch via a first via conductor arranged on the mounting board, and the other end of the second planar coil is connected to the other end of the first switch via a second via conductor arranged on the mounting board.

11. The amplifier circuit according to any one of claims 1 to 9, further comprising a mounting board having first and second main surfaces opposing each other, wherein the first power amplifier and the second power amplifier are arranged on the first main surface, the first switch is arranged on the second main surface, the first inductor is a first planar coil formed on the mounting board, the second inductor is a surface-mounted component arranged on the first main surface, one end of the first planar coil is connected to the first output terminal, the other end of the first planar coil and one end of the surface-mounted component are connected to one end of the first switch via a first via conductor arranged on the mounting board, and the other end of the surface-mounted component is connected to the other end of the first switch via a second via conductor arranged on the mounting board.

12. The amplifier circuit according to claim 10 or 11, wherein the first power amplifier and the second power amplifier are included in a first semiconductor IC, and the first switch is included in a second semiconductor IC.

13. The amplifier circuit according to any one of claims 10 to 12, wherein, in a plan view of the mounting board, the first power amplifier and the second power amplifier do not overlap with the first switch.

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