Capacitive element and imaging element

Abstract

The present technology relates to: a capacitive element which enables capacity increase and miniaturization; and an imaging element. An upper wiring, a lower wiring, and a capacity unit in which three-dimensionally-provided capacitive elements are laminated in an even number of stages between the upper wiring and the lower wiring are provided. The capacitive elements: are formed of upper electrodes, lower electrodes, and capacitive films interposed between the upper electrodes and the lower electrodes; and are laminated such that the upper electrode of the capacitive element in the n-th stage is the lower electrode of the capacitive element in the (n+1)th stage. The present technology can be applied to, for example, a capacitive element included in an imaging element.

Description

Capacitor element, image sensor

[0001] The present technology relates to a capacitive element and an imaging element, and for example, to a capacitive element and an imaging element that can increase capacitance.

[0002] A known pixel structure of an image sensor is one that includes a storage capacitor for storing charge that overflows from a photodiode (see, for example, Patent Documents 1 and 2).

[0003] JP 2020-129795 A JP 2006-245522 A

[0004] Even when the image sensor is made smaller, it is desired to increase the capacitance.

[0005] The present technology has been made in view of such circumstances, and makes it possible to increase the capacity.

[0006] A capacitance element according to one aspect of the present technology comprises an upper layer wiring, a lower layer wiring, and a capacitance section in which capacitance elements arranged in a three-dimensional shape are stacked in an even number of layers between the upper layer wiring and the lower layer wiring, the capacitance elements being composed of an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode, and the capacitance elements are stacked so that the upper electrode of the capacitance element in the nth layer becomes the lower electrode of the capacitance element in the n+1th layer.

[0007] An imaging element according to one aspect of the present technology includes a photoelectric conversion element and a capacitance section that accumulates charge overflowing from the photoelectric conversion element, the capacitance section including upper layer wiring, lower layer wiring, and a capacitance element arranged in a three-dimensional shape, the capacitance element being composed of an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode, the capacitance elements being stacked in an even number of layers between the upper layer wiring and the lower layer wiring, and the upper electrode of the capacitance element in the nth layer becoming the lower electrode of the capacitance element in the n+1th layer.

[0008] A capacitance element according to one aspect of the present technology includes an upper layer wiring, a lower layer wiring, and a capacitance section in which an even number of three-dimensional capacitance elements are stacked between the upper layer wiring and the lower layer wiring, The capacitance elements are composed of an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode, and the upper electrode of the n-th capacitance element is stacked so as to become the lower electrode of the n+1-th capacitance element.

[0009] An imaging element according to one aspect of the present technology includes a photoelectric conversion element and a capacitance unit that accumulates charge overflowing from the photoelectric conversion element, the capacitance unit including upper layer wiring, lower layer wiring, and a capacitance element provided in a three-dimensional shape. The capacitance element is configured to include an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode. The capacitance elements are stacked in an even number of layers between the upper layer wiring and the lower layer wiring, and the upper electrode of the capacitance element in the nth layer is stacked as the lower electrode of the capacitance element in the n+1th layer.

[0010] 1 is a diagram illustrating an example configuration of an embodiment of an imaging device to which the present technology is applied. FIG. 1 is a diagram illustrating an example circuit configuration of a pixel. FIG. 2 is a diagram illustrating an example cross-sectional configuration of a pixel. FIG. 3 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 4 is a diagram illustrating an example circuit configuration of an MIM capacitance element. FIG. 5 is a diagram for explaining symmetry of electrodes. FIG. 6 is a diagram illustrating an example planar configuration of an MIM capacitance element. FIG. 7 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 8 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 9 is a diagram for explaining manufacture of an MIM capacitance element. FIG. 10 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 11 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 12 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 13 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 14 is a diagram illustrating an example cross-sectional configuration of an MIM capacitance element. FIG. 15 is a diagram illustrating an example cross-sectional configuration of a four-layer stacked MIM capacitance element. FIG. 16 is a diagram illustrating an example circuit configuration of a four-layer stacked MIM capacitance element. FIG. 17 is a diagram illustrating an example configuration of an electronic device. FIG. 18 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. FIG. 19 is a block diagram illustrating an example functional configuration of a camera head and a CCU. It is a block diagram showing an example of a schematic configuration of a vehicle control system.It is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0011] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0012] <Configuration Example of Imaging Apparatus> FIG. 1 shows a configuration example of an embodiment of an imaging apparatus to which the present technology is applied.

[0013] 1 includes a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit section around the pixel array section 3. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0014] The pixel 2 has a photodiode as a photoelectric conversion element and a plurality of pixel transistors, such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, which are configured as MOS transistors.

[0015] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the imaging device 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0016] The vertical drive circuit 4 is configured by, for example, a shift register, selects a predetermined pixel drive line 10, supplies a pulse for driving the pixels 2 to the selected pixel drive line 10, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 selects and scans each pixel 2 in the pixel array unit 3 row by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 9.

[0017] The column signal processing circuits 5 are arranged for each column of pixels 2, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 2. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) or DDS (Double Data Sampling) for removing fixed pattern noise specific to each pixel, and AD conversion.

[0018] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0019] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0020] The imaging device 1 configured as above is a CMOS image sensor called a column AD type, in which a column signal processing circuit 5 that performs CDS processing or DDS processing and AD conversion processing is arranged for each pixel column.

[0021] <Example of Pixel Circuit Configuration> A description will be given of the configuration of a unit pixel provided in the pixel array section 3. The unit pixel provided in the pixel array section 3 is configured, for example, as shown in Fig. 2. In Fig. 2, parts corresponding to those in Fig. 1 are assigned the same reference numerals, and their description will be omitted as appropriate.

[0022] Pixel 2, which is a unit pixel, has a photoelectric conversion section 51, a first transfer transistor 52, a first FD (Floating Diffusion) section 53, a second transfer transistor 54, a second FD section 55, a third transfer transistor 56, a third FD section 57, an MIM (Metal-Insulator-Metal) capacitance element 58, a reset transistor 59, an amplification transistor 60, and a selection transistor 61.

[0023] For example, a plurality of drive lines are wired for each pixel row as pixel drive lines 10 for the pixels 2. Then, a drive signal TG, a drive signal FDG, a drive signal FCG, a drive signal RST, and a drive signal SEL are supplied from the vertical drive circuit 4 to the first transfer transistor 52, the second transfer transistor 54, the third transfer transistor 56, the reset transistor 59, and the selection transistor 61, respectively, via the plurality of drive lines.

[0024] These drive signals are pulse signals that are active when high (for example, power supply voltage VDD) and inactive when low (for example, negative potential). That is, when each of the drive signals TG to SEL is at a high level, the transistor to which it is supplied is turned on, i.e., on, and when each drive signal is at a low level, the transistor to which it is supplied is turned off, i.e., off.

[0025] The photoelectric conversion unit 51 is made of, for example, a PN junction photodiode, and receives incident light, performs photoelectric conversion, and accumulates the resulting electric charge.

[0026] The first transfer transistor 52 is provided between the photoelectric conversion unit 51 and the first FD unit 53, and a drive signal TG is supplied to the gate electrode of the first transfer transistor 52. When this drive signal TG becomes high level, the first transfer transistor 52 is turned on, and the charge stored in the photoelectric conversion unit 51 is transferred to the first FD unit 53 via the first transfer transistor 52.

[0027] The first FD section 53, the second FD section 55, and the third FD section 57 are each a floating diffusion region called a floating diffusion, and function as a storage section that temporarily stores transferred charges and charges that overflow from the photoelectric conversion section 51. The third FD section 57 is connected to an MIM capacitance element 58, and is configured so that the MIM capacitance element 58 functions as the third FD section 57. Note that, although the explanation will be continued here using an example in which the MIM capacitance element 58 is connected to the third FD section 57, the third FD section 57 may also be connected to the first FD section 53 or the second FD section 55, or to any two of the first FD section 53, the second FD section 55, and the third FD section 57, or to all of them.

[0028] The second transfer transistor 54 is provided between the first FD section 53 and the second FD section 55, and a drive signal FDG is supplied to the gate electrode of the second transfer transistor 54. When this drive signal FDG becomes high level, the second transfer transistor 54 is turned on, and the charge from the first FD section 53 is transferred to the second FD section 55 via the second transfer transistor 54.

[0029] By turning on the second transfer transistor 54, the region where charges are accumulated becomes the combined region of the first FD section 53 and the second FD section 55, and it is possible to switch the conversion efficiency when converting the charges generated in the photoelectric conversion section into voltage. The second transfer transistor 54 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0030] The third transfer transistor 56 is provided between the second FD section 55 and the third FD section 57, and a drive signal FCG is supplied to the gate electrode of the third transfer transistor 56. When this drive signal FCG becomes high level, the third transfer transistor 56 is turned on, and the charge from the second FD section 55 is transferred to the third FD section 57 via the third transfer transistor 56.

[0031] By turning on the third transfer transistor 56, the region in which charges are accumulated becomes the combined region of the first FD section 53, the second FD section 55, and the third FD section 57, and it is possible to switch the conversion efficiency when converting the charges generated in the photoelectric conversion section into voltage. The third transfer transistor 56 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0032] The third FD section 57 is connected to an MIM capacitance element 58. The third FD section 57 is connected to the MIM capacitance element 58, which can achieve high capacitance without sacrificing the area of ​​the Si (silicon) substrate surface on which pixel transistors are arranged, and has a larger capacitance than the first FD section 53 and the second FD section 55.

[0033] The reset transistor 59 is connected between the power supply VDD and the third FD section 57, and a drive signal RST is supplied to the gate electrode of the reset transistor 59. When the drive signal RST is set to a high level, the reset transistor 59 is turned on and the potential of the third FD section 57 is reset to the level of the power supply voltage VDD.

[0034] The amplifying transistor 60 has a gate electrode connected to the first FD section 53 and a drain connected to a power supply VDD, and serves as an input section of a readout circuit, a so-called source follower circuit, that reads out a signal corresponding to the charge held in the first FD section 53. That is, the amplifying transistor 60 has a source connected to the vertical signal line 9 via the selection transistor 61, and thereby forms a source follower circuit together with a constant current source (not shown) connected to one end of the vertical signal line 9.

[0035] The selection transistor 61 is connected between the source of the amplification transistor 60 and the vertical signal line 9, and a drive signal SEL is supplied to the gate electrode of the selection transistor 61. When the drive signal SEL is set to a high level, the selection transistor 61 is turned on and the pixel 2 is placed in a selected state. As a result, the pixel signal output from the amplification transistor 60 is output to the vertical signal line 9 via the selection transistor 61.

[0036] In the following, when each drive signal is in an active state, i.e., at a high level, it is also referred to as the drive signal being on, and when each drive signal is in an inactive state, i.e., at a low level, it is also referred to as the drive signal being off.

[0037] The pixel 2 shown in Figure 2 includes a first FD section 53, a second FD section 55, and a third FD section 57 (MIM capacitance element 58), and these FD sections are connected in series, so that the conversion efficiency when converting the charge generated in the photoelectric conversion section into a voltage can be switched between three levels.

[0038] The high conversion efficiency (HCG) is composed of the first FD section 53. The medium conversion efficiency (MCG) is composed of (the first FD section 53 + the second FD section 55). The low conversion efficiency (LCG) is composed of (the first FD section 53 + the second FD section 55 + the third FD section 57 (= the MIM capacitance element 58)).

[0039] When the first transfer transistor 52 is turned on, the charge accumulated in the photoelectric conversion unit 51 is received by the first FD unit 53 (high conversion efficiency) or (first FD unit 53 + second FD unit 55) (medium conversion efficiency) and output.

[0040] At times of high illuminance, the charge accumulated in the photoelectric conversion section 51 overflows beyond the first transfer transistor 52 to the first FD section 53 side, and is accumulated in the first FD section 53, the second FD section 55, and the third FD section 57 (MIM capacitance element 58).

[0041] When the received light amount is a small signal, a high conversion efficiency is achieved in which charge is accumulated in the first FD section 53, and when the received light amount is a large signal, a low conversion efficiency is achieved in which charge is accumulated in (first FD section 53 + second FD section 55 + third FD section 57 (= MIM capacitance element 58)). Here, an intermediate conversion efficiency is further provided between the high conversion efficiency and the low conversion efficiency, and a conversion efficiency is provided in which charge is accumulated in (first FD section 53 + second FD section 55).

[0042] The electric charges that have overflowed the photoelectric conversion unit 51 and accumulated in the first FD unit 53, the second FD unit 55, and the third FD unit 57 are received by (the first FD unit 53 + the second FD unit 55 + the third FD unit 57 (= MIM capacitance element 58)) together with the electric charges accumulated in the photoelectric conversion unit 51 and are output.

[0043] The readouts of the high conversion efficiency, medium conversion efficiency, and low conversion efficiency signals are each AD converted separately, and which readout signal to use is determined based on the amount of each readout signal. At the junction between the high conversion efficiency signal and the medium conversion efficiency signal, or the junction between the medium conversion efficiency signal and the low conversion efficiency signal, the two readout signals may be blended and used. By using the blended signal, image quality degradation at the junction is suppressed.

[0044] 3 is a diagram showing an example of the cross-sectional configuration of a pixel 2. The N-type semiconductor region 105 constituting the photoelectric conversion unit 51 of the pixel 2 receives incident light that is incident from the back surface (top surface in the figure) of the semiconductor substrate 100. The N-type semiconductor region 105 is structured to be embedded inside the semiconductor substrate 100, and the N-type semiconductor region 105 is hardly present in the surface portion of the substrate.

[0045] A planarization film 103, a CF (color filter) 102, and a microlens 101 are provided above the N-type semiconductor region 105 (photoelectric conversion section 51), and in the photoelectric conversion section 51, incident light that passes through each section in sequence is received on the light-receiving surface and photoelectric conversion is performed.

[0046] For example, in the photoelectric conversion unit 51, the N-type semiconductor region 105 is formed as a charge accumulation region that accumulates charges (electrons). In the photoelectric conversion unit 51, the N-type semiconductor region 105 is provided inside the P-type semiconductor region 106 of the semiconductor substrate 100.

[0047] A pixel separating section 109 that electrically separates the plurality of pixels 2 is provided inside the semiconductor substrate 100, and a photoelectric conversion section 51 is provided in an area partitioned by this pixel separating section 109. The pixel separating section 109 is formed, for example, in a lattice shape so as to be interposed between the plurality of pixels 2, and the photoelectric conversion section 51 is formed within the area partitioned by this pixel separating section 109.

[0048] The wiring layer 120 is provided on the surface (lower surface) of the semiconductor substrate 100 opposite to the back surface (upper surface) on which the light-shielding film 104, CF 102, microlens 101, and other components are provided.

[0049] The wiring layer 120 includes wiring 122 and an interlayer insulating layer 123, and the wiring 122 is formed so as to be electrically connected to each element within the interlayer insulating layer 123. The wiring layer 120 is a so-called multilayer wiring layer, and is formed by alternately stacking interlayer insulating films that constitute the interlayer insulating layer 123 and wiring 122 multiple times. Here, the wiring 122 includes wiring to transistors for reading out charges from the photoelectric conversion unit 51, such as the first transfer transistor 52, and wiring such as VSL9, which are stacked via the interlayer insulating layer 123.

[0050] A support substrate (not shown) may be provided on the surface of the wiring layer 120 opposite to the side on which the photoelectric conversion unit 51 is provided. For example, a substrate made of a silicon semiconductor and having a thickness of several hundred μm is provided as the support substrate.

[0051] The light-shielding film 104 is provided on the back surface (top surface in the figure) of the semiconductor substrate 100. The light-shielding film 104 is configured to block a portion of incident light traveling from above the semiconductor substrate 100 toward below the semiconductor substrate 100. The light-shielding film 104 is formed of a light-shielding material that blocks light. For example, the light-shielding film 104 is formed by sequentially stacking a titanium (Ti) film and a tungsten (W) film. Alternatively, the light-shielding film 104 can be formed by sequentially stacking a titanium nitride (TiN) film and a tungsten (W) film. The light-shielding film 104 may also be coated with tungsten nitride (WN) or the like.

[0052] The light-shielding film 104 is covered with a planarizing film 103. The planarizing film 103 is made of an insulating material that transmits light.

[0053] A fixed charge film 108 and a P-type semiconductor region 107 are formed on the side surface of the pixel separating portion 109 (FFTI 70).

[0054] The fixed charge film 108 is formed using a high dielectric constant material having a negative fixed charge so that a positive charge (hole) accumulation region is formed at the interface with the semiconductor substrate 100, thereby suppressing the generation of dark current. Since the fixed charge film 108 is formed to have a negative fixed charge, an electric field is applied to the interface with the semiconductor substrate 100 by the negative fixed charge, and a positive charge (hole) accumulation region is formed.

[0055] The fixed charge film 108 can be formed of, for example, a hafnium oxide film (HfO2 film). The fixed charge film 108 can also be formed so as to contain at least one of oxides of other elements, such as hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, and lanthanoid elements.

[0056] A P-type semiconductor region 107 is conformally formed as a solid-phase diffusion layer on the sidewall of the FFTI 70. A PN junction is formed between the P-type semiconductor region 107 and the N-type semiconductor region 105, and photoelectrically converted charges are accumulated there.

[0057] Note that, here, an example will be described in which a PN junction is formed between the N-type semiconductor region 105 contained in the semiconductor substrate 100 and the P-type semiconductor region 107 formed therearound to form a photodiode, but the N-type and P-type may be reversed. If the N-type and P-type are reversed, pixel 2 can be configured by replacing N-type with P-type and P-type with N-type in the above and following descriptions.

[0058] Here, an example will be described in which a P-type semiconductor region 107 and a fixed charge film 108 are provided on the side surface of the FFTI 70, but it is also possible to use a configuration in which either the P-type semiconductor region 107 or the fixed charge film 108 is provided, or a configuration in which neither the P-type semiconductor region 107 nor the fixed charge film 108 is provided.

[0059] A structure in which SiO2 or the like is embedded inside the FFTI 70 may be used. By embedding SiO2 or the like inside the FFTI 70, a structure in which adjacent pixels 2 are more reliably isolated can be achieved.

[0060] By providing such an FFTI 70, the pixels 2 are electrically isolated from each other, and it is possible to prevent charges leaking from the photoelectric conversion unit 51 (PD: Photo Diode) from leaking into adjacent pixels 2. Therefore, it is possible to tighten the overflow barrier on the side of the first transfer transistor 52, and it is possible to increase the Qs (amount of saturated charge) of the photoelectric conversion unit 51.

[0061] The local interconnect 121 is formed of polysilicon or an advanced contact (MIS contact). The advanced contact is a contact that uses a high-dielectric-constant insulating film. When the local interconnect 121 is an advanced contact made of a high-dielectric-constant insulating film, in the example shown in FIG. 3 , it is a metal-based insulating film inserted between the first FD section 53 and the gate electrode of the amplifying transistor 60. For example, the high-dielectric-constant insulating film is formed of a metal oxide with a high dielectric constant, such as titanium dioxide (TiO2), so as to be a thin film with a thickness of about 2.0 nm to 3.0 nm.

[0062] When the local wiring 121 uses an advanced contact, the N-type impurity concentration of the first FD section 53 can be low, thereby reducing contact resistance. By setting the N-type impurity concentration of the first FD section 53 low, the electric field strength of the PN junction with the semiconductor substrate 100 (the P-type semiconductor region 106) is weakened, thereby suppressing the generation of dark current. This prevents dark current from being mixed into the charge signal of the pixel 2, prevents fixed pattern noise (FPN) caused by variations in FD dark current leakage, and improves the S / N ratio at the junction of multiple conversion efficiencies associated with FPN, thereby improving image quality.

[0063] Although an example has been shown here in which the first FD section 53 and the amplifying transistor 60 are connected by the local wiring 121, a configuration in which the local wiring 121 (advanced contact) is used in addition to the contact of the first FD section 53 may also be used. In other words, an advanced contact may also be used as the contact of the second FD section 55 or the third FD section 57.

[0064] The wiring layer 120 of the pixel 2 shown in Fig. 3 is formed with six layers of wiring 122. If the layers are arranged in order from the top (semiconductor substrate 100 side) in the figure as a first layer, a second layer, a third layer, a fourth layer, and a fifth layer, an MIM capacitance element 58 is formed three-dimensionally between the fifth-layer wiring 122 and the sixth-layer wiring 122 (not shown). As will be described later with reference to Fig. 4 and subsequent figures, the MIM capacitance element 58 is a three-dimensionally formed capacitor having a trench (hole) and a capacitance film formed on its sidewall, and the detailed configuration and description will be made with reference to Fig. 4 and subsequent figures, so it is shown in a simplified form in Fig. 3.

[0065] One of the electrodes of the MIM capacitance element 58 is connected to the fifth-layer wiring 122, and the other is connected to the sixth-layer wiring 122. The fifth-layer wiring 122 is electrically connected to the diffusion layer of the third FD section 57, and the MIM capacitance element 58 is configured to be connected to the third FD section 57.

[0066] <Configuration of MIM Capacitor Element> Fig. 4 is a diagram showing an example of the cross-sectional configuration of the MIM capacitor element 58. Here, an example is described in which the MIM capacitor element 58 is included in an imaging element, but when a capacitative element is required in an element or device other than an imaging element, the MIM capacitative element 58 of this embodiment can also be applied as that capacitative element (memory).

[0067] 4 shows an example of the cross-sectional configuration of an MIM capacitance element 58 that is called a trench type (trench structure), etc. As will be described later, the present technology can also be applied to an MIM capacitance element 58 that is called a concave type (concave structure) or an MIM capacitance element 58 that is called a cylinder type (cylinder structure).

[0068] 4, the MIM capacitance element 58 is formed in the wiring layer 120. The MIM capacitance element 58 has a three-dimensional structure in the X, Y, and Z directions. The MIM capacitance element 58 shown in FIG. 4 has a two-tier structure and is composed of a lower MIM capacitance element 58-1 and an upper MIM capacitance element 58-2.

[0069] In the figure, the MIM capacitance elements 58 are designated as the first row (nth row) and the second row (n+1th row) from the bottom, with the MIM capacitance element 58 in the first row being the lower MIM capacitance element 58-1 and the MIM capacitance element 58 in the second row being the upper MIM capacitance element 58-2. When the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are collectively described or when there is no need to distinguish them individually, they are referred to as MIM capacitance elements 58.

[0070] As will be described later, the number of stages of the MIM capacitance elements 58 is not limited to two, and any even number of stages, such as four or six, is within the scope of application of the present technology.

[0071] The MIM capacitance element 58 is provided between a lower layer wiring 201 and an upper layer wiring 202. The upper layer wiring 202 is provided with upper layer wiring 202-1 and upper layer wiring 202-2. The lower layer wiring 201 and the upper layer wirings 202-1 and 202-2 correspond to the wiring 122 in the wiring layer 120. The lower layer wiring 201 and the upper layer wirings 202-1 and 202-2 can be formed of Cu (copper).

[0072] The portion of the MIM capacitance element 58 formed in the vertical direction in FIG. 4 will be referred to as a trench or a hole as appropriate.

[0073] The MIM capacitance element 58 shown in FIG. 4 has a capacitance portion between a lower wiring 201 and an upper wiring 202, and the capacitance portion has a configuration in which a lower MIM capacitance element 58-1 and an upper MIM capacitance element 58-2, which are provided in a three-dimensional shape, are stacked vertically.

[0074] One MIM capacitance element 58 has a stacked structure of a lower electrode 221, an upper electrode 223, and a capacitance film 222 sandwiched between the lower electrode 221 and the upper electrode 223. The lower MIM capacitance element 58-1 has a stacked structure of a lower electrode 221-1, a capacitance film 222-1, and an upper electrode 223-1. The upper MIM capacitance element 58-2 has a stacked structure of a lower electrode 221-2, a capacitance film 222-2, and an upper electrode 223-2.

[0075] In the figure, in region a enclosed by a dotted square, the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are directly connected. "Directly connected" means that they are connected without using connecting members called vias or contacts. In the example shown in FIG. 4, "directly connected" also includes the connection between the upper electrode 223-1 of the lower MIM capacitance element 58-1 and the lower electrode 221-2 of the upper MIM capacitance element 58-2.

[0076] The electrode formed in region a (electrode formed in the horizontal direction) functions as the upper electrode 223-1 of the lower MIM capacitance element 58-1 and also functions as the lower electrode 221-2 of the upper MIM capacitance element 58-2. The stacked lower MIM capacitance element 58-1 and upper MIM capacitance element 58-2 are configured in a state in which the lower electrode 221-2 and the upper electrode 223-1 are stacked (shared, connected) in the stacked portion. Hereinafter, the electrode formed in region a and shared by the stacked lower MIM capacitance element 58-1 and upper MIM capacitance element 58-2 will be referred to as shared electrode a as appropriate.

[0077] The upper electrode 223 is composed of a single layer film made of a material such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN), or a laminated film made of these materials. The lower electrode 221, like the upper electrode 223, is composed of a single layer film or a laminated film made of a material such as titanium nitride (TiN). The capacitive film 222 is composed of a single layer film made of a high-dielectric-constant material such as aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), or niobium oxide (NbO), or a laminated film made of these materials.

[0078] In addition, an insulating film may be formed on a portion of the sidewall of each of the lower layer wiring 201, the upper layer wiring 202, the lower electrode 221, the upper electrode 223, and the via 231, and the insulating film may be made of a film using a material such as silicon nitride (SiN), silicon oxide (SiO), or silicon carbonitride (SiCN).

[0079] A lower electrode 221-1 of the lower MIM capacitance element 58-1 is connected to a lower layer wiring 201. The lower layer wiring 201 is connected to an upper layer wiring 202-1 through a via 231-1. The upper layer wiring 202-1 is also connected to a via 231-2, which is connected to an upper electrode 223-2 of the upper MIM capacitance element 58-2.

[0080] The lower layer wiring 201 is connected to the lower electrode 221-1 of the lower MIM capacitance element 58-1 in the first stage (nth stage, odd-numbered stage) and is also connected to the upper layer wiring 202-1. The upper layer wiring 202-1 is also connected to the upper electrode 223-2 of the upper MIM capacitance element 58-2 in the second stage (n+1th stage, even-numbered stage).

[0081] A via 231-3 is connected to the upper layer wiring 202-2, and is connected to a shared electrode a shared by the upper electrode 223-1 of the lower MIM capacitance element 58-1 and the lower electrode 221-2 of the upper MIM capacitance element 58-2.

[0082] The upper layer wiring 202-2 is connected to the upper electrode 223-1 of the lower MIM capacitance element 58-1 in the first stage (nth stage, odd-numbered stage). In other words, the upper layer wiring 202-2 is connected to the lower electrode 221-2 of the upper MIM capacitance element 58-2 in the second stage (n+1th stage, even-numbered stage).

[0083] Fig. 5 is a circuit diagram of the MIM capacitance element 58 having the cross-sectional configuration shown in Fig. 4. The upper electrode 223-2 of the upper MIM capacitance element 58-2 is connected to the lower layer wiring 201 via the upper layer wiring 202-1, and is further connected to the lower electrode 221-1 of the lower MIM capacitance element 58-1 via the lower layer wiring 201. Therefore, the upper electrode 223-2 of the upper MIM capacitance element 58-2 and the lower electrode 221-1 of the lower MIM capacitance element 58-1 are connected to each other.

[0084] An upper layer wiring 202-2 is connected to the wiring that connects the upper electrode 223-1 of the lower MIM capacitance element 58-1 and the lower electrode 221-2 of the upper MIM capacitance element 58-2, that is, the shared electrode a in the region a.

[0085] The lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are connected in parallel in terms of the circuit. By configuring the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 in parallel, it is possible to increase the capacitance. Furthermore, as shown in Figure 4, in the region a where the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are connected, they are not connected via a via or the like. In other words, the connection portion also functions as part of the capacitance element, which makes it possible to achieve miniaturization at least in the vertical direction (the up-down direction in the figure).

[0086] By configuring the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 with the same material and size, it is possible to match the characteristics of the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2. This will be described with reference to FIG.

[0087] An MIM capacitance element 58 having the cross-sectional configuration example shown in Fig. 4 and the circuit configuration shown in Fig. 5 is shown in Fig. 6. A lower MIM capacitance element 58-1 and an upper MIM capacitance element 58-2 are provided in parallel between terminals X and Y. Terminal X represents a terminal connected to lower layer wiring 201 and upper layer wiring 202-1, and terminal Y represents a terminal connected to upper layer wiring 202-2.

[0088] When a current flows from terminal X to terminal Y, the current flows in the order of lower electrode 221-1, capacitance film 222-1, and upper electrode 223-1 on the lower MIM capacitance element 58-1 side, and the current flows in the order of upper electrode 223-2, capacitance film 222-2, and lower electrode 221-2 on the upper MIM capacitance element 58-2 side. Since the electrode structure of the lower MIM capacitance element 58-1 and the electrode structure of the upper MIM capacitance element 58-2 are symmetrical with respect to terminal X and terminal Y, a structure can be achieved in which the asymmetry of the voltage characteristics is reduced, and a configuration can be achieved in which the dependency of the capacitor characteristics is not impaired.

[0089] The lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 can be made of different materials or can be made to have different sizes. For example, the materials used to make the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 can be adjusted, or the sizes, mainly the height and width of the portions corresponding to the trenches (capacitors formed vertically in the drawing), can be adjusted so that the combined capacitance of the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 becomes a desired capacitance.

[0090] 7 and 8 are diagrams showing the planar configuration of the MIM capacitance element 58 having the cross-sectional configuration shown in Fig. 4. Fig. 7 shows an example of the planar configuration of the MIM capacitance element 58 when the region where the upper MIM capacitance element 58-2 is formed is viewed in plan, and Fig. 8 shows an example of the planar configuration of the MIM capacitance element 58 when the region where the lower MIM capacitance element 58-2 is formed is viewed in plan.

[0091] 7, a rectangular lower electrode 221-2 (upper electrode 223-2) is formed in the center of the figure, and three trenches are formed in the region where the electrode is formed. As shown in the cross-sectional view (FIG. 4), the lower electrode 221-2, the capacitance film 222-2, and the upper electrode 223-2 are stacked on the bottom surface of the trench. FIG. 7 shows the capacitance film 222-2 formed on the bottom surface of the trench, which is formed in a rectangular shape in a plan view.

[0092] The trench-type MIM capacitance element 58 has a rectangular shape in plan view, and has a configuration in which a lower electrode 221, a capacitance film 222, and an upper electrode 223 are stacked in a trench formed to a predetermined depth in a cross-sectional view.

[0093] The upper layer wiring 202-1 is formed in a shape and size such that a portion of the upper layer wiring 202-1 overlaps with the lower electrode 221-2 (upper electrode 223-2) in a plan view. A via 231-2 is formed in a portion of the overlapping region, so that the upper layer wiring 202-1 and the upper electrode 223-2 are connected. A via 231-1 is formed in a portion of the non-overlapping region, so that the via 231-1 is connected to the lower layer wiring 201 (not shown in FIG. 7).

[0094] The upper layer wiring 202-2 is formed in a shape and size such that there is no overlapping area with the lower electrode 221-2 (upper electrode 223-2) in a plan view. While an example in which there is no overlapping area is shown in Fig. 7, it may be formed so that there is an overlapping area. A via 231-3 is formed in part of the area in which the upper layer wiring 202-2 is formed, and is connected to a shared electrode a (the upper electrode 223-1 of the lower MIM capacitance element 58-1, and the electrode that becomes the lower electrode 221-2 of the upper MIM capacitance element 58-2), not shown in Fig. 7.

[0095] 8, the configuration of the lower MIM capacitance element 58-1 is the same as that of the upper MIM capacitance element 58-2 shown in FIG. 7, in that a rectangular lower electrode 221-1 (upper electrode 223-1) is formed in the center of the figure, and three trenches are formed in the region in which the electrode is formed, as shown in FIG. 8. As shown in the cross-sectional view (FIG. 4), the lower electrode 221-1, capacitance film 222-1, and upper electrode 223-1 are stacked on the bottom surface of the trench in cross section. FIG. 8 shows the capacitance film 222-1 formed on the bottom surface of the trench, which is formed in a rectangular shape in plan view.

[0096] The via 231-1 connected to the upper layer wiring 202-1 is formed outside the area where the lower MIM capacitance element 58-1 is formed, and is configured to be connected to the upper layer wiring 202-1 and the lower layer wiring 201, which are not shown in Figure 8.

[0097] The shared electrode a, which is the upper electrode 223-1 of the lower MIM capacitance element 58-1 and the lower electrode 221-2 of the upper MIM capacitance element 58-2, is provided in a shape in which a part of the upper electrode 223-1 (lower electrode 221-2) protrudes in plan view. A via 231-3 is connected to the protruding region.

[0098] <Concave-type MIM capacitance element> Fig. 9 shows a cross-sectional configuration example of a concave-type (concave structure) MIM capacitance element 58, and Figs. 10 and 11 are diagrams showing a planar configuration example of the concave-type MIM capacitance element 58. The same parts as those in the trench-type MIM capacitance element 58 shown in Figs. 4, 7 and 8 are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0099] The concave-type MIM capacitance element 58 has the same basic configuration as the trench-type MIM capacitance element 58, but differs in that the portion formed by the trench is formed by a hole (cylindrical).

[0100] 9, in the case of the concave-type MIM capacitance element 58, the horizontally formed electrode, for example, the horizontal electrode of the shared electrode a formed in region a, has a laminated structure of a capacitance film 222-1 and an upper electrode 223-2 (lower electrode 221-2). For comparison, referring again to the trench-type MIM capacitance element 58 shown in FIG. 4, the horizontally formed electrode of the shared electrode a formed in region a of the trench-type MIM capacitance element 58 has a laminated structure of a lower electrode 221-1, a capacitance film 222-1, and an upper electrode 223-2 (lower electrode 221-2).

[0101] Note that, depending on the manufacturing process, the trench-type MIM capacitance element 58 may also have a configuration in which the horizontal electrode of the shared electrode a formed in the region a is stacked with a capacitance film 222-1 and an upper electrode 223-1 (lower electrode 221-2). Similarly, depending on the manufacturing process, the concave-type MIM capacitance element 58 may also have a configuration in which the horizontal electrode of the shared electrode a formed in the region a is stacked with a lower electrode 221-1, a capacitance film 222-1, and an upper electrode 223-1 (lower electrode 221-2).

[0102] FIG. 10 is a diagram showing an example of the planar configuration of the MIM capacitance element 58 when the region where the upper MIM capacitance element 58-2 of the concave-type MIM capacitance element 58 is formed is viewed in a plane, and FIG. 11 shows an example of the planar configuration of the MIM capacitance element 58 when the region where the lower MIM capacitance element 58-2 is formed is viewed in a plane.

[0103] When comparing the upper MIM capacitance element 58-2 of the concave-type MIM capacitance element 58 shown in Fig. 10 with the upper MIM capacitance element 58-2 of the trench-type MIM capacitance element 58 shown in Fig. 7, they are similar in other respects, except that the capacitance portion formed by a trench is now formed by a hole. Also, when comparing the lower MIM capacitance element 58-1 of the concave-type MIM capacitance element 58 shown in Fig. 11 with the lower MIM capacitance element 58-1 of the trench-type MIM capacitance element 58 shown in Fig. 8, they are similar in other respects, except that the capacitance portion formed by a trench is now formed by a hole.

[0104] In the concave MIM capacitance element 58, each hole is formed in a square shape in a plan view, and a plurality of holes are arranged in a straight line. The holes are arranged, for example, at equal intervals. Each hole may be square as shown in FIGS. 10 and 11, or may be circular. The holes are formed in a rectangular parallelepiped or cylindrical shape.

[0105] The concave MIM capacitance element 58 is a square (circular) hole in a plan view, and has a configuration in which a lower electrode 221, a capacitance film 222, and an upper electrode 223 are stacked within a hole formed to a predetermined depth in a cross-sectional view.

[0106] The circuit diagram of the concave-type MIM capacitance element 58 is as shown in Fig. 5. Therefore, in the concave-type MIM capacitance element 58, as in the trench-type MIM capacitance element 58, the MIM capacitance elements 58 can be connected in parallel to form a capacitance, thereby increasing the capacitance of the MIM capacitance element 58. Furthermore, it is possible to increase the capacitance without impairing the voltage dependency of the capacitor characteristics.

[0107] <Cylinder-Type MIM Capacitor> Fig. 12 is a diagram showing an example of the cross-sectional configuration of a cylinder-type (cylinder structure) MIM capacitive element 58. The same parts as those of the trench-type MIM capacitive element 58 shown in Fig. 4 or the concave-type MIM capacitive element 58 shown in Fig. 9 are denoted by the same reference numerals, and their description will be omitted where appropriate.

[0108] The cylinder-type MIM capacitance element 58 has the same basic configuration as the hole-type MIM capacitance element 58 shown in Figures 9 to 11, but differs in the shapes of the lower electrode 221', capacitance film 222', and upper electrode 223' formed within one hole.

[0109] 12, the MIM capacitance element 58 has a stacked structure of a lower MIM capacitance element 58'-1 and an upper MIM capacitance element 58'-2. The lower MIM capacitance element 58'-1 has a stacked structure of a lower electrode 221'-1, an upper electrode 223'-1, and a capacitance film 222'-1 sandwiched between the lower electrode 221'-1 and the upper electrode 223'-1. Similarly, the upper MIM capacitance element 58'-2 has a stacked structure of a lower electrode 221'-2, an upper electrode 223'-2, and a capacitance film 222'-2 sandwiched between the lower electrode 221'-2 and the upper electrode 223'-2.

[0110] As with the trench-type or concave-type MIM capacitance element 58, the upper electrode 223'-1 of the lower MIM capacitance element 58'-1 and the lower electrode 221'-2 of the upper MIM capacitance element 58'-2 are of a shared structure.

[0111] The cylindrical MIM capacitance element 58, like the concave-type MIM capacitance element 58, can have a structure in plan view as described with reference to Figures 10 and 11, and can be configured with a plurality of holes formed therein. Note that a trench type can also be applied, and a configuration in which a plurality of trenches are formed can also be used.

[0112] In the cylindrical MIM capacitance element 58, a capacitance film 222' is formed in an uneven shape within one hole, and multiple combinations of multiple lower electrodes 221', capacitance films 222', and upper electrodes 223' are formed. For example, referring to one hole shown on the right side of the figure of the lower MIM capacitance element 58'-1, looking at the layers in order from the right side of the hole, the layers are arranged in the following order: lower electrode 221'-1, capacitance film 222'-1, upper electrode 223'-1, capacitance film 222'-1, lower electrode 221'-1, capacitance film 222'-1, and upper electrode 223'-1.

[0113] In the cylindrical MIM capacitance element 58, a capacitance film 222' is formed in a pleated shape in one hole. When the capacitance film 222' in one hole is divided into a portion formed in a convex shape and a portion formed in a concave shape, a lower electrode 221'-1 is provided in the capacitance film 222'-1 formed in a convex shape, and an upper electrode 223'-1 is provided in the capacitance film 222'-1 formed in a concave shape.

[0114] The circuit diagram of the cylinder-type MIM capacitance element 58 is as shown in FIG. 5 , so like the trench-type MIM capacitance element 58, the MIM capacitance elements 58 can be connected in parallel to form a capacitance, thereby increasing the capacitance of the MIM capacitance element 58. It is also possible to increase the capacitance without impairing the voltage dependency of the capacitor characteristics. Furthermore, since the capacitance film 222′ is formed in an uneven shape within one hole, the capacitance within one hole can be increased, thereby further increasing the capacitance of the MIM capacitance element 58.

[0115] <Manufacturing of MIM Capacitance Element> The manufacture of the MIM capacitance element 58 will be described with reference to Fig. 13. Here, the manufacture of the MIM capacitance element 58 (Fig. 9) having a concave structure will be described as an example, but whether it is a trench-type MIM capacitance element 58 or a cylindrical-type MIM capacitance element 58, the manufacturing method described below can basically be applied to manufacture the element.

[0116] In step S11, a lower wiring 201 is formed in an interlayer insulating layer 123 that will become part of the wiring layer 120. A layer that will become the interlayer insulating layer 123 is further deposited on the interlayer insulating layer 123 that includes the lower wiring 201. A resist pattern that opens an area where the lower MIM capacitance element 58-1 is to be formed is formed on the deposited interlayer insulating layer 123. A region (referred to as a recess 252) that will become a hole for the lower MIM capacitance element 58-1 is formed by dry etching. The recess 252 is formed by etching the interlayer insulating layer 123 down to the top surface of the lower wiring 201.

[0117] In step S12, a lower electrode 221-1 of the lower MIM capacitance element 58-1 is formed on the bottom and side surfaces of the recess 252. A capacitance film 222-1 of the lower MIM capacitance element 58-1 is formed on the lower electrode 221-1 formed on the bottom and side surfaces of the recess 252 and on the interlayer insulating layer 123. Furthermore, an upper electrode 223-1 of the lower MIM capacitance element 58-1 fills the recess 252 and is also formed on the capacitance film 222-1 formed on the interlayer insulating layer 123.

[0118] In step S13, the electrodes are processed by removing, for example, by polishing, a portion of the capacitance film 222-1 and the upper electrode 223-1 formed on the interlayer insulating layer 123. Through the steps up to this point, the lower MIM capacitance element 58-1 is formed.

[0119] In step S14, an interlayer insulating layer 123 is formed on the surface to a predetermined thickness. A resist pattern having an opening corresponding to the region where the hole of the upper MIM capacitance element 58-2 is to be formed is formed on the formed interlayer insulating layer 123. A region (referred to as a recess 254) that will become the hole of the upper MIM capacitance element 58-2 is formed by dry etching. The recess 254 is formed by etching the interlayer insulating layer 123 down to the upper surface (interior) of the upper electrode 223-1 of the lower MIM capacitance element 58-1.

[0120] In step S15, the lower electrode 221-2 of the upper MIM capacitance element 58-2 is formed on the bottom and side surfaces of the recess 254. The bottom surface of the recess 254 forms the upper electrode 223-1 of the lower MIM capacitance element 58-1. In step S15, the upper electrode 223-1 of the lower MIM capacitance element 58-1 and the lower electrode 221-2 of the upper MIM capacitance element 58-2 are connected.

[0121] The capacitive film 222-2 of the upper MIM capacitive element 58-2 is deposited on the lower electrode 221-2 deposited on the bottom and side surfaces of the recess 254, and on the interlayer insulating layer 123. Furthermore, the upper electrode 223-2 of the upper MIM capacitive element 58-2 fills the recess 254 and is deposited also on the capacitive film 222-2 deposited on the interlayer insulating layer 123.

[0122] In step S16, the electrodes are processed by removing, for example, by polishing, a portion of the capacitance film 222-2 and the upper electrode 223-2 formed on the interlayer insulating layer 123. In this step, the upper MIM capacitance element 58-2 is formed.

[0123] In step S17, an interlayer insulating layer 123 is formed on the surface to a predetermined thickness. A resist pattern having openings corresponding to the regions where vias 231-1 to 231-3 are to be formed is formed on the formed interlayer insulating layer 123. The regions that will become vias 231 are formed by dry etching.

[0124] The region that becomes the via 231-1 is formed by etching the interlayer insulating layer 123 down to the upper surface of the lower interconnect 201. The region that becomes the via 231-2 is formed by etching the interlayer insulating layer 123 down to the upper surface of the upper electrode 223-1 of the upper MIM capacitance element 58-2. The region that becomes the via 231-3 is formed by etching the interlayer insulating layer 123 down to the upper surface of the shared electrode a that is shared by the lower electrode 221-2 of the upper MIM capacitance element 58-2 and the upper electrode 223-1 of the lower MIM capacitance element 58-1.

[0125] Although the depths of vias 231-1, 231-2, and 231-3 are different, a block layer is formed on the upper surface of the lower wiring 201, the upper surface of the upper electrode 223-1, and the upper surface of the shared electrode a, and even for vias 231 of different depths, processing (etching) can be stopped at the block layer once, and then the block layer can be penetrated all at once.Therefore, vias 231-1 to 231-3 of different depths can be formed all at once in the same process, rather than being formed in separate processes.

[0126] Once the vias 231-1 to 231-3 are formed, a conductive material is filled into the via 231. Thereafter, the upper layer wiring 202-1 and the upper layer wiring 202-2 are formed, thereby manufacturing the MIM capacitance element 58 as shown in FIG.

[0127] The lower MIM capacitance element 58-1 is formed in steps S11 to S13, and the upper MIM capacitance element 58-2 is formed in steps S14 to S16. When the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are formed of the same material, steps S11 to S13 and steps S14 to S16 can basically be performed by repeating the same process using the same material. In this case, as described above, the electrode structure of the lower MIM capacitance element 58-1 and the electrode structure of the upper MIM capacitance element 58-2 are symmetrical, so that a structure with reduced asymmetry in voltage characteristics can be achieved, and a configuration can be achieved that does not impair the dependency of the capacitor characteristics.

[0128] When the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are formed of different materials, the materials used in steps S11 to S13 and the materials used in steps S14 to S16 are considered to be steps using different materials. Also, when the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are formed in different shapes, for example, with different hole sizes or different hole depths, steps S11 to S13 and steps S14 to S16 are considered to be steps including different processes.

[0129] When the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are constructed using different materials or with different sizes, for example, a process can be included in which the materials constituting the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 are adjusted, or the sizes, mainly the width and height of the portions corresponding to the holes, are adjusted so that the combined capacitance of the lower MIM capacitance element 58-1 and the upper MIM capacitance element 58-2 becomes the desired capacitance.

[0130] <Other Configurations of MIM Capacitor Element> Fig. 14 is a diagram showing another cross-sectional configuration example of an MIM capacitive element 58 to which the present technology is applied, and Figs. 15 and 16 are diagrams showing planar configuration examples. Although the planar configuration examples shown in Figs. 15 and 16 do not show the capacitive film 222, the MIM capacitive element 58 described with reference to Figs. 14 to 16 can be applied to any of trench, concave, and cylinder types.

[0131] Although the above-described MIM capacitance element 58 has a configuration in which the MIM capacitance elements 58 are stacked, it can be miniaturized in the vertical direction because the MIM capacitance elements 58 are not stacked via vias, etc. Furthermore, the configuration of the MIM capacitance element 58 that can also be miniaturized in the horizontal direction will be described with reference to FIGS.

[0132] When comparing the MIM capacitance element 58 shown in Figures 9 to 11 with the MIM capacitance element 58 shown in Figures 14 to 16, the difference is that the via 231-1 of the MIM capacitance element 58 shown in Figures 9 to 11 is formed outside the region where the shared electrode a is formed, whereas the via 231-1' of the MIM capacitance element 58 shown in Figures 14 to 16 is formed inside the region where the shared electrode a is formed.

[0133] 14, the via 231-1' is formed so as to penetrate the upper electrode 223-2 of the upper MIM capacitance element 58-2 and the upper electrode 223-1 (shared electrode a) of the lower MIM capacitance element 58-1 in a cross-sectional view. In a plan view, the via 231-1' is provided in a region where the upper electrode 223-2 of the upper MIM capacitance element 58-2 is not formed, as shown in FIG. 15. Compared to the upper electrode 223-2 shown in FIG. 10, the upper electrode 223-2 shown in FIG. 15 is formed in a shape where one corner of the lower left corner of the upper electrode 223-2, which is formed in a rectangular shape, is cut off, and the via 231-1' is provided in the region where the upper electrode 223-2 is not formed.

[0134] As shown in Fig. 16, the via 231-1' is provided in a region where the upper electrode 223-1 (shared electrode a) of the lower MIM capacitance element 58-1 is not formed. Compared to the upper electrode 223-1 shown in Fig. 11, the upper electrode 223-1 shown in Fig. 16 is formed in a shape where one corner of the lower left corner of the upper electrode 223-2, which is formed in a rectangular shape, is cut off, and the via 231-1' is provided in the region where the upper electrode 223-1 is not formed.

[0135] The via 231-1′ is provided in an area where the upper electrode 223-2 and the upper electrode 223-1 (lower electrode 221-2) are not formed, and by providing the via 231-1′ in this area, the via 231-1′ is arranged more inward than the above-mentioned MIM capacitance element 58. This allows the lateral width of the MIM capacitance element 58 to be shortened.

[0136] Since the via 231-1' is configured to be moved to an inner position, the via 231-2' is also configured to be moved to an inner position.

[0137] In plan view, the via 231-3' is provided in a region where the upper electrode 223-2 of the upper MIM capacitance element 58-2 is not formed, as shown in Fig. 15. Compared to the upper electrode 223-2 shown in Fig. 10, the upper electrode 223-2 shown in Fig. 15 is formed in a shape where one upper right corner of the upper electrode 223-2, which is formed in a rectangular shape, is cut off, and the via 231-3' is provided in the region where the upper electrode 223-2 is not formed.

[0138] The upper layer wiring 202-2 shown in FIG. 10 is formed outside the area where the upper electrode 223-2 is provided, but the upper layer wiring 202-2 shown in FIG. 15 is formed so as to have an area that overlaps with the area where the upper electrode 223-2 is provided.

[0139] As shown in Fig. 16, the via 231-3' is provided in the region of the upper left corner of the upper electrode 223-1 (shared electrode a) of the lower MIM capacitance element 58-1. Compared to the upper electrode 223-1 shown in Fig. 11, the upper electrode 223-1 shown in Fig. 11 has a shape in which a region for connection with the via 231-3 is added, whereas the upper electrode 223-1 shown in Fig. 16 does not have a shape in which a region for connection with the via 231-3' is added, but has a configuration in which the via 231-1' is connected to a partial region of the hexagonal upper electrode 223-1.

[0140] The via 231-1' is provided in a region where the upper electrode 223-2 is not formed, and is provided in this region so as to be connected to a partial region of the upper electrode 223-1 (lower electrode 221-2), thereby being configured to be positioned more inward than the above-mentioned MIM capacitance element 58. This allows the lateral width of the MIM capacitance element 58 to be shortened.

[0141] In this way, by arranging the vias 231-1' to 231-3' on the inside, it is possible to further reduce the width of the MIM capacitance element 58. Therefore, the MIM capacitance element 58 can be miniaturized in the lengthwise and widthwise directions (vertical and horizontal directions).

[0142] 17 is a diagram showing an example of a cross-sectional configuration when the capacitance section is configured of an MIM capacitance element 58 having a four-stage configuration. In the above-described embodiment, an MIM capacitance element 58 having a two-stage configuration has been described as an example, but the present technology is not limited to a two-stage configuration and can be applied to an MIM capacitance element 58 configured with an even number of stages, such as four stages or six stages. Here, the description will continue using an MIM capacitance element 58 having a four-stage configuration as an example.

[0143] In the cross-sectional configuration example shown in FIG. 17, a concave type MIM capacitance element 58 will be described as an example, but the present invention can be applied to either a trench type or a cylinder type structure.

[0144] 17 has a four-stage structure, and is designated as the first stage, second stage, third stage, and fourth stage from the bottom in the figure, with the first-stage MIM capacitance element 58 designated as the first-stage MIM capacitance element 58-1, the second-stage MIM capacitance element 58 designated as the second-stage MIM capacitance element 58-2, the third-stage MIM capacitance element 58 designated as the third-stage MIM capacitance element 58-3, and the fourth-stage MIM capacitance element 58 designated as the fourth-stage MIM capacitance element 58-4. When the first-stage to fourth-stage MIM capacitance elements 58-1 to 58-4 are collectively described or when there is no need to distinguish them individually, they are referred to as the MIM capacitance element 58.

[0145] The MIM capacitance element 58 is formed between a lower layer wiring 201 and an upper layer wiring 202. The upper layer wiring 202 includes upper layer wirings 202-1 and 202-2.

[0146] The first-stage MIM capacitance element 58-1 has a structure in which a lower electrode 221-1, a capacitance film 222-1, and an upper electrode 223-1 are stacked. The second-stage MIM capacitance element 58-2 has a structure in which a lower electrode 221-2, a capacitance film 222-2, and an upper electrode 223-2 are stacked. The third-stage MIM capacitance element 58-3 has a structure in which a lower electrode 221-3, a capacitance film 222-3, and an upper electrode 223-3 are stacked. The fourth-stage MIM capacitance element 58-4 has a structure in which a lower electrode 221-4, a capacitance film 222-4, and an upper electrode 223-4 are stacked.

[0147] The first-stage MIM capacitance element 58-1 and the second-stage MIM capacitance element 58-2 are directly connected. In the example shown in Figure 17, the upper electrode 223-1 of the first-stage MIM capacitance element 58-1 and the lower electrode 221-2 of the second-stage MIM capacitance element 58-2 are connected (shared). In other words, the upper electrode 223-1 of the first-stage MIM capacitance element 58-1 functions as the lower electrode 221-2 of the second-stage MIM capacitance element 58-2.

[0148] The second-stage MIM capacitance element 58-2 and the third-stage MIM capacitance element 58-3 are directly connected, and the upper electrode 223-2 of the second-stage MIM capacitance element 58-2 and the lower electrode 221-3 of the third-stage MIM capacitance element 58-3 are connected (shared). That is, the upper electrode 223-2 of the second-stage MIM capacitance element 58-2 functions as the lower electrode 221-3 of the third-stage MIM capacitance element 58-3.

[0149] The third-stage MIM capacitance element 58-3 and the fourth-stage MIM capacitance element 58-4 are directly connected, and the upper electrode 223-3 of the third-stage MIM capacitance element 58-3 and the lower electrode 221-4 of the fourth-stage MIM capacitance element 58-4 are connected (shared). That is, the upper electrode 223-3 of the third-stage MIM capacitance element 58-3 functions as the lower electrode 221-4 of the fourth-stage MIM capacitance element 58-4.

[0150] In the case of the four-stage MIM capacitance element 58, the upper electrode 223 and the lower electrode 221 are also shared at the connection portion of the MIM capacitance elements 58 in each stage.

[0151] The lower electrode 221-1 of the first-stage MIM capacitance element 58-1 is connected to the lower layer wiring 201. The lower layer wiring 201 is connected to the upper layer wiring 202-1 through a via 231-1.

[0152] A via 231-2 is also connected to the upper layer wiring 202-1, and the via 231-2 is connected to the upper electrode 223-4 of the fourth-stage MIM capacitance element 58-4. A via 231-4 is also connected to the upper layer wiring 202-1, and the via 231-4 is connected to a shared electrode that is shared by the upper electrode 223-2 of the second-stage MIM capacitance element 58-2 and the lower electrode 221-3 of the third-stage MIM capacitance element 58-3.

[0153] The lower layer wiring 201 is connected to the bottom electrode 221-1 of the first-stage MIM capacitance element 58-1 in the first stage (nth stage, odd-numbered stage), and is also connected to the upper layer wiring 202-1. The upper layer wiring 202-1 is also connected to the top electrode 223-2 of the second-stage MIM capacitance element 58-2 in the second stage (n+1th stage, even-numbered stage) and the top electrode 223-4 of the fourth-stage MIM capacitance element 58-4 in the fourth stage (n+3th stage, even-numbered stage).

[0154] A via 231-3 is connected to the upper layer wiring 202-2. The via 231-3 is connected to a shared electrode shared by the upper electrode 223-1 of the first-stage MIM capacitance element 58-1 and the lower electrode 221-1 of the second-stage MIM capacitance element 58-2. A via 231-5 is also connected to the upper layer wiring 202-2, and the via 231-5 is connected to a shared electrode shared by the upper electrode 223-3 of the third-stage MIM capacitance element 58-3 and the lower electrode 221-4 of the fourth-stage MIM capacitance element 58-4.

[0155] The upper layer wiring 202-2 is connected to the upper electrode 223-1 of the first-stage MIM capacitance element 58-1 in the first stage (nth stage, odd-numbered stage). In other words, the upper layer wiring 202-1 is connected to the lower electrode 221-2 of the second-stage MIM capacitance element 58-2 in the second stage (n+1th stage, even-numbered stage).

[0156] The upper layer wiring 202-2 is connected to the upper electrode 223-3 of the third-stage MIM capacitance element 58-3 in the third stage (n+2th stage, odd-numbered stage). In other words, the upper layer wiring 202-2 is connected to the lower electrode 221-4 of the fourth-stage MIM capacitance element 58-4 in the fourth stage (n+4th stage, even-numbered stage).

[0157] Fig. 18 is a circuit diagram of an MIM capacitance element 58 having the cross-sectional configuration shown in Fig. 17. The upper electrode 223-4 of the fourth-stage MIM capacitance element 58-4 is connected to the lower-layer wiring 201 through a via 231-1 in the upper-layer wiring 202-1, and is further connected to the lower electrode 221-1 of the first-stage MIM capacitance element 58-1 through the lower-layer wiring 201. Therefore, the upper electrode 223-4 of the fourth-stage MIM capacitance element 58-4 and the lower electrode 221-1 of the first-stage MIM capacitance element 58-1 are connected.

[0158] The wiring connecting the upper electrode 223-2 of the second-stage MIM capacitance element 58-2 and the lower electrode 221-3 of the third-stage MIM capacitance element 58-3 is connected to a via 231-4 (corresponding wiring) connected to the upper layer wiring 202-2.

[0159] A via 231-3 (corresponding wiring) connected to the upper layer wiring 202-2 is connected to the wiring connecting the upper electrode 223-1 of the first-stage MIM capacitance element 58-1 and the lower electrode 221-2 of the second-stage MIM capacitance element 58-2. A via 231-5 (corresponding wiring) connected to the upper layer wiring 202-2 is connected to the wiring connecting the upper electrode 223-3 of the third-stage MIM capacitance element 58-3 and the lower electrode 221-4 of the fourth-stage MIM capacitance element 58-4.

[0160] The first-stage MIM capacitance element 58-1, the second-stage MIM capacitance element 58-2, the third-stage MIM capacitance element 58-1, and the fourth-stage MIM capacitance element 58-2 are connected in parallel in terms of the circuit. By configuring the MIM capacitance elements 58-1 to 58-4 to be connected in parallel in terms of the circuit, it is possible to increase the capacitance.

[0161] As shown in FIG. 17, the stacked MIM capacitance elements 58 are not connected to each other via vias or the like. In other words, the connection portions also function as part of the capacitance elements, which makes it possible to achieve miniaturization at least in the vertical direction (the up-down direction in the figure).

[0162] 14 to 16, the electrode shapes and via arrangements for miniaturizing the MIM capacitance element 58 in the lateral direction (horizontal direction) can also be applied to the four-stage MIM capacitance element 58. In this case, the MIM capacitance element 58 can be miniaturized in the lateral direction as well.

[0163] By configuring the MIM capacitance elements 58-1 to 58-4 with the same material and size, it is possible to match the characteristics of the stacked MIM capacitance elements 58-1 to 58-4. Therefore, even in the four-stage MIM capacitance element 58, it is possible to achieve a configuration that does not impair the dependency of the capacitor characteristics.

[0164] The MIM capacitance elements 58-1 to 58-4 can be made of different materials or can be made to have different sizes. For example, the material constituting each of the MIM capacitance elements 58-1 to 58-4 can be adjusted, or the height of the portion corresponding to the hole (the capacitance formed vertically in the drawing) can be adjusted, so that the combined capacitance of the MIM capacitance elements 58-1 to 58-4 becomes the desired capacitance.

[0165] By stacking the MIM capacitance elements 58 in an even number of stages and configuring the MIM capacitance elements 58 so that they are directly connected without vias or the like, in other words, so that the lower electrode 221 and the upper electrode 223 are shared, or in other words, so that the lower electrode 221 of the (n+1)th stage serves as the upper electrode 223 of the nth stage, the electrode structure of the MIM capacitance elements 58 can be made symmetrical, thereby reducing the asymmetry of the voltage characteristics. Also, the stacked structure MIM capacitance element 58 can be made smaller.

[0166] The stacked MIM capacitance elements 58 are connected without vias, etc., which reduces the number of manufacturing steps and reduces parasitic resistance and contact resistance. The stacked MIM capacitance elements 58 can be configured as being connected in parallel as a circuit, which increases the capacitance of the MIM capacitance elements 58.

[0167] In the above-described embodiment, the MIM capacitance element 58 provided in the imaging element has been described as an example, but when a capacitance element is required in an element or device other than the imaging element, the MIM capacitance element 58 in this embodiment can also be applied as that capacitance element (memory).

[0168] <Application Examples to Electronic Devices> The present technology is applicable to general electronic devices that use an imaging element in an image capture unit (photoelectric conversion unit), such as imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, copiers that use an imaging element in an image reading unit, etc. The imaging element may be formed as a single chip, or may be in the form of a module having an imaging function in which the imaging unit and a signal processing unit or an optical system are packaged together.

[0169] Fig. 19 is a block diagram showing an example configuration of an imaging device as an electronic device to which the present technology is applied. The imaging device 1000 in Fig. 19 includes an optical unit 1001 including a lens group and the like, an imaging element (imaging device) 1002, and a DSP (Digital Signal Processor) circuit 1003 which is a camera signal processing circuit. The imaging device 1000 also includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus line 1009.

[0170] The optical unit 1001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the image sensor 1002. The image sensor 1002 converts the amount of incident light formed on the imaging surface by the optical unit 1001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0171] The display unit 1005 is configured with a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the imaging element 1002. The recording unit 1006 records the moving images or still images captured by the imaging element 1002 on a recording medium such as a hard disk or semiconductor memory.

[0172] An operation unit 1007, under user operation, issues operation commands for various functions of the imaging device 1000. A power supply unit 1008 appropriately supplies various types of power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007 as operating power sources.

[0173] An imaging element including the above-described MIM capacitance element 58 can be applied to a part of the imaging device shown in FIG.

[0174] <Application Example to Endoscopic Surgery System> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0175] FIG. 20 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0176] 20 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0177] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0178] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0179] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0180] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0181] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0182] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0183] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0184] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0185] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0186] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0187] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0188] FIG. 21 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0189] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0190] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0191] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0192] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0193] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0194] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0195] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0196] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0197] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0198] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0199] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0200] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0201] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0202] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0203] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0204] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0205] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0206] FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0207] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0208] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0209] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0210] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0211] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0212] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0213] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0214] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0215] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0216] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 22, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0217] FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.

[0218] In FIG. 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0219] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0220] 23 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0221] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0222] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0223] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0224] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0225] In this specification, a system refers to an entire device made up of multiple devices.

[0226] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0227] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0228] The present technology can also be configured as follows: (1) A capacitor comprising: an upper layer wiring; a lower layer wiring; and a capacitor section in which an even number of capacitor elements provided in a three-dimensional shape are stacked between the upper layer wiring and the lower layer wiring, wherein the capacitor elements are composed of an upper electrode, a lower electrode, and a capacitor film sandwiched between the upper electrode and the lower electrode, and the upper electrode of the nth capacitor element is stacked to become the lower electrode of the n+1th capacitor element. (2) The capacitor according to (1), wherein the upper electrode of the nth capacitor element and the lower electrode of the n+1th capacitor element are shared. (3) The capacitor according to (1) or (2), wherein the lower layer wiring is connected to the lower electrode of the capacitor element in a first stage and also to the upper layer wiring, and the upper layer wiring includes a first upper layer wiring connected to the upper electrode of the capacitor element in an even stage and a second upper layer wiring connecting the upper electrodes of the capacitor elements in an odd stage. (4) The capacitor according to any of (1) to (3), wherein the stacked capacitor elements are formed of the same material. (5) The capacitor according to any of (1) to (3), wherein the stacked capacitor elements are formed of different materials. (6) The capacitor according to any of (1) to (5), wherein the capacitive section is configured such that a plurality of the capacitor elements are stacked and connected in a vertical direction in a cross-sectional view and are electrically connected in parallel. (7) The capacitor according to any of (1) to (6), wherein a via is provided connecting the upper layer wiring and the lower layer wiring, and the via is located in a region where the upper electrode and a portion of the lower electrode are not formed. (8) A capacitance element according to any one of (1) to (7), comprising a via that connects the upper layer wiring to a shared electrode that is shared by the upper electrode and the lower electrode, and the via is arranged in an area where a part of the upper electrode and the lower electrode other than the shared electrode is not formed.(9) An imaging element comprising: a photoelectric conversion element; and a capacitance section for storing charge overflowed from the photoelectric conversion element, wherein the capacitance section comprises upper layer wiring, lower layer wiring, and a capacitance element provided in a three-dimensional shape, wherein the capacitance element is composed of an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode, wherein the capacitance elements are stacked in an even number of layers between the upper layer wiring and the lower layer wiring, and the upper electrode of the capacitance element in the nth layer is stacked as the lower electrode of the capacitance element in the n+1th layer.

[0229] REFERENCE SIGNS LIST 1 imaging device, 2 pixel, 3 pixel array section, 4 vertical drive circuit, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8 control circuit, 9 vertical signal line, 10 pixel drive line, 11 horizontal signal line, 13 input / output terminal, 31 selection transistor, 51 photoelectric conversion section, 52 first transfer transistor, 53 first FD section, 54 second transfer transistor, 55 second FD section, 56 third transfer transistor, 57 third FD section, 58 MIM capacitance element, 59 reset transistor, 60 amplification transistor, 61 selection transistor, 100 semiconductor substrate, 101 microlens, 103 planarization film, 104 light-shielding film, 105 n-type semiconductor region, 106 p-type semiconductor region, 107 P-type semiconductor region, 108 fixed charge film, 109 pixel separation section, 120 wiring layer, 121 local wiring, 122 wiring, 123 interlayer insulating layer, 201 lower layer wiring, 202 upper layer wiring, 221 lower electrode, 222 capacitance film, 223 upper electrode, 231 via, 252, 254 recess

Claims

1. A capacitance element comprising: upper layer wiring; lower layer wiring; and a capacitance section in which capacitance elements arranged in a three-dimensional shape are stacked in an even number of layers between the upper layer wiring and the lower layer wiring, wherein the capacitance elements are composed of an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode, and the upper electrode of the nth capacitance element is stacked so as to become the lower electrode of the n+1th capacitance element.

2. The capacitive element according to claim 1, wherein the upper electrode of the capacitive element in the nth stage and the lower electrode of the capacitive element in the (n+1)th stage are shared.

3. The capacitance element according to claim 1, wherein the lower layer wiring is connected to the lower electrode of the capacitance element in the first stage and is also connected to the upper layer wiring, and the upper layer wiring includes a first upper layer wiring connected to the upper electrode of the capacitance element in the even stage and a second upper layer wiring connecting the upper electrodes of the capacitance element in the odd stage.

4. The capacitor element according to claim 1, wherein the stacked capacitor elements are made of the same material.

5. The capacitive element according to claim 1, wherein the stacked capacitive elements are formed of different materials.

6. The capacitive element according to claim 1, wherein the capacitive section is configured such that a plurality of the capacitive elements are stacked and connected in a vertical direction in a cross-sectional view, and are electrically connected in parallel.

7. The capacitive element according to claim 1, further comprising a via connecting the upper layer wiring and the lower layer wiring, the via being disposed in a region where a portion of the upper electrode and the lower electrode is not formed.

8. The capacitive element according to claim 1, further comprising a via that connects the upper layer wiring to a shared electrode that is shared by the upper electrode and the lower electrode, the via being arranged in an area where the upper electrode and part of the lower electrode other than the shared electrode are not formed.

9. An imaging element comprising: a photoelectric conversion element; and a capacitance section for accumulating charge overflowing from the photoelectric conversion element, wherein the capacitance section comprises upper layer wiring, lower layer wiring, and a capacitance element provided in a three-dimensional shape, wherein the capacitance element is composed of an upper electrode, a lower electrode, and a capacitance film sandwiched between the upper electrode and the lower electrode, and the capacitance elements are stacked in an even number of layers between the upper layer wiring and the lower layer wiring, and the upper electrode of the capacitance element in the nth layer is stacked as the lower electrode of the capacitance element in the n+1th layer.

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