Electric power supply device and output voltage setting method

Abstract

An electric power supply device (1) comprises: a test voltage determination unit (4) that is configured to generate a test voltage (Vt) on the basis of a voltage applied to an electric power supply terminal (T1), and is configured to determine that the test voltage indicates a test mode when the voltage applied to the electric power supply terminal is an overvoltage; a communication circuit (5) that is configured to be able to receive a communication input signal (Sin) by applying an overvoltage to an output terminal (T2); a non-volatile memory (7); and a program control unit (6) that is configured to write data relating to setting of an output voltage (Vout) included in the communication input signal to the non-volatile memory by a command from the communication circuit, on the basis of the determination result by the test voltage determination unit.

Description

Power supply device and output voltage setting method

[0001] The present disclosure relates to a power supply device.

[0002] 2. Description of the Related Art Conventionally, a linear regulator called an LDO (Low Drop Output) has been known (see, for example, Patent Document 1).

[0003] JP 2017-85725 A

[0004] [Summary] A power supply device in which the above-mentioned linear regulator is packaged as a semiconductor device may have three external terminals (a power terminal, an output terminal, and a ground terminal). In order to support various output voltage values ​​in such a power supply device, it has been necessary to prepare power supply devices with different configurations corresponding to each output voltage.

[0005] A power supply device according to one embodiment of the present disclosure comprises: a power supply terminal; an output terminal; a ground terminal; a power supply circuit configured to generate an output voltage output from the output terminal from a power supply voltage applied to the power supply terminal; a test voltage determination unit configured to generate a test voltage based on the voltage applied to the power supply terminal and to determine that the test voltage indicates a test mode when the voltage applied to the power supply terminal is an overvoltage; a communication circuit configured to be able to receive a communication input signal by applying an overvoltage to the output terminal; a non-volatile memory; and a program control unit configured to write data regarding the setting of the output voltage included in the communication input signal to the non-volatile memory in response to a command from the communication circuit based on the determination result by the test voltage determination unit.

[0006] FIG. 1 is a diagram illustrating an overview of a power supply device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating the internal configuration of a power supply device according to a first embodiment. FIG. 3 is a timing chart illustrating an example of an output voltage Vout and a communication input signal Sin for a test mode. FIG. 4 shows an example of the configuration of serial data for a test mode. FIG. 5 is a diagram illustrating the internal configuration of a power supply device according to a second embodiment. FIG. 6 is a diagram illustrating an example of the configuration of a comparator. FIG. 7 is a diagram illustrating the internal configuration of a power supply device according to a third embodiment. FIG. 8 is an external view illustrating an example of a vehicle.

[0007] DETAILED DESCRIPTION Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0008] First Embodiment Fig. 1 is a diagram showing an overview of a power supply device 1 according to a first embodiment. Note that Fig. 1 also applies to second and third embodiments described later.

[0009] The power supply device 1 is configured as a semiconductor device in which a chip integrating a power supply circuit (LDO), which will be described later, is packaged. The power supply device 1 has a power terminal T1, an output terminal T2, and a ground terminal T3 as external terminals for establishing electrical connection with the outside. In this way, the power supply device 1 has only three external terminals.

[0010] The power supply terminal T1 is a terminal for applying a power supply voltage Vdd. As an example, the power supply device 1 is for use in a vehicle, and the power supply voltage Vdd supplied from a battery BT in the vehicle is applied to the power supply terminal T1. The output terminal T2 is a terminal for outputting an output voltage Vout output from the power supply circuit. The ground terminal T3 is a terminal for applying a ground potential GND.

[0011] Fig. 2 is a diagram showing the internal configuration of the power supply device 1 according to the first embodiment. The power supply device 1 includes a chip that integrates the internal configuration shown in Fig. 2. Specifically, the power supply device 1 includes a power supply circuit 2, an inverter 3, a test voltage determination unit 4, a communication circuit 5, a program control unit 6, a nonvolatile memory 7, a resistor selection unit 8, and an internal voltage generation unit 9.

[0012] The power supply circuit 2 is configured as an LDO (linear regulator) and generates an output voltage Vout by stepping down a power supply voltage Vdd. The power supply circuit 2 includes an error amplifier 21, an output transistor 22, variable resistors R1 and R2, and a resistor R3. The variable resistor is not limited to the configuration shown in FIG. 2, and may be at least one of R1 to R3. The variable resistors R1 and R2 and resistor R3 are configured as feedback resistors for generating a feedback voltage Vfb.

[0013] A reference voltage Vref is applied to the inverting input terminal (-) of the error amplifier 21. The output transistor 22 is configured by a P-channel MOSFET (metal-oxide-semiconductor field-effect transistor). The source of the output transistor 22 is connected to the terminal to which the power supply voltage Vdd is applied. The drain of the output transistor 22 is connected to one terminal of a variable resistor R1. The other terminal of the variable resistor R1 is connected to one terminal of a variable resistor R2 at a node N21. The other terminal of the variable resistor R2 is connected to one terminal of a resistor R3 at a node N22. The other terminal of the resistor R3 is connected to the terminal to which the ground potential GND is applied. The node N21 is connected to the non-inverting input terminal (+) of the error amplifier 21. The output terminal of the error amplifier 21 is connected to the gate of the output transistor 22. The drain of the output transistor 22 is connected to the output terminal T2. That is, an output voltage Vout is generated at the drain of the output transistor 22.

[0014] With this configuration of the power supply circuit 2, the output voltage Vout is divided by the variable resistor R1 and the combined resistance (R2+R3) of the variable resistor R2 and resistor R3, and a feedback voltage Vfb is generated at node N21. The output of the error amplifier 21 controls the gate of the output transistor 22, continuously controlling the on-resistance of the output transistor 22, so that the feedback voltage Vfb matches the reference voltage Vref. Therefore, the output voltage Vout is controlled to a target voltage defined by the reference voltage Vref and the ratio of R1 to (R2+R3). For example, when the reference voltage Vref=1 V and R1:(R2+R3)=2:1, Vout=3 V.

[0015] A communication voltage Vc is generated at node N22 by dividing the output voltage Vout by a combined resistance (R1+R2) of variable resistors R1 and R2 and resistor R3. The communication voltage Vc is input to inverter 3. Inverter 3 is composed of a high-side PMOS transistor (P-channel MOSFET) and a low-side NMOS transistor (N-channel MOSFET) (neither of which is shown).

[0016] The source of the PMOS transistor is connected to an application terminal of the internal voltage Vreg. The internal voltage Vreg is generated by an internal voltage generation unit 9 based on the power supply voltage Vdd. The drain of the PMOS transistor is connected to the drain of the NMOS transistor. The source of the NMOS transistor is connected to an application terminal of the ground potential GND. A communication voltage Vc is applied to the gates of the PMOS transistor and the NMOS transistor. A communication input signal Sin is output from a node where the drain of the PMOS transistor and the drain of the NMOS transistor are connected. The level of the communication voltage Vc is logically inverted by an inverter 3 to generate the communication input signal Sin.

[0017] The test voltage determination unit 4 is a circuit that determines whether the internally generated test voltage Vt is in test mode and outputs a determination signal St. The test voltage determination unit 4 includes a pull-down resistor Rp, a Zener diode ZD, and an inverter 41. A predetermined number of Zener diodes ZD are connected in series, with their cathodes connected to the application terminal of the power supply voltage Vdd and their anodes connected to one end of the pull-down resistor Rp. The other end of the pull-down resistor Rp is connected to the application terminal of the ground potential GND. The test voltage Vt is generated at a node N41 where the anode of the Zener diode ZD and one end of the pull-down resistor Rp are connected.

[0018] The test voltage Vt is input to an inverter 41. The inverter 41 is configured similarly to the inverter 3 described above, and is connected between the internal voltage Vreg and the ground potential GND. The level of the test voltage Vt is logically inverted by the inverter 41, and is output from the inverter 41 as a determination signal St.

[0019] A communication input signal Sin is input to the communication circuit 5 together with a determination signal St. A program control unit 6 controls writing of data to a nonvolatile memory 7 based on commands from the communication circuit 5. The nonvolatile memory 7 is configured as an OTP (One Time Programmable ROM) and can be written only once. A resistance selection unit 8 reads data from the nonvolatile memory 7 and selects the resistance values ​​of the variable resistors R1 and R2.

[0020] A method for setting the output voltage using the power supply 1 configured as described above will now be described. This output voltage setting method makes it possible to set the output voltage Vout to various voltage values ​​using the power supply 1 with the same configuration. Furthermore, this setting can be achieved using only three external terminals without increasing the number of terminals. The output voltage setting method may be performed before shipping the power supply 1, or may be performed by the user.

[0021] In order to set the output voltage in the power supply device 1, it is necessary to transition to test mode. To transition to test mode, the determination signal St and the communication input signal Sin input to the communication circuit 5 must each satisfy a predetermined condition. The following explanation will be given using examples of voltage values.

[0022] First, let us explain the test voltage determination unit 4. For test mode, the power supply voltage Vdd is applied to the power supply terminal T1 as an overvoltage. This causes the Zener diode ZD to conduct, current flows through the pull-down resistor Rp, and the test voltage Vt goes high. This causes the determination signal St to go low. For example, let's assume that the normal value of the power supply voltage Vdd due to the battery Vt is 12 V, and the power supply voltage Vdd as an overvoltage is 45 V. Here, if the breakdown voltage of each Zener diode ZD is 5 V and seven Zener diodes ZD are connected in series, the Zener diode ZD will conduct when a Vdd of 5 × 7 = 35 V or more is applied. Therefore, when the power supply voltage Vdd is applied as an overvoltage, the Zener diode ZD conducts, generating a test voltage Vt of 45 - 35 = 10 V. The test voltage Vt of 10 V is high, and the determination signal St goes low. The low-level determination signal St indicates that the test voltage Vt has been determined to be in test mode. It is assumed that the internal voltage Vreg=5V.

[0023] When the power supply voltage Vdd is 12 V (normal value), the Zener diode ZD is not conductive, so no current flows through the pull-down resistor Rp, Vt is 0 V, and the test voltage Vt is at low level. In this case, the determination signal St is at high level. Therefore, it is determined that the test voltage Vt is not in the test mode.

[0024] Next, the communication input signal Sin will be described. Here, for example, assume that the target value of the output voltage Vout is 3 V. The output voltage Vout for test mode is applied from the outside to the output terminal T2. The output voltage Vout for test mode is composed of a high voltage VH and a low voltage VL. The high voltage VH is an overvoltage that is higher than the value to which the output voltage Vout is normally controlled (3 V in the above example). Figure 3 shows an example of the output voltage Vout for test mode and the communication input signal Sin.

[0025] Assuming that the high voltage VH is 20 V and the ratio (R1 + R2):R3 is 9:1, the communication voltage Vc is 20 × 1 / 10 = 2 V, which results in a high level of the communication voltage Vc. This causes the communication input signal Sin to be low. On the other hand, if the low voltage VL is 3 V, the communication voltage Vc is 3 × 1 / 10 = 0.3 V, which results in a low level of Vc. This causes the communication input signal Sin to be high. In this way, the high voltage VH corresponds to a low level of the communication input signal Sin, and the low voltage VL corresponds to a high level of the communication input signal Sin (Figure 3). Note that in the power supply circuit 2 configured as an LDO regulator, it is difficult to lower the output voltage Vout below the target value by applying an external voltage to the output terminal T2, but it is easy to raise the output voltage Vout above the target value.

[0026] In this way, the communication input signal Sin is generated based on the output voltage Vout for the test mode. The communication input signal Sin is input to the communication circuit 5 as a single-wire serial communication signal. The communication circuit 5 acquires serial data by determining whether the bit value is "0" or "1" depending on the level of the communication input signal Sin at the timing when a predetermined time T has elapsed since the rising edge of the communication input signal Sin, as shown in FIG. 3 .

[0027] 4 shows an example of the configuration of serial data for test mode. The serial data includes a magic code MC, address data AD, a read / write bit RW, and write data DT. The magic code MC is a predetermined bit data determined in advance for transitioning to test mode. The address data AD is bit data indicating the address of the nonvolatile memory 7 for writing. The read / write bit RW is bit data (1 bit) indicating read or write. The write data DT is data to be written to the nonvolatile memory 7.

[0028] As described above, when the communication circuit 5 confirms that the serial data acquired via the communication input signal Sin contains the Magic Code MC while the determination signal St is at a low level, it transitions to test mode. In this case, the communication circuit 5 issues a command to the program control unit 6 based on the address data AD, the Read / Write bit RW (indicating Write), and the Write data DT acquired after the Magic Code MC. Based on the command, the program control unit 6 writes the specified Write data to a specified address in the nonvolatile memory 7. The written Write data is used to select the resistance values ​​of the variable resistors R1 and R2, i.e., to set the output voltage Vout. This completes the output voltage setting process.

[0029] In the power supply device 1 in which the output voltage setting has been completed in this manner, the resistor selector 8 reads the write data written above from the nonvolatile memory 7 at each startup and selects the resistance values ​​of the variable resistors R1 and R2 based on the read data. This controls the output voltage Vout to the set target value. During normal use of the power supply device 1, the power supply voltage Vdd is at a normal value (12 V in the above example), so the Zener diode ZD does not conduct, the test voltage Vt is low, and the determination signal St is high, preventing transition to test mode. Note that even if the power supply voltage Vdd overshoots the normal value when the battery BT is started, the Zener diode ZD does not conduct, preventing transition to test mode.

[0030] The configuration of the serial data is not limited to that shown in FIG. 4, and for example, the magic code MC may be included as part of the address data AD.

[0031] 5 is a diagram showing the internal configuration of a power supply device 1X according to a second embodiment. The power supply device 1X differs from the first embodiment in that a comparator 10 is used instead of the inverter 3 as an input / output unit (I / O unit) that receives a communication voltage Vc and outputs a communication input signal Sin.

[0032] The comparator 10 compares the communication voltage Vc with a threshold voltage and outputs a communication input signal Sin at a high or low level depending on the comparison result. Fig. 6 is a diagram showing an example configuration of the comparator 10. The comparator 10 shown in Fig. 6 has a differential input stage 101, a gain stage 102, and an output stage 103.

[0033] The differential input stage 101 includes an input transistor 101A, an input transistor 101B, a constant current source 101C, and a current mirror 101D. The input transistor 101A is an enhancement-mode N-channel MOSFET. The input transistor 101B is a depletion-mode N-channel MOSFET. The enhancement-mode N-channel MOSFET has a positive threshold voltage Vgs (gate-source voltage), while the depletion-mode N-channel MOSFET has a negative threshold voltage Vgs. The sources of the input transistors 101A and 101B are connected to one end of the constant current source 101C. The other end of the constant current source 101C is connected to a terminal to which the ground potential GND is applied. The drain of the input transistor 101A is connected to the input side of the current mirror 101D, which is a P-channel MOSFET. The drain of the input transistor 101B is connected to the output side of the current mirror 101D.

[0034] An input signal IN is applied to the gate of the input transistor 101A. A ground potential GND is applied to the gate of the input transistor 101B. The input signal IN corresponds to the communication voltage Vc in FIG. 5. The comparison output Cpout output from the output stage 103 corresponds to the communication input signal Sin output from the comparator 10.

[0035] If the threshold voltage of the input transistor 101A is Vgs1 (positive voltage) and the threshold voltage of the input transistor 101B is Vgs2 (negative voltage), then the threshold voltage Vth = Vgs1 - Vgs2, and the comparison output CPout becomes high or low depending on whether the input voltage IN is higher than Vth.

[0036] When the communication voltage Vc becomes an intermediate potential, if the inverter 3 is used as in the first embodiment, a current flows through both the PMOS transistor and the NMOS transistor in the inverter 3. However, if the comparator 10 is used as in this embodiment, no leakage current occurs as in the first embodiment.

[0037] 7 is a diagram showing the internal configuration of a power supply device 1Y according to a third embodiment. The power supply device 1Y differs from the first embodiment in the configuration of a test voltage determination unit 4Y. The test voltage determination unit 4Y has voltage dividing resistors Rd1 and Rd2 and a comparator 42.

[0038] One end of the voltage-dividing resistor Rd1 is connected to a terminal to which the power supply voltage Vdd is applied. The other end of the voltage-dividing resistor Rd1 is connected to one end of the voltage-dividing resistor Rd2. The other end of the voltage-dividing resistor Rd2 is connected to a terminal to which the ground potential GND is applied. A test voltage Vt is generated at a node N42 to which the voltage-dividing resistors Rd1 and Rd2 are connected. The test voltage Vt is input to a comparator 42. The comparator 42 compares the test voltage Vt with a threshold voltage and outputs the comparison result as a determination signal St. The comparator 42 can be configured, for example, in the same manner as the comparator 10 described above.

[0039] According to this embodiment, in order to transition to the test mode, the power supply voltage Vdd is set to an overvoltage, and the overvoltage is divided by the voltage-dividing resistors Rd1 and Rd2 to form a test voltage Vt that is higher than the threshold voltage of the comparator 42, and the determination signal St becomes a level indicating the test mode. On the other hand, when the power supply voltage Vdd is a normal value, the test voltage Vt is set to a lower voltage than the threshold voltage of the comparator 42, and the determination signal St becomes a level indicating that the test mode is not in progress. By using the comparator 42 as the input / output unit, leakage current does not occur when the test voltage Vt is an intermediate potential, as occurs when an inverter is used.

[0040] <Vehicle> Fig. 8 is an external view showing an example configuration of a vehicle X. The vehicle X of this example configuration is equipped with various electronic devices X11 to X18 that operate by receiving power supply from a battery (not shown). Note that the installation positions of the electronic devices X11 to X18 in Fig. 8 may differ from the actual positions for convenience of illustration.

[0041] The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

[0042] The electronic device X12 is a lamp control unit that controls the turning on and off of a high intensity discharged lamp (HID) or a daytime running lamp (DRL).

[0043] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0044] The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0045] The electronic device X15 is a security control unit that controls the driving of door locks, security alarms, and the like.

[0046] The electronic devices X16 are electronic devices that are installed in the vehicle X at the factory as standard equipment or manufacturer options, such as wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroofs, and power seats.

[0047] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0048] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.

[0049] The power supply devices 1, 1X, and 1Y according to the above-described embodiments may be applied to any of the electronic devices X11 to X18.

[0050] <Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0051] <Note> As described above, a semiconductor device (1) according to one aspect of the present disclosure includes: a power supply terminal (T1); an output terminal (T2); a ground terminal (T3); a power supply circuit (2) configured to generate an output voltage (Vout) output from the output terminal from a power supply voltage (Vdd) applied to the power supply terminal; a test voltage determination unit (4) configured to generate a test voltage (Vt) based on the voltage applied to the power supply terminal and to determine that the test voltage indicates a test mode when the voltage applied to the power supply terminal is an overvoltage; a communication circuit (5) configured to receive a communication input signal (Sin) by applying an overvoltage to the output terminal; a non-volatile memory (7); and a program control unit (6) configured to write data related to the setting of the output voltage, which is included in the communication input signal, to the non-volatile memory in response to a command from the communication circuit based on a determination result by the test voltage determination unit (first configuration, FIG. 2).

[0052] With this configuration, it is possible to set various output voltage values ​​using a power supply device with the same configuration, without increasing the number of terminals from three external terminals.

[0053] In addition, in the first configuration, the test voltage determination unit may be configured to have a first input / output unit (41) configured to output a high-level or low-level determination signal (St) depending on the input test voltage (second configuration).

[0054] In addition, in the second configuration, the test voltage determination unit may be configured to include a pull-down resistor (Rp) and a Zener diode (ZD) having a cathode connected to the power supply terminal side and an anode connected to the pull-down resistor side (third configuration).

[0055] In addition, in the second configuration, the test voltage determination unit may be configured to have voltage dividing resistors (Rd1, Rd2) configured to divide the voltage applied to the power supply terminal to generate the test voltage (fourth configuration, FIG. 7).

[0056] In the fourth configuration, the first input / output unit may include a comparator (42) (fifth configuration).

[0057] Furthermore, in any of the first to fifth configurations, the power supply circuit may have feedback resistors (R1, R2, R3) configured to generate a feedback voltage (Vfb) by dividing the output voltage, and the power supply device may be configured to include a second input / output unit (3) configured to receive a communication voltage (Vc) generated by dividing the voltage applied to the output terminal by the feedback resistors and to output the communication input signal at a high level or a low level depending on the communication voltage (sixth configuration).

[0058] In the sixth configuration, the second input / output unit may include a comparator (10) (seventh configuration, FIG. 5).

[0059] In the fifth or seventh configuration, the comparator may have a differential input stage (101) including a first input transistor (101A) configured to receive an input signal (IN) at its gate and configured as an enhancement-type N-channel MOSFET, and a second input transistor (101B) configured to receive a ground potential at its gate and configured as a depletion-type N-channel MOSFET (eighth configuration, FIG. 6).

[0060] In addition, in any of the first to eighth configurations, the communication circuit may be configured to cause the program control unit to write the data when it confirms that the serial data obtained from the communication input signal contains a magic code (MC), which is predetermined bit data (ninth configuration, Figure 4).

[0061] In the ninth configuration, the communication input signal may be a single-wire serial communication signal (tenth configuration).

[0062] In addition, in any of the first to tenth configurations, the power supply circuit may have a feedback resistor configured to generate a feedback voltage by dividing the output voltage, and the data may be data for selecting the resistance values ​​of variable resistors (R1, R2) included in the feedback resistor (an eleventh configuration).

[0063] Furthermore, in any of the first to eleventh configurations, the power supply circuit may be configured to have an output transistor (22) connected between the power supply terminal and the output terminal, a feedback voltage generation unit (R1, R2, R3) configured to generate a feedback voltage based on the output voltage, and an error amplifier (21) configured to receive a reference voltage (Vref) and the feedback voltage as input and output a control signal to a control terminal of the output transistor (twelfth configuration).

[0064] Furthermore, in any of the first to twelfth configurations, the power supply device may be configured to be mountable on a vehicle (X), and the power supply terminal may be configured to be able to apply the power supply voltage supplied from a battery (BT) included in the vehicle (13th configuration).

[0065] Another aspect of the present disclosure is a method for setting an output voltage using a power supply device (1) of any one of the first to thirteenth configurations, including: a first step of applying an overvoltage for the test mode to the power supply terminal; and a second step of applying a high voltage, which is an overvoltage, and a low voltage to the output terminal to generate the communication input signal including digital data (fourteenth configuration).

[0066] The present disclosure can be used, for example, in power supply devices for various applications.

[0067] 1, 1X, 1Y Power supply device 2 Power supply circuit 3 Inverter 4, 4Y Test voltage determination unit 5 Communication circuit 6 Program control unit 7 Non-volatile memory 8 Resistor selection unit 9 Internal voltage generation unit 10 Comparator 21 Error amplifier 22 Output transistor 41 Inverter 42 Comparator 101 Differential input stage 101A, 101B Input transistor 101C Constant current source 101D Current mirror 102 Gain stage 103 Output stage BT Battery R1, R2 Variable resistor R3 Resistor Rd1, Rd2 Voltage dividing resistor Rp Pull-down resistor T1 Power supply terminal T2 Output terminal T3 Ground terminal X Vehicle X11 to X18 Electronic device ZD Zener diode

Claims

1. A power supply device comprising: a power supply terminal; an output terminal; a ground terminal; a power supply circuit configured to generate an output voltage output from the output terminal from a power supply voltage applied to the power supply terminal; a test voltage determination unit configured to generate a test voltage based on the voltage applied to the power supply terminal and to determine that the test voltage indicates a test mode when the voltage applied to the power supply terminal is an overvoltage; a communication circuit configured to be able to receive a communication input signal by applying an overvoltage to the output terminal; a non-volatile memory; and a program control unit configured to write data regarding the setting of the output voltage, which is included in the communication input signal, to the non-volatile memory in response to a command from the communication circuit based on the determination result by the test voltage determination unit.

2. The power supply device according to claim 1, wherein the test voltage determination section has a first input / output section configured to output a determination signal of high level or low level in response to the test voltage input.

3. The power supply device according to claim 2, wherein the test voltage determination section comprises: a pull-down resistor; and a Zener diode having a cathode connected to the power supply terminal side and an anode connected to the pull-down resistor side.

4. The power supply device according to claim 2, wherein the test voltage determination section has a voltage dividing resistor configured to divide the voltage applied to the power supply terminal to generate the test voltage.

5. The power supply device according to claim 4, wherein the first input / output section includes a comparator.

6. A power supply device according to any one of claims 1 to 5, wherein the power supply circuit has a feedback resistor configured to generate a feedback voltage by dividing the output voltage, and the power supply device comprises a second input / output unit configured to receive a communication voltage generated by dividing the voltage applied to the output terminal by the feedback resistor, and to output the communication input signal at a high level or a low level depending on the communication voltage.

7. The power supply device according to claim 6, wherein the second input / output section includes a comparator.

8. The power supply device according to claim 5 or 7, wherein the comparator has a differential input stage including a first input transistor configured to receive an input signal at its gate and configured as an enhancement-mode N-channel MOSFET, and a second input transistor configured to receive a ground potential at its gate and configured as a depletion-mode N-channel MOSFET.

9. A power supply device as claimed in any one of claims 1 to 8, wherein the communication circuit causes the program control unit to write the data when it confirms that the serial data obtained from the communication input signal contains a magic code, which is predetermined bit data.

10. The power supply device of claim 9, wherein the communication input signal is a single-wire serial communication signal.

11. A power supply device according to any one of claims 1 to 10, wherein the power supply circuit has a feedback resistor configured to generate a feedback voltage by dividing the output voltage, and the data is data for selecting a resistance value of a variable resistor included in the feedback resistor.

12. A power supply device according to any one of claims 1 to 11, wherein the power supply circuit comprises an output transistor connected between the power supply terminal and the output terminal, a feedback voltage generation unit configured to generate a feedback voltage based on the output voltage, and an error amplifier configured to receive a reference voltage and the feedback voltage as inputs and output a control signal to a control end of the output transistor.

13. A power supply device according to any one of claims 1 to 12, which is configured to be mountable on a vehicle, and the power supply terminals are capable of receiving the power supply voltage supplied from a battery included in the vehicle.

14. A method for setting an output voltage using a power supply device according to any one of claims 1 to 13, comprising: a first step of applying an overvoltage for the test mode to the power supply terminal; and a second step of applying a high voltage, which is an overvoltage, and a low voltage to the output terminal to generate the communication input signal containing digital data.

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