Full-bridge synchronous rectification circuit

Abstract

The invention discloses a full-bridge synchronous rectification circuit, which realizes self-driving of two PMOS (P-channel Metal Oxide Semiconductor) tubes of a full-bridge synchronous rectification structure through a gate-source clamping self-driving module, and controls gate-source voltages of the two self-driving PMOS tubes when an output voltage Vo is high, so that the gate-source voltages of the two self-driving PMOS tubes are always clamped in a voltage withstanding range of the two self-driving PMOS tubes, and the problem of overvoltage breakdown is solved. The working voltage range is expanded, and the circuit reliability is improved. In addition, the gate source clamping self-driving module can release excessive energy when the voltage of the rectification output end abnormally drifts high, the load regulation rate can be optimized, and the problem that the output abnormally drifts high can be relieved or avoided.

Description

Technical Field

[0001] This application relates to the field of switching power supply control, and in particular to full-bridge synchronous rectifier circuits, such as full-bridge synchronous rectifier circuits on the secondary side of a DC-DC converter. Background Technology

[0002] With the booming development of new energy vehicles, industrial control, and medical fields, the demand for isolated switching power supply converters (a type of DC-DC converter) is gradually increasing, mainly due to wider input voltage range, higher power and efficiency, smaller size, and higher reliability. Isolated switching power supply converters include a transformer and its secondary-side rectifier circuit; a full-bridge rectifier circuit is a common choice. Traditional full-bridge rectifier circuits require complex drive circuits, which can lead to efficiency losses. Chinese patent CN109617430B proposes a self-driven full-bridge synchronous rectifier circuit, which has advantages such as simple operation and high efficiency. However, this gate-drain cross-coupled synchronous rectifier circuit architecture suffers from PMOS transistor gate-source withstand voltage issues; voltage spikes on the transformer can easily damage the devices, making it unsuitable for wide voltage ranges. Summary of the Invention

[0003] The purpose of this invention is to propose a solution to the gate-source withstand voltage problem of the PMOS transistor in the self-driven full-bridge synchronous rectifier circuit described in the background art, thereby expanding its operating voltage range and improving the reliability of the circuit.

[0004] The objective of this invention is achieved through the following technical solution: A full-bridge synchronous rectifier circuit, comprising a full-bridge synchronous rectifier structure consisting of two self-driven PMOS transistors, namely power transistors MP3 and MP4, and two externally driven NMOS transistors, namely power transistors MN3 and MN4. The sources of power transistors MP3 and MP4 are connected to the rectified output terminal, the sources of power transistors MN3 and MN4 are connected to ground GND, and the drains of power transistors MP3 and MN3 are connected to the first AC input terminal (V). E The drains of power transistors MP4 and MN4 are connected to the second AC input terminal (V). D The full-bridge synchronous rectifier circuit is connected to the gate of power transistors MP3 and MP4, and includes a control circuit. The control circuit comprises a self-driven power transistor control circuit and a gate-source clamping self-driven module, which is connected to the gate of power transistors MP3 and MP4, and the second AC input terminal (V...). D ), First AC input terminal (V E The rectifier output terminal is connected to the power transistor MP3 and the power transistor MP4 respectively. The gates of the power transistors MP3 and MP4 are connected to the second AC input terminal (V) through their respective gates. D ), First AC input terminal (VE The gate-source clamp self-driving module connects to the rectifier output voltage Vo to achieve self-driving. When the voltage Vo at the rectifier output terminal reaches a set value, causing the power transistors MP3 and MP4 to potentially experience voltage withstand problems, the gate-source clamp self-driving module controls the change in the gate voltage of the power transistors MP3 and MP4 to clamp their gate-source voltage within their withstand voltage range, thus solving their overvoltage breakdown problem and improving circuit reliability.

[0005] The gate-source clamping self-driving module includes a clamping drive circuit and a bias circuit. The clamping drive circuit includes a MOS clamping transistor. The source of the MOS clamping transistor in the clamping drive circuit of power transistor MP3 is connected to the gate of power transistor MP3, and the source of the MOS clamping transistor in the clamping drive circuit of power transistor MP4 is connected to the gate of power transistor MP4. The bias circuit provides a bias voltage to the MOS clamping transistor. By setting the bias voltage of the gate of the MOS clamping transistor, the bias circuit turns it on and makes its source voltage equal to Vo - Vt, thereby clamping the gate-source voltage of power transistors MP3 and MP4. The source of the MOS clamping transistor is connected to the gate of power transistors MP3 and MP4. Thus, the gate-source voltage of power transistors MP3 and MP4 is equal to Vo - (Vo - Vt), which is always equal to Vt, i.e., they are clamped at Vt; Vt ≦ Vt. BV V BV These are the maximum gate-source operating voltages of power transistors MP3 and MP4. It is evident that this solution can resolve the overvoltage breakdown problem of the two PMOS transistors.

[0006] As a preferred embodiment of the present invention: The clamping drive circuit includes two PMOS transistors, namely clamping transistor MP5 and clamping transistor MP6. The source of clamping transistor MP5 is connected to the gate of power transistor MP4, and the drain is connected to the first AC input terminal (V). E The source of clamping transistor MP6 is connected to the gate of power transistor MP3, and the drain is connected to the second AC input terminal (V). D The gates of clamping transistors MP5 and MP6 both receive the bias voltage VBPP output by the bias circuit.

[0007] The above bias voltage VBPP satisfies the formula: VBPP=Vo-V BV -Vgsp; where Vgsp is the gate-source voltage of clamping transistors MP5 and MP6 when they are working; when VBPP < 0, VBPP is set to zero potential.

[0008] As an improvement: the clamping drive circuit further includes NMOS transistors MN5 and MN6. The drain of NMOS transistor MN5 is connected to the source of clamping transistor MP5, and the source is connected to the drain of clamping transistor MP5; the drain of NMOS transistor MN6 is connected to the source of clamping transistor MP6, and the source is connected to the drain of clamping transistor MP6; the gates of NMOS transistors MN5 and MN6 jointly receive the bias voltage VN output by the bias circuit. When Vo is less than V BV When VN is high, NMOS transistors MN5 and MN6 are turned on; When Vo is greater than or equal to V BV When VN is low, NMOS transistors MN5 and MN6 are turned off.

[0009] As a further preferred option: The clamping drive circuit also includes two NMOS transistors, namely clamping transistor MN7 and clamping transistor MN8. The drains of clamping transistor MN7 and clamping transistor MN8 are connected to the rectifier output terminal, and their gates jointly receive the bias voltage VBPN output by the bias circuit. The source of clamping transistor MN7 is connected to the gate of power transistor MP3, and the source of clamping transistor MN8 is connected to the gate of power transistor MP4.

[0010] In a scheme with clamping transistors MN7 and MN8, when the output voltage is abnormally high, a bleed branch can be formed to release excess energy.

[0011] When Vo is lower than the undervoltage threshold Vuvp, power transistors MP3 and MP4 are connected to the second AC input terminal (Vuvp) through clamping transistors MP6 and MP5, respectively. D ), First AC input terminal (V E When connected, clamp transistors MN7, MN8, MN5, and MN6 are turned off; When Vo is greater than or equal to Vuvp and less than V BV When VN outputs a high level, that is, while clamping transistors MP6 and MP5 are turned on, NMOS transistors MN5 and MN6 are also turned on, and clamping transistors MN7 and MN8 are turned off. When Vo is greater than or equal to V BV When the voltage is less than the overvoltage protection voltage Vovp of the power supply system, the VN output is low, which means that NMOS transistors MN5 and MN6 are turned off. At this time, the gate voltages of power transistors MP3 and MP4 are clamped and controlled by clamping transistors MP6, MP5, MN7, and MN8. When Vo is greater than or equal to Vovp, clamping transistors MN7 and MN8 are turned on, while clamping transistors MP6 and MP5 are not turned off at the same time as NMOS transistors MN5 and MN6. Among them, Vuvp <V BV <Vovp。

[0012] As a recommendation: when Vo is greater than or equal to the overvoltage protection voltage Vovp of the power supply system, clamping transistors MN7 and MN8 are turned on, clamping transistors MP6 and MP5 are turned off, and the conduction degree of NMOS transistors MN5 and MN6 increases with the increase of Vo.

[0013] As another preferred embodiment: The clamping drive circuit includes two NMOS clamping transistors MN7 and MN8, and resistors R1 and R2; resistor R1 is connected in series between the gate of power transistor MP4 and the first AC input terminal (V). E Resistor R2 is connected in series between the gate of power transistor MP3 and the second AC input terminal (V). D Between the clamping transistors MN7 and MN8, the drains of the clamping transistors MN7 and MN8 are connected to the rectifier output terminal, and their gates jointly receive the bias voltage VBPN output by the bias circuit. The source of the clamping transistor MN7 is connected to the gate of the power transistor MP3, and the source of the clamping transistor MN8 is connected to the gate of the power transistor MP4.

[0014] The above bias voltage VBPN satisfies the formula: VBPN = Vo - V BV +Vgs n Where Vgsn is the gate-source voltage of clamping transistors MN7 and MN8 when they are working; when VBPN < 0, VBPN is set to zero potential.

[0015] Preferably, the bias circuit includes a bias voltage module, which includes PMOS transistors MP11 and MP12, NMOS transistors MN17, MN16, MN15, MN14, MN13, MN12, MN11 and resistor R3. PMOS transistors MP11, NMOS transistors MN16, MN15, MN14, MN13, and MN12 are all connected in a diode configuration and are sequentially connected in forward mode between the rectifier output terminal and the drain of NMOS transistor MN11. The source of NMOS transistor MN11 is connected to GND, and its gate is connected to the reference voltage VREF. Resistor R3, NMOS transistor MN17, and PMOS transistor MP12 form another branch connected in series between the rectifier output terminal and GND. One end of resistor R3 is connected to the rectifier output terminal, and the other end is connected to the drain of NMOS transistor MN17. NMOS transistor MN17 is connected in a diode configuration, with its source connected to the source of PMOS transistor MP12. The drain of PMOS transistor MP12 is connected to GND, and its gate is connected to the drain of NMOS transistor MN11, serving as the output terminal of the bias voltage VBPP. The common terminal of resistor R3 and NMOS transistor MN17 serves as the output terminal of the bias voltage VBPN.

[0016] Preferably, the bias circuit includes a voltage detection module, which includes a first comparator, a second comparator, a transconductance operational amplifier, resistors R11, R12, and R13, and a MOSFET MN20. The rectified output terminal is connected to GND after being connected in series with resistors R11 and R12. The common terminal of resistors R11 and R12 is the output terminal of the sampling signal Vo1. The drain of the MOSFET MN20 serves as the output terminal of the bias voltage VN. It is also connected to the rectified output terminal through resistor R13, and is also connected to its own gate and the output terminal of the transconductance operational amplifier. The source of the MOSFET MN20 is connected to GND. The voltage Vo at the rectified output terminal is divided to form a sampling signal Vo1, which is then compared with the reference voltage V input via the inverting input terminal of the first comparator. REF The undervoltage lockout control signal UVP is obtained by comparing _uv. The sampled signal Vo1 is compared with the reference voltage VREF_BV input through the inverting input of the second comparator to obtain the gate-source breakdown protection clamping control signal BVP. The sampled signal Vo1 is also compared with the reference voltage VREF_OV input through the inverting input of the transconductance operational amplifier to output a control signal to set the bias voltage VN. The output of the transconductance operational amplifier is simultaneously controlled by the UVP and BVP signals to pull up or down the bias voltage VN, achieving: When UVP is low, VN is pulled low; when UVP is high and BVP is low, VN is pulled high; when UVP and BVP are high, VN is pulled low again, and when the output of the transconductance op-amp is also high, VN is made to follow the voltage change of the non-inverting input of the transconductance op-amp. The above V REF_uv is proportional to Vuvp, so that its comparison with Vo1 can characterize the relationship between Vo and Vuvp; The above VREF_BV and V BV The ratio is proportional so that the comparison result with Vo1 can characterize the relationship between Vo and V. BV Relationship; The above VREF_OV and V OVP The ratio is proportional so that the comparison result with Vo1 can characterize the relationship between Vo and V. OVP Relationship; And V REF _uv <VREF_BV<VREF_OV。

[0017] As a preferred embodiment, the self-driven power transistor control circuit includes an on / off voltage detection module, an on / off time control module, and a drive module. The on / off voltage detection module detects the first AC input terminal (V). E ), second AC input terminal (V D The voltage across the two ends of the circuit outputs an on or off signal when the voltage waveform is detected to cross zero volts, controlling the on and off of power transistors MN3 and MN4. The on / off time control module adds the minimum on time and minimum off time to the on and off signals. The drive module is connected to the on / off time control module and the gates of power transistors MN3 and MN4 to amplify the signal to drive power transistors MN3 and MN4.

[0018] The beneficial effects of this invention are as follows: 1) This invention achieves self-driving of the two PMOS transistors in a full-bridge synchronous rectification structure through a gate-source clamping self-driving module. At a high output voltage Vo, it controls the gate-source voltage of the two self-driven PMOS transistors, ensuring that their gate-source voltage is always clamped within their withstand voltage range. This solves their overvoltage breakdown problem, expands their operating voltage range, and improves circuit reliability. On the other hand, the clamping transistor or resistor connected in series with the gate of the two PMOS transistors in the clamping drive circuit provides a certain on-resistance, which can limit the inrush current and help improve the overcurrent breakdown problem of the PMOS power transistor gate. 2) When the output voltage of the self-driven gate-source clamping module of this invention is abnormally high, it can release excessive energy through the bleed branch, which helps to alleviate or prevent the problem of abnormally high rectified output voltage and greatly improves the load regulation rate of the open-loop system. 3) This invention uses a reference voltage to control multiple MOS transistors connected in series to generate a bias voltage, and then uses the generated bias voltage to control the clamping transistor to perform voltage clamping. The clamping voltage is precise and can be flexibly controlled. Attached Figure Description

[0019] Figure 1 This is a topology diagram of the DC-DC converter circuit used in this invention; Figure 2 This illustrates the overall design concept of the control circuit for the full-bridge synchronous rectifier circuit of the present invention. Figure 3 This is a circuit schematic diagram of one implementation method of the clamping drive circuit; Figure 4 The circuit schematic diagram is for the second implementation method of the clamping drive circuit; Figure 5 The circuit schematic diagram is for the third implementation method of the clamping drive circuit; Figure 6 The circuit schematic diagram is for the fourth implementation method of the clamping drive circuit; Figure 7 Used to reflect V N The process of change as Vo increases; Figure 8 This is the core schematic diagram of the preferred bias voltage module; Figure 9 This is the core schematic diagram of the preferred voltage detection module; Figure 10 The waveforms of the drain and gate voltages of the two self-driven PMOS power transistors during the rectification process are shown. Detailed Implementation

[0020] To better understand the technical solution of this invention and its contributions compared to the prior art, the invention will be described in detail below with reference to specific embodiments and related drawings. It should be understood that the specific embodiments described herein are merely illustrative and do not limit the invention.

[0021] Chinese patent CN109617430B discloses a self-driven full-bridge synchronous rectifier circuit, comprising two PMOS synchronous rectifier diodes and two NMOS synchronous rectifier diodes, along with their control circuitry. The gates of the two PMOS synchronous rectifier diodes are directly connected to the two ends of the transformer secondary winding, allowing the transformer winding to automatically select the path without requiring additional drive circuitry, thus forming a self-driven circuit. Only the two NMOS synchronous rectifier diodes require detection of the voltage waveform across the transformer secondary winding to be driven to turn on or off, thus forming an externally driven circuit. Therefore, it can reduce the complexity of the full-bridge synchronous rectifier circuit's drive circuit, i.e., the aforementioned control circuit. However, this self-driven structure is prone to gate-source breakdown voltage issues with the PMOS diodes when the transformer outputs peak voltage. This invention aims to solve this problem.

[0022] The overall concept of this invention is to design a clamping circuit that limits the gate voltage of the PMOS transistor when the PMOS transistor may have a breakdown voltage problem. This clamping circuit keeps the gate-source voltage of the PMOS transistor within its breakdown voltage range, thereby solving the overvoltage breakdown problem of the PMOS transistor and improving circuit reliability.

[0023] The following is based on Figure 1 Taking the DC-DC converter circuit shown as an example, several recommended embodiments for achieving the purpose of this invention will be described in detail.

[0024] Figure 1 This diagram shows the topology of a DC-DC converter. As can be seen from the diagram, it mainly includes a full-bridge inverter structure, transformer 106, and a full-bridge synchronous rectification structure. The full-bridge inverter structure on the primary side of transformer 106 converts the DC signal V output from power supply 100 into a DC signal V. IN The signal is converted into an AC signal, and the energy is transferred to the secondary side via transformer 106. The full-bridge synchronous rectifier structure on the secondary side of transformer 106 then rectifies the input AC signal into a DC output, Vo. (V in the diagram...) A V B This indicates the two input terminals of transformer 106, V C V D The two output terminals of transformer 106 are shown. The full-bridge inverter structure consists of four power transistors 101-104, controlled by the primary-side control circuit 105. The full-bridge synchronous rectification structure also consists of four power transistors 107-110, controlled by the secondary-side control circuit 200. The full-bridge synchronous rectification structure and its control circuit 200 together constitute the full-bridge synchronous rectification circuit referred to in this invention. Power transistors 107 and 108 in the full-bridge synchronous rectification structure are PMOS transistors, and power transistors 109 and 110 are NMOS transistors. 111 in the figure is the output filter capacitor, and 112 is the load.

[0025] The following embodiments are mainly improved Figure 1 The secondary control circuit 200 in the middle achieves the purpose of the invention. Figure 2 The following embodiment illustrates the overall design scheme of the secondary control circuit 200.

[0026] Power transistors 109 and 110 are externally driven, and their control circuit includes an on / off voltage detection module 202, an on / off time control module 203, and a drive module 204. The on / off voltage detection module 202 detects the voltage across the secondary side of the transformer. E V DThe voltage is controlled by an on / off time control module 203. When the voltage waveform crosses zero volts, an on / off signal is output to control the on / off state of the two power transistors 109 and 110. The on / off time control module 203 adds a minimum on-time and a minimum off-time to the on / off signals. This is to prevent interference from resonant signals or other glitches on the transformer, thus preventing accidental on / off. The drive module 204 connects to the on / off time control module 203 and the gates of the two power transistors 109 and 110, amplifying the signal to drive them.

[0027] It can be seen that the control circuit structure of the self-driven power transistors 109 and 110 is similar to that of the Chinese patent with authorization announcement number CN109617430B. The improvements to the secondary control circuit 200 in the following embodiments are mainly focused on the control circuits of the two self-driven power transistors 107 and 108.

[0028] like Figure 2 As shown, the control circuit for the two self-driven power transistors 107 and 108 uses a gate-source clamp self-driven module, which is connected to the two terminals V on the secondary side of the transformer. E V D The module includes the output signal Vo and the gates of the two power transistors 107 and 108. Using this module, not only can the two PMOS power transistors 107 and 108 be directly driven without complex drive circuits, but the gate-source voltages of the two power transistors 107 and 108 can also be clamped to prevent them from exceeding their withstand voltage range. Below are several implementations of the gate-source clamping self-driven module. In the following implementations, the control circuit for the self-driven power transistors 109 and 110 is represented as the turn-on / turn-off control and drive module 310.

[0029] Example 1 like Figure 3 As shown, the gate-source clamp self-driven module used in this embodiment includes a clamping drive circuit and a bias circuit. The clamping drive circuit consists of two PMOS clamping transistors 303 and 306. The bias circuit includes a bias voltage module 308 and a reference voltage module 309. The specific configuration of the bias circuit in each embodiment will be described uniformly later.

[0030] This replaces the existing structure where the gates of two self-driven power transistors 107 and 108 are directly connected to the two output terminals of the transformer secondary side, i.e., it replaces the direct connection between the gate of power transistor 108 and V... E The gate of power transistor 107 is directly connected to V. D In this embodiment, the gate of the power transistor 108 is directly connected to the V gate. E A clamping transistor 303 is connected in series between the terminals, and the gate of the power transistor 107 is connected to V. D A clamping transistor 306 is connected in series between the terminals. Specifically, the source of the clamping transistor 303 is connected to the gate of the power transistor 108, and the drain is connected to V.E At the terminal, the source of clamping transistor 306 is connected to the gate of power transistor 107, and the drain is connected to V. D At the terminals, their gates receive the bias voltage VBPP output by the bias circuit, which should keep the two clamping transistors 303 and 306 always in the on state.

[0031] In this embodiment, the bias circuit generates a control voltage for the two clamping transistors 303 and 306 by detecting the output voltage Vo, and the formula is as follows: VBPP=Vo-V BV -Vgsp; Where Vo is the rectified output voltage, V BV Vgsp represents the maximum gate-source voltage of power transistors 107 and 108. The maximum gate-source voltage of thin-gate technology is generally 5V. Vgsp represents the gate-source voltage of the two clamped transistors 303 and 306 when they are working.

[0032] At this time, VG P3 or VG P4 =VBPP+Vgsp=Vo-V BV。

[0033] VG P3 VG is the gate-source voltage of power transistor 107. P4 This is the gate-source voltage of power transistor 108.

[0034] Therefore, the gate-source voltage of power transistors 107 and 108 = Vo - (Vo - V BV )=V BV .

[0035] It is evident that, regardless of how Vo changes, the gate-source voltage of power transistors 107 and 108 remains constant at V. BV The value at the end of its withstand voltage range, which is clamped, can obviously also be determined by not setting it to V. BV And take less than V BV The value is used to clamp the gate-source voltage of power transistors 107 and 108 within their withstand voltage range.

[0036] To facilitate the provision of the bias voltage VBPP, VBPP = Vo - V BV When -Vgsp<0, VBPP is set to zero potential (i.e., GND). When VBPP≧0, it follows the change of Vo.

[0037] Advantages of this embodiment: The clamping drive circuit in this embodiment has a simple structure. While retaining the self-driven control of power transistors 107 and 108, it achieves clamping of their gate-source voltage, protects their gates from high voltage breakdown, improves circuit reliability, and enables them to operate in a wider voltage range.

[0038] Example 2 like Figure 4 As shown, the clamping drive circuit of the gate-source clamping self-driven module used in this embodiment is in Embodiment 1. Figure 3 Two more NMOS transistors, 305 and 304, are added to the base circuit, forming a parallel connection with clamping transistors 303 and 305, respectively. The drain of NMOS transistor 305 is connected to the source of clamping transistor 303, and its source is connected to the drain of clamping transistor 303. The drain of NMOS transistor 304 is connected to the source of clamping transistor 306, and its source is connected to the drain of clamping transistor 306. The gates of NMOS transistors 305 and 304 are connected, and they jointly receive the bias voltage VN output by the bias circuit.

[0039] In this embodiment, the bias circuit includes a bias voltage module 308, a reference voltage module 309, and a voltage detection module 307, which will also be described in detail later.

[0040] In this embodiment, the bias voltage VBPP of the two clamping transistors 303 and 306 is applied in the same way as in Embodiment 1.

[0041] The gate voltages of NMOS transistors 305 and 304 are generated by voltage detection module 307 based on Vo, and its basic logic is as follows: When Vo is less than V BV At that time, VN is at a high level; When Vo is greater than or equal to V BV At that time, VN is at a low level; Where Vo is the rectified output voltage, V BV This refers to the maximum operating voltage of the gate and source of power transistors 107 and 108. Generally, the maximum operating voltage of the gate and source in thin-gate technology is 5V.

[0042] Compared to Example 1, the change in the working method of Example 2 is that when Vo is less than V BV At this time, the gates of the two power transistors 107 and 108 are connected to the two terminals V of the secondary side of the transformer through the two NMOS transistors 304 and 305 respectively. D V E Connection, while Vo is greater than or equal to V BV When power transistors 107 and 108 may have voltage withstand issues, the two NMOS transistors 304 and 305 are promptly turned off. The clamping principle thereafter is the same as in Example 1.

[0043] Based on Example 1, this example has the following additional effects: at a lower operating voltage Vo, the gate-source voltage of power transistors 107 and 108 can be higher, resulting in lower bridge arm on-resistance and stronger rectification capability, thereby improving system efficiency. The reason is that when PMOS transistors (303, 304) transmit low voltage, they will raise Vthp by at least 0.7V, which will cause the gate voltage of power transistors 107 and 108 to rise. When the Vo voltage is low (below 2V, generally referring to a short period of system output power-on; there is no problem when the system steady-state output voltage is generally above 3.3V), it will have a certain impact on the impedance of the bridge arm, and the system efficiency will be slightly reduced. Example 2 connects an NMOS transistor (305, 304) in parallel with the PMOS transistors (303, 304). The NMOS transistor can effectively transmit low voltage, which can solve this problem. Even at a higher operating voltage Vo, the gate-source voltage of power transistors 107 and 108 can still be clamped within their withstand voltage range by two clamping transistors 303 and 306, protecting their gates from breakdown.

[0044] Example 3 like Figure 5 As shown, the clamping drive circuit of the gate-source clamping self-driven module used in this embodiment consists of NMOS clamping transistors 301 and 302 and resistors 311 and 312. Resistor 311 is connected in series with the gate of power transistor 108 and V. E Between the terminals, resistor 312 is connected in series in series between the gate of power transistor 107 and V. D Between the terminals, the drains of clamping transistors 301 and 302 are connected to the output terminal Vo, and their gates are connected together, and they jointly receive the bias voltage VBPN output by the bias circuit. The source of clamping transistor 301 is connected to the gate of power transistor 107, and the source of clamping transistor 302 is connected to the gate of power transistor 108.

[0045] The bias circuit generates a control voltage for the two clamping transistors 301 and 302 by detecting the output voltage Vo, and the formula is as follows: VBPN=Vo-V BV +Vgs n ; Where Vo is the rectified output voltage, V BV This refers to the maximum gate-source operating voltage of power transistors 107 and 108. Generally, the maximum gate-source operating voltage using thin-gate technology is 5V, Vgs. n This represents the gate-source voltage when the two clamping transistors 301 and 302 are operating.

[0046] At this time, VG P3 or VG P4 =VBPN-Vgsp=Vo-V BV。

[0047] VG P3VG is the gate-source voltage of power transistor 107. P4 This is the gate-source voltage of power transistor 108.

[0048] Therefore, the gate-source voltage of power transistors 107 and 108 = Vo - (Vo - V BV )=V BV .

[0049] As can be seen, similar to Example 1, regardless of how Vo changes, the gate-source voltage of power transistors 107 and 108 remains constant at V. BV It is clamped within its pressure resistance range.

[0050] Similarly, to facilitate the provision of the bias voltage VBPN, VBPN = Vo - V BV +Vgs n When VBPN is less than 0, set VBPN to zero potential (i.e., GND). When VBPN is greater than or equal to 0, follow the change in Vo. When Vo = V BV Time conduction.

[0051] This embodiment has the following advantages compared to Embodiment 1: At a lower Vo operating voltage, clamping transistors 301 and 302 are not conducting, and there is no voltage drop across resistors 311 and 312 because there is no conducting current. This allows for lower gate voltages for the two power transistors 107 and 108, lower impedance when the bridge arm is conducting, stronger rectification capability, and higher system efficiency. At higher Vo operating voltages, clamping transistors 301 and 302 can still clamp the gate-source voltages of power transistors 107 and 108 within their withstand voltage range, protecting their gates from breakdown. When the output voltage is abnormally high, clamping transistor 302 and resistor 311, and clamping transistor 301 and resistor 312, respectively form a bleed branch to release excessive energy, which helps to reduce the problem of excessive output voltage and damage to external components.

[0052] Example 4 like Figure 6 As shown, the clamping drive circuit of the gate-source clamping self-driven module used in this embodiment is in Embodiment 2. Figure 4 Based on this, NMOS clamping transistors 301 and 302 are added. The drains of clamping transistors 301 and 302 are connected to the output terminal Vo, and their gates are connected together and receive the bias voltage VBPN output by the bias circuit. The source of clamping transistor 301 is connected to the gate of power transistor 107, and the source of clamping transistor 302 is connected to the gate of power transistor 108.

[0053] When clamping is performed using the above clamping tubes (including 301, 302, 303 and 306), the formulas for VBPN and VBPP are as shown in Examples 2 and 3, respectively.

[0054] Figure 7 This embodiment is illustrated. Figure 6 The relationship between various bias values ​​and the output voltage Vo. Where Vo is the rectified output voltage; V BV VGP_L represents the maximum gate-source operating voltage of power transistors 107 and 108. Generally, the maximum gate-source operating voltage of thin-gate technology is 5V. VBPN is the gate voltage of NMOS clamp transistors 301 and 302. VBPP is the gate voltage of PMOS clamp transistors 303 and 306. VGP_L represents the minimum gate voltage relative to GND of power transistors 107 and 108 without breakdown. Vuvp is the undervoltage threshold. Vovp is the overvoltage protection voltage of the power supply system.

[0055] Figure 7 The schematic circuit operation is as follows: During the increase of voltage Vo from low to high, when Vo is lower than the undervoltage threshold Vuvp, power transistors 107 and 108 are connected to Vuvp via clamping transistors 306 and 303, respectively. D V E When connected, normal self-driving is achieved, and clamping tubes 306 and 303 do not perform clamping function.

[0056] When the voltage Vo is higher than or equal to Vuvp and lower than the gate-source breakdown voltage V of the PMOS transistor BV At this time, VN output is high, meaning that while clamp transistors 306 and 303 are conducting, NMOS transistors 305 and 304 are also conducting (fully conducting). NMOS transistors 305 and 304 can control the gate voltage VG of power transistors 107 and 108. P3 and VG P4 By pulling the power transistors 107 and 108 lower (see Example 2 for the principle), the power transistors 107 and 108 can be turned on more fully, resulting in higher rectification efficiency.

[0057] When Vo voltage is greater than or equal to V BV When VN outputs a low level, NMOS transistors 305 and 304 are turned off, and the gate voltage VG of power transistors 107 and 108 is also low. P3 and VG P4 The gate voltages of power transistors 107 and 108 are controlled by clamping transistors 306, 303, 301, and 302. The control strategy is relatively flexible; either clamping transistors 306 and 303 or clamping transistors 301 and 302 can be used to control the gate voltages, or both pairs of clamping transistors can be used simultaneously. The strategy in this embodiment is as follows: Figure 7 As shown, both pairs of clamping transistors are in the on state.

[0058] Finally, when the voltage Vo is greater than or equal to the overvoltage protection voltage Vovp of the power supply system, clamping transistors 306 and 303 are turned off (by...). Figure 7As can be seen, VBPP transitions to a high level), and VN gradually turns on again. At this time, the voltage from Vo through clamping transistor 301 and NMOS transistor 304 reaches V. D Or via clamping transistor 302, NMOS transistor 305 to V E There will be a current branch that discharges too much energy to prevent the output voltage from being too high and damaging external components. The more Vo exceeds Vovp, the larger the discharge current will be, which can effectively limit the overshoot of the output voltage Vo. In this stage, clamping transistors 306 and 303, or clamping transistors 306 and 303 and NMOS transistors 305 and 304 can be used for discharge.

[0059] The main advantage of this embodiment compared to Embodiment 2 is: At lower operating voltages, the gate voltages of power transistors 107 and 108 can be lower, the impedance of the bridge arm can be lower, the rectification capability can be stronger, and the system efficiency can be higher. Under higher operating voltage conditions, the gate-source voltage of power transistors 107 and 108 is clamped to protect their gates from being broken down. It can release excessive energy when the output is overvoltage, preventing the output voltage from being too high and damaging external components.

[0060] In the above embodiments, the clamping transistor or resistor connected in series with the gates of the two power transistors 107 and 108 in the clamping drive circuit provides a certain on-resistance, which can limit the inrush current and help improve their gate overcurrent breakdown problem.

[0061] The following section introduces some recommended designs for the bias circuits used in the above embodiments.

[0062] Figure 8 The diagram shown is the core schematic of the bias voltage module, which is mainly used to provide... Figure 7 The bias voltages VBPP and VBPN (mainly for) Figure 7The portions of VBPP and VBPN that change linearly with Vo (excluding the portions at zero voltage and after the VBPP transition). As shown in the figure, PMOS transistor MP11 and NMOS transistors MN16, MN15, MN14, MN13, and MN12 are all connected in a diode configuration and sequentially connected in forward series between Vo and the drain of NMOS transistor MN11. The source of NMOS transistor MN11 is connected to GND, and its gate is connected to VREF. Resistor R3, NMOS transistor MN17, and PMOS transistor MP12 form another branch connected in series between Vo and GND. One end of resistor R3 is connected to Vo, and the other end is connected to the drain of NMOS transistor MN17. NMOS transistor MN17 is connected in a diode configuration; its source is connected to the source of PMOS transistor MP12, the drain of PMOS transistor MP12 is connected to GND, and its gate is connected to the drain of NMOS transistor MN11, serving as the output of the bias voltage VBPP. The bias voltage VBPN is output from the common terminal of resistor R3 and NMOS transistor MN17. VS represents the voltage value at the source terminal of NMOS transistor MN17.

[0063] When MN11, MN12, MN13, MN14, MN15, and MN16 have the same dimensions, if Vgs of MN11 is 1V, then Vgs of MN12, MN13, MN14, MN15, and MN16 are also 1V. Therefore, VBPP = Vo - 5V - Vgsp (the gate-source voltage of MP11 is basically the same as that of clamping transistors 303 and 306). Then, VS = Vo - 5V - Vgsp + Vgsp = Vo - 5V (MP11 and MP12 have the same dimensions). Therefore, VBPN = Vo - 5V + Vgsn (the gate-source voltage of MN17 is basically the same as that of clamping transistors 301 and 302).

[0064] It can be seen that the bias voltage module described above can obtain bias voltages VBPP and VBPN that meet the requirements of the formulas VBPP=Vo-5V-Vgsp and VBPN=Vo-5V+Vgsn.

[0065] Figure 7 The transition between VBPP and V can be checked by examining Vo and V. OVP Signal relationship control, Figure 7 The zero level of VBPP and VBPN can be controlled by detecting whether VBPP=Vo-5V-Vgsp and VBPN=Vo-5V+Vgsn are less than zero level. The specific implementation method can be clearly understood by those skilled in the art based on existing knowledge, and will not be described in detail here.

[0066] In Examples 1 and 2, VBPP remains on, meaning no output is generated. Figure 7 The transition on the right uses... Figure 8 The bias voltage module shown can be used in conjunction with VBPP zero-level detection and control.

[0067] Figure 9 The diagram shown is the core schematic of the voltage detection module, which aims to form... Figure 7 The V shown N Output. Vo is divided by resistors R11 and R12 to obtain the sampled signal Vo1. Then, Vo1 is compared with the reference voltage V by comparator 901. REF _uv(V) REF _uv and Figure 7 The undervoltage threshold Vuvp is proportional to the value of the voltage, so that the comparison result with Vo1 can characterize the voltage level. Figure 7 The undervoltage lockout control signal UVP is obtained by comparing Vo with Vuvp (the relationship between Vo and Vuvp). Similarly, Vo1 is compared with the reference voltage VREF_BV by comparator 902 (VREF_BV and Vuvp are compared with the reference voltage VREF_BV). Figure 7 V in BV The clamping control signal BVP for gate-source breakdown protection is obtained by comparing the proportional relationship. Additionally, Vo1 is passed through a transconductance operational amplifier 903 and compared with the reference voltage VREF_OV (VREF_OV and...). Figure 7 V in OVP The bias voltage VN is generated by the proportional comparison. This op-amp is also pulled high or low by the UVP and BVP signals: when UVP and BVP are low, VN is pulled low; when UVP is high and BVP is low, VN is pulled high; and when UVP and BVP are high, VN is pulled low again. When UVP, BVP and the output of 903 are high, the VN voltage follows the voltage change of the non-inverting input of op-amp 903.

[0068] The diagram does not show in detail how to raise or lower VN through UVP and BVP, but the applicant believes that, based on the above disclosure, it can be easily implemented by those skilled in the art using existing technology, and will not be elaborated further here.

[0069] The variation pattern of VN in Example 2 and Figure 7 It is slightly different, and its transformation method is simpler and easier to implement, so I will not go into details here.

[0070] Regarding the reference voltage module 309, the applicant believes that it falls within the scope of existing technology, so it will not be discussed in detail.

[0071] Figure 10 The above embodiment shows the waveforms (V) of the drain and gate voltages of power transistors 107 and 108 during the rectification process. GP3 V GP4 (These represent the gate voltages of power transistors 107 and 108, respectively). As shown in the figure, when Vo is a low voltage, the waveforms of the power transistor gate voltages are similar to those of V. D or V ETo maintain consistency, when the Vo voltage is high, exceeding the gate-source withstand voltage V BV At that time, its gate voltage V GP_L It will be clamped between VBPP and VBPN.

[0072] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be construed as limiting the scope of protection of the present invention. The scope of protection of the present invention is determined by the scope defined in its claims. For those skilled in the art, several improvements and modifications can be made without departing from the spirit and scope of the present invention, and these improvements and modifications should also be considered to fall within the scope of protection of the present invention.

Claims

1. A full-bridge synchronous rectifier circuit, comprising a full-bridge synchronous rectifier structure consisting of two self-driven PMOS transistors, namely power transistors MP3 and MP4, and two externally driven NMOS transistors, namely power transistors MN3 and MN4. The sources of power transistors MP3 and MP4 are connected to the rectified output terminal, the sources of power transistors MN3 and MN4 are connected to ground GND, and the drains of power transistors MP3 and MN3 are connected to a first AC input terminal (V). E The drains of power transistors MP4 and MN4 are connected to the second AC input terminal (V). D The full-bridge synchronous rectifier circuit further includes a control circuit, which comprises a self-driven power transistor control circuit and a power transistor control circuit. The characteristic of this circuit is that... The self-driven power transistor control circuit adopts a gate-source clamp self-driven module, which is connected to the gate of power transistors MP3 and MP4, and the second AC input terminal (V D ), First AC input terminal (V E The rectifier output terminal is connected to the power transistor MP3 and the power transistor MP4 respectively. The gates of the power transistors MP3 and MP4 are connected to the second AC input terminal (V) through their respective gates. D ), First AC input terminal (V E The gate-source clamp self-driving module connects to the rectifier output voltage Vo to achieve self-drive. When the voltage Vo at the rectifier output terminal reaches a set value, causing the power transistors MP3 and MP4 to potentially experience voltage withstand problems, the gate-source clamp self-driving module controls the change in the gate voltage of the power transistors MP3 and MP4 to clamp their gate-source voltage within their withstand voltage range.

2. The full-bridge synchronous rectifier circuit according to claim 1, characterized in that, The gate-source clamping self-driving module includes a clamping driving circuit and a bias circuit. The clamping driving circuit includes a MOS clamping transistor. The source of the MOS clamping transistor in the clamping driving circuit of power transistor MP3 is connected to the gate of power transistor MP3, and the source of the MOS clamping transistor in the clamping driving circuit of power transistor MP4 is connected to the gate of power transistor MP4. The bias circuit is used to provide a bias voltage for the MOS clamping transistor. The bias circuit sets the bias voltage of the gate of the MOS clamping transistor to turn it on and make its source voltage equal to Vo-Vt, thereby clamping the gate-source voltage of power transistors MP3 and MP4; Vt≦V BV V BV This represents the maximum gate-source operating voltage for power transistors MP3 and MP4.

3. The full-bridge synchronous rectifier circuit according to claim 2, characterized in that, The clamping drive circuit includes two PMOS transistors, namely clamping transistor MP5 and clamping transistor MP6. The source of clamping transistor MP5 is connected to the gate of power transistor MP4, and the drain is connected to the first AC input terminal (V). E The source of clamping transistor MP6 is connected to the gate of power transistor MP3, and the drain is connected to the second AC input terminal (V). D The gates of clamping transistors MP5 and MP6 both receive the bias voltage VBPP output by the bias circuit.

4. The full-bridge synchronous rectifier circuit according to claim 3, characterized in that, The clamping drive circuit further includes NMOS transistors MN5 and MN6. The drain of NMOS transistor MN5 is connected to the source of clamping transistor MP5, and the source is connected to the drain of clamping transistor MP5. The drain of NMOS transistor MN6 is connected to the source of clamping transistor MP6, and the source is connected to the drain of clamping transistor MP6. The gates of NMOS transistors MN5 and MN6 jointly receive the bias voltage VN output by the bias circuit.

5. The full-bridge synchronous rectifier circuit according to claim 4, characterized in that, The clamping drive circuit also includes two NMOS transistors, namely clamping transistor MN7 and clamping transistor MN8. The drains of clamping transistor MN7 and clamping transistor MN8 are connected to the rectifier output terminal, and their gates jointly receive the bias voltage VBPN output by the bias circuit. The source of clamping transistor MN7 is connected to the gate of power transistor MP3, and the source of clamping transistor MN8 is connected to the gate of power transistor MP4.

6. The full-bridge synchronous rectifier circuit according to claim 3, characterized in that, The bias voltage VBPP satisfies the formula: VBPP=Vo-V BV -Vgsp; where Vgsp is the gate-source voltage of clamping transistors MP5 and MP6 when they are working; when VBPP < 0, VBPP is set to zero potential.

7. The full-bridge synchronous rectifier circuit according to claim 4, characterized in that, The bias voltage VBPP satisfies the formula: VBPP=Vo-V BV -Vgsp; where Vgsp is the gate-source voltage of clamping transistors MP5 and MP6 when they are working; when VBPP < 0, VBPP is set to zero potential; The bias voltage VN satisfies the following condition: When Vo is less than V BV When VN is high, NMOS transistors MN5 and MN6 are turned on; When Vo is greater than or equal to V BV When VN is low, NMOS transistors MN5 and MN6 are turned off.

8. The full-bridge synchronous rectifier circuit according to claim 5, characterized in that, When Vo is lower than the undervoltage threshold Vuvp, power transistors MP3 and MP4 are connected to the second AC input terminal (Vuvp) through clamping transistors MP6 and MP5, respectively. D ), First AC input terminal (V E When connected, clamp transistors MN7, MN8, MN5, and MN6 are turned off; When Vo is greater than or equal to Vuvp and less than V BV When VN outputs a high level, that is, while clamping transistors MP6 and MP5 are turned on, NMOS transistors MN5 and MN6 are also turned on, and clamping transistors MN7 and MN8 are turned off. When Vo is greater than or equal to V BV When the voltage is less than the overvoltage protection voltage Vovp of the power supply system, the VN output is low, which means that NMOS transistors MN5 and MN6 are turned off. At this time, the gate voltages of power transistors MP3 and MP4 are clamped and controlled by clamping transistors MP6, MP5, MN7, and MN8. When Vo is greater than or equal to Vovp, clamping transistors MN7 and MN8 are turned on, while clamping transistors MP6 and MP5 are not turned off at the same time as NMOS transistors MN5 and MN6. Among them, Vuvp <V BV <Vovp。 9. The full-bridge synchronous rectifier circuit according to claim 8, characterized in that, When Vo is greater than or equal to the overvoltage protection voltage Vovp of the power supply system, clamping transistors MN7 and MN8 are turned on, clamping transistors MP6 and MP5 are turned off, and the conduction degree of NMOS transistors MN5 and MN6 increases with the increase of Vo.

10. The full-bridge synchronous rectifier circuit according to claim 2, characterized in that, The clamping drive circuit includes two NMOS clamping transistors MN7 and MN8, and resistors R1 and R2; resistor R1 is connected in series between the gate of power transistor MP4 and the first AC input terminal (V). E Resistor R2 is connected in series between the gate of power transistor MP3 and the second AC input terminal (V). D Between the clamping transistors MN7 and MN8, the drains of the clamping transistors MN7 and MN8 are connected to the rectifier output terminal, and their gates jointly receive the bias voltage VBPN output by the bias circuit. The source of the clamping transistor MN7 is connected to the gate of the power transistor MP3, and the source of the clamping transistor MN8 is connected to the gate of the power transistor MP4.

11. The full-bridge synchronous rectifier circuit according to claim 10, characterized in that, The bias voltage VBPN satisfies the formula: VBPN = Vo - V BV +Vgs n Where Vgsn is the gate-source voltage of clamping transistors MN7 and MN8 when they are working; when VBPN < 0, VBPN is set to zero potential.

12. The full-bridge synchronous rectifier circuit according to claim 2, characterized in that, The bias circuit includes a bias voltage module, which includes PMOS transistors MP11 and MP12, NMOS transistors MN17, MN16, MN15, MN14, MN13, MN12, MN11 and resistor R3. PMOS transistors MP11, NMOS transistors MN16, MN15, MN14, MN13, and MN12 are all connected in a diode configuration and are sequentially connected in forward mode between the rectifier output terminal and the drain of NMOS transistor MN11. The source of NMOS transistor MN11 is connected to GND, and its gate is connected to the reference voltage VREF. Resistor R3, NMOS transistor MN17, and PMOS transistor MP12 form another branch connected in series between the rectifier output terminal and GND. One end of resistor R3 is connected to the rectifier output terminal, and the other end is connected to the drain of NMOS transistor MN17. NMOS transistor MN17 is connected in a diode configuration, with its source connected to the source of PMOS transistor MP12. The drain of PMOS transistor MP12 is connected to GND, and its gate is connected to the drain of NMOS transistor MN11, serving as the output terminal of the bias voltage VBPP. The common terminal of resistor R3 and NMOS transistor MN17 serves as the output terminal of the bias voltage VBPN.

13. The full-bridge synchronous rectifier circuit according to claim 2, characterized in that, The bias circuit includes a voltage detection module, which includes a first comparator, a second comparator, a transconductance operational amplifier, resistors R11, R12, and R13, and a MOSFET MN20. The rectified output terminal is connected to GND after being connected in series with resistors R11 and R12. The common terminal of resistors R11 and R12 is the output terminal of the sampling signal Vo1. The drain of the MOSFET MN20 serves as the output terminal of the bias voltage VN. It is also connected to the rectified output terminal through resistor R13, and is also connected to its own gate and the output terminal of the transconductance operational amplifier. The source of the MOSFET MN20 is connected to GND. The voltage Vo at the rectified output terminal is divided to form a sampling signal Vo1, which is then compared with the reference voltage V input via the inverting input terminal of the first comparator. REF The undervoltage lockout control signal UVP is obtained by comparing _uv. The sampled signal Vo1 is compared with the reference voltage VREF_BV input through the inverting input of the second comparator to obtain the gate-source breakdown protection clamping control signal BVP. The sampled signal Vo1 is also compared with the reference voltage VREF_OV input through the inverting input of the transconductance operational amplifier to output a control signal to set the bias voltage VN. The output of the transconductance operational amplifier is simultaneously controlled by the UVP and BVP signals to pull up or down the bias voltage VN, achieving: When UVP is low, VN is pulled low; when UVP is high and BVP is low, VN is pulled high; when UVP and BVP are high, VN is pulled low again, and when the output of the transconductance op-amp is also high, VN is made to follow the voltage change of the non-inverting input of the transconductance op-amp. The above V REF _uv is proportional to Vuvp, so that its comparison with Vo1 can characterize the relationship between Vo and Vuvp; The above VREF_BV and V BV The ratio is proportional so that the comparison result with Vo1 can characterize the relationship between Vo and V. BV Relationship; The above VREF_OV and V OVP The ratio is proportional so that the comparison result with Vo1 can characterize the relationship between Vo and V. OVP Relationship; And V REF _uv <VREF_BV<VREF_OV。 14. The full-bridge synchronous rectifier circuit according to claim 1 or 2, characterized in that, The self-driven power transistor control circuit includes an on / off voltage detection module, an on / off time control module, and a drive module. The on / off voltage detection module detects the first AC input terminal (V). E ), second AC input terminal (V D The voltage across the two ends of the circuit outputs an on or off signal when the voltage waveform is detected to cross zero volts, controlling the on and off of power transistors MN3 and MN4. The on / off time control module adds the minimum on time and minimum off time to the on and off signals. The drive module is connected to the on / off time control module and the gates of power transistors MN3 and MN4 to amplify the signal to drive power transistors MN3 and MN4.

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