Thin-film type solar cell device, thin-film type solar cell module, and manufacturing method therefor

Abstract

A thin-film type solar cell device according to an embodiment of the present invention may include: a substrate; a solar cell including a first lower conductive layer, a first semiconductor layer, and a first upper conductive layer which are sequentially stacked on the substrate in an upward direction; a connection portion including a second lower conductive layer connected to the first lower conductive layer, a second semiconductor layer formed on the second lower conductive layer, and a second upper conductive layer formed on the second semiconductor layer so as to be connected to the second lower conductive layer; and a bypass diode including a third upper conductive layer connected to the second upper conductive layer, and a third semiconductor layer and a third lower conductive layer, which are sequentially stacked in a downward direction from the second upper conductive layer. Therefore, the thin-film type solar cell device according to embodiments of the present invention may have a built-in bypass diode. In addition, a thin-film type solar cell device including a bypass diode may be manufactured simply and at low costs.

Description

Thin-film solar cell devices, thin-film solar cell modules, and methods for manufacturing them

[0001] The present invention relates to a thin film solar cell device, a thin film solar cell module, and a method for manufacturing the same, and more particularly, to a thin film solar cell device with a built-in bypass diode, a thin film solar cell module, and a method for manufacturing the same.

[0002] A solar cell module includes a plurality of solar cells connected in series and a bypass diode connected in parallel to one or more solar cells. When sunlight falls on the solar cells, photoelectric conversion generates and causes current to flow. At this time, a reverse voltage is applied to the bypass diode connected to the solar cells, so the bypass diode remains turned off. On the other hand, if some of the solar cells are defective and do not operate normally, or if some of the solar cells are shaded (shading), a forward voltage is applied to the bypass diode, turning it on and allowing current to flow through the bypass diode.

[0003] Accordingly, the current applied to the solar cell module is not applied to the solar cell that is not operating normally, but flows along the bypass diode connected to the solar cell that is not operating normally. Accordingly, even if a problem occurs in some of the multiple solar cells, the current generated in the remaining functioning solar cells is prevented from flowing and being blocked, thereby preventing the occurrence of solar cell module failure.

[0004] Solar cell modules including bypass diodes are divided into a type in which the solar cell and bypass diode are provided separately and the bypass diode is attached to the solar cell (external type), and a type in which the solar cell and bypass diode are formed together on the same substrate (built-in type).

[0005] In the case of the external type, the solar cell and bypass diode must be manufactured separately and then connected to the solar cell, which causes the process to be complicated and increases the cost.

[0006] Additionally, for embedded types, a bypass diode is manufactured simultaneously with the solar cell. Specifically, a lower conductive layer, a photoelectric conversion semiconductor layer, and an upper conductive layer are sequentially layered on a substrate, then etched using a photolithography process to form the solar cell and bypass diode. However, the photolithography process is extremely expensive. Consequently, the cost of forming a solar cell module increases.

[0007] (Prior art document) (Patent document 1) Korean registered patent KR2271899

[0008] The present invention provides a thin film solar cell device with a built-in bypass diode, a thin film solar cell module, and a method for manufacturing the same.

[0009] The present invention provides a thin-film solar cell device with a built-in bypass diode, a solar cell module, and a method for manufacturing the same, which can be manufactured at low cost.

[0010] A thin film solar cell device according to an embodiment of the present invention may include a substrate; a solar cell including a first lower conductive layer, a first semiconductor layer, and a first upper conductive layer sequentially stacked upward on the substrate; a connecting portion including a second lower conductive layer connected to the first lower conductive layer, a second semiconductor layer formed on the second lower conductive layer, and a second upper conductive layer formed on the second semiconductor layer so as to be connected to the second lower conductive layer; a bypass diode including a third upper conductive layer connected to the second upper conductive layer, and a third semiconductor layer and a third lower conductive layer sequentially stacked downward on the third upper conductive layer.

[0011] The solar cell may extend in a first horizontal direction on the substrate, the connecting portion and the bypass diode may be arranged in the first horizontal direction, and the direction in which the connecting portion and the bypass diode and the solar cell are arranged may be a second horizontal direction intersecting the first horizontal direction.

[0012] The solar cell includes a first lower pattern formed to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first semiconductor layer; and a first intermediate pattern formed to penetrate the first semiconductor layer in the thickness direction and formed of a material for the first upper conductive layer; and the connecting portion includes a second lower pattern formed between the second lower conductive layer and the third lower conductive layer and formed of a material for the second semiconductor layer; and a second intermediate pattern formed to penetrate the second semiconductor layer in the thickness direction and formed of a material for the second upper conductive layer; wherein the first lower pattern and the first intermediate pattern are arranged in a first horizontal direction, and the second lower pattern and the second intermediate pattern are arranged in a first horizontal direction, and the direction in which the first lower pattern and the first intermediate pattern are arranged in the order may be opposite to the direction in which the second lower pattern and the second intermediate pattern are arranged in the order.

[0013] The solar cell may include a first insulating pattern formed on an upper side of the first lower conductive layer and disposed on the outer side of the first lower pattern and the first intermediate pattern based on the first horizontal direction; and the connecting portion may include a second insulating pattern formed on an upper side of the second lower conductive layer and disposed on the outer side of the second lower pattern and the second intermediate pattern based on the first horizontal direction; and a third insulating pattern provided between the connecting portion, the bypass diode, and the solar cell based on the second horizontal direction.

[0014] The first to third insulating patterns may be formed as empty spaces or formed of an insulating material.

[0015] When one end of the one end and the other end of the substrate are referred to as one end and the other end as the other end, with respect to the first horizontal direction, the bypass diode may be arranged on one side of the connection portion, and the first lower pattern, the first intermediate pattern, and the first insulating pattern may be arranged in that order, with respect to the first horizontal direction, the first intermediate pattern may be arranged on one side of the first lower pattern, the first insulating pattern may be arranged on one side of the first intermediate pattern, and the second lower pattern, the second intermediate pattern, and the second insulating pattern may be arranged in that order, with respect to the first horizontal direction, the second intermediate pattern may be arranged on the other side of the second lower pattern, and the second insulating pattern may be arranged on the other side of the second intermediate pattern.

[0016] The first to third lower conductive layers may be formed of the same material, the first to third semiconductor layers may be formed of the same material, and the first to third upper conductive layers may be formed of the same material.

[0017]

[0018] A thin film solar cell module according to an embodiment of the present invention may include a plurality of battery parts including a substrate; a solar cell formed on the substrate; a connecting portion formed on the substrate to be connected to a lower conductive layer of the solar cell; and a bypass diode formed on the substrate to be connected to an upper conductive layer of the solar cell.

[0019] The solar cell of each of the plurality of battery units may include a first lower conductive layer, a first semiconductor layer, and a first upper conductive layer sequentially stacked in an upward direction on the substrate, and the connecting portion of each of the plurality of battery units may include a second lower conductive layer connected to the first lower conductive layer, a second semiconductor layer formed on the second lower conductive layer, and a second upper conductive layer formed on the second semiconductor layer so as to be connected to the second lower conductive layer, and the bypass diode of each of the plurality of battery units may include a third upper conductive layer connected to the second upper conductive layer, a third semiconductor layer sequentially stacked in a downward direction on the second upper conductive layer, and a third lower conductive layer.

[0020] A plurality of the above-described battery sections are arranged in a first horizontal direction, the solar cells extend in the first horizontal direction on the substrate, and in each of the above-described battery sections, the connecting portion and the bypass diode are arranged in the first horizontal direction, and in each of the above-described battery sections, the direction in which the connecting portion and the bypass diode and the solar cells are arranged may be a second horizontal direction intersecting the first horizontal direction.

[0021] The solar cell comprises: a first lower pattern formed to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first semiconductor layer; and a first intermediate pattern formed to penetrate the first semiconductor layer in the thickness direction and formed of a material for the first upper conductive layer; wherein the first lower pattern and the first intermediate pattern are arranged in a first horizontal direction, and the connecting portion comprises: a second lower pattern formed between the second lower conductive layer and the third lower conductive layer and formed of a material for the second semiconductor layer; And a second intermediate pattern formed to penetrate the second semiconductor layer in the thickness direction, and formed of a material for the second upper conductive layer; wherein the first lower pattern and the first intermediate pattern are arranged in a first horizontal direction, and the second lower pattern and the second intermediate pattern are arranged in a first horizontal direction, and the direction in which the first lower pattern and the first intermediate pattern are arranged in order and the direction in which the second lower pattern and the second intermediate pattern are arranged in order may be opposite.

[0022] The solar cell may include a first insulating pattern formed on an upper side of the first lower conductive layer and disposed on the outer side of the first lower pattern and the first middle pattern based on the first horizontal direction; the connecting portion may include a second insulating pattern formed on an upper side of the second lower conductive layer and disposed on the outer side of the second lower pattern and the second middle pattern based on the first horizontal direction; and each of the plurality of battery portions may include a third insulating pattern provided between the connecting portion and the bypass diode and the solar cell based on the second horizontal direction.

[0023] The first to third insulating patterns may be formed as empty spaces or formed of an insulating material.

[0024] When one end of the one end and the other end of the substrate are referred to as one end and the other end as the other end, with respect to the first horizontal direction, the bypass diode may be arranged on one side of the connection portion, and the first lower pattern, the first intermediate pattern, and the first insulating pattern may be arranged in that order, with respect to the first horizontal direction, the first intermediate pattern may be arranged on one side of the first lower pattern, the first insulating pattern may be arranged on one side of the first intermediate pattern, and the second lower pattern, the second intermediate pattern, and the second insulating pattern may be arranged in that order, with respect to the first horizontal direction, the second intermediate pattern may be arranged on the other side of the second lower pattern, and the second insulating pattern may be arranged on the other side of the second intermediate pattern.

[0025] The first to third lower conductive layers may be formed of the same material, the first to third semiconductor layers may be formed of the same material, and the first to third upper conductive layers may be formed of the same material.

[0026]

[0027] An embodiment of the present invention is a method for manufacturing a thin film solar cell device formed on a substrate, the thin film solar cell device including a solar cell, a connecting portion connected to a lower conductive layer of the solar cell, and a bypass diode in which an upper conductive layer is connected to the connecting portion, wherein the process for manufacturing the solar cell, the connecting portion, and the bypass diode may include a scribing process.

[0028] A method for manufacturing a thin-film solar cell device according to an embodiment of the present invention includes a step of preparing a substrate extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, and the step of manufacturing the solar cell, the connecting portion, and the bypass diode may include a step of forming a lower conductive layer on the substrate; a step of forming a lower groove by etching the lower conductive layer in a thickness direction using a scribing process; a step of forming a semiconductor layer capable of converting received sunlight into electricity on the lower conductive layer, and filling the lower groove with a material for the semiconductor layer to form a lower pattern; a step of etching the lower conductive layer in a thickness direction using a scribing process to form an intermediate groove so that the position in the first horizontal direction is different from that of the lower pattern; and a step of forming an upper conductive layer on the semiconductor layer, and filling the intermediate groove with a material for the upper conductive layer to form an intermediate pattern.

[0029] The process of forming the lower groove may include forming a first lower groove extending from one end of the substrate to the other end with respect to the second horizontal direction, and forming a second lower groove extending from the other end of the substrate to the one end, and when one end of the one end and the other end of the substrate, which are opposite ends of the substrate with respect to the first horizontal direction, is referred to as one side and the other end is referred to as the other side, in forming the first and second lower grooves, the first lower groove may be formed so as to be disposed on one side of the second lower groove, and the process of forming the lower pattern may include forming the first and second lower patterns by filling the semiconductor layer material into the first and second lower grooves.

[0030] The process of forming the intermediate groove may include a process of forming a first intermediate groove extending from one end of the substrate to the other end, and a process of forming a second intermediate groove extending from the other end of the substrate to one end, based on the second horizontal direction; and in forming the first and second intermediate grooves, the first intermediate groove may be arranged on one side of the first lower groove, and the second intermediate groove may be formed on the other side of the second lower groove, and the process of forming the intermediate pattern may include a process of filling the semiconductor layer material into the first and second intermediate grooves to form the first and second intermediate patterns.

[0031] The process for manufacturing the solar cell, the connecting portion, and the bypass diode includes: a process for forming a first insulating pattern on one side of the first intermediate pattern; and a process for forming a second insulating pattern on the other side of the second intermediate pattern; wherein the process for forming the first insulating pattern includes a process for forming a void on one side of the first intermediate pattern by etching the upper conductive layer and the semiconductor layer formed on one side of the first intermediate pattern in the thickness direction using a scribing process; wherein the process for forming the second insulating pattern includes a process for etching the upper conductive layer and the semiconductor layer formed on the other side of the second intermediate pattern in the thickness direction using a scribing process; wherein, in forming the first insulating pattern, it may be formed to extend from one end of the substrate to the other end based on the second horizontal direction, and in forming the second insulating pattern, it may be formed to extend from the other end of the substrate to the one end based on the second horizontal direction.

[0032] The process for manufacturing the solar cell, the connecting portion, and the bypass diode may include a process of forming a third insulating pattern extending in the first horizontal direction between the first lower pattern and the first intermediate pattern and the second lower pattern and the second intermediate pattern based on the second horizontal direction; and the process of forming the third insulating pattern may include a process of etching an upper conductive layer, a semiconductor layer, and an upper conductive layer between the first lower pattern and the first intermediate pattern and the second lower pattern and the second intermediate pattern in a thickness direction using a scribing process based on the second horizontal direction, thereby forming an empty space extending in the second horizontal direction.

[0033] The process of forming the first insulating pattern may include a process of filling an insulating material into a void formed on one side of the first intermediate pattern, the process of forming the second insulating pattern may include a process of filling an insulating material into a void formed on the other side of the second intermediate pattern, and the process of forming the third insulating pattern may include a process of filling an insulating material into a void extending in the second horizontal direction.

[0034]

[0035] An embodiment of the present invention is a method for manufacturing a solar cell module, which includes a plurality of battery sections formed on a substrate and having solar cells, a connecting portion connected to a lower conductive layer of the solar cell, and a bypass diode in which an upper conductive layer is connected to the connecting portion, wherein a process for manufacturing the plurality of battery sections may include a scribing process.

[0036] A method of manufacturing a plurality of battery parts may include: preparing a substrate extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, wherein the method comprises: forming a lower conductive layer on the substrate; etching the lower conductive layer in a thickness direction using a scribing process to form a plurality of lower grooves arranged in the first horizontal direction; forming a semiconductor layer capable of converting sunlight received into electricity on the lower conductive layer, and filling the lower grooves with a material for the semiconductor layer to form a plurality of lower patterns; etching the lower conductive layer in a thickness direction using a scribing process to form a plurality of intermediate grooves arranged in the first horizontal direction so that the positions of the lower patterns and the first horizontal direction are different; and forming an upper conductive layer on the semiconductor layer, and filling the upper conductive layer material into the plurality of intermediate grooves to form a plurality of intermediate patterns.

[0037] The process of forming a plurality of the lower grooves may include: a process of forming a plurality of first lower grooves, each extending from one end of the substrate to the other end based on a second horizontal direction, and being lined up in a first horizontal direction; a process of forming a plurality of second lower grooves, each extending from the other end of the substrate to one end based on a second horizontal direction, and being lined up in a first horizontal direction; wherein the number of the first lower grooves and the number of the second lower grooves are the same, and the first lower grooves and the second lower grooves are formed to be alternately arranged in the order of the first lower grooves and the second lower grooves from one end of the substrate to the other end based on the first horizontal direction; and the process of forming the lower pattern may include a process of filling the semiconductor layer material into the plurality of the first lower grooves and the plurality of the second lower grooves to form a plurality of first lower patterns and a plurality of second lower patterns.

[0038] The process of forming a plurality of intermediate grooves may include: a process of forming a plurality of first intermediate grooves, each extending from one end of the substrate toward the other end with respect to the second horizontal direction; a process of forming a plurality of second intermediate grooves, each extending from the other end of the substrate toward the one end with respect to the second horizontal direction; and, when one end of the one end and the other end, which are opposite ends of the substrate with respect to the first horizontal direction, is referred to as one side and the other end as the other side, the first intermediate groove may be formed on one side of the lower pattern set, and the second intermediate groove may be formed on the other side of the lower pattern set, based on a lower pattern set including a first lower pattern and a second lower pattern that are arranged adjacently among a plurality of first lower patterns and a plurality of second lower patterns. The process of forming the intermediate patterns may include a process of filling the semiconductor layer material into the plurality of first intermediate grooves and the plurality of second intermediate grooves to form a plurality of first intermediate patterns and a plurality of second intermediate patterns.

[0039] A process for manufacturing a plurality of the above-described battery parts includes a process for forming a first insulating pattern on one side of the first intermediate pattern; and a process for forming a second insulating pattern on the other side of the second intermediate pattern. The process for forming the first insulating pattern includes a process for forming a void on one side of the first intermediate pattern by etching the upper conductive layer and the semiconductor layer formed on one side of the first intermediate pattern in the thickness direction using a scribing process. The process for forming the second insulating pattern includes a process for etching the upper conductive layer and the semiconductor layer formed on the other side of the second intermediate pattern in the thickness direction using a scribing process. In forming the first insulating pattern, the second insulating pattern may be formed to extend from one end of the substrate to the other end based on the second horizontal direction, and in forming the second insulating pattern, the second insulating pattern may be formed to extend from the other end of the substrate to the one end based on the second horizontal direction.

[0040] The process for manufacturing a plurality of the above-described battery parts includes a process of forming a third insulating pattern extending in the first horizontal direction between the first lower pattern and the first middle pattern and the second lower pattern and the second middle pattern based on the second horizontal direction; and the process of forming the third insulating pattern may include a process of etching an upper conductive layer, a semiconductor layer, and an upper conductive layer between the first lower pattern and the first middle pattern and the second lower pattern and the second middle pattern in a thickness direction using a scribing process based on the second horizontal direction, thereby forming an empty space extending in the second horizontal direction.

[0041] The process of forming the first insulating pattern may include a process of filling an insulating material into a void formed on one side of the first intermediate pattern, the process of forming the second insulating pattern may include a process of filling an insulating material into a void formed on the other side of the second intermediate pattern, and the process of forming the third insulating pattern may include a process of filling an insulating material into a void extending in the second horizontal direction.

[0042] Thin film solar cell devices and thin film solar cell modules according to embodiments of the present invention may include built-in bypass diodes. Furthermore, thin film solar cell devices and thin film solar cell modules including bypass diodes can be manufactured simply and at low cost.

[0043] FIG. 1 is a three-dimensional diagram illustrating a thin-film solar cell module according to an embodiment of the present invention.

[0044] FIG. 2 is a drawing illustrating a cutaway view of area F of FIG. 1 to more specifically explain a solar cell according to an embodiment of the present invention.

[0045] FIG. 3 is a drawing for explaining the polarity of the solar cell and the bypass section in the second battery section illustrated in FIG. 2.

[0046] Figure 4 is a front view of Figure 1.

[0047] Figures 5 to 9 are process diagrams sequentially showing a method for manufacturing a thin-film solar cell module according to an embodiment of the present invention.

[0048] Figure 10 is a plan view of Figure 6.

[0049] Figure 11 is a plan view of Figure 8.

[0050] Figure 12 is a plan view of Figure 9.

[0051] Fig. 13 is a plan view of Fig. 1.

[0052] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention. To illustrate the embodiments of the present invention, the drawings may be exaggerated, and like reference numerals in the drawings represent like components.

[0053]

[0054] FIG. 1 is a three-dimensional view illustrating a thin-film solar cell module according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along area F of FIG. 1 to more specifically explain the solar cell according to an embodiment of the present invention. FIG. 3 is a drawing illustrating the polarity of the solar cell and the bypass section in the second battery section illustrated in FIG. 2. FIG. 4 is a front view of FIG. 1.

[0055]

[0056] The present invention relates to a thin-film solar cell device and a thin-film solar cell module, and more particularly, to a thin-film solar cell device and a thin-film solar cell module including a bypass diode. In other words, the present invention relates to a thin-film solar cell device and a thin-film solar cell module with a built-in bypass diode.

[0057] Thin-film solar cell devices and thin-film solar cell modules may be components of artificial satellites. Furthermore, the artificial satellites may be military satellites, such as reconnaissance satellites.

[0058] Referring to FIGS. 1 and 2, a thin-film solar cell module according to an embodiment of the present invention includes a thin-film solar cell section (200: 200a, 200b, 200c) having a substrate (100), solar cells (SC: SC1, SC2, SC3) formed on the substrate (100), and a bypass section (BP: BP1, BP2, BP3). In addition, the solar cell module may include a blocking section (not shown) installed on the upper portion of the bypass section (BP: BP1, BP2, BP3) to prevent sunlight from being incident thereon. Accordingly, sunlight may be incident on the solar cells (SC: SC1, SC2, SC3), and sunlight may be blocked from being received by the bypass section (BP: BP1, BP2, BP3). Here, the thin film type battery unit (200: 200a, 200b, 200c) may be referred to as a thin film type solar cell device.

[0059] These solar cell modules can be connected to a battery (not shown), and the current generated by the solar cell modules can be stored in the battery.

[0060] For convenience of explanation, the thin film battery parts (200: 200a, 200b, 200c) are briefly referred to as 'battery parts (200: 200a, 200b, 200c)' below.

[0061] The substrate (100) may be, for example, a substrate made of polyimide (PI). Of course, the substrate (100) is not limited to the above-described examples, and various substrates may be applied. For example, the substrate may be at least one of glass, ultra-thin glass (UTG), and space coverglass. Of course, the substrate is not limited to these, and various insulating materials may be used.

[0062] A thin film solar cell module may include a plurality of cell sections (200: 200a, 200b, 200c). In addition, the plurality of cell sections (200: 200a, 200b, 200c) may be arranged in at least one direction, for example, the plurality of cell sections (200: 200a, 200b, 200c) may be arranged in a first horizontal direction (X-axis direction).

[0063] In the above, it has been described that multiple battery units are arranged in one direction, for example, in the first horizontal direction (X-axis direction). However, this is not limited to this, and multiple battery units may be arranged in a second horizontal direction (Y-axis direction) that intersects or is perpendicular to the first horizontal direction (X-axis direction).

[0064] Hereinafter, the three battery sections (200a, 200b, 200c) are referred to as the first battery section (200a), the second battery section (200b), and the third battery section (200c) from one end of the substrate to the other end. It is merely an example that the solar cell module includes three battery sections (200a, 200b, 200c), and the battery sections may be provided in various numbers. That is, the solar cell module may be provided with various numbers of battery sections exceeding three, or with two or fewer battery sections.

[0065] Hereinafter, for the convenience of explanation, an example will be described in which a solar cell module includes three cell sections (200a, 200b, 200c) as illustrated in FIGS. 1 and 2. Then, the left end of the substrate (100) in the first horizontal direction (X-axis direction) is defined as one end, and the right end is defined as the other end. In addition, one end of the substrate (100) with respect to a reference target is defined as one side, and the other end of the substrate (100) is defined as the other end.

[0066] Each of the first to third battery sections (200a, 200b, 200c) includes a solar cell (SC: SC1, SC2, SC3) that can receive sunlight and convert it into electricity (photoelectric conversion), a bypass section (BP: BP1, BP2, BP3) connected to the solar cell (SC: SC1, SC2, SC3), and an insulating pattern (P) that is a blank space that can spatially divide the space between the solar cell (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3). h3 ) may be included.

[0067] As described above, each of the plurality of battery sections (200: 200a, 200b, 200c) includes a solar cell (SC: SC1, SC2, SC3), a bypass section (BP: BP1, BP2, BP3), and an insulating pattern (P h3 ) is included. To explain this again based on the solar cell module, the solar cell module includes a plurality of solar cells (SC: SC1, SC2, SC3), a plurality of bypass sections (BP: BP1, BP2, BP3), and an insulating pattern (P) provided between the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3). h3 ) is included.

[0068] A plurality of solar cells (SC: SC1, SC2, SC3) can be connected in series. In addition, in each battery section (200: 200a, 200b, 200c), the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3) can be connected in parallel. And in each battery section (200: 200a, 200b, 200c), the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3) can be arranged in the second horizontal direction (Y-axis direction), for example. That is, the first solar cell (SC1) and the first bypass section (BP1) can be arranged in the second horizontal direction (Y-axis direction) and connected in parallel. In the case of the second and third battery units (200b, 200c), the second and third solar cells (SC1, SC2) and the second and third bypass units (BP1, BP2) can be connected in parallel and arranged in the second horizontal direction (Y-axis direction).

[0069]

[0070] Hereinafter, the solar cell, bypass section, and insulation pattern constituting the battery section will be described with reference to FIGS. 1 to 3. For convenience of explanation, the end located opposite the second region of the solar cell among the two ends of the second horizontal direction (Y-axis direction) of the substrate (100) is defined as one end, and the end located opposite the first region is defined as the other end.

[0071] The solar cell (SC: SC1, SC2, SC3) includes a first lower conductive layer (210a), a first semiconductor layer (220a) formed on the first lower conductive layer (210a), a first upper conductive layer (230a) formed on the first semiconductor layer (220a), and a first lower pattern (P) formed of a material for the first semiconductor layer, connecting the first lower conductive layer (210a) and the first semiconductor layer (220a). b1 ), connecting the first semiconductor layer (220a) and the first upper conductive layer (230a), and forming a first intermediate pattern (P) made of a material for the first upper conductive layer c1 ) and the first lower pattern (P) based on the first horizontal directionb1 ) and the first intermediate pattern (P c1 ) is a blank space provided on the outside of the first insulating pattern (P) h1 ) may be included.

[0072] Here, the first semiconductor layer (220a) may be named as any one of a solar cell layer, a photoelectric conversion layer, or a light absorption layer.

[0073] The solar cells (SC: SC1, SC2, SC3) may include a first region (A1) extending in a first horizontal direction (X-axis direction) on the substrate (100) and a second region (A2) extending in a second horizontal direction (Y-axis direction) intersecting or orthogonal to the first horizontal direction (X-axis direction) from a part of the first region (A1). At this time, the second region (A2) may be arranged on the other side of the center of the first region (A1) in the first horizontal direction (X-axis direction). Accordingly, in each battery section (200a, 200b, 200c), the solar cells (SC1, SC2, SC3) may have a shape roughly like the Korean letter 'ㄱ'. The shapes of the solar cells (SC: SC1, SC2, SC3) described above are merely examples, and the shapes of the solar cells (SC: SC1, SC2, SC3) may be variously changed.

[0074] First insulation pattern (P h1 ) may be a hollow space or groove shape extending in the second horizontal direction (Y-axis direction). In addition, the first insulating pattern (P h1 ) can be formed to extend from one end of the second horizontal direction (Y-axis direction) of the substrate to the other end. The first insulating pattern (P h1 ) is the first intermediate pattern (P c1 ) can be placed on one side of the first insulating pattern (P h1 ) may be a hollow space or groove shape located on the upper side of the first lower conductive layer (210a). That is, among the first lower conductive layers (210a) of the solar cells SC: SC1, SC2, SC3), the first middle pattern (P c1 ) is placed on one side of the first insulating pattern (P h1) are. The upper conductive layer and semiconductor layers of two adjacently arranged solar cells are formed by a first insulating pattern (P h1 ) can be divided or separated.

[0075] The bypass section (BP: BP1, BP2, BP3) may include a connection section (IC: IC1, IC2, IC3) connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and a bypass diode (BD: BD1, BD2, BD3) connected to the connection section (IC: IC1, IC2, IC3).

[0076] The second region (A2) of the connecting portion (IC: IC1, IC2, IC3), the bypass diode (BD: BD1, BD2, BD3) and the solar cell (SC: SC1, SC2, SC3) may be arranged in one direction, for example, in the first horizontal direction (X-axis direction). At this time, the connecting portion (IC: IC1, IC2, IC3) may be arranged on the other side of the bypass diode (BD: BD1, BD2, BD3), and the second region (A2) of the solar cell (SC: SC1, SC2, SC3) may be arranged on the other side of the connecting portion (IC: IC1, IC2, IC3). In addition, a second insulating pattern (P) may be arranged between the connecting portion (IC: IC1, IC2, IC3) and the second region (A2). h2 ) can be placed.

[0077] The first region (A1) and the bypass portion (BP: BP1, BP2, BP3) of the solar cell (SC: SC1, SC2, SC3) may be arranged in the second horizontal direction (Y-axis direction). That is, the direction in which the connection portion (IC: IC1, IC2, IC3) and the bypass diode (BD: BD1, BD2, BD3) and the first region (A1) of the solar cell (SC: SC1, SC2, SC3) are arranged may be the second horizontal direction (Y-axis direction). In addition, a third insulating pattern (P) is provided between the first region (A1) of the solar cell (SC: SC1, SC2, SC3) and the bypass portion (BP: BP1, BP2, BP3). h3) can be placed.

[0078] When sunlight is received by solar cells (SC: SC1, SC2, SC3), current is generated and flows through photoelectric conversion. At this time, a reverse voltage is applied to the bypass diodes (BD: BD1, BD2, BD3) connected to the solar cells (SC: SC1, SC2, SC3), so the bypass diodes (BD: BD1, BD2, BD3) are kept turned off. On the other hand, if some of the plurality of solar cells (SC: SC1, SC2, SC3) are shaded or some of them do not operate normally, a forward voltage higher than the operating voltage is applied to the bypass diodes (BD: BD1, BD2, BD3) by other solar cells that are operating normally. Accordingly, the bypass diodes to which the forward voltage is applied are turned on, and current flows through the turned-on bypass diodes. In other words, current is not applied to the malfunctioning solar cell, but instead flows through the bypass diode connected to the malfunctioning solar cell. Accordingly, even if a problem occurs in some of the multiple solar cells, the phenomenon of the malfunctioning solar cell blocking the flow of current can be suppressed or prevented, thereby preventing the occurrence of solar cell module failure.

[0079] The connection part (IC: IC1, IC2, IC3) of each battery part (200: 200a, 200b, 200c) is formed between the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and the second lower conductive layer (210b), the second semiconductor layer (220b) formed on the second lower conductive layer (210b), the second upper conductive layer (230b) formed on the second semiconductor layer (220b), the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) and the second lower conductive layer (210b), and the second lower pattern (P) formed of a material for the second semiconductor layer (220b). b2), a second intermediate pattern (P) formed by penetrating the second semiconductor layer (220b) in the thickness direction so as to connect the second lower conductive layer (210b) and the second upper conductive layer (230b) and formed of a material for the second upper conductive layer c2 ) and the second insulating pattern (P), which is an empty space placed on the other side of the second intermediate pattern h2 ) may be included.

[0080] Second insulation pattern (P h2 ) may be a hollow space or groove shape extending in the second horizontal direction (Y-axis direction). In addition, the second insulating pattern (P h2 ) can be formed to extend from the other end of the second horizontal direction (Y-axis direction) of the substrate to one end. The second insulating pattern (P h2 ) can be placed between the second region (A2) of the solar cell (SC: SC1, SC2, SC3) and the connecting portion (IC: IC1, IC2, IC3). That is, the second insulating pattern (P h2 ) can be placed on the other side of the connection part (IC: IC1, IC2, IC3) or on one side of the second area (A2). More specifically, the second insulating pattern (P h2 ) may be provided between the second semiconductor layer (220b) and the second upper conductive layer (230b) of the connection portion (IC: IC1, IC2, IC3) and the first semiconductor layer (220a) and the first upper conductive layer (230a) of the second region (A2). In other words, the second insulating pattern (P h2 ) may be provided on the upper side of the lower conductive layer connecting the second lower conductive layer (210b) of the connection part (IC: IC1, IC2, IC3) and the first lower conductive layer (210a) of the second region (A2).

[0081] The bypass diode (BD: BD1, BD2, BD3) may include a third lower conductive layer (210c), a third semiconductor layer (220c) formed on the third lower conductive layer (210c), and a third upper conductive layer (230c) formed on the third semiconductor layer (220c) and connected to the second upper conductive layer (220b) of the connection section (IC: IC1, IC2, IC3).

[0082] Third insulation pattern (P h3 ) may be a hollow space or groove shape extending in the first horizontal direction (X-axis direction). The third insulating pattern (P h3 ) can be placed between the first region (A1) of the solar cell (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3). That is, the third insulating pattern (P h3 ) can be placed between the connection part (IC: IC1, IC2, IC3) and the bypass diode (BD: BD1, BD2, BD3) and the first region (A1). More specifically, the third insulating pattern (P h3 ) may be provided between the second and third lower conductive layers (210b, 210c), the second and third semiconductor layers (220b, 220c), the second and third upper conductive layers (230b, 230c) of the bypass section (BP: BP1, BP2, BP3) and the first region (A1). This third insulating pattern (P h3 ) may expose the upper surface of the substrate (100) between the first region (A1) and the bypass section (BP: BP1, BP2, BP3).

[0083] The first to third lower conductive layers (210a, 210b, 210c) may be formed of a material having electrical conductivity. And the first to third lower conductive layers (210a, 210b, 210c) may be formed of the same material. The first to third lower conductive layers (210a, 210b, 210c) may be formed of a metal, for example, molybdenum (Mo). Of course, the first to third lower conductive layers (210a, 210b, 210c) are not limited to the examples described above and may be formed of various materials having electrical conductivity. For example, the first to third lower conductive layers (210a, 210b, 210c) may be formed of a material having light transmittance and electrical conductivity. That is, the first to third lower conductive layers (210a, 210b, 210c) may be formed of a TCO (Transparent Conductive Oxide), and may be formed of, for example, at least one of ITO (Indium tin oxide) and IZO (Indium Zinc Oxide).

[0084] The first to third lower conductive layers (210a, 210b, 210c) can be formed using at least one of, for example, a sputtering deposition method, a thermal evaporation method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a coating method, a printing method, and an inkjet method. In addition, a slot-die coating method can be used as the coating method. Of course, the first to third lower conductive layers (210a, 210b, 210c) are not limited to the above-described examples, and can be formed using various methods.

[0085] The first to third semiconductor layers (220a, 220b, 220c) are layers that can absorb sunlight and convert it into electricity, and may have a structure in which multiple layers are stacked. That is, the first to third semiconductor layers (220a, 220b, 220c) may have a structure in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. At this time, the first to third semiconductor layers (220a, 220b, 220c) may have a PN stacked structure in which a p-type semiconductor layer is an upper layer and an n-type semiconductor layer is a lower layer, or an NP stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer. As another example, that is, the first to third semiconductor layers (220a, 220b, 220c) may have a structure in which an i-type semiconductor layer is inserted between a p-type semiconductor layer and an n-type semiconductor layer. At this time, the first to third semiconductor layers (220a, 220b, 220c) may be a PiN stacked structure in which a p-type semiconductor layer is the upper layer and an n-type semiconductor layer is the lower layer, or a NiP stacked structure in which an n-type semiconductor layer is the upper layer and a p-type semiconductor layer is the lower layer.

[0086] The first to third semiconductor layers (220a, 220b, 220c) may be formed of a CIGS compound, which is a compound containing copper (Cu), indium (In), gallium (Ga), and cerium (Se). The first to third semiconductor layers (220a, 220b, 220c) are not limited to being formed of a CIGS compound as described above, and may be formed of, for example, a perovskite structure semiconductor. The first to third semiconductor layers (220a, 220b, 220c) may be formed, for example, by using at least one of a thermal evaporation method, a chemical vapor deposition (CVD), an atomic layer deposition (ALD) method, a sputtering deposition method, a coating method, a printing method, and an inkjet method. In addition, a slot-die coating method may be used as the coating method. Of course, the semiconductor layers are not limited to the examples described above, and may be formed using various methods.

[0087] The first to third semiconductor layers (220a, 220b, 220c) can be formed with the same structure and material.

[0088] The first lower semiconductor layer (220a) and the first upper semiconductor layer (240a) described above may be named as any one of a solar cell layer, a photoelectric conversion layer, or a light absorption layer.

[0089]

[0090] As described above, the first semiconductor layer (220a) of the solar cell (SC: SC1 to SC3) may be named as any one of a solar cell layer, a photoelectric conversion layer, and a light absorption layer. In addition, as described above, the second semiconductor layer (220b) of the connecting portion (IC: IC1 to IC3) and the third semiconductor layer (220c) of the bypass diode (BD: BD1 to BD3) are formed of the same material as the first semiconductor layer (220a) of the solar cell. Therefore, each of the second semiconductor layer (220b) of the connecting portion (IC: IC1 to IC3) and the third semiconductor layer (220c) of the bypass diode (BD: BD1 to BD3) may be named as any one of a solar cell layer, a photoelectric conversion layer, and a light absorption layer. However, the second semiconductor layer (220b) of the connection part (IC: IC1 to IC3) and the third semiconductor layer (220c) of the bypass diode (BD: BD1 to BD3) may be layers that do not function as solar cells due to reasons such as blocking sunlight or an electrical short circuit.

[0091] The first to third upper conductive layers (230a, 230b, 230c) may be formed of a material that is transparent to sunlight and has electrical conductivity. In addition, the first to third upper conductive layers (230a, 230b, 230c) may be formed of the same material. For example, the first to third upper conductive layers (230a, 230b, 230c) may be formed by depositing either ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Of course, the first to third upper conductive layers (230a, 230b, 230c) are not limited to the above-described examples and may be formed of various materials that are transparent to sunlight and have electrical conductivity. The first to third upper conductive layers (230a, 230b, 230c) may be formed, for example, by a deposition method. For example, the first to third upper conductive layers (230a, 230b, 230c) can be formed using at least one of a sputtering deposition method, a thermal evaporation method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, a coating method, a printing method, and an inkjet method. In addition, the coating method can use, for example, a slot-die coating method. Of course, the first to third upper conductive layers (230a, 230b, 230c) are not limited to the above-described examples, and can be formed using various methods.

[0092] As described above, each of the solar cells (SC: SC1, SC2, SC3) and the bypass portion (BP: BP1, BP2, BP3) includes a lower conductive layer (210: 210a, 210b, 210c), a semiconductor layer (220: 220a, 220b, 220c), an upper conductive layer (230: 230a, 230b, 230c), and a lower pattern (P b :P b1 , P b2) and intermediate pattern (P c :P c1 , P c2 ) is included. And, the solar cell (SC: SC1, SC2, SC3) comprises a first lower conductive layer (210a), a first semiconductor layer (220a), a first upper conductive layer (230a), and a first lower pattern (P b1 ) and the first intermediate pattern (P c1 ) and the second and third lower conductive layers (210b, 210c), the second and third semiconductor layers (220b, 220c), the second and third upper conductive layers (230b, 230c), the second lower pattern (P) constituting the bypass section (BP: BP1, BP2, BP3) b2 ) and the second intermediate pattern (P c2 ) are of the same material. In addition, the first to third lower conductive layers (210a, 210b, 210c) are formed simultaneously or together, and the first to third semiconductor layers (220a, 220b, 220c) and the first and second lower patterns (P b1 , P b2 ) are formed simultaneously or together, and the first to third upper conductive layers (230a, 230b, 230c) and the first and second intermediate patterns (P c1 , P c2 ) are formed simultaneously or together. Here, forming simultaneously or together can mean forming through the same process at the same time.

[0093] Hereinafter, the solar cells (SC) of the first to third battery units (200a, 200b, 200c) are named as the first to third solar cells (SC1, SC2, SC3), and the bypass units (BP) are named as the first to third bypass units (BP1, BP2, BP3). In addition, the bypass diodes (BD) of the first to third bypass units (BP1, BP2, BP3) are named as the first to third bypass diodes (BD1, BD2, BD3), and the connecting units (IC) are named as the first to third connecting units (IC1, IC2, IC3).

[0094] In the solar cell section, the solar cells (SC: SC1, SC2, SC3) and the bypass section (BP: BP1, BP2, BP3) must be connected with opposite polarities. To this end, in the embodiment, a connection section (IC: IC1, IC2, IC3) connecting the solar cells (SC: SC1, SC2, SC3) and the bypass diode (BD: BD1, BD2, BD3) is formed. That is, a connection section (IC: IC1, IC2, IC3) connecting the first lower conductive layer (210a) of the solar cells (SC: SC1, SC2, SC3) and the third upper conductive layer (230c) of the bypass diode (BP: BP1, BP2, BP3) is formed between the solar cells (SC: SC1, SC2, SC3) and the bypass diode (BP: BP1, BP2, BP3).

[0095] For this purpose, the first sub-pattern (P) of the solar cell (SC: SC1, SC2, SC3) b1 ) and the first intermediate pattern (P c1 ) and the second sub-pattern (P) of the connection (IC: IC1, IC2, IC3) in the listed direction b2 ), second intermediate pattern (P c2 ) are formed so that the directions in which they are listed are different. In addition, the first sub-pattern (P) of the solar cell (SC: SC1, SC2, SC3) b1 ), first intermediate pattern (P c1 ) and the first insulation pattern (P h1 ) and the second sub-pattern (P) of the connection part (IC: IC1, IC2, IC3) b2 ), second intermediate pattern (P c2 ), second insulation pattern (P h2 ) are formed so that the listed directions are opposite.

[0096] Referring to Fig. 2, a more specific example will be described, for example, of the first sub-pattern (P) of the solar cell (SC: SC1, SC2, SC3) b1 ) and the first intermediate pattern (P c1 ) are listed in the first horizontal direction (X-axis direction). In addition, the first intermediate pattern (P c1) and the first insulation pattern (P h1 ) are listed in the first horizontal direction (X-axis direction). At this time, the first lower pattern (P) is arranged from the other end of the substrate (100) to one end. b1 ), first intermediate pattern (P c1 ), first insulation pattern (P h1 ) are listed in order. That is, the first sub-pattern (P b1 ) on one side of the first intermediate pattern (P c1 ) is placed, and the first intermediate pattern (P c1 ) on one side of the first insulating pattern (P h1 ) is placed.

[0097] The second sub-pattern (P) of the connection (IC: IC1, IC2, IC3) b2 ), second intermediate pattern (P c2 ) and the second insulation pattern (P h2 ) are listed in the first horizontal direction (X-axis direction). However, the second lower pattern (P b2 ), second intermediate pattern (P c2 ) and the second insulation pattern (P h2 ) is listed in the first sub-pattern (P) described above. b1 ), first intermediate pattern (P c1 ), first insulation pattern (P h1 ) is the opposite order. That is, from one end of the substrate (100) to the other end, the second lower pattern (P b2 ), second intermediate pattern (P c2 ) and the second insulation pattern (P h2 ) are listed in order. That is, the second sub-pattern (P b2 ) on the other side of the second intermediate pattern (P c2 ) is placed, and the second intermediate pattern (P c2 ) on the other side of the second insulating pattern (P h2 ) is placed.

[0098] The first insulating pattern (P) formed in this way h1) are separated from each other, and the first upper conductive layers (230a) of the adjacently arranged solar cells are separated from each other, and the first semiconductor layers (220a) are separated. In addition, in each solar cell (SC: SC1, SC2, SC3), the first lower conductive layer (210a) is separated from the first lower pattern (P b1 ) is divided into two regions, and the two regions are connected to different conductive layers. That is, the first lower pattern (P) among the first lower conductive layers (210a) of the solar cell (SC: SC1, SC2, SC3) b1 ) is positioned on one side of the first lower conductive layer (210a) protrudes or extends to one side of the first semiconductor layer (220a) and is connected to the first lower conductive layer (210a) of the solar cell positioned on one side of the solar cell. In addition, the first lower conductive layer (210a) protrudes or extends to one side of the first semiconductor layer (220a) and may extend in the second horizontal direction (Y-axis direction) and be connected to the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3). In addition, the first lower pattern (P) of the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) b1 ) is connected to the second lower conductive layer (210b) of the connecting portion (IC: IC1, IC2, IC3). And, the first lower pattern (P) of the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) b1 ) is connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) located on the other side of the solar cell (SC: SC1, SC2, SC3). The second upper conductive layer (230b) and the second semiconductor layer (220b) of the connection portion (IC: IC1, IC2, IC3) are connected to the second insulating pattern (P h2) is divided into the first semiconductor layer (220a) and the first upper conductive layer (230a) of the solar cell (SC: SC1, SC2, SC3). In addition, the second upper conductive layer (230b) of the connection part (IC: IC1, IC2, IC3) is divided into the second intermediate pattern (P c2 ) is connected to the second lower conductive layer (210b), and the second upper conductive layer (230b) is connected to the third upper conductive layer (230c) of the bypass diode (BD: BD1, BD2, BD3). At this time, the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) is connected to the second lower pattern (P b2 ) is separated from the second lower conductive layer (210b) of the connecting portion (IC: IC1, IC2, IC3) and connected to the first lower conductive layer (210a) of the solar cell of another battery portion arranged adjacently.

[0099] The first sub-pattern (P) as described above b1 ), first intermediate pattern (P c1 ), first insulation pattern (P h1 ) are listed in the direction and the second sub-pattern (P b2 ), second intermediate pattern (P c2 ), second insulation pattern (P h2 ) By making the listed directions opposite, the solar cells (SC: SC1, SC2, SC3) and the bypass diodes (BD: BD1, BD2, BD3) can have opposite polarities.

[0100] The second battery part will be described in more detail with reference to FIGS. 1 to 3, for example. The second battery part (200b) includes a first insulating pattern (P h1 ) are spatially separated from the first and third battery units arranged adjacent to each other. In addition, referring to FIG. 3, the first lower conductive layer (210a) of the second solar cell (SC2) is formed by the first lower pattern (P b1) is divided into two regions, and the two regions are connected to different lower conductive layers. That is, the first lower pattern (P) of the first lower conductive layer (210a) of the second solar cell (SC2) b1 ) is connected to the first lower conductive layer (210a) of the first solar cell (SC1) and the third lower conductive layer (210c) of the second bypass diode (BD2). In addition, the first lower pattern (P) of the first lower conductive layer (210a) of the second solar cell (SC2) b1 ) is connected to the second lower conductive layer (210b) of the second connecting portion (IC2). In addition, the first lower pattern (P) of the first lower conductive layer (210a) of the second solar cell (SC2) b1 ) is connected to the first lower conductive layer (210a) of the third solar cell (SC3). The second upper conductive layer (230b) and the second semiconductor layer (220b) of the second connecting portion (IC2) are connected to the second insulating pattern (P h2 ) is divided from the first semiconductor layer (220a) and the first upper conductive layer (230a) of the second solar cell (SC2). In addition, the second upper conductive layer (230b) of the second connecting portion (IC2) is divided from the second intermediate pattern (P c2 ) is connected to the second lower conductive layer (210b) by the second upper conductive layer (230b), and the second upper conductive layer (230b) is connected to the third upper conductive layer (230c) of the second bypass diode (BD2). At this time, the third lower conductive layer (210c) of the second bypass diode (BD2) is connected to the second lower pattern (P b2 ) is separated from the second lower conductive layer (210b) of the second connecting portion (IC2) and connected to the first lower conductive layer (210a) of the first solar cell (SC1).

[0101] Accordingly, the polarity of the second solar cell (SC2) and the polarity of the second bypass diode (BD2) may be opposite. More specifically, when sunlight is received by the first semiconductor layer (220a) of the second solar cell (SC2), the first lower pattern (P) of the second solar cell (SC2) b1 ) may have a positive (+) polarity, and the first upper conductive layer (230a) may have a negative (-) polarity. Accordingly, the second lower conductive layer (210b) connected to the first lower conductive layer (210a) of the second solar cell (SC2) among the second connecting portions (IC2) may have a positive (+) polarity, and the second middle pattern (p) connected to the second lower conductive layer (210b) may have a positive (+) polarity. c2 ) and the second upper conductive layer (230b) also have a positive (+) polarity. The second upper conductive layer (230b) of the second connector (IC2) is connected to the third upper conductive layer (230c) of the second bypass diode (BD2). Accordingly, the third upper conductive layer (230c) of the second bypass diode (BD2) has a positive (+) polarity, and the third lower conductive layer (210c), which faces the third upper conductive layer (230c) with the third semiconductor layer (220c) interposed therebetween, has a negative (-) polarity.

[0102] In this way, the first sub-pattern (P) of the second solar cell (SC2) b1 ) has a positive (+) polarity, and the third lower conductive layer (210c) of the second bypass diode (BD2) has a negative (-) polarity, so the polarities are opposite. In addition, the first upper conductive layer (230a) of the second solar cell (SC2) has a negative (-) polarity, and the third upper conductive layer (230c) of the second bypass diode (BD2) has a positive (+) polarity, so the polarities are opposite. In addition, the first lower pattern (P) of the second solar cell (SC2) b1 ) both have a negative polarity. Accordingly, the first lower pattern (P) of the second solar cell (SC2) b1) may be a dead area. That is, the first sub-pattern (P) of the second solar cell (SC2) b1 ) may not cause photoelectric conversion in some areas on one side of the battery, and may cause photoelectric conversion in other areas, generating current but causing a short circuit so that the current cannot flow to the battery and is dissipated.

[0103] The polarities of the first and third solar cells (SC1, SC2) of the first and third battery units (200a, 200c) are the same as the polarity of the second solar cell (SC2), the polarities of the first and third connectors (IC1, IC2) are the same as the polarity of the second connector (IC2), and the polarities of the first and third bypass diodes (BD1, BD3) are the same as the polarity of the second bypass diode (BD2).

[0104] In this way, in the embodiment, the first sub-pattern (P) is provided in each battery section. b1 ), first intermediate pattern (P c1 ), first insulation pattern (P h1 ) are listed in the direction and the second sub-pattern (P b2 ), second intermediate pattern (P c2 ) and the second insulation pattern (P h2 ) are formed so that the listed directions are opposite. That is, as in the example described above, the first sub-pattern (P b1 ), first intermediate pattern (P c1 ), first insulation pattern (P h1 ) are arranged toward one end of the substrate in order, and the second lower pattern (P b2 ), second intermediate pattern (P c2 ) and the second insulation pattern (P h2)) are arranged in order toward the other end of the substrate. In addition, the second lower conductive layer (210b) of the connection portion (IC: IC1, IC2, IC3) is connected to the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3), and the second upper conductive layer (230b) of the connection portion (IC: IC1, IC2, IC3) is connected to the third upper conductive layer (230c) of the bypass diode (BD: BD1, BD2, BD3).

[0105] Therefore, the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) and the second lower conductive layer (210b) of the connection part (IC: IC1, IC2, IC3), the second intermediate pattern (P b2 ), the second upper conductive layer (230b) may have the same polarity. In addition, due to this, the third upper conductive layer (230c) of the bypass diode (BD: BD1, BD2, BD3) may have the same polarity as the second lower conductive layer (210b) of the connection (IC: IC1, IC2, IC3) but may have the opposite polarity to the first upper conductive layer (230a) of the solar cell (SC: SC1, SC2, SC3). Accordingly, the polarity of the third lower conductive layer (210c) of the bypass diode (BD: BD1, BD2, BD3) and the polarity of the first lower conductive layer (210a) of the solar cell (SC: SC1, SC2, SC3) may be opposite. Additionally, the polarity of the third upper conductive layer (230c) of the bypass diode (BD: BD1, BD2, BD3) and the polarity of the first upper conductive layer (230a) of the solar cell (SC: SC1, SC2, SC3) may be opposite.

[0106]

[0107] Hereinafter, with reference to FIG. 4, when a failure occurs in any one of a plurality of solar cells (SC: SC1, SC2, SC3), the flow of current in the solar cells (SC: SC1, SC2, SC3), the connectors (IC: IC1, IC2, IC3), and the bypass diodes (BP: BP1, BP2, BP3) will be described. At this time, a situation in which a second solar cell (SC2) among the plurality of solar cells (SC: SC1, SC2, SC3) fails will be described as an example. In FIG. 4, arrows (→, ←, ↑, ↓, etc.) indicate a situation in which current flows, and the direction of the arrows indicates the direction in which current flows. In addition, 'X' in FIG. 4 indicates that the movement of current is blocked.

[0108] For example, the current can flow from the third solar cell (SC3) to the second solar cell (SC2). That is, the current can flow through the first lower conductive layer (210a), the first lower semiconductor layer (220a), the first middle conductive layer (230a), the first upper semiconductor layer (240a), the first upper conductive layer (250a), and the first upper pattern (P) of the third solar cell (SC3). t1 ) can be moved to the first lower conductive layer (210a) of the second solar cell (SC2).

[0109] At this time, since the second solar cell (SC2) is in an abnormal state, the current movement from the first lower conductive layer (210a) to the first lower semiconductor layer (220a) is blocked, and the current moves to the first solar cell (SC1) by bypassing the second bypass diode (BD2).

[0110] To be more specific, since a reverse voltage is applied to the first and third bypass diodes (BD1, BD2) connected to the first and third solar cells (SC1, SC3) that are operating normally, the first and third bypass diodes (BD1, BD2) are kept in a turned-off state. On the other hand, since the second solar cell (SC2) is not operating normally, a forward voltage higher than the operating voltage is applied to the second bypass diode (BD2) by the first and third solar cells (SC1, SC3) that are operating normally. Accordingly, the second bypass diode (BD2) to which the forward voltage is applied is turned on, and current flows through the turned-on second bypass diode (BD2). That is, the current is not applied to the first semiconductor layer (220a) of the second solar cell (SC2) that is not operating normally, but bypasses the second bypass diode (BD2) connected to the second solar cell (SC2) and moves to the first lower conductive layer (210a) of the first solar cell (SC1). This will be described in more detail with reference to FIG. 4. The current that has moved to the first lower conductive layer (210a) of the second solar cell (SC2) does not move to the first semiconductor layer (220a), but moves along the second connecting portion (IC2) and the second bypass diode (BD2) connected to the second solar cell (SC2) and moves to the first lower conductive layer (210a) of the first solar cell (SC1). That is, the current is applied to the second lower conductive layer (210b) of the second connecting portion (IC2), the second intermediate pattern (P c2 ), the second upper conductive layer (230b) and moves to the third upper conductive layer (230c) of the second bypass diode (BD2). Then, the current moves to the first solar cell (SC1) through the third semiconductor layer (220c) and the third lower conductive layer (210c) of the second bypass diode (BD2).

[0111] In this way, since an abnormality has occurred in the second solar cell (SC2), the current does not pass through the second solar cell (SC2), but instead bypasses the second connector (IC2) and the second bypass diode (BD2) and moves to the first solar cell (SC1). Accordingly, even if a problem occurs in some of the plurality of solar cells, the phenomenon of the solar cell in which the problem occurred blocking the flow of current can be suppressed or prevented, and thus, the occurrence of a defect in the solar cell module can be prevented.

[0112]

[0113] In the above, the first to third insulating patterns (P h1 , P h2 , P h2 ) is formed as an empty space. That is, the first to third insulating patterns (P h1 , P h2 , P h2 ) is an example of an empty space that is not filled with a separate material or filled with air. However, the first to third insulating patterns (P h1 , P h2 , P h2 ) can be formed of an insulating material. That is, the first to third insulating patterns (P h1 , P h2 , P h2 ) can also be formed by filling, depositing, or applying an insulating material in the empty space as described above. The first to third insulating patterns (P h1 , P h2 , P h2 ) is not particularly limited, and various materials having insulating properties can be used.

[0114]

[0115] In addition, the above described solar cells (SC: SC1, SC2, SC3) have a shape that extends to a first region (A1) extending in a first horizontal direction (X-axis direction) and a second region (A2) extending in a second horizontal direction (Y-axis direction). That is, the solar cells (SC: SC1, SC2, SC3) were described above as having the shape of the Korean letter 'ㄱ' as an example. However, the shape of the solar cells (SC: SC1, SC2, SC3) is not limited to the example of the Korean letter 'ㄱ' shape, and may be changed to various shapes. For example, the solar cell (SC: SC1, SC2, SC3) may include a first region (A1) extending in a first horizontal direction (X-axis direction), a second region (A2) extending in a second horizontal direction (Y-axis direction) from the other end of the first region (A1) based on the first horizontal direction (X-axis direction) and having one end connected to the first region (A1), and a third region (not shown) extending in the first horizontal direction (X-axis direction) from the other end of the second region (A2) so as to face the first region (A1) in the second horizontal direction (Y-axis direction). Accordingly, the solar cell (SC: SC1, SC2, SC3) may resemble the shape of the Korean consonant 'ㄷ'.

[0116]

[0117] Figures 5 to 9 are process diagrams sequentially showing a method for manufacturing a thin-film solar cell module according to an embodiment of the present invention. Figure 10 is a plan view of Figure 6, Figure 11 is a plan view of Figure 8, Figure 12 is a plan view of Figure 9, and Figure 13 is a plan view of Figure 1.

[0118] Hereinafter, a method for manufacturing a solar cell module according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2, and FIGS. 5 to 13. Any content that overlaps with the previously described content will be omitted or briefly described.

[0119] First, a substrate (100) is prepared. For example, a substrate (100) made of polyimide (PI) is prepared. Then, a lower conductive layer (210) is formed on the substrate. For example, molybdenum (Mo) can be deposited on the substrate (100) to form the lower conductive layer (210).

[0120] Next, as shown in Fig. 5, a plurality of lower grooves (H) are formed that penetrate the lower conductive layer (210) in the thickness direction (Z-axis direction). b ) is formed. That is, the first lower groove (H) extends from one end to the other end based on the second horizontal direction (Y-axis direction) of the lower conductive layer (210). b1 ) is provided, and the second lower groove (H) is extended from the other end to one end. b2 ) is provided. And in the second horizontal direction (Y-axis direction), the first lower groove (H) is provided in the extended length. b1 ) is the length of the second lower groove (H b1 ) is formed to be longer than the first lower groove (H). Of course, the first lower groove (H) b1 ) compared to the extended length of the second lower groove (H b1 ) is long in length or the first lower groove (H) b1 ) and the second lower groove (H b1 ) may have the same extension length.

[0121] First lower home (H b1 ) and the second lower groove (H b2 ) are provided in multiples, and can be provided in the same number. In addition, the first lower groove (H b1 ) and the second lower groove (H b2 ) can be formed to be alternately arranged. The first lower groove (H) is formed in the direction toward the other end based on the first horizontal direction (X-axis direction) of the substrate (100). b1 ), second lower groove (H b2 ), first lower groove (H b1 ), second lower groove (H b2 ), first lower groove (H b1 ), second lower groove (H b2) are formed in the order of . In addition, two first lower grooves (H) are formed based on the first horizontal direction (X-axis direction). b1 ) located between the second lower groove (H b2 ) is a first lower groove (H) arranged relatively adjacent to one end of the substrate (100). b1 ) can be formed to be positioned more closely.

[0122] First and second lower grooves (H b1 , H b2 ) can be formed using a scribing method, for example, can be formed using a scribing etching method using a laser. That is, the first and second lower grooves (H) are formed by etching the lower conductive layer (210) using a laser scribing etching method. b1 , H b2 ) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0123]

[0124] Next, a semiconductor layer (220) is formed on the lower conductive layer (210) as shown in FIGS. 6 and 10. At this time, for example, the semiconductor layer (220) may be formed using a CIGS compound, which is a compound containing copper (Cu), indium (In), gallium (Ga), and cerium (Se). In addition, the semiconductor layer may be formed in a PN stacked structure in which an n-type semiconductor layer is an upper layer and a p-type semiconductor layer is a lower layer.

[0125] When a semiconductor layer (220) is formed on a lower conductive layer (210), a material for the semiconductor layer is formed in a plurality of first lower grooves (H) provided in the lower conductive layer (210). b1 ) and multiple second lower grooves (H b1 ) can be filled or introduced into the interior of the first lower groove (H). In this way, a plurality of first lower grooves (Hb1 ) is formed by filling or introducing a semiconductor layer material into the first lower pattern (P b1 ) and multiple second lower grooves (H b2 ) is filled with a semiconductor layer material and deposited as a second sub-pattern (P b2 )am.

[0126] Here, when a semiconductor layer (220) is formed on the lower conductive layer (210), the material for the semiconductor layer is formed in the first lower groove (H b1 ) and the second lower groove (H b1 ) is not a separately performed process. That is, when a semiconductor layer (220) is formed on the lower conductive layer (210), the semiconductor layer material is formed not only on the lower conductive layer (210) but also on the first lower groove (H b1 ) and the second lower groove (H b1 ) are filled with the first and second sub-patterns (P b1 , P b2 ) is formed.

[0127] Below are multiple first sub-patterns (P b1 ) and multiple second sub-patterns (P b2 ), one first sub-pattern (P) arranged adjacently or adjacently b1 ) and the second sub-pattern (P b2 ) as a group of 'sub-pattern sets (S b ) is named as '. In the embodiment, three first sub-patterns (P b1 ) and three second sub-patterns (P b2 ) is provided, so three sub-pattern sets (1S b , 2S b , 3S b ) is provided. Below, for the three lower pattern sets, the first lower pattern set (1S) is sequentially arranged from one end to the other end of the substrate (100). b ), second sub-pattern set (2S b ), 3rd sub-pattern set (3S) b ) is named.

[0128] Next, as shown in Fig. 7, a plurality of grooves (hereinafter, intermediate grooves (H)) penetrating the semiconductor layer (220) in the thickness direction (Z-axis direction) c )) is formed. That is, the first middle groove (H) extends from one end to the other end based on the second horizontal direction (Y-axis direction) of the semiconductor layer (220). c1 ) is provided, and the second middle groove (H) is extended from the other end to one end. c2 ) is provided. The first middle groove (H c1 ) and the second intermediate groove (H c2 ) are provided in multiples, and can be provided in the same number. And in the length extended in the second horizontal direction (Y-axis direction), the first middle groove (H c1 ) is the same length as the first lower pattern (Hb1), and the second middle groove (H c2 ) is the length of the second lower pattern (H b2 ) is preferably formed to be the same length.

[0129] 1st middle groove (H c1 ), the first sub-pattern set (1S b ) of the second lower pattern set (2S) b ) one side and third lower pattern set (3S) b ) on each side of the first intermediate groove (H c1 ) is prepared. Accordingly, the first sub-pattern set (1S b ) of the first lower groove (H b1 ) on one side of the first intermediate groove (H c1 ) is provided, and the second sub-pattern set (2S b ) of the first lower groove (H b1 ) on one side of the first middle groove (H c1 ) is provided, and the third sub-pattern set (3S b ) of the first lower groove (H b1 ) on one side of the first middle groove (H c1 ) is provided. In addition, the second middle groove (H c2 ), the first sub-pattern set (1S b ) of the other side, the second lower pattern set (2S)b ) of the other side and third lower pattern set (3S) b ) on each side of the second middle groove (H c2 ) is prepared. Accordingly, the first sub-pattern set (1S b ) of the second lower groove (H b2 ) Second center groove (H) on the other side c2 ) is provided, and the second sub-pattern set (2S b ) of the second lower groove (H b2 ) Second center groove (H) on the other side c2 ) is provided, and the third sub-pattern set (3S b ) of the second lower groove (H b2 ) Second center groove (H) on the other side c2 ) is provided.

[0130] First and second intermediate grooves (H c1 , H c2 ) can be formed using a scribing method, for example, can be formed by a scribing etching method using a laser. That is, the semiconductor layer is etched using a laser scribing etching method to form the first and second intermediate grooves (H c1 , H c2 ) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0131] Next, as shown in FIGS. 8 and 11, an upper conductive layer (230) is formed on the semiconductor layer (220). At this time, for example, ITO is laminated on the semiconductor layer (220) to form the upper conductive layer (230).

[0132] When the upper conductive layer (230) is formed on the semiconductor layer (220), the material for the upper conductive layer is formed in the plurality of first intermediate grooves (H) provided in the semiconductor layer (220). c1 ) and multiple second intermediate grooves (H c2) is also filled or introduced into the interior. In this way, a plurality of first intermediate grooves (H c1 ) is filled and formed as a first intermediate pattern (P c1 ) and multiple second intermediate grooves (H c2 ) is filled with a second intermediate pattern (P c2 ) becomes.

[0133] Here, when the upper conductive layer (230) is formed on the semiconductor layer (220), the material for the upper conductive layer is formed in the first intermediate groove (H c1 ) and the second intermediate groove (H c2 ) is not a separately performed process. That is, when the upper conductive layer (230) is formed on the semiconductor layer (220), the material for the upper conductive layer is formed not only on the semiconductor layer (220) but also on the first intermediate groove (H c1 ) and the second intermediate groove (H c2 ) are filled with the first and second intermediate patterns (P c1 , P c2 ) is formed.

[0134] Referring to Figure 11, the first sub-pattern set (1S b ) of the second lower pattern set (2S) b ) one side and third lower pattern set (3S) b ) on each side of the first intermediate pattern (P c1 ) are formed. That is, the first to third sub-pattern sets (1S b , 2S b , 3S b ) each first sub-pattern (H b1 ) on one side of the first intermediate pattern (P c1 ) is formed. The first sub-pattern set (1S b ) of the other side, the second lower pattern set (2S) b ) of the other side and third lower pattern set (3S) b ) on each side of the second intermediate pattern (P c2 ) are formed. That is, the first to third sub-pattern sets (1S b , 2S b , 3Sb ) each second sub-pattern (H b2 ) on the other side of the second intermediate pattern (P c2 ) is formed.

[0135] Below are multiple first intermediate patterns (P c1 ) and multiple second intermediate patterns (P c2 ), one first intermediate pattern (P) arranged adjacently or adjacently c1 ) and the second intermediate pattern (P c2 ) as a group of 'intermediate pattern sets (S c ) is named as '. In the embodiment, three first intermediate patterns (P c1 ) and three second intermediate patterns (P c2 ) are provided, so three intermediate pattern sets (1S c , 2S c , 3S c ) is provided. Below, for three intermediate pattern sets, the first intermediate pattern set (1S) is provided in order from one end of the substrate to the other end. c ), 2nd intermediate pattern set (2S c ), 3rd intermediate pattern set (3S) c ) is named.

[0136] Next, as shown in FIGS. 9 and 12, a plurality of first insulating patterns (P) are formed as empty spaces penetrating the upper conductive layer (230) and the semiconductor layer (220) in the thickness direction (Z-axis direction). h1 ) and the second insulation pattern (P h2 ) is formed. That is, the first insulating pattern (P) extends from one end to the other end based on the second horizontal direction (Y-axis direction) of the upper conductive layer (230) and the semiconductor layer (220). h1 ) is provided, and the second insulation pattern (P) is extended from the other end to one end. h2 ) is provided. And in the second horizontal direction (Y-axis direction), the first insulating pattern (P h1 ) is the length of the second insulating pattern (P h2 ) can be formed to be longer than the second insulating pattern (Ph2 ) is extended in the second horizontal direction (Y-axis direction) to the second lower pattern (P b2 ) and the second intermediate pattern (P c2 ) can be equal to the length of the string.

[0137] First insulation pattern (P h1 ) and the second insulation pattern (P h2 ) can be formed between two adjacently arranged intermediate pattern sets. At this time, the first insulating pattern (P h1 ) and the second insulation pattern (P h2 ) among the second insulation patterns (P h2 ) is relatively close to one end of the substrate, and the first insulating pattern (P h1 ) can be formed relatively close to the other end of the substrate. That is, the second intermediate pattern set (2S c )'s first intermediate pattern (P c1 ) on one side of the first insulation pattern (P h1 ) is formed, and the first intermediate pattern set (1S c ) Second intermediate pattern (P c2 ) on the other side, the second insulation pattern (P h2 ) is formed. In addition, the third intermediate pattern set (3S c )'s first intermediate pattern (P c1 ) on one side of the first insulation pattern (P h1 ) is formed, and the second intermediate pattern set (2S c ) Second intermediate pattern (P c2 ) on the other side, the second insulation pattern (P h2 ) is formed. Then, a second insulating pattern (P) is formed on the other side of the intermediate pattern set closest to the other end of the substrate. h2 ) is further formed. That is, the third intermediate pattern set (3S) c ) Second intermediate pattern (P c2 ) on the other side of the second insulating pattern (P h2 ) is formed.

[0138] First insulation pattern (P h1 ) and the second insulation pattern (P h2) can be formed using a scribing method, for example, can be formed using a scribing etching method using a laser. That is, the semiconductor layer (220) is etched using a laser scribing etching method to form a first insulating pattern (P h1 ) and the second insulation pattern (P h2 ) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0139] First insulation pattern (P h1 ) is formed, multiple battery parts (200a, 200b, 200c) are divided or separated. That is, as shown in Fig. 1, two first insulating patterns (P h1 ) is divided into first to third battery parts (200a, 200b, 200c). That is, from one end of the substrate (100) to the other end, it is divided into the first battery part (200a), the second battery part (200b), and the third battery part (200c).

[0140] Next, as shown in FIG. 1 and FIG. 13, a third insulating pattern (P) extending in the first horizontal direction (X-axis direction) while penetrating the upper conductive layer (230), the semiconductor layer (220), and the lower conductive layer (210) in the thickness direction (Z-axis direction) h3 ) is formed. The third insulating pattern (P h3 ) is the first lower pattern (P) based on the second horizontal direction (Y-axis direction). b1 ) and the first intermediate pattern (P c1 ) and the second sub-pattern (P b2 ), second intermediate pattern (P c2 ) and the second insulation pattern (P h2 ) are arranged to be positioned between them. Accordingly, each of the third insulating patterns (P) extending in the second horizontal direction (Y-axis direction) h3 ) is formed.

[0141] Third insulation pattern (P h3 ) can be formed using a scribing method, for example, can be formed using a scribing etching method using a laser. That is, the upper conductive layer (230), the semiconductor layer (220), and the lower conductive layer (210) are etched using a laser scribing etching method to form a third insulating pattern (P h3 ) can be formed. At this time, for example, etching can be performed using a laser of 500 nm to 1100 nm or a laser of 200 nm to less than 500 nm. More specifically, a laser of 532 nm wavelength, a laser of 1064 nm wavelength, or a laser of 266 nm wavelength can be used.

[0142] The above describes scribing using a laser etching method. However, this is not limited to this method and etching can also be performed using a needle.

[0143]

[0144] The second insulating pattern (P) formed in this way h2 ) and the third insulation pattern (P h3 ) is divided into a solar cell (SC: SC1, SC2, SC3) and a bypass section (BP: BP1, BP2, BP3).

[0145] Also, the first and second sub-patterns (P b1 ,P b2 ), first and second intermediate patterns (P c1 ,P c2 ), first insulation pattern (P h1 ) and the second insulation pattern (P h2), a battery unit (200: 200a, 200b, 200c) including a bypass diode (BD: BD1, BD2, BD3) and a solar cell module can be manufactured. That is, a solar cell (SC: SC1, SC2, SC3), a connection unit, and a bypass diode (BD: BD1, BD2, BD3) can be integrally formed on one substrate (100). In addition, when forming a solar cell (SC: SC1, SC2, SC3), the bypass diode (BD: BD1, BD2, BD3) can be formed simultaneously or together with the solar cell (SC: SC1, SC2, SC3). Therefore, the cost and time for manufacturing a battery unit (200: 200a, 200b, 200c) including a bypass diode (BD: BD1, BD2, BD3) and a solar cell module can be saved.

[0146] Thin film solar cell devices and thin film solar cell modules according to embodiments of the present invention may include built-in bypass diodes. Furthermore, thin film solar cell devices and thin film solar cell modules including bypass diodes can be manufactured simply and at low cost.

Claims

1. Substrate; A solar cell comprising a first lower conductive layer, a first semiconductor layer, and a first upper conductive layer sequentially stacked in an upward direction on the substrate; A connecting portion including a second lower conductive layer connected to the first lower conductive layer, a second semiconductor layer formed on the second lower conductive layer, and a second upper conductive layer formed on the second semiconductor layer so as to be connected to the second lower conductive layer; A thin film solar cell device comprising a bypass diode including a third upper conductive layer connected to the second upper conductive layer, a third semiconductor layer sequentially stacked downward from the third upper conductive layer, and a third lower conductive layer.

2. In claim 1, The above solar cell extends in a first horizontal direction on the substrate, The above connecting portion and bypass diode are arranged in the first horizontal direction, A thin film solar cell device in which the direction in which the above connecting portion and bypass diode and the above solar cell are listed is a second horizontal direction intersecting the first horizontal direction.

3. In claim 2, The above solar cell, A first lower pattern formed so as to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first semiconductor layer; and A first intermediate pattern formed to penetrate the first semiconductor layer in the thickness direction and formed of a material for the first upper conductive layer; The above connection part, A second lower pattern formed between the second lower conductive layer and the third lower conductive layer and formed of a material for the second semiconductor layer; and A second intermediate pattern formed to penetrate the second semiconductor layer in the thickness direction and formed of a material for the second upper conductive layer; The first lower pattern and the first middle pattern are arranged in the first horizontal direction, and the second lower pattern and the second middle pattern are arranged in the first horizontal direction. A thin film solar cell device in which the directions listed in the order of the first lower pattern and the first middle pattern are opposite to the directions listed in the order of the second lower pattern and the second middle pattern.

4. In claim 3, The solar cell includes a first insulating pattern formed on the upper side of the first lower conductive layer, and is arranged on the outer side of the first lower pattern and the first middle pattern based on the first horizontal direction; The above connecting portion is arranged on the outside of the second lower pattern and the second middle pattern based on the first horizontal direction, and includes a second insulating pattern formed on the upper side of the second lower conductive layer. A thin film solar cell device including a third insulating pattern provided between the connecting portion and the bypass diode and the solar cell, based on the second horizontal direction.

5. In claim 4, A thin film solar cell device in which the first to third insulating patterns are formed as empty spaces or formed of an insulating material.

6. In claim 4 or claim 5, When one end of the substrate is referred to as one side and the other end is referred to as the other side based on the first horizontal direction, Based on the first horizontal direction, the bypass diode is placed on one side of the connection part, In the order of the first lower pattern, the first middle pattern, and the first insulating pattern, the first middle pattern is arranged on one side of the first lower pattern based on the first horizontal direction, and the first insulating pattern is arranged on one side of the first middle pattern. A thin film solar cell device in which the second lower pattern, the second intermediate pattern, and the second insulating pattern are arranged in that order, and the second intermediate pattern is arranged on the other side of the second lower pattern with respect to the first horizontal direction, and the second insulating pattern is arranged on the other side of the second intermediate pattern.

7. In any one of claims 1 to 5, The first to third lower conductive layers are formed of the same material, The first to third semiconductor layers are formed of the same material, A thin film solar cell device in which the first to third upper conductive layers are formed of the same material.

8. Substrate; A thin film solar cell module comprising a plurality of battery sections, each section comprising a solar cell formed on the substrate, a connecting portion formed on the substrate to be connected to a lower conductive layer of the solar cell, and a bypass diode formed on the substrate to be connected to an upper conductive layer of the solar cell.

9. In claim 8, Each of the plurality of solar cells of the battery section includes a first lower conductive layer, a first semiconductor layer, and a first upper conductive layer sequentially stacked in an upward direction on the substrate, Each of the plurality of connecting portions of the above-described battery parts includes a second lower conductive layer connected to the first lower conductive layer, a second semiconductor layer formed on the second lower conductive layer, and a second upper conductive layer formed on the second semiconductor layer so as to be connected to the second lower conductive layer. A thin film solar cell module in which each of the plurality of battery sections includes a third upper conductive layer connected to the second upper conductive layer, a third semiconductor layer sequentially stacked downward from the second upper conductive layer, and a third lower conductive layer.

10. In claim 9, A plurality of the above-described electric parts are arranged in the first horizontal direction, The above solar cell extends in a first horizontal direction on the substrate, In each of the above battery sections, the connecting portion and the bypass diode are arranged in the first horizontal direction, A thin film solar cell module in which, in each of the above-mentioned battery sections, the direction in which the connecting section and the bypass diode and the solar cell are arranged is a second horizontal direction intersecting the first horizontal direction.

11. In claim 10, The above solar cell, A first lower pattern formed so as to penetrate the first lower conductive layer in the thickness direction and formed of a material for the first semiconductor layer; and A first intermediate pattern formed to penetrate the first semiconductor layer in the thickness direction and formed of a material for the first upper conductive layer; The above first lower pattern and the first middle pattern are arranged in the first horizontal direction, The above connection part, A second lower pattern formed between the second lower conductive layer and the third lower conductive layer and formed of a material for the second semiconductor layer; and A second intermediate pattern formed to penetrate the second semiconductor layer in the thickness direction and formed of a material for the second upper conductive layer; The first lower pattern and the first middle pattern are arranged in the first horizontal direction, and the second lower pattern and the second middle pattern are arranged in the first horizontal direction. A thin film solar cell module in which the directions listed in the order of the first lower pattern and the first middle pattern are opposite to the directions listed in the order of the second lower pattern and the second middle pattern.

12. In claim 11, The solar cell includes a first insulating pattern formed on the upper side of the first lower conductive layer, and is arranged on the outer side of the first lower pattern and the first middle pattern based on the first horizontal direction; The above connecting portion is arranged on the outside of the second lower pattern and the second middle pattern based on the first horizontal direction, and includes a second insulating pattern formed on the upper side of the second lower conductive layer. A thin film solar cell module, wherein each of the plurality of battery sections includes a third insulating pattern provided between the connecting section and the bypass diode and the solar cell, based on the second horizontal direction.

13. In claim 12, A thin film solar cell module in which the first to third insulating patterns are formed as empty spaces or formed of an insulating material.

14. In claim 12 or claim 13, When one end of the substrate is referred to as one side and the other end is referred to as the other side based on the first horizontal direction, Based on the first horizontal direction, the bypass diode is placed on one side of the connection part, In the order of the first lower pattern, the first middle pattern, and the first insulating pattern, the first middle pattern is arranged on one side of the first lower pattern based on the first horizontal direction, and the first insulating pattern is arranged on one side of the first middle pattern. A thin film solar cell module in which the second lower pattern, the second intermediate pattern, and the second insulating pattern are arranged in that order, and the second intermediate pattern is arranged on the other side of the second lower pattern with respect to the first horizontal direction, and the second insulating pattern is arranged on the other side of the second intermediate pattern.

15. In any one of claims 9 to 12, The first to third lower conductive layers are formed of the same material, The first to third semiconductor layers are formed of the same material, A thin film solar cell module in which the first to third upper conductive layers are formed of the same material.

16. A method for manufacturing a solar cell device formed on a substrate, comprising a solar cell, a connecting portion connected to a lower conductive layer of the solar cell, and a bypass diode in which an upper conductive layer is connected to the connecting portion, A method for manufacturing a thin film solar cell device, the process comprising manufacturing a solar cell, a connector, and a bypass diode, the method comprising a scribing process.

17. In claim 16, A process for preparing a substrate extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, The process for manufacturing the above solar cell, connector, and bypass diode is as follows: A process of forming a lower conductive layer on a substrate; A process of forming a lower groove by etching the lower conductive layer in the thickness direction using a scribing process; A process of forming a semiconductor layer capable of converting sunlight received on the lower conductive layer into photoelectric energy, and filling the lower groove with a material for the semiconductor layer to form a lower pattern; A process of forming an intermediate groove by etching the lower conductive layer in the thickness direction using a scribing process so that the lower pattern and the first horizontal direction position are different; and A method for manufacturing a thin film solar cell device, comprising: forming an upper conductive layer on the semiconductor layer, and filling the upper conductive layer material into the intermediate groove to form an intermediate pattern.

18. In claim 17, The process of forming the above lower groove is: It includes a process of forming a first lower groove extending from one end of the substrate to the other end based on the second horizontal direction, and forming a second lower groove extending from the other end of the substrate to one end. When one end of the substrate is referred to as one side and the other end is referred to as the other side based on the first horizontal direction, In forming the first and second lower grooves, the first lower groove is formed so as to be positioned on one side of the second lower groove, A method for manufacturing a thin film solar cell device, wherein the process of forming the lower pattern includes a process of forming the first and second lower patterns by filling the semiconductor layer material into the first and second lower grooves.

19. In claim 18, The process of forming the above intermediate groove is: A process of forming a first intermediate groove extending from one end of the substrate to the other end based on the second horizontal direction, and forming a second intermediate groove extending from the other end of the substrate to one end; In forming the first and second intermediate grooves, the first intermediate groove is formed so that it is arranged on one side of the first lower groove, and the second intermediate groove is formed so that it is arranged on the other side of the second lower groove. A method for manufacturing a thin film solar cell device, wherein the process of forming the intermediate pattern includes a process of filling the first and second intermediate grooves with the material for the semiconductor layer to form the first and second intermediate patterns.

20. In claim 19, The process for manufacturing the above solar cell, connector, and bypass diode is as follows: A process of forming a first insulating pattern on one side of the first intermediate pattern; and A process of forming a second insulating pattern on the other side of the second intermediate pattern; The process of forming the first insulating pattern includes a process of forming an empty space on one side of the first intermediate pattern by etching the upper conductive layer and semiconductor layer formed on one side of the first intermediate pattern in the thickness direction using a scribing process. The process of forming the second insulating pattern includes a process of forming an empty space on the other side of the second intermediate pattern by etching the upper conductive layer and semiconductor layer formed on the other side of the second intermediate pattern in the thickness direction using a scribing process; In forming the first insulating pattern, it is formed to extend from one end of the substrate to the other end based on the second horizontal direction, A method for manufacturing a thin film solar cell device, wherein the second insulating pattern is formed to extend from the other end of the substrate to one end based on the second horizontal direction.

21. In claim 20, The process for manufacturing the above solar cell, connector, and bypass diode is as follows: A process of forming a third insulating pattern extending in the first horizontal direction between the first lower pattern and the first middle pattern and the second lower pattern and the second middle pattern based on the second horizontal direction; The process of forming the third insulating pattern is as follows: A method for manufacturing a thin film solar cell device, comprising a process of forming an empty space extending in the second horizontal direction by etching the upper conductive layer, the semiconductor layer, and the upper conductive layer between the first lower pattern and the first middle pattern and the second lower pattern and the second middle pattern in the thickness direction using a scribing process based on the second horizontal direction.

22. In claim 21, The process of forming the first insulating pattern includes a process of filling an insulating material into a blank space formed on one side of the first intermediate pattern. The process of forming the second insulating pattern includes a process of filling an insulating material into a blank space formed on the other side of the second intermediate pattern. A method for manufacturing a thin film solar cell device, wherein the process of forming the third insulating pattern includes a process of filling an insulating material into an empty space extending in the second horizontal direction.

23. A method for manufacturing a solar cell module, comprising a plurality of cell sections formed on a substrate, each cell comprising a solar cell, a connecting portion connected to a lower conductive layer of the solar cell, and a bypass diode in which an upper conductive layer is connected to the connecting portion, A method for manufacturing a thin film solar cell module, wherein the process for manufacturing a plurality of the above-described battery parts includes a scribing process.

24. In claim 23, A process for preparing a substrate extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, The process for manufacturing a plurality of the above-mentioned battery parts is as follows: A process of forming a lower conductive layer on a substrate; A process of forming a plurality of lower grooves arranged in a first horizontal direction by etching the lower conductive layer in the thickness direction using a scribing process; A process of forming a semiconductor layer capable of converting sunlight received on the lower conductive layer into photoelectric energy, and filling a plurality of lower grooves with a material for the semiconductor layer to form a plurality of lower patterns; A process of forming a plurality of intermediate grooves arranged in the first horizontal direction such that the lower conductive layer is etched in the thickness direction using a scribing process so that the lower pattern and the first horizontal direction positions are different; and A method for manufacturing a thin film solar cell module, comprising: forming an upper conductive layer on the semiconductor layer, and filling a plurality of intermediate grooves with a material for the upper conductive layer to form a plurality of intermediate patterns.

25. In claim 24, The process of forming multiple lower grooves is as follows: A process of forming a plurality of first lower grooves, each extending from one end of the substrate to the other end based on the second horizontal direction and arranged in the first horizontal direction; A process of forming a plurality of second lower grooves, each extending from the other end of the substrate to one end based on the second horizontal direction and arranged in the first horizontal direction; The number of the first and second lower grooves is the same, Based on the first horizontal direction, the first lower groove and the second lower groove are formed alternately from one end of the substrate to the other end, A method for manufacturing a thin film solar cell module, wherein the process of forming the lower pattern includes a process of filling a plurality of the first lower grooves and a plurality of the second lower grooves with the material for the semiconductor layer to form a plurality of first lower patterns and a plurality of second lower patterns.

26. In claim 25, The process of forming multiple intermediate grooves is as follows: A process of forming a plurality of first intermediate grooves, each extending from one end of the substrate to the other end based on the second horizontal direction; A process of forming a plurality of second intermediate grooves extending from the other end of the substrate to one end based on the second horizontal direction; When one end of the substrate is referred to as one side and the other end is referred to as the other side based on the first horizontal direction, Among a plurality of first lower patterns and a plurality of second lower patterns, a lower pattern set including a first lower pattern and a second lower pattern arranged adjacently is formed, and the first intermediate groove is formed on one side of the lower pattern set, and the second intermediate groove is formed on the other side of the lower pattern set. A method for manufacturing a thin film solar cell module, wherein the process of forming the intermediate pattern includes a process of filling a plurality of the first intermediate grooves and a plurality of the second intermediate grooves with the material for the semiconductor layer to form a plurality of first intermediate patterns and a plurality of second intermediate patterns.

27. In claim 26, The process for manufacturing a plurality of the above-mentioned battery parts is as follows: A process of forming a first insulating pattern on one side of the first intermediate pattern; and A process of forming a second insulating pattern on the other side of the second intermediate pattern; The process of forming the first insulating pattern includes a process of forming an empty space on one side of the first intermediate pattern by etching the upper conductive layer and semiconductor layer formed on one side of the first intermediate pattern in the thickness direction using a scribing process. The process of forming the second insulating pattern includes a process of forming an empty space on the other side of the second intermediate pattern by etching the upper conductive layer and semiconductor layer formed on the other side of the second intermediate pattern in the thickness direction using a scribing process; In forming the first insulating pattern, in forming the second insulating pattern, it is formed to extend from one end of the substrate to the other end based on the second horizontal direction, A method for manufacturing a thin film solar cell module, wherein the second insulating pattern is formed to extend from the other end of the substrate to one end based on the second horizontal direction.

28. In claim 27, The process for manufacturing a plurality of the above-mentioned battery parts is as follows: A process of forming a third insulating pattern extending in the first horizontal direction between the first lower pattern and the first middle pattern and the second lower pattern and the second middle pattern based on the second horizontal direction; The process of forming the third insulating pattern is as follows: A method for manufacturing a thin film solar cell module, comprising a process of forming an empty space extending in the second horizontal direction by etching the upper conductive layer, the semiconductor layer, and the upper conductive layer between the first lower pattern and the first middle pattern and the second lower pattern and the second middle pattern in the thickness direction using a scribing process based on the second horizontal direction.

29. In claim 28, The process of forming the first insulating pattern includes a process of filling an insulating material into a blank space formed on one side of the first intermediate pattern. The process of forming the second insulating pattern includes a process of filling an insulating material into a blank space formed on the other side of the second intermediate pattern. A method for manufacturing a thin film solar cell module, wherein the process of forming the third insulating pattern includes a process of filling an insulating material into the empty space extending in the second horizontal direction.

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