Display device and electronic device comprising same

Abstract

The display device comprises: a pixel-driving circuit unit including a transistor; a connection electrode disposed on the pixel-driving circuit unit and electrically connected to the transistor of the pixel-driving circuit unit; a first electrode layer which is disposed on the connection electrode, receives a power voltage, and includes a plurality of first electrodes; a transmission line group disposed on a layer different from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane; a separator disposed on the first electrode layer; and a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator.

Description

Display device and electronic device including same

[0001] The present disclosure relates to a display device. More specifically, the present disclosure relates to a display device that provides visual information.

[0002] As information technology advances, display devices, which serve as a link between users and information, are increasingly important and play a crucial role in people's daily lives. These display devices include light-emitting elements and pixel driving circuits for driving the light-emitting elements. The light-emitting elements are driven by the pixel driving circuits to emit light. To improve the reliability of these display devices, ongoing research is being conducted on the connection between the light-emitting elements and the pixel driving circuits.

[0003] One object of the present disclosure is to provide a display device with improved display quality.

[0004] Another object of the present disclosure is to provide an electronic device including the display device.

[0005] However, the purpose of the present disclosure is not limited to this purpose, and may be expanded in various ways without departing from the spirit and scope of the present disclosure.

[0006] A display device according to the present disclosure may include a pixel driving circuit portion including a transistor, a connection electrode disposed on the pixel driving circuit portion and electrically connected to the transistor of the pixel driving circuit portion, a first electrode layer disposed on the connection electrode, receiving a power supply voltage, and including a plurality of first electrodes, a group of transmission lines disposed on a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane, a separator disposed on the first electrode layer, and a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator.

[0007] In one embodiment, the first electrode layer may be connected to receive the power supply voltage through the transmission line group.

[0008] In one embodiment, the first electrode layer may have a mesh pattern in which the first electrodes extending in different directions are integrally connected.

[0009] In one embodiment, the group of transmission lines may include transmission lines extending in one direction and arranged in a cross direction that is not parallel to the one direction and intersects it.

[0010] In one embodiment, the transistor includes an active pattern including a semiconductor material, a gate electrode disposed on the active pattern, and a contact electrode disposed on the gate electrode and in contact with the active pattern, wherein the transmission lines may be disposed on the same layer as the contact electrode.

[0011] In one embodiment, the transmission lines may be arranged in the same layer as the connecting electrodes.

[0012] In one embodiment, the group of transmission lines may include first transmission lines extending in one direction and arranged in a cross direction that is not parallel to the one direction and intersects the one direction, and second transmission lines extending in the cross direction and arranged in the one direction.

[0013] In one embodiment, the transistor includes an active pattern including a semiconductor material, a gate electrode disposed on the active pattern, and a contact electrode disposed on the gate electrode and in contact with the active pattern, wherein the first transmission lines may be disposed on the same layer as the contact electrode, and the second transmission lines may be disposed on the same layer as the connection electrode.

[0014] In one embodiment, the first electrode layer includes electrode lines extending in one direction and arranged in a cross direction that is not parallel to the one direction and intersects the one direction, the electrode lines are physically separated from each other, and each of the electrode lines may have a structure in which some of the first electrodes extending in different directions are integrally connected.

[0015] In one embodiment, the first electrode layer includes electrode patterns arranged in one direction and in a cross direction that is not parallel to the one direction and intersects the one direction, the electrode patterns are physically separated from each other, and each of the electrode patterns may have a structure in which some of the first electrodes are integrally connected.

[0016] In one embodiment, the group of transmission lines may include first transmission lines extending in the one direction and arranged in the cross direction and second transmission lines extending in the cross direction and arranged in the one direction.

[0017] In one embodiment, the first transmission lines and the second transmission lines are connected to at least one of the electrode patterns, and the first transmission lines, the second transmission lines, and the electrode patterns can form the mesh structure.

[0018] In one embodiment, the electrode patterns can be electrically connected to each other via the first transmission lines and the second transmission lines.

[0019] In one embodiment, the transistor includes an active pattern including a semiconductor material, a gate electrode disposed on the active pattern, and a contact electrode disposed on the gate electrode and in contact with the active pattern, wherein the first transmission lines may be disposed on the same layer as the contact electrode, and the second transmission lines may be disposed on the same layer as the connection electrode.

[0020] In one embodiment, the first electrodes are arranged in one direction and in a cross direction that is not parallel to the one direction and intersects the one direction, and the first electrodes can be physically separated from each other.

[0021] In one embodiment, the display device may further include an intermediate layer disposed between the first electrode layer and the second electrode layer and including a light-emitting material.

[0022] In one embodiment, at least one of the second electrodes may be electrically connected to the connecting electrode and electrically connected to the transistor of the pixel driving circuit unit through the connecting electrode.

[0023] A display device according to the present disclosure may include a pixel driving circuit unit including a transistor, a connection electrode disposed on the pixel driving circuit unit and electrically connected to the transistor of the pixel driving circuit unit, a first electrode layer disposed on the connection electrode and receiving a power supply voltage and including a plurality of first electrodes, a group of transmission lines disposed on a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane, a pixel defining film disposed on the first electrode layer and defining a light-emitting area, a connection pattern electrically connected to the connection electrode and surrounding the light-emitting area on a plane, a separator disposed on the pixel defining film and the connection pattern and covering at least a portion of the connection pattern, and a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator.

[0024] In one embodiment, at least one of the second electrodes may be in contact with the connection pattern at a position adjacent to or overlapping the separator, and may be electrically connected to the transistor of the pixel driving circuit unit through the connection electrode and the connection pattern.

[0025] An electronic device according to the present disclosure may include a display device including a pixel driving circuit unit including a transistor, a connection electrode disposed on the pixel driving circuit unit and electrically connected to the transistor of the pixel driving circuit unit, a first electrode layer disposed on the connection electrode and receiving a power supply voltage and including a plurality of first electrodes, a group of transmission lines disposed on a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane, a separator disposed on the first electrode layer, and a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator, and a power module supplying the power supply voltage to the display device.

[0026] In a display device according to embodiments of the present disclosure, a cathode disposed above an anode may be connected to a pixel driving circuit. Specifically, the cathode disposed above the anode may be connected to a drain of a driving transistor of the pixel driving circuit. Accordingly, even when a light-emitting element deteriorates, a gate-source voltage (Vgs) of the driving transistor may not change. Accordingly, a range of change in driving current due to deterioration of the light-emitting element may be reduced. Accordingly, afterimage defects of the display device due to increased usage time may be reduced, and the lifespan of the display device may be improved.

[0027] In addition, according to embodiments of the present disclosure, the display device may include transmission lines that are disposed on a different layer from the anode to which a power voltage is applied, and that receive the power voltage. The transmission lines may be connected to the anode. Accordingly, the transmission lines may provide the power voltage to the anode, and the anode and the transmission lines may define a mesh structure on a plane. For example, when the anode itself has a mesh pattern, the mesh characteristics of the transmission path of the power voltage may be further enhanced by the mesh structure defined by the anode and the transmission lines. Furthermore, even when the anode itself does not have a mesh pattern, the mesh characteristics of the transmission path of the power voltage may be implemented by the mesh structure defined by the anode and the transmission lines. Accordingly, the voltage drop of the power voltage may be reduced. Accordingly, the power consumption of the display device may be improved, and the luminance uniformity may be enhanced. Accordingly, the display quality of the display device may be improved.

[0028] However, the effects of the present disclosure are not limited to the above effects, and may be expanded in various ways without departing from the spirit and scope of the present disclosure.

[0029] FIG. 1A is a plan view showing a display device according to one embodiment of the present disclosure.

[0030] FIG. 1b is a plan view showing a display device according to one embodiment of the present disclosure.

[0031] FIG. 2a is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1a and FIG. 1b.

[0032] FIG. 2b is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1a and FIG. 1b.

[0033] FIG. 2c is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1a and FIG. 1b.

[0034] FIG. 3 is a plan view schematically illustrating an example of a portion of the display device of FIGS. 1a and 1b.

[0035] Fig. 4 is an enlarged view of one of the unit light-emitting areas of Fig. 3.

[0036] Figure 5 is a cross-sectional view taken along line II` of Figure 4.

[0037] FIG. 6 is a plan view schematically illustrating a first embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​FIG. 1a and FIG. 1b.

[0038] Figure 7 is an enlarged view of the AA area of ​​Figure 6.

[0039] Fig. 8a is a cross-sectional view showing an example cut along line II-II` of Fig. 7.

[0040] Fig. 8b is a cross-sectional view showing an example cut along line II-II` of Fig. 7.

[0041] FIG. 9 is a plan view schematically illustrating a second embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​FIG. 1a and FIG. 1b.

[0042] Figure 10 is an enlarged view of the BB area of ​​Figure 9.

[0043] Fig. 11a is a cross-sectional view showing an example cut along line III-III` of Fig. 10.

[0044] Fig. 11b is a cross-sectional view showing an example cut along line III-III` of Fig. 10.

[0045] FIG. 12 is a plan view schematically showing a third embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​FIG. 1a and FIG. 1b.

[0046] Figure 13 is an enlarged view of the CC area of ​​Figure 12.

[0047] Fig. 14a is a cross-sectional view showing an example cut along line IV-IV` of Fig. 13.

[0048] Fig. 14b is a cross-sectional view showing an example cut along line IV-IV` of Fig. 13.

[0049] FIG. 15 is a plan view schematically showing a fourth embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​FIG. 1a and FIG. 1b.

[0050] Figure 16 is an enlarged view of the DD area of ​​Figure 15.

[0051] Fig. 17a is a cross-sectional view showing an example cut along line VV` of Fig. 16.

[0052] Fig. 17b is a cross-sectional view showing an example cut along line VV` of Fig. 16.

[0053] FIG. 18 is a plan view schematically showing a fifth embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​the display device of FIGS. 1a and 1b.

[0054] Figure 19 is an enlarged view of the EE area of ​​Figure 18.

[0055] Fig. 20a is a cross-sectional view showing an example cut along line VI-VI` of Fig. 19.

[0056] Fig. 20b is a cross-sectional view showing an example cut along line VI-VI` of Fig. 19.

[0057] FIG. 21 is a plan view schematically showing a sixth embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​FIG. 1a and FIG. 1b.

[0058] Figure 22 is an enlarged view of the FF area of ​​Figure 21.

[0059] Fig. 23a is a cross-sectional view showing an example cut along line VII-VII` of Fig. 22.

[0060] Fig. 23b is a cross-sectional view showing an example cut along line VII-VII` of Fig. 23.

[0061] FIG. 24 is a plan view schematically showing a seventh embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​FIG. 1a and FIG. 1b.

[0062] Figure 25 is an enlarged view of the GG area of ​​Figure 24.

[0063] Fig. 26a is a cross-sectional view showing an example cut along line VIII-VIII` of Fig. 25.

[0064] Fig. 26b is a cross-sectional view showing an example cut along line VIII-VIII` of Fig. 25.

[0065] Fig. 27 is a plan view schematically showing an example of a part of the display device of Figs. 1a and 1b.

[0066] Fig. 28 is an enlarged view of one of the unit light-emitting areas of Fig. 27.

[0067] Fig. 29 is a cross-sectional view taken along line IX-IX` of Fig. 28.

[0068] FIG. 30 is a block diagram illustrating an electronic device according to embodiments of the present disclosure.

[0069] FIG. 31 is a schematic diagram showing an electronic device according to various embodiments.

[0070] With respect to the embodiments of the present disclosure disclosed in the text, specific structural and functional descriptions are merely illustrative for the purpose of explaining the embodiments of the present disclosure, and the embodiments of the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments described in the text.

[0071] This disclosure may be subject to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the disclosure to any specific form, and it should be understood that the disclosure encompasses all modifications, equivalents, and alternatives falling within the spirit and technical scope of the disclosure.

[0072] While terms like "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms may be used to distinguish one component from another. For example, without departing from the scope of the present disclosure, a first component could be referred to as a "second component," and similarly, a second component could also be referred to as a "first component."

[0073] When a component is referred to as being "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components intervening. Other expressions describing the relationship between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted similarly.

[0074] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present disclosure. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprises" or "has" indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0075] Terms such as "below," "below," "underneath," "below," "above," "above," "above," and "above" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0076] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0077] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the attached drawings. Identical components in the drawings will be designated by the same reference numerals, and redundant descriptions of identical components will be omitted.

[0078] FIG. 1a is a plan view showing a display device according to one embodiment of the present disclosure, and FIG. 1b is a plan view showing a display device according to one embodiment of the present disclosure.

[0079] Referring to FIGS. 1A and 1B, the display devices (DD, DDa) may be devices activated according to an electrical signal. For example, the display device (DD) may be a small display device used in small electronic devices such as smartphones, mobile phones, smart watches, game consoles, and cameras. In addition, the display device (DDa) may be a medium- to large-sized display device used in medium- to large-sized electronic devices such as laptops, tablet PCs, televisions, computer monitors, vehicle monitors, and outdoor billboards. FIG. 1A illustrates the display device (DD) as an example of the small display device, and FIG. 1B illustrates the display device (DDa) as an example of the medium- to large-sized display device.

[0080] A display device (DD, DDa) may include a display area (DA) and a peripheral area (NDA). The display area (DA) may be an area that generates light or displays an image by controlling the transmittance of light provided from an external light source. The peripheral area (NDA) may be located around the display area (DA). For example, the peripheral area (NDA) may surround at least a portion of the display area (DA). In one embodiment, the peripheral area (NDA) may be an area that does not display an image. However, the present disclosure is not necessarily limited thereto, and an image may be displayed in at least a portion of the peripheral area (NDA). For example, a light-emitting element that emits light may be disposed in at least a portion of the peripheral area (NDA).

[0081] The display device (DD, DDa) may include a substrate (SUB), pixels (PX), a gate line (GL), a data line (DL), a data driver (DDV), and a gate driver (GDV).

[0082] The substrate (SUB) may form the base of the display device (DD, DDa). In one embodiment, examples of materials that may be used as the substrate (SUB) include glass, quartz, silicon, polymers, etc. These may be used alone or in combination. In addition, the substrate (SUB) may have a single-layer structure or a multi-layer structure in which multiple layers containing different materials are laminated.

[0083] Pixels (PX) may be arranged in a display area (DA) on a substrate (SUB). The pixels (PX) may be electrically connected to a gate line (GL) and a data line (DL). For example, the pixels (PX) may be arranged in a matrix form along a first direction (DR1) and a second direction (DR2). The first direction (DR1) and the second direction (DR2) may be orthogonal to each other and may define a plane. The image may be displayed in a third direction (DR3), which is a normal direction of the plane. That is, the third direction (DR3) may be orthogonal to both the first direction (DR1) and the second direction (DR2). Each of the pixels (PX) may include a pixel driving circuit and a light-emitting element. The light-emitting element may emit light. The light-emitting element may be an organic light-emitting diode or an inorganic light-emitting diode.

[0084] The gate line (GL) and the data line (DL) may intersect each other. For example, the gate line (GL) may generally extend in the first direction (DR1) and be arranged along the second direction (DR2). The data line (DL) may generally extend in the second direction (DR2) and be arranged along the first direction (DR1). However, the present disclosure is not necessarily limited thereto.

[0085] A data driver (DDV) may be arranged in a peripheral area (NDA) on a substrate (SUB). The data driver (DDV) may generate a data voltage. The data driver (DDV) may output the data voltage to a data line (DL). The data voltage may be applied to pixels (PX) via the data line (DL).

[0086] In one embodiment, the data driver (DDV) may be mounted on the substrate (SUB). However, the present disclosure is not necessarily limited thereto, and the data driver (DDV) may also be positioned on a flexible film bonded to the substrate (SUB). That is, the display device (DD) may have a chip-on-film (COF) structure.

[0087] In one embodiment, the display device (DDa) of FIG. 1B may include a plurality of data drivers (DDVs). For example, the data drivers (DDVs) may be arranged on both sides of the display area (DA) in the second direction (DR2). For example, the data drivers (DDVs) may be arranged along the long side of the display panel (DP). However, the present disclosure is not necessarily limited thereto.

[0088] A gate driver (GDV) may be disposed in a peripheral area (NDA) on a substrate (SUB). The gate driver (GDV) may generate a gate signal. The gate driver (GDV) may output the gate signal to a gate line (GL). The gate signal may be applied to pixels (PX) through the gate line (GL). In one embodiment, the gate driver (GDV) may be disposed on both sides of the display area (DA) in the first direction (DR1). However, the present disclosure is not necessarily limited thereto.

[0089] In one embodiment, a light emitting driver unit that generates a light emitting control signal may be further disposed in the peripheral area (NDA). The light emitting control signal may be applied to the pixels (PX) via a light emitting control line.

[0090] Meanwhile, the number or arrangement relationship of the data driving units (DDV) and the number or arrangement relationship of the gate driving units (GDV) illustrated in FIGS. 1A and 1B are merely examples, and the present disclosure is not necessarily limited thereto.

[0091] In addition, although the display device (DD) in FIG. 1A is illustrated as having a substantially rectangular planar shape having a short side extending in the first direction (DR1) and a long side extending in the second direction (DR2), the present disclosure is not necessarily limited thereto. In addition, although the display device (DDa) in FIG. 1B is illustrated as having a rectangular planar shape having a long side extending in the first direction (DR1) and a short side extending in the second direction (DR2), the present disclosure is not necessarily limited thereto. That is, the planar shapes of the display devices (DD, DDa) may be variously changed depending on the embodiments.

[0092] Meanwhile, the following descriptions can be applied to the display device (DD) of FIG. 1a and the display device (DDa) of FIG. 1b. Therefore, for convenience of explanation, the expression is unified as the display device (DD) below.

[0093] FIG. 2a is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1a and FIG. 1b.

[0094] Referring to FIG. 2A, in one embodiment, a pixel (PX) may include a light-emitting element (LED) and a pixel driving circuit (PC) connected to the light-emitting element (LED). In one embodiment, the pixel driving circuit (PC) may include a first transistor (T1), a second transistor (T2), and a first capacitor (C1). In FIG. 2A, both the first transistor (T1) and the second transistor (T2) are illustrated as n-type transistors. However, the present disclosure is not limited thereto, and some of the first transistor (T1) and the second transistor (T2) may be n-type transistors, and others may be p-type transistors. For example, the first transistor (T1) may be an n-type transistor, and the second transistor (T2) may be a p-type transistor.

[0095] When the pixel (PX) includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, the present disclosure is not necessarily limited thereto, and both the active pattern of the n-type transistor and the active pattern of the p-type transistor may include a silicon semiconductor material.

[0096] The pixel driving circuit (PC) can be connected to a first gate line (GWL), a data line (DL), a first voltage line (VL1), and a second voltage line (VL2). The first gate line (GWL) can transmit a first gate signal (GW). The data line (DL) can transmit a data voltage (VDATA). The first voltage line (VL1) can transmit a first power voltage (ELVDD) having a relatively high voltage level. The second voltage line (VL2) can transmit a second power voltage (ELVSS) having a relatively low voltage level.

[0097] A first transistor (T1) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the first transistor (T1) may be a source, and the second terminal of the first transistor (T1) may be a drain. The gate terminal of the first transistor (T1) may be connected to a first node (N1). The first terminal of the first transistor (T1) may be connected to a second node (N2). The second terminal of the first transistor (T1) may be connected to a third node (N3). The second terminal of the first transistor (T1) may be connected to a light emitting element (LED). The first transistor (T1) may provide a driving current (ID) to the light emitting element (LED).

[0098] The second transistor (T2) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the second transistor (T2) may be a source, and the second terminal of the second transistor (T2) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the second transistor (T2) may be a drain, and the second terminal of the second transistor (T2) may be a source. The gate terminal of the second transistor (T2) may be connected to a first gate line (GWL). The first terminal of the second transistor (T2) may be connected to a data line (DL). The second terminal of the second transistor (T2) may be connected to a first node (N1).

[0099] The gate terminal of the second transistor (T2) can receive a first gate signal (GW) through a first gate line (GWL). The second transistor (T2) can be turned on or off in response to the first gate signal (GW). For example, when the second transistor (T2) is an n-type transistor, the second transistor (T2) can be turned off in response to the first gate signal (GW) having a negative voltage level, and can be turned on in response to the first gate signal (GW) having a positive voltage level. In addition, when the second transistor (T2) is a p-type transistor, the second transistor (T2) can be turned off in response to the first gate signal (GW) having a positive voltage level, and can be turned on in response to the first gate signal (GW) having a negative voltage level. The first terminal of the second transistor (T2) can receive a data voltage (VDATA) through a data line (DL). The second terminal of the second transistor (T2) can provide a data voltage (VDATA) to the first node (N1) during the period in which the second transistor (T2) is turned on. Accordingly, the second transistor (T2) can drive the first transistor (T1).

[0100] A first capacitor (C1) may include a first terminal and a second terminal. The first terminal of the first capacitor (C1) may be connected to a first node (N1). The second terminal of the first capacitor (C1) may be connected to a second node (N2). The first capacitor (C1) may be charged and discharged according to a data voltage (VDATA) transmitted to the first node (N1).

[0101] A light emitting diode (LED) may include an anode and a cathode. The anode of the LED may be connected to a first voltage line (VL1). The cathode of the LED may be connected to a third node (N3). Specifically, the cathode of the LED may be connected to the second terminal of the first transistor (T1).

[0102] FIG. 2b is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1a and FIG. 1b.

[0103] Compared to the embodiment of the circuit structure of the pixel (PX) described with reference to FIG. 2a, the pixel driving circuit unit (PC`) in the embodiment of the circuit structure of the pixel (PX) described with reference to FIG. 2b may further include third to sixth transistors (T3, T4, T5, T6) and a second capacitor (C2). Therefore, redundant descriptions of some components are omitted or simplified.

[0104] Referring to FIG. 2B, in one embodiment, a pixel (PX) may include a light-emitting element (LED) and a pixel driving circuit (PC`) connected to the light-emitting element (LED). In one embodiment, the pixel driving circuit (PC`) may include first to sixth transistors (T1`, T2, T3, T4, T5, T6), a first capacitor (C1), and a second capacitor (C2). In FIG. 2B, all of the first to sixth transistors (T1`, T2, T3, T4, T5, T6) are illustrated as n-type transistors. However, the present disclosure is not limited thereto, and some of the first to sixth transistors (T1`, T2, T3, T4, T5, T6) may be n-type transistors, and others may be p-type transistors. For example, the first transistor (T1`) may be an n-type transistor, some of the second to sixth transistors (T2, T3, T4, T5, T6) may be n-type transistors, and others may be p-type transistors.

[0105] When the pixel (PX) includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, the present disclosure is not necessarily limited thereto, and both the active pattern of the n-type transistor and the active pattern of the p-type transistor may include a silicon semiconductor material.

[0106] The pixel driving circuit (PC`) can be connected to first to third gate lines (GWL, GCL, GRL), a data line (DL), first to fourth voltage lines (VL1, VL2, VL3, VL4), a first emission control line (ECL1), and a second emission control line (ECL2). The first gate line (GWL) can transmit a first gate signal (GW). The second gate line (GCL) can transmit a second gate signal (GC). The third gate line (GRL) can transmit a third gate signal (GR). The data line (DL) can transmit a data voltage (VDATA). The first voltage line (VL1) can transmit a first power voltage (ELVDD) having a high voltage level. The second voltage line (VL2) can transmit a second power voltage (ELVSS) having a low voltage level. The third voltage line (VL3) can transmit a first initialization voltage (Vcint). The fourth voltage line (VL4) can transmit a reference voltage (Vref). The reference voltage (Vref) can have a voltage level lower than the first power supply voltage (ELVDD).

[0107] The first transistor (T1`) of FIG. 2b may be substantially the same as the first transistor (T1) referring to FIG. 2a, except that the second terminal is connected to the light-emitting element (LED) through the fifth transistor (T5). Therefore, any redundant description will be omitted or simplified. That is, the first transistor (T1`) of the pixel driving circuit (PC`) may be connected to the light-emitting element (LED) through the fifth transistor (T5) and may provide a driving current (ID) to the light-emitting element (LED).

[0108] The second transistor (T2) of Fig. 2b may be substantially identical to the second transistor (T2) described with reference to Fig. 2a. Accordingly, the description of the second transistor (T2) of Fig. 2a may be applied. The second transistor (T2) may drive the first transistor (T1`) during the period in which the second transistor (T2) is turned on.

[0109] The third transistor (T3) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the third transistor (T3) may be a source, and the second terminal of the third transistor (T3) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the third transistor (T3) may be a drain, and the second terminal of the third transistor (T3) may be a source. The gate terminal of the third transistor (T3) may be connected to a second gate line (GCL). The first terminal of the third transistor (T3) may be connected to a third node (N3). The second terminal of the third transistor (T3) may be connected to a third voltage line (VL3).

[0110] The gate terminal of the third transistor (T3) can receive a second gate signal (GC) through the second gate line (GCL). The third transistor (T3) can be turned on or off in response to the second gate signal (GC). For example, when the third transistor (T3) is an n-type transistor, the third transistor (T3) can be turned off in response to the second gate signal (GC) having a negative voltage level, and can be turned on in response to the second gate signal (GC) having a positive voltage level. In addition, when the third transistor (T3) is a p-type transistor, the third transistor (T3) can be turned off in response to the second gate signal (GC) having a positive voltage level, and can be turned on in response to the second gate signal (GC) having a negative voltage level. During the period in which the third transistor (T3) is turned on, the third transistor (T3) can provide a first initialization voltage (Vcint) to the third node (N3). Specifically, the third transistor (T3) can initialize the voltage of the cathode by providing the first initialization voltage (Vcint) to the cathode of the light-emitting element (LED) in response to the second gate signal (GC).

[0111] The fourth transistor (T4) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the fourth transistor (T4) may be a source, and the second terminal of the fourth transistor (T4) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the fourth transistor (T4) may be a drain, and the second terminal of the fourth transistor (T4) may be a source. The gate terminal of the fourth transistor (T4) may be connected to a third gate line (GRL). The first terminal of the fourth transistor (T4) may be connected to a first node (N1). The second terminal of the fourth transistor (T4) may be connected to a fourth voltage line (VL4).

[0112] The gate terminal of the fourth transistor (T4) can receive a third gate signal (GR) through a third gate line (GRL). The fourth transistor (T4) can be turned on or off in response to the third gate signal (GR). For example, when the fourth transistor (T4) is an n-type transistor, the fourth transistor (T4) can be turned off in response to the third gate signal (GR) having a negative voltage level, and can be turned on in response to the third gate signal (GR) having a positive voltage level. In addition, when the fourth transistor (T4) is a p-type transistor, the fourth transistor (T4) can be turned off in response to the third gate signal (GR) having a positive voltage level, and can be turned on in response to the third gate signal (GR) having a negative voltage level. During the period in which the fourth transistor (T4) is turned on, the fourth transistor (T4) can provide a reference voltage (Vref) to the first node (N1).

[0113] The fifth transistor (T5) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the fifth transistor (T5) may be a source, and the second terminal of the fifth transistor (T5) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the fifth transistor (T5) may be a drain, and the second terminal of the fifth transistor (T5) may be a source. The gate terminal of the fifth transistor (T5) may be connected to a first emission control line (ECL1). The first terminal of the fifth transistor (T5) may be connected to the second terminal of the first transistor (T1). The second terminal of the fifth transistor (T5) may be connected to a third node (N3). The second terminal of the fifth transistor (T5) may be connected to a light-emitting element (LED).

[0114] The gate terminal of the fifth transistor (T5) can receive the first emission control signal (EM1) through the first emission control line (ECL1). The fifth transistor (T5) can be turned on or off in response to the first emission control signal (EM1). For example, when the fifth transistor (T5) is an n-type transistor, the fifth transistor (T5) can be turned off in response to the first emission control signal (EM1) having a negative voltage level, and can be turned on in response to the first emission control signal (EM1) having a positive voltage level. In addition, when the fifth transistor (T5) is a p-type transistor, the fifth transistor (T5) can be turned off in response to the first emission control signal (EM1) having a positive voltage level, and can be turned on in response to the first emission control signal (EM1) having a negative voltage level. During the period in which the fifth transistor (T5) is turned on, the fifth transistor (T5) can electrically connect the first transistor (T1`) and the light-emitting element (LED). Specifically, the fifth transistor (T5) can electrically connect the second terminal of the first transistor (T1`) and the cathode of the light-emitting element (LED) in response to the first light-emitting control signal (EM1).

[0115] The sixth transistor (T6) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the sixth transistor (T6) may be a source, and the second terminal of the sixth transistor (T6) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the sixth transistor (T6) may be a drain, and the second terminal of the sixth transistor (T6) may be a source. The gate terminal of the sixth transistor (T6) may be connected to a second emission control line (ECL2). The first terminal of the sixth transistor (T6) may be connected to a second voltage line (VL2). The second terminal of the sixth transistor (T6) may be connected to a second node (N2).

[0116] The gate terminal of the sixth transistor (T6) can receive a second light emission control signal (EM2) through a second light emission control line (ECL2). The sixth transistor (T6) can be turned on or off in response to the second light emission control signal (EM2). For example, when the sixth transistor (T6) is an n-type transistor, the sixth transistor (T6) can be turned off in response to the second light emission control signal (EM2) having a negative voltage level, and can be turned on in response to the second light emission control signal (EM2) having a positive voltage level. In addition, when the sixth transistor (T6) is a p-type transistor, the sixth transistor (T6) can be turned off in response to the second light emission control signal (EM2) having a positive voltage level, and can be turned on in response to the second light emission control signal (EM2) having a negative voltage level. During the period in which the sixth transistor (T6) is turned on, the sixth transistor (T6) can provide the second power voltage (ELVSS) to the second node (N2).

[0117] Although the fifth transistor (T5) and the sixth transistor (T6) in FIG. 2B are illustrated as being independently driven by different light emission control signals, the present disclosure is not necessarily limited thereto. For example, the first light emission control signal (EM1) and the second light emission control signal (EM2) may be provided as a substantially single light emission control signal, and the fifth transistor (T5) and the sixth transistor (T6) may be turned on / off simultaneously. In this case, the first light emission control line (ECL1) and the second light emission control line (ECL2) may also be provided as a single light emission control line.

[0118] The first capacitor (C1) of Fig. 2b may be identical to the first capacitor (C1) described with reference to Fig. 2a. Accordingly, the description of the first capacitor (C1) of Fig. 2a may be applied. That is, the first capacitor (C1) may be charged and discharged according to the data voltage (VDATA) transmitted to the first node (N1).

[0119] The second capacitor (C2) may include a first terminal and a second terminal. The first terminal of the second capacitor (C2) may be connected to a second node (N2). The second terminal of the second capacitor (C2) may be connected to a second voltage line (VL2). Specifically, the second capacitor (C2) may be connected in series with the first capacitor (C1). The data voltage (VDATA) may be transmitted to the first node (N1), and the data voltage (VDATA) may be voltage-divided due to the series connection of the first capacitor (C1) and the second capacitor (C2) and transmitted to the second node (N2). Since the first transistor (T1) generates a driving current based on the voltage of the first node (N1) and the voltage of the second node (N2), the data range may be expanded.

[0120] The light emitting element (LED) of FIG. 2B may be substantially the same as the light emitting element (LED) referring to FIG. 2A, except that the cathode is connected to the second terminal of the first transistor (T1`) via the fifth transistor (T5). Therefore, any redundant description will be omitted or simplified. That is, the cathode of the light emitting element (LED) may be connected to the second terminal of the first transistor (T1`) via the fifth transistor (T5). In addition, the cathode of the light emitting element (LED) may be provided with a first initialization voltage (Vcint) via the third transistor (T3).

[0121] FIG. 2c is a circuit diagram showing an example of the circuit structure of a pixel included in the display device of FIG. 1a and FIG. 1b.

[0122] Compared to the embodiment of the circuit structure of the pixel (PX) described with reference to FIG. 2b, the pixel driving circuit unit (PC``) in the embodiment of the circuit structure of the pixel (PX) described with reference to FIG. 2c may further include a seventh transistor (T7) and an eighth transistor (T8). Therefore, redundant descriptions of some components are omitted or simplified.

[0123] Referring to FIG. 2C, in one embodiment, a pixel (PX) may include a light-emitting element (LED) and a pixel driving circuit (PC``) connected to the light-emitting element (LED). In one embodiment, the pixel driving circuit (PC``) may include first to eighth transistors (T1`, T2, T3, T4, T5, T6, T7, T8), a first capacitor (C1), and a second capacitor (C2). In FIG. 2C, all of the first to eighth transistors (T1`, T2, T3, T4, T5, T6, T7, T8) are illustrated as n-type transistors. However, the present disclosure is not limited thereto, and some of the first to eighth transistors (T1`, T2, T3, T4, T5, T6, T7, T8) may be n-type transistors, and others may be p-type transistors. For example, the first transistor (T1`) may be an n-type transistor, some of the second to eighth transistors (T2, T3, T4, T5, T6, T7, T8) may be n-type transistors, and others may be p-type transistors.

[0124] When the pixel (PX) includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, the present disclosure is not necessarily limited thereto, and both the active pattern of the n-type transistor and the active pattern of the p-type transistor may include a silicon semiconductor material.

[0125] The pixel driving circuit (PC``) can be connected to first to fourth gate lines (GWL, GCL, GRL, GIL), a data line (DL), first to fifth voltage lines (VL1, VL2, VL3, VL4, VL5), and an emission control line (ECL). The first gate line (GWL) can transmit a first gate signal (GW). The second gate line (GCL) can transmit a second gate signal (GC). The third gate line (GRL) can transmit a third gate signal (GR). The fourth gate line (GIL) can transmit a fourth gate signal (GI). The data line (DL) can transmit a data voltage (VDATA). The first voltage line (VL1) can transmit a first power voltage (ELVDD) having a relatively high voltage level. The second voltage line (VL2) can transmit a second power voltage (ELVSS) having a relatively low voltage level. The third voltage line (VL3) can transmit the first initialization voltage (Vcint). The fourth voltage line (VL4) can transmit the reference voltage (Vref). The reference voltage (Vref) can have a voltage level lower than the first power supply voltage (ELVDD). The fifth voltage line (VL5) can transmit the second initialization voltage (Vint). The first initialization voltage (Vcint) and the second initialization voltage (Vint) can have different voltage levels.

[0126] The first to sixth transistors (T1`, T2, T3, T4, T5, T6), the first capacitor (C1), and the second capacitor (C2) of FIG. 2c may be substantially the same as the first to sixth transistors (T1`, T2, T3, T4, T5, T6), the first capacitor (C1), and the second capacitor (C2) described with reference to FIG. 2b. Therefore, the description of the first to sixth transistors (T1`, T2, T3, T4, T5, T6), the first capacitor (C1), and the second capacitor (C2) described with reference to FIG. 2b may be applied. Therefore, redundant descriptions are omitted.

[0127] Meanwhile, although the fifth transistor (T5) and the sixth transistor (T6) in FIG. 2c are illustrated as being simultaneously driven by the light emission control signal (EM), the present disclosure is not necessarily limited thereto. For example, as in FIG. 2b, the fifth transistor (T5) and the sixth transistor (T6) may be independently driven by different light emission control signals (e.g., the first light emission control signal (EM1) and the second light emission control signal (EM2) in FIG. 2b). At this time, the light emission control line connected to the fifth transistor (T5) and the light emission control line connected to the sixth transistor (T6) may be different light emission control lines that are distinct from each other (e.g., the first light emission control line (ECL1) and the second light emission control line (ECL2) in FIG. 2b).

[0128] The seventh transistor (T7) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the seventh transistor (T7) may be a source, and the second terminal of the seventh transistor (T7) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the seventh transistor (T7) may be a drain, and the second terminal of the seventh transistor (T7) may be a source. The gate terminal of the seventh transistor (T7) may be connected to a second gate line (GCL). The first terminal of the seventh transistor (T7) may be connected to a fourth node (N4). The second terminal of the seventh transistor (T7) may be connected to a third voltage line (VL3).

[0129] The gate terminal of the seventh transistor (T7) can receive a second gate signal (GC) through a second gate line (GCL). The seventh transistor (T7) can be turned on or off in response to the second gate signal (GC). For example, when the seventh transistor (T7) is an n-type transistor, the seventh transistor (T7) can be turned off in response to the second gate signal (GC) having a negative voltage level, and can be turned on in response to the second gate signal (GC) having a positive voltage level. In addition, when the seventh transistor (T7) is a p-type transistor, the seventh transistor (T7) can be turned off in response to the second gate signal (GC) having a positive voltage level, and can be turned on in response to the second gate signal (GC) having a negative voltage level. During the period in which the seventh transistor (T7) is turned on, the seventh transistor (T7) can provide a first initialization voltage (Vcint) to the fourth node (N4). Specifically, the seventh transistor (T7) can compensate for the threshold voltage (Vth) of the first transistor (T1) by providing the first initialization voltage (Vcint) to the fourth node (N4) in response to the second gate signal (GC).

[0130] Meanwhile, although the gate line connected to the third transistor (T3) and the gate line connected to the seventh transistor (T7) in FIG. 2c are illustrated as being a single gate line (i.e., the second gate line (GCL)), the present disclosure is not necessarily limited thereto. For example, the gate line connected to the third transistor (T3) and the gate line connected to the seventh transistor (T7) may be different gate lines that are distinct from each other.

[0131] In addition, although the third transistor (T3) and the seventh transistor (T7) are illustrated as being simultaneously driven by the second gate signal (GC) in FIG. 2C, the present disclosure is not necessarily limited thereto. For example, the third transistor (T3) and the seventh transistor (T7) may be independently driven by different gate signals. In this case, the gate line connected to the third transistor (T3) and the gate line connected to the seventh transistor (T7) may be different gate lines that are distinct from each other.

[0132] The eighth transistor (T8) may include a gate terminal, a first terminal, and a second terminal. In one embodiment, the first terminal of the eighth transistor (T8) may be a source, and the second terminal of the eighth transistor (T8) may be a drain. However, the present disclosure is not necessarily limited thereto, and the first terminal of the eighth transistor (T8) may be a drain, and the second terminal of the eighth transistor (T8) may be a source. The gate terminal of the eighth transistor (T8) may be connected to a fourth gate line (GIL). The first terminal of the eighth transistor (T8) may be connected to a second node (N2). The second terminal of the eighth transistor (T8) may be connected to a fifth voltage line (VL5).

[0133] The gate terminal of the eighth transistor (T8) can receive a fourth gate signal (GI) through a fourth gate line (GIL). The eighth transistor (T8) can be turned on or off in response to the fourth gate signal (GI). For example, when the eighth transistor (T8) is an n-type transistor, the eighth transistor (T8) can be turned off in response to the fourth gate signal (GI) having a negative voltage level, and can be turned on in response to the fourth gate signal (GI) having a positive voltage level. In addition, when the eighth transistor (T8) is a p-type transistor, the eighth transistor (T8) can be turned off in response to the fourth gate signal (GI) having a positive voltage level, and can be turned on in response to the fourth gate signal (GI) having a negative voltage level. During the period in which the eighth transistor (T8) is turned on, the eighth transistor (T8) can provide a second initialization voltage (Vint) to the second node (N2).

[0134] The light-emitting element (LED) of Fig. 2c may be substantially identical to the light-emitting element (LED) described with reference to Fig. 2b. Therefore, the description of the light-emitting element (LED) with reference to Fig. 2c may be applied. Therefore, redundant descriptions are omitted.

[0135] As illustrated in FIGS. 2A to 2C, according to the present disclosure, the anode of the light-emitting element (LED) can receive a first power supply voltage (ELVDD) through a first voltage line (VL1), and the cathode of the light-emitting element (LED) can be connected to the second terminal of the first transistor (T1, T1`). That is, the potential of the cathode of the light-emitting element (LED) can be controlled by being electrically connected to the first transistor (T1, T1`).

[0136] Since the first voltage line (VL1) provides a first power supply voltage (ELVDD) of a high voltage level, and the second voltage line (VL2) provides a second power supply voltage (ELVSS) of a low voltage level, when the first transistor (T1, T1`) is an n-type transistor, the second terminal of the first transistor (T1, T1`) may be a drain. That is, according to the present disclosure, the cathode of the light-emitting element (LED) may be connected to the drain of the first transistor (T1, T1`).

[0137] When the first transistor (T1, T1`) is an n-type transistor, if the anode of the light-emitting element (LED) is connected to the source of the first transistor (T1, T1`), the source voltage of the first transistor (T1, T1`) may shift due to deterioration of the light-emitting element (LED), causing the gate-source voltage (Vgs) of the first transistor (T1, T1`) to change. As a result, the range of change in the driving current (ID) may increase, causing afterimage defects and reducing the lifespan of the display device.

[0138] According to the present disclosure, the anode of a light-emitting element (LED) can receive a first power supply voltage (ELVDD), and the cathode of the light-emitting element (LED) can be connected to the drain of a first transistor (T1, T1`). Accordingly, even when the light-emitting element (LED) deteriorates, the gate-source voltage (Vgs) of the first transistor (T1, T1`) may not change. Accordingly, the range of change in the driving current (ID) due to deterioration of the light-emitting element (LED) can be reduced. Accordingly, the afterimage defect of the display device (DD) due to increased use time can be reduced, and the lifespan of the display device (DD) can be improved.

[0139] Meanwhile, the circuit structure of the pixels illustrated in FIGS. 2A to 2C (e.g., the number or arrangement of transistors, the number or arrangement of capacitors) is merely an example and may be changed in various ways depending on the embodiments.

[0140] Fig. 3 is a plan view schematically illustrating an example of a portion of the display device of Figs. 1a and 1b. Fig. 4 is an enlarged view of one of the unit light-emitting regions of Fig. 3. Fig. 5 is a cross-sectional view taken along line II` of Fig. 4.

[0141] Specifically, FIG. 3 illustrates four regions arranged in a matrix form consisting of a two-row, two-column matrix, two of which are first unit light-emitting regions (UEA1) positioned diagonally from each other, and the remaining two regions are second unit light-emitting regions (UEA2) positioned diagonally from each other. FIG. 4 illustrates one first unit light-emitting region (UEA1) among the first and second unit light-emitting regions (UEA1, UEA2) illustrated in FIG. 3. For convenience of explanation, some of the configurations illustrated in FIG. 5 are omitted or emphasized in FIGS. 3 and 4. In addition, although second electrodes (E2a, E2b, E2c) are illustrated in FIG. 4, they are omitted in FIG. 3 for clarity of explanation.

[0142] Referring to FIGS. 3 and 4, the display device (DD) may include first to third pixel driving circuits (PCa, PCb, PCc), first to third light-emitting elements (LEDa, LEDb, LEDc), first to third connection electrodes (CEa, CEb, CEc), first to third connection patterns (CNPa, CNPb, CNPc), and a separator (SPR).

[0143] Each of the first to third pixel driving circuits (PCa, PCb, PCc) may correspond to at least one of the pixel driving circuits (PC, PC`, PC``) described with reference to FIGS. 2a to 2c. That is, each of the first to third pixel driving circuits (PCa, PCb, PCc) may include at least one transistor and at least one capacitor. For example, each of the first to third pixel driving circuits (PCa, PCb, PCc) may include a first transistor (TR1), a second transistor (TR2), a first capacitor (CAP1), and a second capacitor (CAP2) illustrated in FIG. 5.

[0144] At this time, the first transistor (TR1) of FIG. 5 may be a transistor connected to a light-emitting element through a connection electrode and a connection pattern. For example, when the first to third pixel driving circuits (PCa, PCb, PCc) are the pixel driving circuit (PC) of FIG. 2a, the first transistor (TR1) may be the first transistor (T1) of FIG. 2a, and the second transistor (TR2) may be the second transistor (T2) of FIG. 2a. In addition, when the first to third pixel driving circuits (PCa, PCb, PCc) are the pixel driving circuit (PC`) of FIG. 2b, the first transistor (TR1) may be the fifth transistor (T5) of FIG. 2b, and the second transistor (TR2) may be any one of the first to fourth transistors (T1`, T2, T3, T4) and the sixth transistor (T6) of FIG. 2b. In addition, when the first to third pixel driving circuits (PCa, PCb, PCc) are the pixel driving circuits (PC``) of FIG. 2C, the first transistor (TR1) may be the fifth transistor (T5) of FIG. 2C, and the second transistor (TR2) may be any one of the first to fourth transistors (T1`, T2, T3, T4) and the sixth to eighth transistors (T6, T7, T8) of FIG. 2C. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0145] In one embodiment, the first capacitor (CAP1) of FIG. 5 may correspond to the first capacitor (C1) of FIGS. 2A to 2C, and the second capacitor (CAP2) of FIG. 5 may correspond to the second capacitor (C2) of FIGS. 2B and 2C. That is, when the first to third pixel driving circuits (PCa, PCb, PCc) are the pixel driving circuits (PC) of FIG. 2A, the second capacitor (CAP2) may be omitted. However, the present disclosure is not necessarily limited thereto, and in one embodiment, the first capacitor (CAP1) of FIG. 5 may correspond to the second capacitor (C2) of FIGS. 2A to 2C, and the second capacitor (CAP2) of FIG. 5 may correspond to the first capacitor (C1) of FIGS. 2B and 2C. In this case, if the first to third pixel driving circuits (PCa, PCb, PCc) are the pixel driving circuits (PC) of FIG. 2a, the first capacitor (CAP1) may be omitted.

[0146] The components of the first transistor (TR1), the second transistor (TR2), the first capacitor (CAP1), and the second capacitor (CAP2) will be described in more detail later with reference to FIG. 5.

[0147] Meanwhile, in FIGS. 3 and 4, the first to third pixel driving circuits (PCa, PCb, PCc) are illustrated as being sequentially arranged along the first direction (DR1) in a rectangular shape. However, the present disclosure is not necessarily limited thereto, and the shape and arrangement of the first to third pixel driving circuits (PCa, PCb, PCc) may be varied in various ways depending on the embodiments.

[0148] Each of the first to third light-emitting elements (LEDa, LEDb, LEDc) may correspond to the light-emitting elements (LED) described with reference to FIGS. 2a to 2c. For example, the first to third light-emitting elements (LEDa, LEDb, LEDc) may be formed of a first electrode layer (e.g., the first electrode layer E1 of FIG. 5), an intermediate layer (e.g., the intermediate layer ML of FIG. 5) disposed on the first electrode layer, and a second electrode layer (E2) disposed on the intermediate layer. In one embodiment, the first electrode layer may function as the anode of FIGS. 2a to 2c, and the second electrode layer (E2) may function as the cathode of FIGS. 2a to 2c.

[0149] In one embodiment, the first electrode layer (E1) may include first electrodes (E1a, E1b, E1c, see FIG. 7) described below. Specifically, the first electrode layer (E1) may include a first electrode (E1a) of a first light-emitting element (LEDa), a first electrode (E1b) of a second light-emitting element (LEDb), and a first electrode (E1c) of a third light-emitting element (LEDc). This will be described in more detail below with reference to FIG. 7.

[0150] In one embodiment, the second electrode layer (E2) may be separated (or disconnected) into second electrodes (E2a, E2b, E2c) by a separator (SPR). Specifically, the second electrode layer (E2) may be separated (or disconnected) into a second electrode (E2a) of a first light-emitting element (LEDa), a second electrode (E2b) of a second light-emitting element (LEDb), and a second electrode (E2c) of a third light-emitting element (LEDc), and the second electrodes (E2a, E2b, E2c) may be electrically independent of each other. This will be described in more detail below.

[0151] That is, the first light-emitting element (LEDa) may include a first electrode (E1a, see FIG. 7) functioning as the anode and a second electrode (E2a) functioning as the cathode, the second light-emitting element (LEDb) may include a first electrode (E1b, see FIG. 7) functioning as the anode and a second electrode (E2b) functioning as the cathode, and the third light-emitting element (LEDc) may include a first electrode (E1c, see FIG. 7) functioning as the anode and a second electrode (E2c) functioning as the cathode.

[0152] The first to third light-emitting elements (LEDa, LEDb, LEDc) can emit light of different colors. For example, the first light-emitting element (LEDa) can emit red light, the second light-emitting element (LEDb) can emit green light, and the third light-emitting element (LEDc) can emit blue light. However, the present disclosure is not necessarily limited thereto.

[0153] In one embodiment, the display device (DD) may include a first unit light-emitting area (UEA1) and a second unit light-emitting area (UEA2). The first unit light-emitting area (UEA1) and the second unit light-emitting area (UEA2) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). Although four unit light-emitting areas are illustrated in FIG. 3, this is not a limitation of the present disclosure, and more unit light-emitting areas in the display area (DA, see FIGS. 1A and 1B) may be arranged in a matrix form overall along the first direction (DR1) and the second direction (DR2).

[0154] Within each of the first unit light emitting area (UEA1) and the second unit light emitting area (UEA2), first to third light emitting elements (LEDa, LEDb, LEDc) adjacent to each other may be arranged. For example, within each of the first unit light emitting area (UEA1) and the second unit light emitting area (UEA2), first to third light emitting areas (EAa, EAb, EAc) adjacent to each other may be defined, and the first to third light emitting elements (LEDa, LEDb, LEDc) may be arranged in the first to third light emitting areas (EAa, EAb, EAc), respectively.

[0155] The first to third light-emitting regions (EAa, EAb, EAc) may be defined by pixel openings of a pixel defining layer (PDL, see FIG. 5) described later. That is, the first to third light-emitting regions (EAa, EAb, EAc) may be regions where light is emitted by light-emitting elements. For example, the first light-emitting element (LEDa) may be disposed in the first light-emitting region (EAa), and the first light-emitting region (EAa) may be a region where light is emitted by the first light-emitting element (LEDa). In addition, the second light-emitting element (LEDb) may be disposed in the second light-emitting region (EAb), and the second light-emitting region (EAb) may be a region where light is emitted by the second light-emitting element (LEDb). In addition, the third light-emitting element (LEDc) may be disposed in the third light-emitting region (EAc), and the third light-emitting region (EAc) may be a region where light is emitted by the third light-emitting element (LEDc).

[0156] In one embodiment, the first unit light emitting area (UEA1) and the second unit light emitting area (UEA2) can be distinguished based on the arrangement of the first to third light emitting elements (LEDa, LEDb, LEDc) (or the arrangement of the first to third light emitting areas (EAa, EAb, EAc)). That is, the positions of the first to third light emitting elements (LEDa, LEDb, LEDc) (or the first to third light emitting areas (EAa, EAb, EAc)) in each first unit light emitting area (UEA1) can be the same, and the positions of the first to third light emitting elements (LEDa, LEDb, LEDc) (or the first to third light emitting areas (EAa, EAb, EAc)) in each second unit light emitting area (UEA2) can be the same.

[0157] As illustrated in FIG. 3, in one embodiment, the first unit light emitting area (UEA1) and the second unit light emitting area (UEA2) may be alternately arranged along the first direction (DR1) (i.e., row direction) and the second direction (DR2) (i.e., column direction). However, the present disclosure is not necessarily limited thereto, and the number of different unit light emitting areas included in the display device (DD) or the arrangement relationship between the unit light emitting areas may vary depending on the embodiments.

[0158] Meanwhile, in FIGS. 3 and 4, the first to third light-emitting areas (EAa, EAb, EAc) are illustrated as being arranged in an S-stripe type. However, the present disclosure is not necessarily limited thereto, and the arrangement of the first to third light-emitting areas (EAa, EAb, EAc) may be varied in various ways depending on the embodiments.

[0159] The first to third light-emitting elements (LEDa, LEDb, LEDc) may be connected to the first to third pixel driving circuits (PCa, PCb, PCc), respectively. For example, the first light-emitting element (LEDa) may be connected to the first pixel driving circuit (PCa), the second light-emitting element (LEDb) may be connected to the second pixel driving circuit (PCb), and the third light-emitting element (LEDc) may be connected to the third pixel driving circuit (PCc). Accordingly, the first pixel driving circuit (PCa) and the first light-emitting element (LEDa) may form one pixel, the second pixel driving circuit (PCb) and the second light-emitting element (LEDb) may form one pixel, and the third pixel driving circuit (PCc) and the third light-emitting element (LEDc) may form one pixel.

[0160] Hereinafter, the connection relationship between the first to third light-emitting elements (LEDa, LEDb, LEDc) and the first to third pixel driving circuits (PCa, PCb, PCc) will be described in more detail with respect to the first unit light-emitting area (UEA1) of FIG. 4 as the center. The following description regarding the connection relationship between the first to third light-emitting elements (LEDa, LEDb, LEDc) and the first to third pixel driving circuits (PCa, PCb, PCc) can be applied to all unit light-emitting areas.

[0161] As described above, the display device (DD) may include first to third connection electrodes (CEa, CEb, CEc) and first to third connection patterns (CNPa, CNPb, CNPc). The first connection electrode (CEa) and the first connection pattern (CNPa) may connect the first light-emitting element (LEDa) and the first pixel driving circuit unit (PCa), the second connection electrode (CEb) and the second connection pattern (CNPb) may connect the second light-emitting element (LEDb) and the second pixel driving circuit unit (PCb), and the third connection electrode (CEc) and the third connection pattern (CNPc) may connect the third light-emitting element (LEDc) and the third pixel driving circuit unit (PCc).

[0162] The first to third connecting electrodes (CEa, CEb, CEc) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. Examples of the conductive material that can be used as the first to third connecting electrodes (CEa, CEb, CEc) include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), an alloy containing silver (Ag), an alloy containing copper (Cu), an alloy containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), tin oxide (SnO), gallium oxide (GaO), indium gallium zinc oxide (IGZO), indium tin zinc There may be oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), aluminum zinc oxide (AZO), etc. These may be used alone or in combination with each other. In one embodiment, the first to third connecting electrodes (CEa, CEb, CEc) may have a single-layer structure or a multi-layer structure in which a plurality of conductive layers are stacked.

[0163] In one embodiment, the first to third connecting patterns (CNPa, CNPb, CNPc) may include a transparent conductive oxide. Examples of the transparent conductive oxide that may be used as the first to third connecting patterns (CNPa, CNPb, CNPc) may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), gallium oxide (GaO), aluminum zinc oxide (AZO), and the like. These may be used alone or in combination with each other.

[0164] However, the present disclosure is not necessarily limited thereto, and the first to third connection patterns (CNPa, CNPb, CNPc) may include a conductive material such as a metal, an alloy, or a conductive metal nitride. Examples of the conductive material that can be used as the first to third connecting patterns (CNPa, CNPb, CNPc) include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), an alloy containing silver (Ag), an alloy containing copper (Cu), an alloy containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), and the like. These can be used alone or in combination with each other.

[0165] In one embodiment, the first to third connection patterns (CNPa, CNPb, CNPc) may have a single-layer structure or a multi-layer structure in which a plurality of conductive layers are stacked.

[0166] The first connecting electrode (CEa) may include a first circuit connecting portion (CPa) and a first light emitting connecting portion (CNa).

[0167] The first circuit connection portion (CPa) may be a portion of the first connection electrode (CEa) that is connected to the first pixel driving circuit portion (PCa). Specifically, the first circuit connection portion (CPa) may be a portion of the first connection electrode (CEa) that is connected to the first transistor (TR1, see FIG. 5) of the first pixel driving circuit portion (PCa). Accordingly, the position of the first circuit connection portion (CPa) may correspond to the position of the first transistor (TR1) of the first pixel driving circuit portion (PCa). Specifically, the position of the first circuit connection portion (CPa) may correspond to the position of a contact hole that extends so as to be in contact with the first connection electrode (CEa) through an insulating layer (the fifth insulating layer (IL5) of FIG. 5).

[0168] The first light-emitting connection portion (CNa) may be a portion of the first connection electrode (CEa) that is connected to the first connection pattern (CNPa). Specifically, the first light-emitting connection portion (CNa) may be a portion that is exposed from the sixth insulating layer (IL6, see FIG. 5) and the pixel defining layer (PDL, see FIG. 5) to be connected to the first connection pattern (CNPa) of the first connection electrode (CEa). Accordingly, the position of the first light-emitting connection portion (CNa) may correspond to the position of the opening of the sixth insulating layer (IL6) that is aligned with the opening of the pixel defining layer (PDL). In a plan view, the first light-emitting connection portion (CNa) may not overlap the first light-emitting area (EAa). For example, in a plan view, the first light-emitting connection portion (CNa) may be disposed between the first light-emitting area (EAa) and the separator (SPR) (e.g., see FIG. 4).

[0169] The first connection pattern (CNPa) may be connected to the first connection electrode (CEa). For example, the first connection pattern (CNPa) may be in contact with the first light-emitting connection portion (CNa) of the first connection electrode (CEa). However, the present disclosure is not necessarily limited to this exact structure, and the first connection pattern (CNPa) may not be in direct contact with the first connection electrode (CEa). For example, the first connection pattern (CNPa) may be in contact with a capping layer that is in contact with the first light-emitting connection portion (CNa) of the first connection electrode (CEa), and may be connected to the first light-emitting connection portion (CNa) of the first connection electrode (CEa) through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be formed simultaneously with the first electrode layer (E1, see FIG. 5) described below, and may include the same material.

[0170] The first connection pattern (CNPa) may not overlap the first light-emitting area (EAa) on a plane. In one embodiment, the first connection pattern (CNPa) may surround at least a portion of the first light-emitting area (EAa) on a plane. For example, the first connection pattern (CNPa) may have a closed ring shape that entirely surrounds the first light-emitting area (EAa) on a plane. However, the present disclosure is not necessarily limited thereto.

[0171] The second electrode (E2a) of the first light-emitting element (LEDa) can be connected to the first connection pattern (CNPa). Specifically, the second electrode (E2a) of the first light-emitting element (LEDa) can be in contact with the first connection pattern (CNPa). Accordingly, the first connection pattern (CNPa) can connect the first connection electrode (CEa) and the second electrode (E2a) of the first light-emitting element (LEDa). As a result, the second electrode (E2a) of the first light-emitting element (LEDa) can be connected to the first pixel driving circuit (PCa) through the first connection electrode (CEa) and the first connection pattern (CNPa).

[0172] In one embodiment, the planar profile of the area where the second electrode (E2a) of the first light-emitting element (LEDa) and the first connection pattern (CNPa) come into contact may be substantially the same as or similar to the planar profile of the edge of the first connection pattern (CNPa). For example, when the first connection pattern (CNPa) has a closed shape that entirely surrounds the first light-emitting area (EAa) on a planar surface, the area where the second electrode (E2a) of the first light-emitting element (LEDa) and the first connection pattern (CNPa) come into contact may have a closed shape on a planar surface. That is, the second electrode (E2a) of the first light-emitting element (LEDa) and the first connection pattern (CNPa) may come into contact with each other at a position that does not overlap the first light-emitting area (EAa). Accordingly, the second electrode (E2a) of the first light-emitting element (LEDa) and the first pixel driving circuit (PCa) can be connected through the first connection pattern (CNPa) and the first connection electrode (CEa) without reducing the light-emitting area of ​​the first light-emitting region (EAa).

[0173] The second connecting electrode (CEb) may include a second circuit connecting portion (CPb) and a second light emitting connecting portion (CNb).

[0174] The second circuit connection portion (CPb) may be a portion of the second connection electrode (CEb) that is connected to the second pixel driving circuit portion (PCb). Specifically, the second circuit connection portion (CPb) may be a portion of the second connection electrode (CEb) that is connected to the first transistor (TR1, see FIG. 5) of the second pixel driving circuit portion (PCb). Accordingly, the position of the second circuit connection portion (CPb) may correspond to the position of the first transistor (TR1) of the second pixel driving circuit portion (PCb). Specifically, the position of the second circuit connection portion (CPb) may correspond to the position of a contact hole that extends through an insulating layer (the fifth insulating layer (IL5) of FIG. 5) so as to be in contact with the first transistor (TR1) of the second pixel driving circuit portion (PCb).

[0175] The second light-emitting connection portion (CNb) may be a portion of the second connection electrode (CEb) that is connected to the second connection pattern (CNPb). Specifically, the second light-emitting connection portion (CNb) may be a portion that is exposed from the sixth insulating layer (IL6, see FIG. 5) and the pixel defining layer (PDL, see FIG. 5) to be connected to the second connection pattern (CNPb) of the second connection electrode (CEb). Accordingly, the position of the second light-emitting connection portion (CNb) may correspond to the position of the opening of the sixth insulating layer (IL6) that is aligned with the opening of the pixel defining layer (PDL). In a plan view, the second light-emitting connection portion (CNb) may not overlap the second light-emitting area (EAb). For example, in a plan view, the second light-emitting connection portion (CNb) may be disposed between the second light-emitting area (EAb) and the separator (SPR).

[0176] In one embodiment, the second connection electrode (CEb) may be spaced apart from the first connection electrode (CEa) in a plane. In other words, the first connection electrode (CEa) and the second connection electrode (CEb) may be distinct electrodes.

[0177] The second connection pattern (CNPb) may be connected to the second connection electrode (CEb). For example, the second connection pattern (CNPb) may be in contact with the second light-emitting connection portion (CNb) of the second connection electrode (CEb). However, the present disclosure is not necessarily limited to this exact structure, and the second connection pattern (CNPb) may not be in direct contact with the second connection electrode (CEb). For example, the second connection pattern (CNPb) may be in contact with a capping layer that is in contact with the second light-emitting connection portion (CNb) of the second connection electrode (CEb), and may be connected to the second light-emitting connection portion (CNb) of the second connection electrode (CEb) through the capping layer. The capping layer may include a conductive material. For example, the capping layer may be formed simultaneously with the first electrode layer (E1, see FIG. 5) described below, and may include the same material.

[0178] The second connection pattern (CNPb) may not overlap the second light-emitting area (EAb) on a plane. In one embodiment, the second connection pattern (CNPb) may surround at least a portion of the second light-emitting area (EAb) on a plane. For example, the second connection pattern (CNPb) may have a closed ring shape that entirely surrounds the second light-emitting area (EAb) on a plane. However, the present disclosure is not necessarily limited thereto.

[0179] In one embodiment, the second connection pattern (CNPb) may be spaced apart from the first connection pattern (CNPa). In other words, the first connection pattern (CNPa) and the second connection pattern (CNPb) may be distinct and separate patterns.

[0180] The second electrode (E2b) of the second light-emitting element (LEDb) can be connected to the second connection pattern (CNPb). Specifically, the second electrode (E2b) of the second light-emitting element (LEDb) can be in contact with the second connection pattern (CNPb). Accordingly, the second connection pattern (CNPb) can connect the second connection electrode (CEb) and the second electrode (E2b) of the second light-emitting element (LEDb). As a result, the second electrode (E2b) of the second light-emitting element (LEDb) can be connected to the second pixel driving circuit (PCb) through the second connection electrode (CEb) and the second connection pattern (CNPb).

[0181] In one embodiment, the planar profile of the area where the second electrode (E2b) of the second light-emitting element (LEDb) and the second connection pattern (CNPb) come into contact may be substantially the same as or similar to the planar profile of the edge of the second connection pattern (CNPb). For example, when the second connection pattern (CNPb) has a closed shape that entirely surrounds the second light-emitting area (EAb) on a planar surface, the area where the second electrode (E2b) of the second light-emitting element (LEDb) and the second connection pattern (CNPb) come into contact may have a closed shape on a planar surface. That is, the second electrode (E2b) of the second light-emitting element (LEDb) and the second connection pattern (CNPb) may come into contact with each other at a position that does not overlap the second light-emitting area (EAb). Accordingly, the second electrode (E2b) of the second light-emitting element (LEDb) and the second pixel driving circuit (PCb) can be connected through the second connection pattern (CNPb) and the second connection electrode (CEb) without reducing the light-emitting area of ​​the second light-emitting region (EAb).

[0182] The third connecting electrode (CEc) may include a third circuit connecting portion (CPc) and a third light emitting connecting portion (CNc).

[0183] The third circuit connection portion (CPc) may be a portion of the third connection electrode (CEc) that is connected to the third pixel driving circuit portion (PCc). Specifically, the third circuit connection portion (CPc) may be a portion of the third connection electrode (CEc) that is connected to the first transistor (TR1, see FIG. 5) of the third pixel driving circuit portion (PCc). Accordingly, the position of the third circuit connection portion (CPc) may correspond to the position of the first transistor (TR1) of the third pixel driving circuit portion (PCc). Specifically, the position of the third circuit connection portion (CPc) may correspond to the position of a contact hole that extends through an insulating layer (the fifth insulating layer (IL5) of FIG. 5) so that the third connection electrode (CEc) is in contact with the first transistor (TR1) of the third pixel driving circuit portion (PCc).

[0184] The third light-emitting connection portion (CNc) may be a portion of the third connection electrode (CEc) that is connected to the third connection pattern (CNPc). Specifically, the third light-emitting connection portion (CNc) may be a portion that is exposed from the sixth insulating layer (IL6, see FIG. 5) and the pixel defining layer (PDL, see FIG. 5) to make contact with the third connection pattern (CNPc) of the third connection electrode (CEc). Accordingly, the position of the third light-emitting connection portion (CNc) may correspond to the position of the opening of the sixth insulating layer (IL6) that is aligned with the opening of the pixel defining layer (PDL). In a plan view, the third light-emitting connection portion (CNc) may not overlap the third light-emitting area (EAc). For example, in a plan view, the third light-emitting connection portion (CNc) may be disposed between the third light-emitting area (EAc) and the separator (SPR).

[0185] In one embodiment, the third connection electrode (CEc) may be spaced apart from the first connection electrode (CEa) and the second connection electrode (CEb) in a plane. In other words, the first connection electrode (CEa), the second connection electrode (CEb), and the third connection electrode (CEc) may be distinct electrodes.

[0186] The third connection pattern (CNPc) may be connected to the third connection electrode (CEc). For example, the third connection pattern (CNPc) may be in contact with the third light-emitting connection portion (CNc) of the third connection electrode (CEc). However, the present disclosure is not necessarily limited to this exact structure, and the third connection pattern (CNPc) may not be in direct contact with the third connection electrode (CEc). For example, the third connection pattern (CNPc) may be in contact with a capping layer that is in contact with the third light-emitting connection portion (CNc) of the third connection electrode (CEc), and may be connected to the third light-emitting connection portion (CNc) of the third connection electrode (CEc) through the capping layer. The capping layer may include a conductive material. The capping layer may include a conductive material. For example, the capping layer may be formed simultaneously with the first electrode layer (E1, see FIG. 5) described below, and may include the same material.

[0187] The third connection pattern (CNPc) may not overlap the third light-emitting area (EAc) on a plane. In one embodiment, the third connection pattern (CNPc) may surround at least a portion of the third light-emitting area (EAc) on a plane. For example, the third connection pattern (CNPc) may have a closed ring shape that entirely surrounds the third light-emitting area (EAc) on a plane. However, the present disclosure is not necessarily limited thereto.

[0188] In one embodiment, the third connection pattern (CNPc) may be spaced apart from the first connection pattern (CNPa) and the second connection pattern (CNPb). In other words, the first connection pattern (CNPa), the second connection pattern (CNPb), and the third connection pattern (CNPc) may be distinct and separate patterns.

[0189] The second electrode (E2c) of the third light-emitting element (LEDc) can be connected to the third connection pattern (CNPc). Specifically, the second electrode (E2c) of the third light-emitting element (LEDc) can be in contact with the third connection pattern (CNPc). Accordingly, the third connection pattern (CNPc) can connect the third connection electrode (CEc) and the second electrode (E2c) of the third light-emitting element (LEDc). As a result, the second electrode (E2c) of the third light-emitting element (LEDc) can be connected to the third pixel driving circuit (PCc) through the third connection electrode (CEc) and the third connection pattern (CNPc).

[0190] In one embodiment, the planar profile of the area where the second electrode (E2c) of the third light-emitting element (LEDc) and the third connection pattern (CNPc) come into contact may be substantially the same as or similar to the planar profile of the edge of the third connection pattern (CNPc). For example, when the third connection pattern (CNPc) has a closed shape that entirely surrounds the third light-emitting area (EAc) on a planar surface, the area where the second electrode (E2c) of the third light-emitting element (LEDc) and the third connection pattern (CNPc) come into contact may have a closed shape on a planar surface. That is, the second electrode (E2c) of the third light-emitting element (LEDc) and the third connection pattern (CNPc) may come into contact with each other at a position that does not overlap the third light-emitting area (EAc). Accordingly, the second electrode (E2c) of the third light-emitting element (LEDc) and the third pixel driving circuit (PCc) can be connected through the third connection pattern (CNPc) and the third connection electrode (CEc) without reducing the light-emitting area of ​​the third light-emitting region (EAc).

[0191] According to one embodiment of the present disclosure, the second electrodes (E2a, E2b, E2c) can be brought into contact with the first to third connection patterns (CNPa, CNPb, CNPc) at positions that do not overlap with the first to third light-emitting areas (EAa, EAb, EAc), respectively. Accordingly, the second electrodes (E2a, E2b, E2c) can be brought into contact with the first to third connection patterns (CNPa, CNPb, CNPc) without reducing the light-emitting area.

[0192] In addition, according to one embodiment of the present disclosure, the second electrodes (E2a, E2b, E2c) may be connected to the first to third pixel driving circuits (PCa, PCb, PCc) through the first to third connection electrodes (CEa, CEb, CEc) and the first to third connection patterns (CNPa, CNPb, CNPc), respectively. Accordingly, constraints on the position, shape, and size of the first to third light-emitting areas (EAa, EAb, EAc) in the design of the first to third pixel driving circuits (PCa, PCb, PCc) may be reduced. For example, even if at least some of the first to third circuit connection portions (CPa, CPb, CPc) overlap with the first to third light-emitting areas (EAa, EAb, EAc), the second electrodes (E2a, E2b, E2c) can be easily connected to the first to third pixel driving circuit portions (PCa, PCb, PCc) through the first to third connection electrodes (CEa, CEb, CEc) and the first to third connection patterns (CNPa, CNPb, CNPc). Therefore, the shape and arrangement of the first to third pixel driving circuit portions (PCa, PCb, PCc) can be designed independently from the position, shape, and size of the first to third light-emitting areas (EAa, EAb, EAc). Therefore, the degree of freedom in the design of the first to third pixel driving circuit portions (PCa, PCb, PCc) can be increased.

[0193] In one embodiment, the first to third pixel driving circuits (PCa, PCb, PCc) may be designed to be identical to each other regardless of the position, shape, size, etc. of the first to third light-emitting areas (EAa, EAb, EAc). In addition, as described above, the position of the first circuit connection portion (CPa) may correspond to the position of the first transistor (TR1, see FIG. 5) of the first pixel driving circuit portion (PCa), the position of the second circuit connection portion (CPb) may correspond to the position of the first transistor (TR1) of the second pixel driving circuit portion (PCb), and the position of the third circuit connection portion (CPc) may correspond to the position of the first transistor (TR1) of the third pixel driving circuit portion (PCc). Accordingly, when the first to third pixel driving circuits (PCa, PCb, PCc) are formed to have substantially the same size and to be arranged along the first direction (DR1), the position of the first circuit connection portion (CPa), the position of the second circuit connection portion (CPb), and the position of the third circuit connection portion (CPc) can be arranged along the first direction (DR1).

[0194] Meanwhile, as illustrated in FIG. 3, the shapes or arrangements of the first to third connection electrodes (CEa, CEb, CEc) and the positions of the first to third connection electrodes (CEa, CEb, CEc) in each first unit light-emitting area (UEA1) may be the same as each other. In addition, the shapes or arrangements of the first to third connection electrodes (CEa, CEb, CEc) and the positions of the first to third connection electrodes (CEa, CEb, CEc) in each second unit light-emitting area (UEA2) may be the same as each other.

[0195] In addition, the shape or arrangement of each of the first to third connection patterns (CNPa, CNPb, CNPc) corresponding to each first unit light-emitting area (UEA1) and the arrangement relationship between the first to third connection patterns (CNPa, CNPb, CNPc) may be the same. In addition, the shape or arrangement of each of the first to third connection patterns (CNPa, CNPb, CNPc) corresponding to each second unit light-emitting area (UEA2) and the arrangement relationship between the first to third connection patterns (CNPa, CNPb, CNPc) may be the same.

[0196] As described above, the display device (DD) may include a separator (SPR).

[0197] A separator (SPR) may be disposed on a pixel defining layer (PDL, see FIG. 5) and the first to third connection patterns (CNPa, CNPb, CNPc). In one embodiment, the separator (SPR) may include an organic insulating material. For example, the separator (SPR) may include a photosensitive resin (e.g., photoresist). However, the present disclosure is not necessarily limited thereto.

[0198] The separator (SPR) can overlap the first to third connection patterns (CNPa, CNPb, CNPc) on a plane. Specifically, the separator (SPR) can cover a portion of the first to third connection patterns (CNPa, CNPb, CNPc) and between adjacent connection patterns. That is, at least a portion of the separator (SPR) can extend along the edges of the first to third connection patterns (CNPa, CNPb, CNPc) on a plane. Accordingly, regions where the second electrodes (E2a, E2b, E2c) and the first to third connection patterns (CNPa, CNPb, CNPc) come into contact can be adjacent to or overlap the separator (SPR) on a plane.

[0199] The second electrode layer (E2) can be separated (or disconnected) into second electrodes (E2a, E2b, E2c) by a separator (SPR). That is, the second electrode (E2a) of the first light-emitting element (LEDa), the second electrode (E2b) of the second light-emitting element (LEDb), and the second electrode (E2c) of the third light-emitting element (LEDc) can be electrically independent of each other by the separator (SPR).

[0200] The separator (SPR) can define first to third open areas (OA1, OA2, OA3) corresponding to the second electrodes (E2a, E2b, E2c), respectively. For example, the separator (SPR) can have a mesh structure surrounding the second electrodes (E2a, E2b, E2c) on a plane. The second electrode (E2a) of the first light-emitting element (LEDa) can be arranged in the first open area (OA1) of the separator (SPR), the second electrode (E2b) of the second light-emitting element (LEDb) can be arranged in the second open area (OA2) of the separator (SPR), and the second electrode (E2c) of the third light-emitting element (LEDc) can be arranged in the third open area (OA3) of the separator (SPR).

[0201] In one embodiment, the outer shape of the first open area (OA1) may be substantially the same as the outer shape of the second electrode (E2a) of the first light-emitting element (LEDa) on a plane, the outer shape of the second open area (OA2) may be substantially the same as the outer shape of the second electrode (E2b) of the second light-emitting element (LEDb) on a plane, and the outer shape of the third open area (OA3) may be substantially the same as the outer shape of the second electrode (E2c) of the third light-emitting element (LEDc) on a plane.

[0202] The first to third open areas (OA1, OA2, OA3) of the separator (SPR) may correspond to the first to third connection patterns (CNPa, CNPb, CNPc), respectively. For example, the first connection pattern (CNPa) may overlap the first open area (OA1), the second connection pattern (CNPb) may overlap the second open area (OA2), and the third connection pattern (CNPc) may overlap the third open area (OA3).

[0203] Hereinafter, the cross-sectional structure of the display device (DD) will be described in more detail with reference to FIG. 5, focusing on the first light-emitting area (EAa). The following description of the cross-sectional structure of the display device (DD) can be applied to all light-emitting areas.

[0204] Referring further to FIG. 5, in one embodiment, the display device (DD) may include a substrate (SUB), a first lower conductive layer (BML1), a second lower conductive layer (BML2), a first transistor (TR1), a second transistor (TR2), a first capacitor (CAP1), a second capacitor (CAP2), a first connection electrode (CEa), first to sixth insulating layers (IL1, IL2, IL3, IL4, IL5, IL6), a pixel defining layer (PDL), a first connection pattern (CNPa), a first light-emitting element (LEDa), a separator (SPR), a first dummy layer (DP1), a second dummy layer (DP2), and an encapsulation layer (ENC).

[0205] The first transistor (TR1) may include a first active pattern (AP1), a first gate electrode (GE1), a first contact electrode (SE1), and a second contact electrode (DE1). The second transistor (TR2) may include a second active pattern (AP2), a second gate electrode (GE2), a third contact electrode (SE2), and a fourth contact electrode (DE2). The first capacitor (CAP1) may include a first capacitor electrode (CPE1) and a second capacitor electrode (CPE2). The second capacitor (CAP2) may include a first capacitor electrode (CPE1) and a third capacitor electrode (CPE3). The first light-emitting element (LEDa) may include a first electrode (E1a), an intermediate layer (ML), and a second electrode (E2a).

[0206] As described above, the first transistor (TR1), the second transistor (TR2), the first capacitor (CAP1), and the second capacitor (CAP2) may be components included in the first pixel driving circuit unit (PCa).

[0207] The substrate (SUB) may form the base of the display device (DD). In one embodiment, examples of materials that may be used as the substrate (SUB) include glass, quartz, silicon, polymers, etc. These may be used alone or in combination. In addition, the substrate (SUB) may have a single-layer structure or a multi-layer structure in which multiple layers containing different materials are laminated.

[0208] The first lower conductive layer (BML1), the second lower conductive layer (BML2), and the third capacitor electrode (CPE3) may be disposed on the substrate (SUB). The first lower conductive layer (BML1), the second lower conductive layer (BML2), and the third capacitor electrode (CPE3) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide.

[0209] A first insulating layer (IL1) may be disposed on a substrate (SUB) and may cover a first lower conductive layer (BML1), a second lower conductive layer (BML2), and a third capacitor electrode (CPE3). The first insulating layer (IL1) may prevent metal atoms or impurities from diffusing from the substrate (SUB) to the first active pattern (AP1) and / or the second active pattern (AP2). The first insulating layer (IL1) may include an insulating material. Examples of the insulating material that may be used as the first insulating layer (IL1) may include silicon oxide, silicon nitride, silicon oxynitride, and the like. These may be used alone or in combination with each other.

[0210] A first active pattern (AP1) may be disposed on a first insulating layer (IL1). In one embodiment, the first active pattern (AP1) may overlap a first lower conductive layer (BML1). The first active pattern (AP1) may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The first active pattern (AP1) may include a first contact area (S1), a second contact area (D1), and a first channel area (CH1) between the first contact area (S1) and the second contact area (D1). The first contact area (S1) and the second contact area (D1) may have higher conductivity than the first channel area (CH1).

[0211] The second active pattern (AP2) may be disposed on the first insulating layer (IL1). In one embodiment, the second active pattern (AP2) may overlap the second lower conductive layer (BML2). The second active pattern (AP2) may include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The second active pattern (AP2) may include a third contact area (S2), a fourth contact area (D2), and a second channel area (CH2) between the third contact area (S2) and the fourth contact area (D2). The third contact area (S2) and the fourth contact area (D2) may have higher conductivity than the second channel area (CH2).

[0212] In one embodiment, the first active pattern (AP1) and the second active pattern (AP2) may include an oxide semiconductor material. Examples of the oxide semiconductor material that can be used as the first active pattern (AP1) and the second active pattern (AP2) may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin zinc oxide (ITZO). These may be used alone or in combination with each other. However, the present disclosure is not necessarily limited thereto, and the first active pattern (AP1) and the second active pattern (AP2) may include different materials. For example, one of the first active pattern (AP1) and the second active pattern (AP2) may include an oxide semiconductor material, and the other may include a silicon semiconductor material.

[0213] Meanwhile, in FIG. 5, the first active pattern (AP1) and the second active pattern (AP2) are illustrated as being arranged on the same layer. However, the present disclosure is not necessarily limited thereto, and the first active pattern (AP1) and the second active pattern (AP2) may be arranged on different layers.

[0214] The second insulating layer (IL2) covers the first active pattern (AP1) and the second active pattern (AP2) and may be disposed on the first insulating layer (IL1). The second insulating layer (ILD2) may include an insulating material. Examples of the insulating material that may be used as the second insulating layer (IL2) may include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0215] The first gate electrode (GE1) may be disposed on the second insulating layer (IL2). The first gate electrode (GE1) may overlap the first channel region (CH1) of the first active pattern (AP1). The first gate electrode (GE1) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. Although not illustrated, in one embodiment, the first gate electrode (GE1) may be in contact with the first lower conductive layer (BML1).

[0216] The second gate electrode (GE2) may be disposed on the second insulating layer (IL2). The second gate electrode (GE2) may overlap the second channel region (CH2) of the second active pattern (AP2). The second gate electrode (GE2) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. Although not illustrated, in one embodiment, the second gate electrode (GE2) may be in contact with the second lower conductive layer (BML2).

[0217] A first capacitor electrode (CPE1) may be disposed on a second insulating layer (IL2). The first capacitor electrode (CPE1) may overlap a third capacitor electrode (CPE3). The first capacitor electrode (CPE1) and the third capacitor electrode (CPE3) may form a second capacitor (CAP2). The first capacitor electrode (CPE1) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide.

[0218] The third insulating layer (IL3) covers the first gate electrode (GE1), the second gate electrode (GE2), and the first capacitor electrode (CPE1) and may be disposed on the second insulating layer (IL2). The third insulating layer (IL3) may include an insulating material. Examples of the insulating material that may be used as the third insulating layer (IL3) may include silicon oxide, silicon nitride, silicon oxynitride, and the like. These may be used alone or in combination with each other.

[0219] The second capacitor electrode (CPE2) may be disposed on the third insulating layer (IL3). The second capacitor electrode (CPE2) may overlap the first capacitor electrode (CPE1). The first capacitor electrode (CPE1) and the second capacitor electrode (CPE2) may form a first capacitor (CAP1). The second capacitor electrode (CPE2) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide.

[0220] The fourth insulating layer (IL4) covers the second capacitor electrode (CPE2) and may be disposed on the third insulating layer (IL3). The fourth insulating layer (IL4) may include an insulating material. Examples of the insulating material that may be used as the fourth insulating layer (IL4) include silicon oxide, silicon nitride, silicon oxynitride, and the like. These may be used alone or in combination with each other.

[0221] The first to fourth contact electrodes (SE1, DE1, SE2, DE2) may be disposed on the fourth insulating layer (IL4). The first contact electrode (SE1) may be in contact with the first contact area (S1) of the first active pattern (AP1), the second contact electrode (DE1) may be in contact with the second contact area (D1) of the first active pattern (AP1), the third contact electrode (SE2) may be in contact with the third contact area (S2) of the second active pattern (AP2), and the fourth contact electrode (DE2) may be in contact with the fourth contact area (D2) of the second active pattern (AP2). The first to fourth contact electrodes (SE1, DE1, SE2, DE2) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide.

[0222] In one embodiment, the first contact electrode (SE1) may be in contact with the first lower conductive layer (BML1), and the third contact electrode (SE2) may be in contact with the second lower conductive layer (BML2). However, the present disclosure is not necessarily limited thereto. For example, when the first gate electrode (GE1) is in contact with the first lower conductive layer (BML1), the first contact electrode (SE1) may not be in contact with the first lower conductive layer (BML1). Additionally, when the second gate electrode (GE2) is in contact with the second lower conductive layer (BML2), the third contact electrode (SE2) may not be in contact with the second lower conductive layer (BML2).

[0223] The fifth insulating layer (IL5) covers the first to fourth contact electrodes (SE1, DE1, SE2, DE2) and may be disposed on the fourth insulating layer (IL4). The fifth insulating layer (IL5) may include an insulating material. For example, the fifth insulating layer (IL5) may include an organic insulating material. Examples of the organic insulating material that may be used as the fifth insulating layer (IL5) may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic resin, an epoxy-based resin, and the like. These may be used alone or in combination with each other.

[0224] The first connection electrode (CEa) may be disposed on the fifth insulating layer (IL5). As described above, the first connection electrode (CEa) may be connected to the first transistor (TR1). Specifically, the first connection electrode (CEa) may contact the first transistor (TR1) through a contact hole (CNT) extending through the fifth insulating layer (IL5). Accordingly, the position of the first circuit connection portion (CPa) may correspond to the position of the contact hole (CNT). The first connection electrode (CEa) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. In one embodiment, the first connection electrode (CEa) may have a single-layer structure or a multi-layer structure in which a plurality of conductive layers are stacked.

[0225] As described above, the first transistor (TR1) may be a transistor connected to the light-emitting element through a connection electrode and a connection pattern. For example, when the first pixel driving circuit unit (PCa) is the pixel driving circuit unit (PC) of FIG. 2A, the first transistor (TR1) may be the first transistor (T1) of FIG. 2A. In addition, when the first pixel driving circuit unit (PCa) is the pixel driving circuit unit (PC`) of FIG. 2B, the first transistor (TR1) may be the fifth transistor (T5) of FIG. 2B. In addition, when the first pixel driving circuit unit (PCa) is the pixel driving circuit unit (PC``) of FIG. 2C, the first transistor (TR1) may be the fifth transistor (T5) of FIG. 2C.

[0226] The sixth insulating layer (IL6) partially covers the first connection electrode (CEa) and may be disposed on the fifth insulating layer (IL5). That is, the sixth insulating layer (IL6) may define the first sub-opening (SO1) on at least a portion of the first connection electrode (CEa). The sixth insulating layer (IL6) may include an insulating material. For example, the sixth insulating layer (IL6) may include an organic insulating material. Examples of the organic insulating material that may be used as the sixth insulating layer (IL6) may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic resin, an epoxy-based resin, and the like. These may be used alone or in combination with each other.

[0227] A first electrode layer (E1) may be disposed on the sixth insulating layer (IL6). As described above, the first electrode layer (E1) may include the first electrode (E1a) of the first light-emitting element (LEDa). That is, the first electrode (E1a) may be disposed on the sixth insulating layer (IL6). The first electrode layer (E1) (i.e., the first electrode (E1a)) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. The structure of the first electrode layer (E1) will be described in more detail below.

[0228] A pixel defining layer (PDL) may be disposed on the sixth insulating layer (IL6) and the first electrode layer (E1) (i.e., the first electrode (E1a)). The pixel defining layer (PDL) may be formed of an insulating material. The pixel defining layer (PDL) may define a pixel opening that exposes at least a portion of the first electrode layer (E1) (i.e., the first electrode (E1a)). A first emission area (EAa) may be defined by the pixel opening. Meanwhile, the pixel defining layer (PDL) may further define a second sub-opening (SO2) that is aligned with the first sub-opening (SO1) of the sixth insulating layer (IL6). The second sub-opening (SO2) may be positioned on the first sub-opening (SO1), and the first sub-opening (SO1) and the second sub-opening (SO2) may be connected to each other to form a continuous and deeper opening. That is, the first sub-opening (SO1) and the second sub-opening (SO2) may be connected to each other. An opening (OP) connected to the opening (SO2) can be defined, and at least a portion of the first connecting electrode (CEa) can be located at the bottom of the opening (OP).

[0229] The first connection pattern (CNPa) may be disposed on the first connection electrode (CEa), the sixth insulating layer (IL6), and the pixel defining layer (PDL). As described above, the first connection pattern (CNPa) may be connected to the first connection electrode (CEa). Specifically, the first connection pattern (CNPa) may be connected to the first connection electrode (CEa) through an opening (OP) extending through the sixth insulating layer (IL6) and the pixel defining layer (PDL). Accordingly, the position of the first light-emitting connection portion (CNa) may correspond to the position of the opening (OP). In one embodiment, the first connection pattern (CNPa) may include a transparent conductive oxide. However, the present disclosure is not necessarily limited thereto, and the first connection pattern (CNPa) may also include a conductive material such as a metal, an alloy, a conductive metal oxide, or a conductive metal nitride. In one embodiment, the first connection pattern (CNPa) may have a single-layer structure or a multi-layer structure in which a plurality of conductive layers are stacked.

[0230] A separator (SPR) may be disposed on the pixel defining layer (PDL) and the first connection pattern (CNPa). The separator (SPR) may overlap the first connection pattern (CNPa) in a plane. For example, the separator (SPR) may cover a portion of the first connection pattern (CNPa).

[0231] The separator (SPR) may have a cross-sectional shape in which the width of the upper portion is greater than the width of the lower portion. That is, the side surface of the separator (SPR) connecting the upper surface of the separator (SPR) and the lower surface of the separator (SPR) may have a tapered or inclined surface. That is, the cross-section of at least a portion of the separator (SPR) may be trapezoidal.

[0232] In one embodiment, as illustrated in FIG. 5, the side surface of the separator (SPR) may have a plurality of inclined surfaces. That is, the separator (SPR) may have a tapered structure. Accordingly, the separation (or disconnection) of the second electrode layer (E2) by the separator (SPR) can be more easily implemented.

[0233] The intermediate layer (ML) may be disposed on the first electrode layer (E1), the pixel defining layer (PDL), and the first connection pattern (CNPa). A portion of the intermediate layer (ML) may be disposed within the pixel opening of the pixel defining layer (PDL). In one embodiment, the intermediate layer (ML) may include a first functional layer including an organic material, an emission layer disposed on the first functional layer and including an emission material, and a second functional layer disposed on the emission layer and including an organic material. For example, the first functional layer may include a hole injection layer, a hole transport layer, etc., and the second functional layer may include an electron transport layer, an electron injection layer, etc.

[0234] A shadow region in which it is difficult to deposit an intermediate layer (ML) may exist around a separator (SPR) having an inclined surface. Accordingly, the intermediate layer (ML) in the shadow region and / or around the shadow region may have a structure that is disconnected by the separator (SPR). For example, the first and second functional layers included in the intermediate layer (ML) may have a structure that is disconnected in order to accommodate the separator (SPR). Since the intermediate layer (ML) has a disconnected structure, the intermediate layer (ML) may not entirely cover the first connection pattern (CNPa). That is, the intermediate layer (ML) may expose a part of the first connection pattern (CNPa) at a position adjacent to or overlapping the separator (SPR). Accordingly, the second electrode (E2a) of the first light-emitting element (LEDa) may come into contact with the first connection pattern (CNPa).

[0235] Meanwhile, a first dummy layer (DP1) may be disposed on the separator (SPR). The first dummy layer (DP1) may be formed by having a structure in which the intermediate layer (ML) is disconnected by the separator (SPR). That is, the first dummy layer (DP1) may be formed in the same process as the intermediate layer (ML). In one embodiment, the first dummy layer (DP1) may be omitted.

[0236] The second electrode layer (E2) (i.e., the second electrodes (E2a, E2b, E2c)) may be disposed on the intermediate layer (ML). The second electrode layer (E2) (i.e., the second electrodes (E2a, E2b, E2c)) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. In one embodiment, the second electrode layer (E2) (i.e., the second electrodes (E2a, E2b, E2c)) may have a single-layer structure. However, the present disclosure is not necessarily limited thereto, and the second electrode layer (E2) (i.e., the second electrodes (E2a, E2b, E2c)) may have a multi-layer structure in which a plurality of conductive layers are stacked. For example, the second electrode layer (E2) (i.e., the second electrodes (E2a, E2b, E2c)) may have a two-layer structure in which a first sub-electrode layer including a metal material and a second sub-electrode layer including a transparent conductive oxide are laminated on the first sub-electrode layer.

[0237] A shadow region in which the second electrode layer (E2) is difficult to deposit may exist around the separator (SPR) having a tapered slope. Accordingly, the second electrode layer (E2) may be discontinuous around the separator (SPR) in the shadow region and / or around the shadow region. For example, as illustrated in FIG. 4, the second electrode layer (E2) may be separated into a second electrode (E2a) of a first light-emitting element (LEDa) disposed in a first open region (OA1) of the separator (SPR), a second electrode (E2b) of a second light-emitting element (LEDb) disposed in a second open region (OA2) of the separator (SPR), and a second electrode (E2c) of a third light-emitting element (LEDc) disposed in a third open region (OA3) of the separator (SPR). That is, the second electrodes (E2a, E2b, E2c) can be electrically independent of each other.

[0238] As illustrated in FIG. 5, the second electrode (E2a) of the first light-emitting element (LEDa) can be connected to the first connection pattern (CNPa). Specifically, the second electrode (E2a) can be in contact with the first connection pattern (CNPa) at a position adjacent to or overlapping the separator (SPR). For example, when the deposition angle of the deposition process for forming the second electrode layer (E2) is greater than the deposition angle of the deposition process for forming the intermediate layer (ML), the second electrode layer (E2) (specifically, the second electrode (E2a)) can be formed to cover the side of the disconnected intermediate layer (ML) and be in contact with the first connection pattern (CNPa). As a result, the second electrode (E2a) can be connected to the first transistor (TR1) through the first connection electrode (CEa) and the first connection pattern (CNPa).

[0239] Meanwhile, a second dummy layer (DP2) may be disposed on the separator (SPR). Specifically, the second dummy layer (DP2) may be disposed on the first dummy layer (DP1). The second dummy layer (DP2) may be formed by having a structure in which the second electrode layer (E2) is separated (or disconnected) by the separator (SPR). That is, the second dummy layer (DP2) may be formed in the same process as the second electrode layer (E2). In one embodiment, the second dummy layer (DP2) may be omitted.

[0240] The encapsulation layer (ENC) may be disposed on the second electrode layer (E2). The encapsulation layer (ENC) may entirely cover the second electrode layer (E2), the connection patterns (CNPa, CNPb, CNPc), the separator (SPR), the first dummy layer (DP1), and the second dummy layer (DP2). In one embodiment, the encapsulation layer (ENC) may include a first inorganic encapsulation layer (IEL1) including an inorganic insulating material, an organic encapsulation layer (OEL) disposed on the first inorganic encapsulation layer (IEL1) and including an organic insulating material, and a second inorganic encapsulation layer (IEL2) disposed on the organic encapsulation layer (OEL) and including an inorganic insulating material.

[0241] Although not shown, in one embodiment, a touch-sensitive layer may be disposed on the encapsulation layer (ENC). For example, the touch-sensitive layer may include a plurality of touch electrode arrays for sensing a user's handling in an electrostatic capacitive manner, a touch pad portion, and a plurality of touch wires electrically connecting the touch pad portion and the touch electrode arrays. However, the present disclosure is not necessarily limited thereto. Meanwhile, in one embodiment, the touch-sensitive layer may be omitted.

[0242] According to one embodiment of the present disclosure, the display device (DD) may include connection electrodes (CEa, CEb, CEc), connection patterns (CNPa, CNPb, CNPc), and a separator (SPR). Accordingly, the second electrode layer (E2) (e.g., cathode) disposed above the first electrode layer (E1) (e.g., anode) may be easily connected to the pixel driving circuit units (PCa, PCb, PCc). Specifically, the second electrode layer (E2) disposed above the first electrode layer (E1) may be connected to the drain of the driving transistor (e.g., the first transistor (T1, T1`) of FIGS. 2A to 2C) of each of the pixel driving circuit units (PCa, PCb, PCc) through the connection electrodes (CEa, CEb, CEc) and the connection patterns (CNPa, CNPb, CNPc). Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor may not change. Accordingly, the range of change in driving current due to deterioration of the light-emitting element may be reduced. Accordingly, afterimage defects of the display device (DD) due to increased usage time may be reduced, and the lifespan of the display device (DD) may be improved.

[0243] Fig. 6 is a plan view schematically illustrating a first embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display areas of Figs. 1a and 1b. Fig. 7 is an enlarged view illustrating area AA of Fig. 6.

[0244] Referring to FIGS. 6 and 7, the display area (DA) may include unit circuit areas (PCU). In one embodiment, the unit circuit areas (PCU) may be unit areas in which first to third pixel driving circuit units (PCa, PCb, PCc) arranged in a first direction (DR1) are arranged. In one embodiment, the unit circuit areas (PCU) may be repeatedly arranged along the first direction (DR1) and the second direction (DR2).

[0245] The display device (DD) may include a first electrode layer (E1) and a transmission line group (TLG).

[0246] In one embodiment, a first electrode layer (E1) may be disposed in a display area (DA). The first electrode layer (E1) may be applied with a first power voltage (ELVDD, see FIGS. 2A to 2C). For example, the first electrode layer (E1) may be connected to a first voltage line (VL1, see FIGS. 2A to 2C) and may be applied with the first power voltage (ELVDD) through the first voltage line (VL1). In one embodiment, the first power voltage (ELVDD) may be commonly provided to the first to third light-emitting elements (LEDa, LEDb, LEDc) through the first electrode layer (E1).

[0247] As illustrated in FIG. 7, the first electrode layer (E1) may include first electrodes (E1a, E1b, E1c). Specifically, the first electrode layer (E1) may include a first electrode (E1a) of a first light-emitting element (LEDa), a first electrode (E1b) of a second light-emitting element (LEDb), and a first electrode (E1c) of a third light-emitting element (LEDc). In one embodiment, the first electrodes (E1a, E1b, E1c) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). For example, in an embodiment in which the first to third light-emitting areas (EAa, EAb, EAc, see FIGS. 3 and 4) are arranged in an S-stripe type, the first electrode (E1a) of the first light-emitting element (LEDa) and the first electrode (E1b) of the second light-emitting element (LEDb) may be arranged alternately in odd columns, and the first electrode (E1c) of the third light-emitting element (LEDc) may be arranged alternately in even columns. In addition, the first electrode (E1a) of the first light-emitting element (LEDa) and the first electrode (E1c) of the third light-emitting element (LEDc) may be arranged alternately in odd rows, and the first electrode (E1b) of the second light-emitting element (LEDb) and the first electrode (E1c) of the third light-emitting element (LEDc) may be arranged alternately in even rows. However, the present disclosure is not necessarily limited thereto.

[0248] In one embodiment, a transmission line group (TLG) may be arranged in a display area (DA). The transmission line group (TLG) may be arranged in a different layer from the first electrode layer (E1). Specifically, the transmission line group (TLG) may be arranged in a layer closer to the substrate (SUB) than the first electrode layer (E1).

[0249] The transmission line group (TLG) can be supplied with a first power voltage (ELVDD, see FIGS. 2A to 2C). For example, the transmission line group (TLG) can be connected to a first voltage line (VL1, see FIGS. 2A to 2C) and can be supplied with the first power voltage (ELVDD) through the first voltage line (VL1). In one embodiment, the transmission line group (TLG) can be directly connected to a power voltage supply unit disposed in a peripheral area (NDA) to be supplied with the first power voltage (ELVDD). In this case, the power voltage supply unit can provide the first power voltage (ELVDD), and the transmission line group (TLG) can extend to the peripheral area (NDA). The transmission line group (TLG) can be connected to a first electrode layer (E1). Accordingly, the first electrode layer (E1) can be supplied with the first power voltage (ELVDD) through the transmission line group (TLG). For example, the first electrode layer (E1) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the transmission line group (TLG).

[0250] A transmission line group (TLG) may include a plurality of transmission lines extending in one direction and arranged in another direction intersecting the one direction. The transmission lines may be connected to a first electrode layer (E1). Accordingly, the transmission line group (TLG) (i.e., the transmission lines) may form a mesh structure on a plane with the first electrode layer (E1).

[0251] In one embodiment, the first electrode layer (E1) may have a mesh pattern in which the first electrodes (E1a, E1b, E1c) are integrally connected. For example, all of the first electrodes (E1a, E1b, E1c) may be integrally connected to each other through bridges (BR1, BR2). For example, the first electrode layer (E1) may include first bridges (BR1) connecting first electrodes that are adjacent to each other in a first direction (DR1) among the first electrodes (E1a, E1b, E1c). In addition, the first electrode layer (E1) may include second bridges (BR2) connecting first electrodes that are adjacent to each other in a second direction (DR2) among the first electrodes (E1a, E1b, E1c). The first bridges (BR1) and the second bridges (BR2) may be integral with the first electrodes (E1a, E1b, E1c). Since the first electrode layer (E1) has a mesh pattern, the transmission path of the first power voltage (ELVDD) can have mesh characteristics. Accordingly, the voltage drop of the first power voltage (ELVDD) can be reduced. Accordingly, the power consumption of the display device (DD) can be improved, and the brightness uniformity can be enhanced. Accordingly, the display quality of the display device (DD) can be improved.

[0252] In one embodiment, the transmission line group (TLG) may include first transmission lines (TL1). For example, the transmission line group (TLG) may be a set of first transmission lines (TL1).

[0253] The first transmission lines (TL1) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. The first transmission lines (TL1) may have a single-layer structure or a multi-layer structure in which a plurality of conductive layers are stacked.

[0254] The first transmission lines (TL1) can be applied with a first power voltage (ELVDD, see FIGS. 2A to 2C). For example, the first transmission lines (TL1) can be connected to a first voltage line (VL1, see FIGS. 2A to 2C) and can be applied with the first power voltage (ELVDD) through the first voltage line (VL1). In one embodiment, the first transmission lines (TL1) can be directly connected to the power voltage supply unit disposed in the peripheral area (NDA) to be applied with the first power voltage (ELVDD). In this case, the first transmission lines (TL1) can extend to the peripheral area (NDA). The first transmission lines (TL1) can be connected to the first electrode layer (E1). For example, the first transmission lines (TL1) can be electrically connected to the first electrode layer (E1) through the first contact hole (CNT1). Accordingly, the first electrode layer (E1) can receive the first power voltage (ELVDD) through the first transmission lines (TL1). For example, the first electrode layer (E1) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the first transmission lines (TL1).

[0255] In one embodiment, the first transmission lines (TL1) can extend in the second direction (DR2) and be arranged in the first direction (DR1). Accordingly, the first transmission lines (TL1) and the first electrode layer (E1) can form a mesh structure on a plane. That is, in addition to the mesh pattern of the first electrode layer (E1) itself, the first electrode layer (E1) can additionally form the mesh structure together with the first transmission lines (TL1).

[0256] FIGS. 6 and 7 illustrate that the first transmission lines (TL1) are arranged in the first direction (DR1) such that three first transmission lines (TL1) correspond to each of the unit circuit areas (PCU). However, the present disclosure is not limited thereto. For example, if the first transmission lines (TL1) form the mesh structure together with the first electrode layer (E1), the interval at which the first transmission lines (TL1) are repeated may vary depending on the embodiments.

[0257] According to one embodiment of the present disclosure, first transmission lines (TL1) receiving a first power voltage (ELVDD) may be connected to a first electrode layer (E1). Accordingly, the first transmission lines (TL1) may provide the first power voltage (ELVDD) to the first electrode layer (E1). In addition, the first transmission lines (TL1) and the first electrode layer (E1) may form a mesh structure on a plane. Accordingly, the mesh characteristics of the transmission path of the first power voltage (ELVDD) may be further enhanced. Accordingly, the voltage drop of the first power voltage (ELVDD) may be further reduced. Accordingly, the power consumption of the display device (DD) may be improved, and the luminance uniformity may be improved. Accordingly, the display quality of the display device (DD) may be improved.

[0258] Fig. 8a is a cross-sectional view showing an example cut along line II-II` of Fig. 7.

[0259] For convenience of explanation, Fig. 8a focuses on the first transmission lines (TL1) and the first electrode layer (E1), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0260] Referring further to FIG. 8A, in one embodiment, the first transmission lines (TL1) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the first transmission lines (TL1) may be disposed on the fourth insulating layer (IL4) and may be at least partially covered by the fifth insulating layer (IL5). In this case, the first contact hole (CNT1) may extend through the fifth insulating layer (IL5) and the sixth insulating layer (IL6) to expose the first transmission lines (TL1), and the first electrode layer (E1) may be electrically connected to the first transmission lines (TL1) through the first contact hole (CNT1).

[0261] In one embodiment, the first transmission lines (TL1) may be formed together with the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5) in the same process and may include the same material as the first contact electrode (SE1) and the second contact electrode (DE1). For example, a preliminary conductive layer may be formed on the fourth insulating layer (IL4) and the preliminary conductive layer may be patterned to form the first transmission lines (TL1), the first contact electrode (SE1), and the second contact electrode (DE1) together. However, the present disclosure is not necessarily limited thereto.

[0262] Fig. 8b is a cross-sectional view showing an example cut along line II-II` of Fig. 7.

[0263] For convenience of explanation, Fig. 8b focuses on the first transmission lines (TL1) and the first electrode layer (E1), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0264] Referring to FIG. 8B, in one embodiment, the first transmission lines (TL1) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the first transmission lines (TL1) may be disposed on the fifth insulating layer (IL5) and at least partially covered by the sixth insulating layer (IL6). In this case, the first contact hole (CNT1) may extend through the sixth insulating layer (IL6) to expose the first transmission lines (TL1), and the first electrode layer (E1) may be electrically connected to the first transmission lines (TL1) through the first contact hole (CNT1).

[0265] In one embodiment, the first transmission lines (TL1) may be formed together with the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5) in the same process and may include the same material as the first to third connection electrodes (CEa, CEb, CEc). For example, a preliminary conductive layer may be formed on the fifth insulating layer (IL5), and the first transmission lines (TL1) and the first to third connection electrodes (CEa, CEb, CEc) may be formed together by patterning the preliminary conductive layer. However, the present disclosure is not necessarily limited thereto.

[0266] Fig. 9 is a plan view schematically illustrating a second embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​Figs. 1a and 1b. Fig. 10 is an enlarged view illustrating the BB area of ​​Fig. 9.

[0267] The embodiment of the display device (DD) described with reference to FIGS. 9 and 10 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 6 and 7, except for the transmission line group (TLG`). Therefore, any redundant description will be omitted or simplified.

[0268] Referring to FIGS. 9 and 10 , the display device (DD) may include a first electrode layer (E1) and a transmission line group (TLG`). The description of the first electrode layer (E1) with reference to FIGS. 6 and 7 may be applied to the first electrode layer (E1) of FIGS. 9 and 10 . Therefore, any redundant description will be omitted or simplified.

[0269] In one embodiment, a transmission line group (TLG`) may be arranged in a display area (DA). The transmission line group (TLG`) may be arranged in a different layer from the first electrode layer (E1). Specifically, the transmission line group (TLG`) may be arranged closer to the substrate (SUB) than the first electrode layer (E1).

[0270] The transmission line group (TLG`) can be supplied with a first power voltage (ELVDD, see FIGS. 2A to 2C). For example, the transmission line group (TLG`) can be connected to a first voltage line (VL1, see FIGS. 2A to 2C) and can be supplied with the first power voltage (ELVDD) through the first voltage line (VL1). In one embodiment, the transmission line group (TLG`) can be directly connected to the power voltage supply unit arranged in the peripheral area (NDA) to be supplied with the first power voltage (ELVDD). In this case, the transmission line group (TLG`) can extend to the peripheral area (NDA). The transmission line group (TLG`) can be connected to the first electrode layer (E1). Accordingly, the first electrode layer (E1) can be supplied with the first power voltage (ELVDD) through the transmission line group (TLG`). For example, the first electrode layer (E1) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the transmission line group (TLG`).

[0271] A transmission line group (TLG`) may include a plurality of transmission lines extending in one direction and arranged in another direction intersecting the one direction. The transmission lines may be connected to the first electrode layer (E1). Accordingly, the transmission line group (TLG`) (i.e., the transmission lines) may form a mesh structure on a plane with the first electrode layer (E1).

[0272] In one embodiment, the transmission line group (TLG`) may include second transmission lines (TL2). For example, the transmission line group (TLG`) may be a set of second transmission lines (TL2).

[0273] The second transmission lines (TL2) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. The second transmission lines (TL2) may have a single-layer structure or a multi-layer structure in which multiple conductive layers are stacked.

[0274] The second transmission lines (TL2) can be applied with a first power voltage (ELVDD, see FIGS. 2A to 2C). For example, the second transmission lines (TL2) can be connected to a first voltage line (VL1, see FIGS. 2A to 2C) and can be applied with the first power voltage (ELVDD) through the first voltage line (VL1). In one embodiment, the second transmission lines (TL2) can be directly connected to the power voltage supply unit disposed in the peripheral area (NDA) to be applied with the first power voltage (ELVDD). In this case, the second transmission lines (TL2) can extend to the peripheral area (NDA). The second transmission lines (TL2) can be connected to the first electrode layer (E1). For example, the second transmission lines (TL2) can be electrically connected to the first electrode layer (E1) through the second contact hole (CNT2). Accordingly, the first electrode layer (E1) can receive the first power voltage (ELVDD) through the second transmission lines (TL2). For example, the first electrode layer (E1) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the second transmission lines (TL2).

[0275] In one embodiment, the second transmission lines (TL2) can extend in the first direction (DR1) and be arranged in the second direction (DR2). Accordingly, the second transmission lines (TL2) and the first electrode layer (E1) can form a mesh structure on a plane. That is, in addition to the mesh pattern of the first electrode layer (E1) itself, the first electrode layer (E1) can additionally form the mesh structure together with the second transmission lines (TL2).

[0276] Meanwhile, in FIGS. 9 and 10, the second transmission lines (TL2) are arranged in the second direction (DR2) so that three second transmission lines (TL2) correspond to each of the unit circuit areas (PCU). However, the present disclosure is not necessarily limited thereto. For example, if the second transmission lines (TL2) form the mesh structure together with the first electrode layer (E1), the interval at which the second transmission lines (TL2) are repeated may vary depending on the embodiments.

[0277] According to one embodiment of the present disclosure, second transmission lines (TL2) receiving a first power voltage (ELVDD) may be connected to a first electrode layer (E1). Accordingly, the second transmission lines (TL2) may provide the first power voltage (ELVDD) to the first electrode layer (E1). In addition, the second transmission lines (TL2) and the first electrode layer (E1) may form the mesh structure on a plane. Accordingly, the mesh characteristics of the transmission path of the first power voltage (ELVDD) may be further strengthened, the voltage drop of the first power voltage (ELVDD) may be further reduced, the power consumption of the display device (DD) may be improved, and the brightness uniformity may be improved. Furthermore, the display quality of the display device (DD) may be improved.

[0278] Fig. 11a is a cross-sectional view showing an example cut along line III-III` of Fig. 10.

[0279] For convenience of explanation, Fig. 11a focuses on the second transmission lines (TL2) and the first electrode layer (E1), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0280] Referring to FIG. 11A, in one embodiment, the second transmission lines (TL2) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the second transmission lines (TL2) may be disposed on the fifth insulating layer (IL5) and at least partially covered by the sixth insulating layer (IL6). In this case, the second contact hole (CNT2) may extend to the second transmission lines (TL2) through the sixth insulating layer (IL6), and the first electrode layer (E1) may be electrically connected to the second transmission lines (TL2) through the second contact hole (CNT2).

[0281] In one embodiment, the second transmission lines (TL2) may be formed together with the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5) and may include the same material as the first to third connection electrodes (CEa, CEb, CEc). For example, a preliminary conductive layer may be formed on the fifth insulating layer (IL5), and the second transmission lines (TL2) and the first to third connection electrodes (CEa, CEb, CEc) may be formed together by patterning the preliminary conductive layer. However, the present disclosure is not necessarily limited thereto.

[0282] Fig. 11b is a cross-sectional view showing an example cut along line III-III` of Fig. 10.

[0283] For convenience of explanation, Fig. 11b focuses on the second transmission lines (TL2) and the first electrode layer (E1), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0284] Referring to FIG. 11B, in one embodiment, the second transmission lines (TL2) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the second transmission lines (TL2) may be disposed on the fourth insulating layer (IL4) and may be at least partially covered by the fifth insulating layer (IL5). In this case, the second contact hole (CNT2) may extend to the second transmission lines (TL2) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1) may be electrically connected to the second transmission lines (TL2) through the second contact hole (CNT2).

[0285] In one embodiment, the second transmission lines (TL2) may be formed together with the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5) in the same process and may include the same material as the first contact electrode (SE1) and the second contact electrode (DE1). For example, a preliminary conductive layer may be formed on the fourth insulating layer (IL4) and the preliminary conductive layer may be patterned to form the second transmission lines (TL2), the first contact electrode (SE1), and the second contact electrode (DE1) together. However, the present disclosure is not necessarily limited thereto.

[0286] Fig. 12 is a plan view schematically illustrating a third embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display areas of Figs. 1a and 1b. Fig. 13 is an enlarged view illustrating the CC area of ​​Fig. 12.

[0287] The embodiment of the display device (DD) described with reference to FIGS. 12 and 13 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 6 and 7, except for the transmission line group (TLG``). Therefore, redundant descriptions are omitted.

[0288] Referring to FIGS. 12 and 13, the display device (DD) may include a first electrode layer (E1) and a transmission line group (TLG``). The description of the first electrode layer (E1) with reference to FIGS. 6 and 7 may be applied to the first electrode layer (E1) of FIGS. 12 and 13. Therefore, redundant descriptions are omitted.

[0289] In one embodiment, a transmission line group (TLG``) may be arranged in a display area (DA). The transmission line group (TLG``) may be arranged in a different layer from the first electrode layer (E1). Specifically, the transmission line group (TLG``) may be arranged lower than the first electrode layer (E1).

[0290] The transmission line group (TLG``) can be supplied with a first power voltage (ELVDD, see FIGS. 2A to 2C). For example, the transmission line group (TLG``) can be connected to a first voltage line (VL1, see FIGS. 2A to 2C) and can be supplied with the first power voltage (ELVDD) through the first voltage line (VL1). In one embodiment, the transmission line group (TLG``) can be directly connected to the power voltage supply unit arranged in the peripheral area (NDA) to be supplied with the first power voltage (ELVDD). In this case, the transmission line group (TLG``) can extend to the peripheral area (NDA). The transmission line group (TLG``) can be connected to the first electrode layer (E1). Accordingly, the first electrode layer (E1) can be supplied with the first power voltage (ELVDD) through the transmission line group (TLG``). For example, the first electrode layer (E1) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the transmission line group (TLG``).

[0291] A transmission line group (TLG``) may include a plurality of first transmission lines extending in one direction and arranged in another direction intersecting the one direction. In addition, the transmission line group (TLG``) may include a plurality of second transmission lines extending in the other direction and arranged in the one direction. The first transmission lines and the second transmission lines may be connected to the first electrode layer (E1). Accordingly, the transmission line group (TLG``) (i.e., the first transmission lines and the second transmission lines) may form a mesh structure on a plane with the first electrode layer (E1).

[0292] In one embodiment, the transmission line group (TLG``) may include first transmission lines (TL1) and second transmission lines (TL2). For example, the transmission line group (TLG``) may be a set of first transmission lines (TL1) and second transmission lines (TL2).

[0293] The description of the first transmission lines (TL1) of FIGS. 12 and 13 with reference to FIGS. 6 and 7 may be applied to the first transmission lines (TL1). Therefore, any redundant description will be omitted or simplified. In addition, the description of the second transmission lines (TL2) of FIGS. 12 and 13 with reference to FIGS. 9 and 10 may be applied to the second transmission lines (TL2). Therefore, any redundant description will be omitted or simplified.

[0294] As described above, the first transmission lines (TL1) and the second transmission lines (TL2) can be applied with a first power voltage (ELVDD, see FIGS. 2A to 2C). The first transmission lines (TL1) can be electrically connected to the first electrode layer (E1) through the first contact hole (CNT1), and the second transmission lines (TL2) can be electrically connected to the first electrode layer (E1) through the second contact hole (CNT2). Accordingly, the first electrode layer (E1) can be applied with the first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2).

[0295] In one embodiment, the first transmission lines (TL1) can extend in the second direction (DR2) and can be arranged in the first direction (DR1). The second transmission lines (TL2) can extend in the first direction (DR1) and can be arranged in the second direction (DR2). Accordingly, the first transmission lines (TL1), the second transmission lines (TL2) and the first electrode layer (E1) can form the mesh structure on a plane. That is, in addition to the mesh pattern of the first electrode layer (E1) itself, the first electrode layer (E1) can additionally form the mesh structure together with the first transmission lines (TL1) and the second transmission lines (TL2).

[0296] According to one embodiment of the present disclosure, first transmission lines (TL1) and second transmission lines (TL2) receiving a first power voltage (ELVDD) may be connected to a first electrode layer (E1). Accordingly, the first transmission lines (TL1) and the second transmission lines (TL2) may provide the first power voltage (ELVDD) to the first electrode layer (E1). In addition, the first transmission lines (TL1), the second transmission lines (TL2) and the first electrode layer (E1) may form the mesh structure on a plane. As a result, the mesh characteristics of the transmission path of the first power voltage (ELVDD) may be further strengthened, the voltage drop of the first power voltage (ELVDD) may be further reduced, the power consumption of the display device (DD) may be reduced, and the luminance uniformity may be improved. Furthermore, the display quality of the display device (DD) may be improved.

[0297] Fig. 14a is a cross-sectional view showing an example cut along line IV-IV` of Fig. 13.

[0298] For convenience of explanation, Fig. 14a focuses on the first transmission lines (TL1), the second transmission lines (TL2), and the first electrode layer (E1), and some of the configurations illustrated in Figs. 3 to 5 are omitted.

[0299] Referring to FIG. 14A, in an embodiment in which the display device (DD) includes a first electrode layer (E1) and a transmission line group (TLG``), the second transmission lines (TL2) may be arranged above the first transmission lines (TL1). In one embodiment, the first transmission lines (TL1) may be arranged on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5), and the second transmission lines (TL2) may be arranged on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the first transmission lines (TL1) may be arranged on the fourth insulating layer (IL4) and at least part of the first transmission lines (TL1) may be covered by the fifth insulating layer (IL5). Additionally, the second transmission lines (TL2) may be disposed on the fifth insulating layer (IL5) and at least partially covered by the sixth insulating layer (IL6). In this case, the first contact hole (CNT1) may extend to the first transmission lines (TL1) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1) may be electrically connected to the first transmission lines (TL1) through the first contact hole (CNT1). Additionally, the second contact hole (CNT2) may extend to the second transmission lines (TL2) through the sixth insulating layer (IL6), and the first electrode layer (E1) may be electrically connected to the second transmission lines (TL2) through the second contact hole (CNT2).

[0300] Fig. 14b is a cross-sectional view showing an example cut along line IV-IV` of Fig. 13.

[0301] For convenience of explanation, Fig. 14b focuses on the first transmission lines (TL1), the second transmission lines (TL2) and the first electrode layer (E1), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0302] Referring to FIG. 14B, in an embodiment in which the display device (DD) includes a first electrode layer (E1) and a transmission line group (TLG``), the first transmission lines (TL1) may be disposed above the second transmission lines (TL2). In one embodiment, the first transmission lines (TL1) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5), and the second transmission lines (TL2) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the first transmission lines (TL1) may be disposed on the fifth insulating layer (IL5) and at least partly covered by the sixth insulating layer (IL6). Additionally, the second transmission lines (TL2) may be disposed on the fourth insulating layer (IL4) and at least partially covered by the fifth insulating layer (IL5). In this case, the first contact hole (CNT1) may extend to the first transmission lines (TL1) through the sixth insulating layer (IL6), and the first electrode layer (E1) may be electrically connected to the first transmission lines (TL1) through the first contact hole (CNT1). Additionally, the second contact hole (CNT2) may extend to the second transmission lines (TL2) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1) may be electrically connected to the second transmission lines (TL2) through the second contact hole (CNT2).

[0303] Meanwhile, in FIG. 13, the second transmission lines (TL2) are illustrated as being positioned above the first transmission lines (TL1), but according to the embodiment illustrated in FIG. 14b, the illustration in FIG. 13 may be changed so that the first transmission lines (TL1) are positioned above the second transmission lines (TL2).

[0304] Additionally, although not shown, in one embodiment, at least one of the first transmission lines (TL1) may be connected to at least one of the second transmission lines (TL2) through a contact hole. In this case, the voltage drop of the first power supply voltage (ELVDD) may be further reduced. However, the present disclosure is not necessarily limited thereto, and the contact between the first transmission lines (TL1) and the second transmission lines (TL2) may be omitted.

[0305] Fig. 15 is a plan view schematically illustrating a fourth embodiment of the arrangement relationship between the first electrode layer and the transmission line group arranged in the display area of ​​Figs. 1a and 1b. Fig. 16 is an enlarged view illustrating the DD area of ​​Fig. 15.

[0306] The embodiment of the display device (DD) described with reference to FIGS. 15 and 16 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 9 and 10, except for the first electrode layer (E1`). In addition, the first electrode layer (E1`) may be substantially the same as the first electrode layer (E1) described above, except that the first electrodes (E1a, E1b, E1c) are not all connected in a mesh shape but include first electrode lines (EL1) that are physically separated from each other. Therefore, any redundant description will be omitted or simplified.

[0307] Referring to FIGS. 15 and 16, the display device (DD) may include a first electrode layer (E1`) and a transmission line group (TLG`). The description of the transmission line group (TLG`) with reference to FIGS. 9 and 10 may be equally applied to the transmission line group (TLG`) of FIGS. 15 and 16. Therefore, any redundant description will be omitted or simplified.

[0308] In one embodiment, the first electrode layer (E1`) may include first electrode lines (EL1). The first electrode lines (EL1) may extend in one direction and be arranged in another direction intersecting the one direction. For example, the first electrode lines (EL1) may extend in a second direction (DR2) and be arranged in the first direction (DR1). Each of the first electrode lines (EL1) may have a structure in which some of the first electrodes (E1a, E1b, E1c) are integrally connected. Additionally, the first electrode lines (EL1) may be physically separated from each other.

[0309] For example, as illustrated in FIG. 16, all of the first electrodes arranged in the i column (i is a natural number) may be integrally connected through the second bridges (BR2) to form first electrode lines (EL1), and the first electrode lines (EL1) arranged in the first direction (DR1) may be physically separated from each other. That is, in one embodiment, the shape of the first electrode layer (E1`) may be substantially the same as the shape of the first electrode layer (E1, see FIG. 10) in which the first bridges (BR1) are omitted on a plane.

[0310] In one embodiment, the first electrode lines (EL1) may be electrically connected to each other through a transmission line group (TLG`). That is, the first electrode lines (EL1) may be electrically connected to each other through the second transmission lines (TL2). The second transmission lines (TL2) may be electrically connected to the first electrode lines (EL1) through the third contact hole (CNT3). Accordingly, the first electrode lines (EL1) may be electrically connected to each other and may receive a first power voltage (ELVDD) through the second transmission lines (TL2). That is, the first electrode layer (E1`) may receive a first power voltage (ELVDD) through the second transmission lines (TL2). For example, the first electrode layer (E1`) (i.e., the first electrode lines (EL1)) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the second transmission lines (TL2).

[0311] As described above, the second transmission lines (TL2) can extend in the first direction (DR1) and be arranged in the second direction (DR2). Accordingly, the second transmission lines (TL2) and the first electrode lines (EL1) can form a mesh structure on a plane. That is, even when the first electrode layer (E1`) itself does not have a mesh pattern but has another structure including the first electrode lines (EL1), the first electrode layer (E1`) can form the mesh structure together with the second transmission lines (TL2). Accordingly, the mesh characteristic of the transmission path of the first power voltage (ELVDD) can be implemented. Accordingly, the design difficulty of the first electrode layer (E1`) can be lowered, while reducing the voltage drop of the first power voltage (ELVDD).

[0312] Although not shown, in an embodiment in which the display device (DD) includes the first electrode layer (E1`), the display device (DD) may include the transmission line group (TLG`) described with reference to FIGS. 12 to 14 instead of the transmission line group (TLG`). That is, in one embodiment, the display device (DD) may further include first transmission lines (TL1, see FIGS. 12 to 14) connected to the first electrode layer (E1`) (i.e., the first electrode lines EL1). In other words, the first electrode layer (E1`) (i.e., the first electrode lines EL1) may receive the first power voltage (ELVDD) through the first transmission lines TL1 and the second transmission lines TL2.

[0313] Fig. 17a is a cross-sectional view showing an example cut along line VV` of Fig. 16.

[0314] For convenience of explanation, Fig. 17a focuses on the second transmission lines (TL2) and the first electrode layer (E1`), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0315] Referring to FIG. 17a, in an embodiment in which the display device (DD) includes the first electrode layer (E1`), the second transmission lines (TL2) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the second transmission lines (TL2) may be disposed on the fifth insulating layer (IL5) and at least partially covered by the sixth insulating layer (IL6). In this case, the third contact hole (CNT3) may extend to the second transmission lines (TL2) through the sixth insulating layer (IL6), and the first electrode layer (E1`) (i.e., the first electrode lines (EL1)) may be electrically connected to the second transmission lines (TL2) through the third contact hole (CNT3).

[0316] Fig. 17b is a cross-sectional view showing an example cut along line VV` of Fig. 16.

[0317] For convenience of explanation, Fig. 17b focuses on the second transmission lines (TL2) and the first electrode layer (E1`), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0318] Referring to FIG. 17b, in an embodiment in which the display device (DD) includes the first electrode layer (E1`), the second transmission lines (TL2) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the second transmission lines (TL2) may be disposed on the fourth insulating layer (IL4) and may be at least partially covered by the fifth insulating layer (IL5). In this case, the third contact hole (CNT3) may extend to the second transmission lines (TL2) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1`) (i.e., the first electrode lines (EL1)) may be electrically connected to the second transmission lines (TL2) through the third contact hole (CNT3).

[0319] Fig. 18 is a plan view schematically illustrating a fifth embodiment of the arrangement of a first electrode layer and a transmission line group arranged in a display area of ​​the display device of Figs. 1a and 1b. Fig. 19 is an enlarged view illustrating the EE area of ​​Fig. 18.

[0320] The embodiment of the display device (DD) described with reference to FIGS. 18 and 19 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 6 and 7, except for the first electrode layer (E1``). In addition, the first electrode layer (E1``) may be substantially the same as the first electrode layer (E1) described above, except that the first electrodes (E1a, E1b, E1c) are not all integrally connected in a mesh pattern but include second electrode lines (EL2) that are physically separated from each other. Therefore, any overlapping description will be omitted or simplified.

[0321] Referring to FIGS. 18 and 19, the display device (DD) may include a first electrode layer (E1``) and a transmission line group (TLG). The description of the transmission line group (TLG) with reference to FIGS. 6 and 7 may be applied to the transmission line group (TLG) of FIGS. 18 and 19. Therefore, any redundant description will be omitted or simplified.

[0322] In one embodiment, the first electrode layer (E1``) may include second electrode lines (EL2). The second electrode lines (EL2) may extend in one direction and be arranged in another direction intersecting the one direction. For example, the second electrode lines (EL2) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Each of the second electrode lines (EL2) may have a structure in which some of the first electrodes (E1a, E1b, E1c) are integrally connected. Additionally, the second electrode lines (EL2) may be physically separated from each other.

[0323] For example, as illustrated in FIGS. 18 and 19, all of the first electrodes arranged in the j row and the j+1 row (j is an odd number greater than or equal to 1) may be integrally connected through the first bridges (BR1) to form the second electrode lines (EL2), and the second electrode lines (EL2) arranged in the second direction (DR2) may be physically separated from each other. That is, in one embodiment, the shape of the first electrode layer (E1``) may be substantially the same as the shape of the first electrode layer (E1, see FIG. 7) in which the second bridges (BR2) are omitted on a plane.

[0324] In one embodiment, the second electrode lines (EL2) may be electrically connected to each other through a transmission line group (TLG). That is, the second electrode lines (EL2) may be electrically connected to each other through the first transmission lines (TL1). The first transmission lines (TL1) may be electrically connected to the second electrode lines (EL2) through the fourth contact hole (CNT4). Accordingly, the second electrode lines (EL2) may be electrically connected to each other and may receive a first power voltage (ELVDD) through the first transmission lines (TL1). That is, the first electrode layer (E1``) may receive a first power voltage (ELVDD) through the first transmission lines (TL1). For example, the first electrode layer (E1``) (i.e., the second electrode lines (EL2)) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the first transmission lines (TL1).

[0325] As described above, the first transmission lines (TL1) can extend in the second direction (DR2) and be arranged in the first direction (DR1). Accordingly, the first transmission lines (TL1) and the second electrode lines (EL2) can form a mesh structure on a plane. That is, even when the first electrode layer (E1``) itself does not have a mesh pattern but has another structure including the second electrode lines (EL2), the first electrode layer (E1``) can form the mesh structure together with the first transmission lines (TL1). Accordingly, the mesh characteristic of the transmission path of the first power voltage (ELVDD) can be implemented. Accordingly, the design difficulty of the first electrode layer (E1``) can be lowered, while reducing the voltage drop of the first power voltage (ELVDD).

[0326] Although not shown, in an embodiment in which the display device (DD) includes the first electrode layer (E1``), the display device (DD) may include the transmission line group (TLG``) described with reference to FIGS. 12 to 14 instead of the transmission line group TLG. That is, in one embodiment, the display device (DD) may further include second transmission lines (TL2, see FIGS. 12 to 14) connected to the first electrode layer (E1``) (i.e., the second electrode lines EL2). In other words, the first electrode layer (E1``) (i.e., the second electrode lines EL2) may receive the first power voltage (ELVDD) through the first transmission lines TL1 and the second transmission lines TL2.

[0327] Fig. 20a is a cross-sectional view showing an example cut along line VI-VI` of Fig. 19.

[0328] For convenience of explanation, Fig. 20a focuses on the first transmission lines (TL1) and the first electrode layer (E1``), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0329] Referring to FIG. 20A, in an embodiment in which the display device (DD) includes the first electrode layer (E1``), the first transmission lines (TL1) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the first transmission lines (TL1) may be disposed on the fourth insulating layer (IL4) and may be at least partially covered by the fifth insulating layer (IL5). In this case, the fourth contact hole (CNT4) may extend to the first transmission lines (TL1) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1``) (i.e., the second electrode lines (EL2)) may be electrically connected to the first transmission lines (TL1) through the fourth contact hole (CNT4).

[0330] Fig. 20b is a cross-sectional view showing an example cut along line VI-VI` of Fig. 19.

[0331] For convenience of explanation, Fig. 20b focuses on the first transmission lines (TL1) and the first electrode layer (E1``), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0332] Referring to FIG. 20b, in an embodiment in which the display device (DD) includes the first electrode layer E1``, the first transmission lines (TL1) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the first transmission lines (TL1) may be disposed on the fifth insulating layer IL5 and at least partially covered by the sixth insulating layer IL6. In this case, the fourth contact hole (CNT4) may extend to the first transmission lines (TL1) through the sixth insulating layer IL6, and the first electrode layer (E1``) (i.e., the second electrode lines (EL2)) may be electrically connected to the first transmission lines (TL1) through the fourth contact hole (CNT4).

[0333] Fig. 21 is a schematic plan view of a sixth embodiment of the arrangement of the first electrode layer and the transmission line group arranged in the display area of ​​Figs. 1a and 1b. Fig. 22 is an enlarged view of the FF area of ​​Fig. 21.

[0334] The embodiment of the display device (DD) described with reference to FIGS. 21 and 22 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 12 and 13, except for the first electrode layer (E1```). In addition, the first electrode layer (E1```) may be substantially the same as the first electrode layer (E1) described above, except that the first electrodes (E1a, E1b, E1c) are not integrally connected in a mesh pattern but include electrode patterns (EP) that are physically separated from each other. Therefore, any redundant description will be omitted or simplified.

[0335] Referring to FIGS. 21 and 22, the display device (DD) may include a first electrode layer (E1```) and a transmission line group (TLG``). With respect to the transmission line group (TLG``) of FIGS. 18 and 19, the description of the transmission line group (TLG``) with reference to FIGS. 12 and 13 may be applied, except that the interval at which the transmission lines are repeated is changed so that two first transmission lines (TL1) correspond to each of the unit circuit areas (PCU) and two second transmission lines (TL2) correspond to each of the unit circuit areas. Therefore, overlapping descriptions are omitted or simplified.

[0336] In one embodiment, the first electrode layer (E1```) may include electrode patterns (EP). Each of the electrode patterns (EP) may have a structure in which first electrodes (E1a, E1b, E1c) corresponding to one of the unit circuit areas (PCU) are integrally connected. The electrode patterns (EP) may be arranged in one direction and another direction crossing the one direction. For example, the electrode patterns (EP) may be arranged in the first direction (DR1) and the second direction (DR2). That is, the electrode patterns (EP) may be arranged in a matrix form. In addition, the electrode patterns (EP) may be physically separated from each other.

[0337] The electrode patterns (EP) may be electrically connected to each other through a transmission line group (TLG``). That is, the electrode patterns (EP) may be electrically connected to each other through the first transmission lines (TL1) and the second transmission lines (TL2). The first transmission lines (TL1) may be electrically connected to the electrode patterns (EP) through the fifth contact hole (CNT5). The second transmission lines (TL2) may be electrically connected to the electrode patterns (EP) through the sixth contact hole (CNT6). Accordingly, the electrode patterns (EP) may be electrically connected to each other and may receive a first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2). That is, the first electrode layer (E1```) may receive a first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2). For example, the first electrode layer (E1```) (i.e., the electrode patterns (EP)) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2).

[0338] As described above, the first transmission lines (TL1) may extend in the second direction (DR2) and be arranged in the first direction (DR1). In addition, the second transmission lines (TL2) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Accordingly, the first transmission lines (TL1), the second transmission lines (TL2) and the electrode patterns (EP) may form a mesh structure on a plane. That is, even when the first electrode layer (E1```) itself does not have a mesh pattern but has another structure including the electrode patterns (EP), the first electrode layer (E1```) may form the mesh structure together with the first transmission lines (TL1) and the second transmission lines (TL2). Accordingly, the mesh characteristic of the transmission path of the first power voltage (ELVDD) may be implemented. Therefore, the voltage drop of the first power supply voltage (ELVDD) can be reduced while reducing the design difficulty of the first electrode layer (E1```).

[0339] Fig. 23a is a cross-sectional view showing an example cut along line VII-VII` of Fig. 22.

[0340] For convenience of explanation, Fig. 22a focuses on the first transmission lines (TL1), the second transmission lines (TL2), and the first electrode layer (E1```), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0341] Referring to FIG. 23a, in an embodiment in which the display device (DD) includes a first electrode layer (E1```) and a transmission line group (TLG``), the second transmission lines (TL2) may be arranged above the first transmission lines (TL1). In one embodiment, the first transmission lines (TL1) may be arranged on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5), and the second transmission lines (TL2) may be arranged on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the first transmission lines (TL1) may be arranged on the fourth insulating layer (IL4) and at least part of the first transmission lines (TL1) may be covered by the fifth insulating layer (IL5). In addition, the second transmission lines (TL2) may be arranged on the fifth insulating layer (IL5) and may be at least partially covered by the sixth insulating layer (IL6). In this case, the fifth contact hole (CNT5) may extend to the first transmission lines (TL1) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1```) (i.e., the electrode patterns (EP)) may be electrically connected to the first transmission lines (TL1) through the fifth contact hole (CNT5). In addition, the sixth contact hole (CNT6) may extend to the second transmission lines (TL2) through the sixth insulating layer (IL6), and the first electrode layer (E1```) (i.e., the electrode patterns (EP)) may be electrically connected to the second transmission lines (TL2) through the sixth contact hole (CNT6).

[0342] Fig. 23b is a cross-sectional view showing an example cut along line VII-VII` of Fig. 23.

[0343] For convenience of explanation, Fig. 23b focuses on the first transmission lines (TL1), the second transmission lines (TL2) and the first electrode layer (E1```), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0344] Referring to FIG. 23b, in an embodiment in which the display device (DD) includes a first electrode layer (E1```) and a transmission line group (TLG``), the first transmission lines (TL1) may be disposed above the second transmission lines (TL2). In one embodiment, the first transmission lines (TL1) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5), and the second transmission lines (TL2) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the first transmission lines (TL1) may be disposed on the fifth insulating layer (IL5) and at least part of the first transmission lines (TL1) may be covered by the sixth insulating layer (IL6). In addition, the second transmission lines (TL2) may be arranged on the fourth insulating layer (IL4) and may be at least partially covered by the fifth insulating layer (IL5). In this case, the fifth contact hole (CNT5) may extend to the first transmission lines (TL1) through the sixth insulating layer (IL6), and the first electrode layer (E1```) (i.e., the electrode patterns (EP)) may be electrically connected to the first transmission lines (TL1) through the fifth contact hole (CNT5). In addition, the sixth contact hole (CNT6) may extend to the second transmission lines (TL2) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1```) (i.e., the electrode patterns (EP)) may be electrically connected to the second transmission lines (TL2) through the sixth contact hole (CNT6).

[0345] Fig. 24 is a schematic plan view of a seventh embodiment of the arrangement of the first electrode layer and the transmission line group arranged in the display area of ​​Figs. 1a and 1b. Fig. 25 is an enlarged view of the GG area of ​​Fig. 24.

[0346] The embodiment of the display device (DD) described with reference to FIGS. 24 and 25 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 12 and 13, except for the first electrode layer (E1````). In addition, the first electrode layer (E1````) may be substantially the same as the first electrode layer (E1) described above, except that the first electrodes (E1a, E1b, E1c) are not integrally connected in a mesh pattern but include first electrodes (E1a, E1b, E1c) that are physically separated from each other. Therefore, any overlapping description will be omitted or simplified.

[0347] Referring to FIGS. 24 and 25, the display device (DD) may include a first electrode layer (E1````) and a transmission line group (TLG``). With respect to the transmission line group (TLG``) of FIGS. 24 and 25, the description of the transmission line group (TLG``) with reference to FIGS. 12 and 13 may be applied, except that the interval at which the transmission lines are repeated is changed so that two first transmission lines (TL1) correspond to each of the unit circuit areas (PCU) and two second transmission lines (TL2) correspond to each of the unit circuit areas. Therefore, overlapping descriptions are omitted or simplified.

[0348] In one embodiment, all of the first electrodes (E1a, E1b, E1c) included in the first electrode layer (E1````) may be physically separated from each other. In addition, all of the first electrodes (E1a, E1b, E1c) included in the first electrode layer (E1````) may be electrically connected to each other through a transmission line group (TLG``). That is, all of the first electrodes (E1a, E1b, E1c) may be electrically connected to each other through the first transmission lines (TL1) and the second transmission lines (TL2). The first transmission lines (TL1) may be electrically connected to the first electrodes (E1a, E1b, E1c) through the seventh contact hole (CNT7). The second transmission lines (TL2) can be electrically connected to the first electrodes (E1a, E1b, E1c) through the eighth contact hole (CNT8). Accordingly, all of the first electrodes (E1a, E1b, E1c) can be electrically connected to each other, and can receive the first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2). That is, the first electrode layer (E1````) can receive the first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2). For example, the first electrode layer (E1````) (i.e., the first electrodes (E1a, E1b, E1c)) can directly receive the first power voltage (ELVDD) from the first voltage line (VL1), and can additionally receive the first power voltage (ELVDD) through the first transmission lines (TL1) and the second transmission lines (TL2).

[0349] As described above, the first transmission lines (TL1) may extend in the second direction (DR2) and be arranged in the first direction (DR1). In addition, the second transmission lines (TL2) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Accordingly, the first transmission lines (TL1), the second transmission lines (TL2) and the first electrodes (E1a, E1b, E1c) may form a mesh structure on a plane. That is, even if the first electrode layer (E1````) itself does not have a mesh pattern and has another structure including first electrodes (E1a, E1b, E1c) that are physically separated from each other, the first electrode layer (E1````) may form the mesh structure together with the first transmission lines (TL1) and the second transmission lines (TL2). Accordingly, the mesh characteristic of the transmission path of the first power voltage (ELVDD) may be implemented. Therefore, the voltage drop of the first power supply voltage (ELVDD) can be reduced while reducing the design difficulty of the first electrode layer (E1````).

[0350] Fig. 26a is a cross-sectional view showing an example cut along line VIII-VIII` of Fig. 25.

[0351] For convenience of explanation, Fig. 26a focuses on the first transmission lines (TL1), the second transmission lines (TL2), and the first electrode layer (E1````), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0352] Referring to FIG. 26a, in an embodiment in which the display device (DD) includes a first electrode layer (E1````) and a transmission line group (TLG``), the second transmission lines (TL2) may be disposed above the first transmission lines (TL1). In one embodiment, the first transmission lines (TL1) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5), and the second transmission lines (TL2) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5). For example, the first transmission lines (TL1) may be disposed on the fourth insulating layer (IL4) and at least part of the first transmission lines (TL1) may be covered by the fifth insulating layer (IL5). Additionally, the second transmission lines (TL2) may be arranged on the fifth insulating layer (IL5) and may be at least partially covered by the sixth insulating layer (IL6). In this case, the seventh contact hole (CNT7) may extend to the first transmission lines (TL1) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1````) (i.e., the first electrodes (E1a, E1b, E1c)) may be electrically connected to the first transmission lines (TL1) through the seventh contact hole (CNT7). Additionally, the eighth contact hole (CNT8) extends to the second transmission lines (TL2) through the sixth insulating layer (IL6), and the first electrode layer (E1````) (i.e., the first electrodes (E1a, E1b, E1c)) can be electrically connected to the second transmission lines (TL2) through the eighth contact hole (CNT8).

[0353] Fig. 26b is a cross-sectional view showing an example cut along line VIII-VIII` of Fig. 25.

[0354] For convenience of explanation, Fig. 26b focuses on the first transmission lines (TL1), the second transmission lines (TL2) and the first electrode layer (E1````), and some of the configurations shown in Figs. 3 to 5 are omitted.

[0355] Referring to FIG. 26b, in an embodiment in which the display device (DD) includes a first electrode layer (E1````) and a transmission line group (TLG``), the first transmission lines (TL1) may be disposed above the second transmission lines (TL2). In one embodiment, the first transmission lines (TL1) may be disposed on the same layer as the first to third connection electrodes (CEa, CEb, CEc, see FIGS. 3 to 5), and the second transmission lines (TL2) may be disposed on the same layer as the first contact electrode (SE1, see FIG. 5) and the second contact electrode (DE1, see FIG. 5). For example, the first transmission lines (TL1) may be disposed on the fifth insulating layer (IL5) and at least part of the first transmission lines (TL1) may be covered by the sixth insulating layer (IL6). Additionally, the second transmission lines (TL2) may be arranged on the fourth insulating layer (IL4) and at least partially covered by the fifth insulating layer (IL5). In this case, the seventh contact hole (CNT7) may extend to the first transmission lines (TL1) through the sixth insulating layer (IL6), and the first electrode layer (E1````) (i.e., the first electrodes (E1a, E1b, E1c)) may be electrically connected to the first transmission lines (TL1) through the seventh contact hole (CNT7). Additionally, the eighth contact hole (CNT8) extends to the second transmission lines (TL2) through the fifth insulating layer (IL5) and the sixth insulating layer (IL6), and the first electrode layer (E1````) (i.e., the first electrodes (E1a, E1b, E1c)) can be electrically connected to the second transmission lines (TL2) through the eighth contact hole (CNT8).

[0356] According to embodiments of the present disclosure, a display device (DD) may include a first electrode layer that forms a light-emitting element and receives a first power voltage (ELVDD), and transmission lines that are disposed on a different layer from the first electrode layer and receive the first power voltage (ELVDD). The transmission lines may be connected to the first electrode layer. Accordingly, the transmission lines may provide the first power voltage (ELVDD) to the first electrode layer, and the first electrode layer and the transmission lines may form a mesh structure on a plane. For example, when the first electrode layer itself has a mesh pattern, the mesh characteristics of the transmission path of the first power voltage (ELVDD) may be further enhanced by the mesh structure formed by the first electrode layer and the transmission lines. In addition, even when the first electrode layer itself does not have a mesh pattern, the mesh characteristics of the transmission path of the first power voltage (ELVDD) may be implemented by the mesh structure formed by the first electrode layer and the transmission lines. Accordingly, the voltage drop of the first power supply voltage (ELVDD) can be reduced, the power consumption of the display device (DD) can be reduced, and the brightness uniformity can be improved. Furthermore, the display quality of the display device (DD) can be improved.

[0357] Fig. 27 is a plan view schematically illustrating an example of a portion of the display device of Figs. 1a and 1b. Fig. 28 is an enlarged view illustrating one of the unit light-emitting regions of Fig. 27. Fig. 29 is a cross-sectional view taken along line IX-IX` of Fig. 28.

[0358] Fig. 27 illustrates an area including four unit light-emitting areas (UEA1, UEA2) arranged in a matrix form of a two-row, two-column matrix. Fig. 28 illustrates a first unit light-emitting area (UEA1) among the unit light-emitting areas (UEA1, UEA2). For convenience of explanation, some of the configurations illustrated in Fig. 29 are omitted or emphasized in Figs. 27 and 28. In addition, the second electrodes (E2a`, E2b`, E2c`) among the configurations illustrated in Fig. 28 are omitted in Fig. 27.

[0359] The embodiment of the display device (DD) described with reference to FIGS. 27 to 29 may be substantially the same as the embodiment of the display device (DD) described with reference to FIGS. 3 to 5, except for the first to third light-emitting elements (LEDa`, LEDb`, LEDc`), the first to third connection electrodes (CEa`, CEb`, CEc`), and the separator (SPR`). Hereinafter, differences from the embodiment of the display device (DD) described with reference to FIGS. 3 to 5 will be mainly described, and overlapping descriptions will be omitted or simplified.

[0360] Referring to FIGS. 27 to 29, the display device (DD) may include first to third pixel driving circuits (PCa, PCb, PCc), first to third light-emitting elements (LEDa`, LEDb`, LEDc`), first to third connection electrodes (CEa`, CEb`, CEc`), and a separator (SPR`).

[0361] The description of the first to third pixel driving circuits (PCa, PCb, PCc) with reference to FIGS. 3 to 5 may be applied to the first to third pixel driving circuits (PCa, PCb, PCc) of FIGS. 27 and 28. Therefore, redundant descriptions are omitted.

[0362] In addition, with respect to the first to third light-emitting elements (LEDa`, LEDb`, LEDc`) of FIGS. 27 to 29, the description of the first to third light-emitting elements (LEDa`, LEDb`, LEDc`) with reference to FIGS. 3 to 5 may be applied, except for the intermediate layer (ML`) and the second electrode layer (E2`). Therefore, redundant descriptions are omitted.

[0363] In particular, the description of the first electrode layers (E1, E1`, E1``, E1```, E1```) described above can be applied to the first electrode layer (E1) of FIG. 29. That is, various embodiments of the first electrode layer described above can be applied to the first electrode layer (E1) of FIG. 29. Therefore, redundant descriptions are omitted.

[0364] Each of the first to third light-emitting elements (LEDa`, LEDb`, LEDc`) may correspond to the light-emitting elements (LEDs) described with reference to FIGS. 2a to 2c. For example, each of the first to third light-emitting elements (LEDa`, LEDb`, LEDc`) may include a first electrode layer (e.g., the first electrode layer E1 of FIG. 29), an intermediate layer (e.g., the intermediate layer ML` of FIG. 29) disposed on the first electrode layer, and a second electrode layer E2` disposed on the intermediate layer. In one embodiment, the first electrode layer may function as the anode of FIGS. 2a to 2c, and the second electrode layer E2` may function as the cathode of FIGS. 2a to 2c.

[0365] In one embodiment, the second electrode layer (E2`) may be separated (or disconnected) into second electrodes (E2a`, E2b`, E2c`) by a separator (SPR`). Specifically, the second electrode layer (E2`) may be separated (or disconnected) into a second electrode (E2a`) of a first light-emitting element (LEDa`), a second electrode (E2b`) of a second light-emitting element (LEDb`), and a second electrode (E2c`) of a third light-emitting element (LEDc`), and the second electrodes (E2a`, E2b`, E2c`) may be electrically independent of each other. This will be described in more detail later.

[0366] The first light-emitting element (LEDa`) may include a first electrode (E1a, see FIG. 7) functioning as the anode and a second electrode (E2a`) functioning as the cathode, the second light-emitting element (LEDb`) may include a first electrode (E1b, see FIG. 7) functioning as the anode and a second electrode (E2b`) functioning as the cathode, and the third light-emitting element (LEDc`) may include a first electrode (E1c, see FIG. 7) functioning as the anode and a second electrode (E2c`) functioning as the cathode.

[0367] As described above, the display device (DD) may include first to third connection electrodes (CEa`, CEb`, CEc`). The first connection electrode (CEa`) may connect the first light-emitting element (LEDa`) and the first pixel driving circuit (PCa), the second connection electrode (CEb`) may connect the second light-emitting element (LEDb`) and the second pixel driving circuit (PCb), and the third connection electrode (CEc`) may connect the third light-emitting element (LEDc`) and the third pixel driving circuit (PCc).

[0368] The first to third connecting electrodes (CEa`, CEb`, CEc`) may include a conductive material such as a metal, an alloy, a conductive metal nitride, or a transparent conductive oxide. Examples of the conductive material that can be used as the first to third connecting electrodes (CEa`, CEb`, CEc`) include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum (Al), an alloy containing silver (Ag), an alloy containing copper (Cu), an alloy containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), tin oxide (SnO), gallium oxide (GaO), indium gallium zinc oxide (IGZO), indium tin There may be zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), aluminum zinc oxide (AZO), etc. These may be used alone or in combination with each other. In one embodiment, the first to third connection electrodes (CEa`, CEb`, CEc`) may have a multilayer structure in which a plurality of conductive layers are stacked. This will be described in more detail later with reference to FIG. 29.

[0369] The first connecting electrode (CEa`) may include a first circuit connecting portion (CPa`) and a first light emitting connecting portion (CNa`).

[0370] The first circuit connection portion (CPa`) may be a portion of the first connection electrode (CEa`) that is connected to the first pixel driving circuit portion (PCa). Specifically, the first circuit connection portion (CPa`) may be a portion of the first connection electrode (CEa`) that is connected to the first transistor (TR1, see FIG. 8) of the first pixel driving circuit portion (PCa). Accordingly, the position of the first circuit connection portion (CPa`) may correspond to the position of the first transistor (TR1) of the first pixel driving circuit portion (PCa). Specifically, the position of the first circuit connection portion (CPa`) may correspond to the position of a contact hole that extends to the first transistor (TR1) of the first pixel driving circuit portion (PCa) and extends through the fifth insulating layer (IL5, see FIG. 29).

[0371] The first light-emitting connection portion (CNa`) may be a portion of the first connection electrode (CEa`) that is connected to the second electrode (E2a`) of the first light-emitting element (LEDa`). Specifically, the first light-emitting connection portion (CNa`) may be a portion positioned in an opening of the sixth insulating layer (IL6, see FIG. 29) and an opening of the pixel defining layer (PDL, see FIG. 29) to make contact with the second electrode (E2a`) of the first connection electrode (CEa`). Accordingly, the position of the first light-emitting connection portion (CNa`) may correspond to the position of the opening that exposes the first connection electrode (CEa`) and extends through the pixel defining layer (PDL) and the sixth insulating layer (IL6).

[0372] The second electrode (E2a`) of the first light-emitting element (LEDa`) can be connected to the first connection electrode (CEa`). For example, the second electrode (E2a`) of the first light-emitting element (LEDa`) can be in contact with the first connection electrode (CEa`). Consequently, the second electrode (E2a`) of the first light-emitting element (LEDa`) can be connected to the first pixel driving circuit (PCa) via the first connection electrode (CEa`).

[0373] In one embodiment, the first light-emitting connection portion (CNa`) may be disposed at a position that does not overlap the first light-emitting area (EAa). For example, on a plane, the first light-emitting connection portion (CNa`) may be disposed between the first light-emitting area (EAa) and the separator (SPR`). For example, the second electrode (E2a`) of the first light-emitting element (LEDa`) may have a protruding portion that protrudes from the first light-emitting area (EAa) on a plane at a position that does not overlap the first light-emitting area (EAa), and the second electrode (E2a`) of the first light-emitting element (LEDa`) and the first connection electrode (CEa`) may contact each other at a position that does not overlap the first light-emitting area (EAa). Accordingly, the second electrode (E2a`) of the first light-emitting element (LEDa`) and the first pixel driving circuit (PCa) can be connected via the first connection electrode (CEa`) without reducing the light-emitting area of ​​the first light-emitting region (EAa).

[0374] The second connecting electrode (CEb`) may include a second circuit connecting portion (CPb`) and a second light-emitting connecting portion (CNb`).

[0375] The second circuit connection portion (CPb`) may be a portion of the second connection electrode (CEb`) that is connected to the second pixel driving circuit portion (PCb). Specifically, the second circuit connection portion (CPb`) may be a portion of the second connection electrode (CEb`) that is connected to the first transistor (TR1, see FIG. 29) of the second pixel driving circuit portion (PCb). Accordingly, the position of the second circuit connection portion (CPb`) may correspond to the position of the first transistor (TR1) of the second pixel driving circuit portion (PCb). Specifically, the position of the second circuit connection portion (CPb`) may correspond to the position of a contact hole that extends to the first transistor (TR1) of the second pixel driving circuit portion (PCb) through the fifth insulating layer (IL5, see FIG. 29).

[0376] The second light-emitting connection portion (CNb`) may be a portion of the second connection electrode (CEb`) that is connected to the second electrode (E2b`) of the second light-emitting element (LEDb`). Specifically, the second light-emitting connection portion (CNb`) may be a portion located in openings of the sixth insulating layer (IL6, see FIG. 29) and the pixel defining layer (PDL, see FIG. 29) that contact the second electrode (E2b`) of the second connection electrode (CEb`). Accordingly, the position of the second light-emitting connection portion (CNb`) may correspond to the position of the opening that extends to the second connection electrode (CEb`) through the pixel defining layer (PDL) and the sixth insulating layer (IL6).

[0377] In one embodiment, the second connection electrode (CEb`) may be spaced apart from the first connection electrode (CEa`) in a plane. In other words, the first connection electrode (CEa`) and the second connection electrode (CEb`) may be distinct electrodes.

[0378] The second electrode (E2b`) of the second light-emitting element (LEDb`) may be connected to the second connection electrode (CEb`). For example, the second electrode (E2b`) of the second light-emitting element (LEDb`) may be in contact with the second connection electrode (CEb`). Consequently, the second electrode (E2b`) of the second light-emitting element (LEDb`) may be connected to the second pixel driving circuit (PCb) via the second connection electrode (CEb`).

[0379] In one embodiment, the second light-emitting connection portion (CNb`) may be disposed at a position that does not overlap the second light-emitting area (EAb). For example, on a plane, the second light-emitting connection portion (CNb`) may be disposed between the second light-emitting area (EAb) and the separator (SPR`). For example, the second electrode (E2b`) of the second light-emitting element (LEDb`) may have a protruding portion that protrudes from the second light-emitting area (EAb) at a position that does not overlap the second light-emitting area (EAb) on a plane, and the second electrode (E2b`) and the second connection electrode (CEb`) of the second light-emitting element (LEDb`) may contact each other at a position that does not overlap the second light-emitting area (EAb). Accordingly, the second electrode (E2b`) of the second light-emitting element (LEDb`) and the second pixel driving circuit (PCb) can be connected via the second connection electrode (CEb`) without reducing the light-emitting area of ​​the second light-emitting region (EAb).

[0380] The third connecting electrode (CEc`) may include a third circuit connecting portion (CPc`) and a third light-emitting connecting portion (CNc`).

[0381] The third circuit connection portion (CPc`) may be a portion of the third connection electrode (CEc`) that is connected to the third pixel driving circuit portion (PCc). Specifically, the third circuit connection portion (CPc`) may be a portion of the third connection electrode (CEc`) that is connected to the first transistor (TR1, see FIG. 29) of the third pixel driving circuit portion (PCc). Accordingly, the position of the third circuit connection portion (CPc`) may correspond to the position of the first transistor (TR1) of the third pixel driving circuit portion (PCc). Specifically, the position of the third circuit connection portion (CPc`) may correspond to the position of a contact hole that extends to the first transistor (TR1) of the third pixel driving circuit portion (PCc) through the fifth insulating layer (IL5, see FIG. 29).

[0382] The third light-emitting connection portion (CNc`) may be a portion of the third connection electrode (CEc`) that is connected to the second electrode (E2c`) of the third light-emitting element (LEDc`). Specifically, the third light-emitting connection portion (CNc`) may be a portion located in openings of the sixth insulating layer (IL6, see FIG. 29) and the pixel defining layer (PDL, see FIG. 29) that are in contact with the second electrode (E2c`) of the third connection electrode (CEc`). Accordingly, the position of the third light-emitting connection portion (CNc`) may correspond to the position of the opening that extends to the third connection electrode (CEc`) through the pixel defining layer (PDL) and the sixth insulating layer (IL6).

[0383] In one embodiment, the third connection electrode (CEc`) may be spaced apart from the first connection electrode (CEa`) and the second connection electrode (CEb`) in a plane. In other words, the first connection electrode (CEa`), the second connection electrode (CEb`), and the third connection electrode (CEc`) may be distinct electrodes.

[0384] The second electrode (E2c`) of the third light-emitting element (LEDc`) may be connected to the third connection electrode (CEc`). For example, the second electrode (E2c`) of the third light-emitting element (LEDc`) may be in contact with the third connection electrode (CEc`). Consequently, the second electrode (E2c`) of the third light-emitting element (LEDc`) may be connected to the third pixel driving circuit (PCc) via the third connection electrode (CEc`).

[0385] In one embodiment, the third light-emitting connection portion (CNc`) may be positioned at a position that does not overlap the third light-emitting area (EAc). For example, on a plane, the third light-emitting connection portion (CNc`) may be positioned between the third light-emitting area (EAc) and the separator (SPR`). For example, the second electrode (E2c`) of the third light-emitting element (LEDc`) may have a protruding portion that protrudes from the third light-emitting area (EAc) at a position that does not overlap the third light-emitting area (EAc) on a plane, and the second electrode (E2c`) of the third light-emitting element (LEDc`) and the third connection electrode (CEc`) may contact each other at a position that does not overlap the third light-emitting area (EAc). Therefore, the second electrode (E2c`) of the third light-emitting element (LEDc`) and the third pixel driving circuit (PCc) can be connected via the third connection electrode (CEc`) without reducing the light-emitting area of ​​the third light-emitting region (EAc).

[0386] According to one embodiment of the present disclosure, the second electrodes (E2a`, E2b`, E2c`) can be connected to the first to third connection electrodes (CEa`, CEb`, CEc`) at positions that do not overlap the first to third light-emitting areas (EAa, EAb, EAc), respectively. Accordingly, the second electrodes (E2a`, E2b`, E2c`) can be connected to the first to third connection electrodes (CEa`, CEb`, CEc`) without reducing the light-emitting area.

[0387] In addition, according to one embodiment of the present disclosure, the second electrodes (E2a`, E2b`, E2c`) may be connected to the first to third pixel driving circuits (PCa, PCb, PCc) via the first to third connection electrodes (CEa`, CEb`, CEc`), respectively. Accordingly, constraints on the position, shape, and size of the first to third light-emitting areas (EAa, EAb, EAc) in the design of the first to third pixel driving circuits (PCa, PCb, PCc) may be reduced. For example, even if at least some of the first to third circuit connection parts (CPa`, CPb`, CPc`) overlap with the first to third light-emitting areas (EAa, EAb, EAc), the second electrodes (E2a`, E2b`, E2c`) can be easily connected to the first to third pixel driving circuit parts (PCa, PCb, PCc) through the first to third connection electrodes (CEa`, CEb`, CEc`). Therefore, the shape and arrangement of the first to third pixel driving circuit parts (PCa, PCb, PCc) can be designed independently from the position, shape, and size of the first to third light-emitting areas (EAa, EAb, EAc). Therefore, the degree of freedom in the design of the first to third pixel driving circuit parts (PCa, PCb, PCc) can be increased.

[0388] As illustrated in FIG. 27, the shape or arrangement of each of the first to third connection electrodes (CEa`, CEb`, CEc`) corresponding to each of the first unit light-emitting areas (UEA1) and the arrangement relationship between the first to third connection electrodes (CEa`, CEb`, CEc`) may be the same. In addition, the shape or arrangement of each of the first to third connection electrodes (CEa`, CEb`, CEc`) corresponding to each of the second unit light-emitting areas (UEA2) and the arrangement relationship between the first to third connection electrodes (CEa`, CEb`, CEc`) may be the same.

[0389] As described above, the display device (DD) may include a separator (SPR`).

[0390] The separator (SPR`) may be disposed on a pixel defining layer (PDL, see FIG. 29). In one embodiment, the separator (SPR`) may include an organic insulating material. For example, the separator (SPR`) may include a photosensitive resin (e.g., photoresist). However, the present disclosure is not necessarily limited thereto.

[0391] The second electrode layer (E2`) can be separated (or disconnected) into second electrodes (E2a`, E2b`, E2c`) by a separator (SPR`). That is, the second electrode (E2a`) of the first light-emitting element (LEDa`), the second electrode (E2b`) of the second light-emitting element (LEDb`), and the second electrode (E2c`) of the third light-emitting element (LEDc`) can be electrically independent from each other by the separator (SPR`).

[0392] The separator (SPR`) can define first to third open areas (OA1, OA2, OA3) corresponding to the second electrodes (E2a`, E2b`, E2c`), respectively. For example, the separator (SPR`) can have a mesh pattern surrounding the second electrodes (E2a`, E2b`, E2c`) on a plane. The second electrode (E2a`) of the first light-emitting element (LEDa`) can be arranged in the first open area (OA1) of the separator (SPR`), the second electrode (E2b`) of the second light-emitting element (LEDb`) can be arranged in the second open area (OA2) of the separator (SPR`), and the second electrode (E2c`) of the third light-emitting element (LEDc`) can be arranged in the third open area (OA3) of the separator (SPR`).

[0393] In one embodiment, the outer shape of the first open area (OA1) may be substantially the same as the outer shape of the second electrode (E2a`) of the first light-emitting element (LEDa`) on a plane, the outer shape of the second open area (OA2) may be substantially the same as the outer shape of the second electrode (E2b`) of the second light-emitting element (LEDb`) on a plane, and the outer shape of the third open area (OA3) may be substantially the same as the outer shape of the second electrode (E2c`) of the third light-emitting element (LEDc`) on a plane.

[0394] Hereinafter, with reference to FIG. 29, a cross-sectional structure of a display device (DD) according to the embodiments of FIGS. 27 to 29 will be described in more detail, focusing on the first light-emitting area (EAa). The following description of the cross-sectional structure of the display device (DD) can be applied to all light-emitting areas.

[0395] Below, the differences from the cross-sectional structure of the display device (DD) according to the embodiment described with reference to FIG. 5 will be described, and overlapping descriptions will be omitted or simplified.

[0396] In one embodiment, the display device (DD) may include a substrate (SUB), a first lower conductive layer (BML1), a second lower conductive layer (BML2), a first transistor (TR1), a second transistor (TR2), a first capacitor (CAP1), a second capacitor (CAP2), a first connection electrode (CEa`), first to sixth insulating layers (IL1, IL2, IL3, IL4, IL5, IL6), a pixel defining layer (PDL), a first light-emitting element (LEDa`), a separator (SPR`), a first dummy layer (DP1), a second dummy layer (DP2), and an encapsulation layer (ENC).

[0397] The first connection electrode (CEa`) may be disposed on the fifth insulating layer (IL5). As described above, the first connection electrode (CEa`) may be connected to the first transistor (TR1). Specifically, the first connection electrode (CEa`) may contact the first transistor (TR1) through a contact hole (CNT) extending through the fifth insulating layer (IL5). Accordingly, the position of the first circuit connection portion (CPa`) may correspond to the position of the contact hole (CNT).

[0398] The first connection electrode (CEa`) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or a transparent conductive oxide. In one embodiment, the first connection electrode (CEa`) may have a multilayer structure in which a plurality of conductive layers are stacked. For example, the first connection electrode (CEa`) may include a first conductive layer (CL1), a second conductive layer (CL2), and a third conductive layer (CL3) that are sequentially stacked.

[0399] In one embodiment, the first conductive layer (CL1) may include a metal and / or a transparent conductive oxide. Examples of the metal that can be used as the first conductive layer (CL1) may include titanium (Ti), molybdenum (Mo), etc. Examples of the transparent conductive oxide that can be used as the first conductive layer (CL1) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. The first conductive layer (CL1) may have a relatively thin thickness compared to the second conductive layer (CL2).

[0400] The second conductive layer (CL2) may include a different material from the first conductive layer (CL1). For example, the second conductive layer (CL2) may include a different metal from the first conductive layer (CL1). Examples of the metal that may be used as the second conductive layer (CL2) include aluminum (Al), copper (Cu), etc. The second conductive layer (CL2) may have a relatively thicker thickness than the first conductive layer (CL1).

[0401] The third conductive layer (CL3) may include a different material from the second conductive layer (CL2). For example, the third conductive layer (CL3) may include a different metal and / or transparent conductive oxide from the second conductive layer (CL2). Examples of the metal that can be used as the third conductive layer (CL3) may include titanium (Ti), molybdenum (Mo), etc. Examples of the transparent conductive oxide that can be used as the third conductive layer (CL3) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InO), indium gallium oxide (IGO), aluminum zinc oxide (AZO), etc. The third conductive layer (CL3) may have a relatively thin thickness compared to the second conductive layer (CL2).

[0402] In one embodiment, the first conductive layer (CL1) and the third conductive layer (CL3) may comprise the same material. However, the present disclosure is not necessarily limited thereto.

[0403] The side surface (CL1-S) of the first conductive layer (CL1) and the side surface (CL3-S) of the third conductive layer (CL3) may extend beyond the side surface (CL2-S) of the second conductive layer (CL2). Accordingly, the first connection electrode (CEa`) may have a tip structure due to a portion of the third conductive layer (CL3) that protrudes compared to the second conductive layer (CL2). For example, when the second conductive layer (CL2) is etched using an etching material having a higher etching rate for the second conductive layer (CL2) than the first conductive layer (CL1) and the third conductive layer (CL3) based on the same etching process, the first connection electrode (CEa`) may be formed to have the tip structure.

[0404] Meanwhile, in FIG. 29, the first connection electrode (CEa`) is illustrated as having a three-layer structure in which first to third conductive layers (CL1, CL2, CL3) are stacked. However, the present disclosure is not limited to this structure, and the first connection electrode (CEa`) may have a two-layer structure in which the second conductive layer (CL2) and the third conductive layer (CL3) are stacked. That is, the first conductive layer (CL1) may be omitted.

[0405] The sixth insulating layer (IL6) may be disposed on the fifth insulating layer (IL5) and partially cover the first connection electrode (CEa`). That is, the sixth insulating layer (IL6) may define a first sub-opening (SO1`) that exposes at least a portion of the first connection electrode (CEa`). Specifically, the first sub-opening (SO1`) may expose the tip structure of the first connection electrode (CEa`).

[0406] The pixel defining layer (PDL) can further define a second sub-aperture (SO2`) corresponding to the first sub-aperture (SO1`) of the sixth insulating layer (IL6). The second sub-aperture (SO2`) can overlap the first sub-aperture (SO1`) on a plane, and the first sub-aperture (SO1`) and the second sub-aperture (SO2`) can be spatially connected to each other. That is, the opening (OP`) formed by the first sub-aperture (SO1`) and the second sub-aperture (SO2`) can be defined such that at least a part of the first connection electrode (CEa`) is positioned at the bottom of the opening (OP`). Specifically, the tip structure of the first connection electrode (CEa`) can be positioned in the opening (OP`).

[0407] The separator (SPR`) may be disposed on the pixel defining layer (PDL). The separator (SPR`) may have a shape in which the width of the upper portion is greater than the width of the lower portion. That is, the separator (SPR`) connecting the upper surface of the separator (SPR`) and the lower surface of the separator (SPR`) may have a tapered cross-section with slanted sides. That is, the cross-section of at least a portion of the separator (SPR`) may be trapezoidal.

[0408] In Fig. 29, the separator (SPR`) is illustrated as having a tapered cross-section with inclined sides. However, the present disclosure is not necessarily limited to this structure, and the separator (SPR`) may have multiple inclined sides. For example, the separator (SPR`) may have a double tapered structure.

[0409] The intermediate layer (ML`) may be disposed on the first electrode (E1) and the pixel defining layer (PDL). A portion of the intermediate layer (ML`) may be disposed within the pixel opening of the pixel defining layer (PDL). In one embodiment, the intermediate layer (ML`) may include a first functional layer including an organic material, an emission layer disposed on the first functional layer and including an emission material, and a second functional layer disposed on the emission layer and including an organic material. For example, the first functional layer may include a hole injection layer, a hole transport layer, etc., and the second functional layer may include an electron transport layer, an electron injection layer, etc.

[0410] A shadow region in which it is difficult to deposit an intermediate layer (ML`) may exist around a separator (SPR`) having a tapered slope. Accordingly, the intermediate layer (ML`) in the shadow region and / or around the shadow region may have a structure separated by the separator (SPR`). For example, the first and second functional layers included in the intermediate layer (ML`) may have a structure separated by the separator (SPR`).

[0411] A first dummy layer (DP1) may be disposed on the separator (SPR`). The first dummy layer (DP1) may be formed by having a structure in which the intermediate layer (ML`) is separated by the separator (SPR`). That is, the first dummy layer (DP1) may be formed in the same process as the intermediate layer (ML`). In one embodiment, the first dummy layer (DP1) may be omitted.

[0412] The intermediate layer (ML`) can also be separated (or disconnected) by the tip structure of the first connecting electrode (CEa`). As the intermediate layer (ML`) is separated (or disconnected) by the tip structure of the first connecting electrode (CEa`), the intermediate layer (ML`) can expose at least a portion of the side surface (CL2-S) of the second conductive layer (CL2). Accordingly, the second electrode (E2a`) of the first light-emitting element (LEDa`) can be electrically connected to the second conductive layer (CL2).

[0413] The second electrode layer (E2`) (i.e., the second electrodes (E2a`, E2b`, E2c`)) may be disposed on the intermediate layer (ML`). The second electrode layer (E2`) (i.e., the second electrodes (E2a`, E2b`, E2c`)) may include a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive oxide, or the like. In one embodiment, the second electrode layer (E2`) (i.e., the second electrodes (E2a`, E2b`, E2c`)) may have a single-layer structure. However, the present disclosure is not necessarily limited thereto, and the second electrode layer (E2`) (i.e., the second electrodes (E2a`, E2b`, E2c`)) may have a multi-layer structure in which a plurality of conductive layers are stacked. For example, the second electrode layer (E2`) (i.e., the second electrodes (E2a`, E2b`, E2c`)) may have a two-layer structure in which a first sub-electrode layer including a metal material and a second sub-electrode layer including a transparent conductive oxide are laminated on the first sub-electrode layer.

[0414] A shadow region in which it is difficult to deposit a second electrode layer (E2`) may exist around a separator (SPR`) having a tapered, inclined side surface. In the shadow region and / or around the shadow region, the second electrode layer (E2`) may have a structure that is disconnected by the separator (SPR`). For example, as illustrated in FIG. 28, the second electrode layer (E2`) may be disconnected by a second electrode (E2a`) of a first light-emitting element (LEDa`) disposed in a first open region (OA1) of the separator (SPR`), a second electrode (E2b`) of a second light-emitting element (LEDb`) disposed in a second open region (OA2) of the separator (SPR`), and a second electrode (E2c`) of a third light-emitting element (LEDc`) disposed in a third open region (OA3) of the separator (SPR`). That is, the second electrodes (E2a`, E2b`, E2c`) can be electrically independent of each other.

[0415] As illustrated in FIG. 29, the second electrode (E2a`) of the first light-emitting element (LEDa`) can be connected to the first connection electrode (CEa`). For example, the second electrode (E2a`) can be in contact with the side surface (CL2-S) of the second conductive layer (CL2). For example, when the deposition angle of the deposition process for forming the second electrode layer (E2`) is greater than the deposition angle of the deposition process for forming the intermediate layer (ML`), the second electrode layer (E2`) (specifically, the second electrode (E2a`)) can be formed to cover the intermediate layer (ML`) disconnected by the tip structure and be connected to the side surface (CL2-S) of the second conductive layer (CL2). As a result, the second electrode (E2a`) can be connected to the first transistor (TR1) via the first connection electrode (CEa`).

[0416] In one embodiment, the second electrode layer (E2`) (specifically, the second electrode (E2a`)) may also be disconnected by the tip structure of the first connection electrode (CEa`). However, the present disclosure is not necessarily limited thereto, and the second electrode layer (E2`) (specifically, the second electrode (E2a`)) may be formed to extend without being disconnected by the tip structure.

[0417] Meanwhile, a second dummy layer (DP2) may be disposed on the separator (SPR`). Specifically, the second dummy layer (DP2) may be disposed on the first dummy layer (DP1). The second dummy layer (DP2) may be formed by having a structure in which the second electrode layer (E2`) is separated (or disconnected) by the separator (SPR`). That is, the second dummy layer (DP2) may be formed in the same process as the second electrode layer (E2`). In one embodiment, the second dummy layer (DP2) may be omitted.

[0418] According to one embodiment of the present disclosure, the display device (DD) may include connection electrodes (CEa`, CEb`, CEc`) having a tip structure and a separator (SPR`). Accordingly, the second electrode layer (E2`) (e.g., cathode) disposed above the first electrode layer (E1) (e.g., anode) may be easily connected to the pixel driving circuit units (PCa, PCb, PCc). Specifically, the second electrode layer (E2`) disposed above the first electrode layer (E1) may be connected to the drain of the driving transistor (e.g., the first transistor (T1) of FIGS. 2A to 2C) of each of the pixel driving circuit units (PCa, PCb, PCc) through the connection electrodes (CEa`, CEb`, CEc`). Accordingly, even when the light-emitting element deteriorates, the gate-source voltage (Vgs) of the driving transistor may not change. Accordingly, the range of change in driving current due to deterioration of the light-emitting element can be reduced. Accordingly, afterimage defects of the display device (DD) due to increased usage time can be reduced, and the lifespan of the display device (DD) can be improved.

[0419] FIG. 30 is a block diagram illustrating an electronic device according to embodiments of the present disclosure.

[0420] Referring to FIG. 30, the electronic device (10) may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0421] The display device according to the embodiments (for example, the display device (DD, DDa) of FIGS. 1 to 29) can be applied to various electronic devices (10). The electronic device (10) includes the above-described display device, and may further include a module or device having additional functions in addition to the display device.

[0422] The above processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0423] The above memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0424] The power module (14) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (10). Specifically, the power module (14) may supply power (e.g., ELVSS and ELVDD of FIGS. 2A to 2C) to the display device.

[0425] At least one of the components of the electronic device (10) described above may be included in the display device according to the embodiments described above. In addition, some of the individual modules functionally included in one module may be included in the display device, and other parts may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), the memory (13), and the power module (14) may be provided in the form of other devices within the electronic device (10) rather than the display device.

[0426] FIG. 31 is a schematic diagram showing an electronic device according to various embodiments.

[0427] Referring to FIG. 31, the various electronic devices (10) to which the display devices (for example, the display devices (DD, DDa) of FIGS. 1 to 29) according to the embodiments are applied may include not only image display electronic devices such as a smart phone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and vehicle electronic devices (10_3) including display modules such as a CID (Center Information Display) and a room mirror display arranged on an instrument panel, center fascia, or dashboard of an automobile.

[0428] Although the present disclosure has been described above with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the claims below.

[0429] The present disclosure can be applied to display devices and electronic devices including the same. For example, the present disclosure can be applied to high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, and the like.

[0430] <Explanation of symbols>

[0431] DD, DDa: Display device DA: Display area

[0432] NDA: Peripheral Area SUB: Substrate

[0433] PX: pixels GL: gate lines

[0434] DL: Data line DDV: Data drive

[0435] GDV: Gate Driver LED: Light Emitting Diode

[0436] PC, PC`, PC``: pixel driving circuit

[0437] UEA1: First unit light-emitting area UEA2: Second unit light-emitting area

[0438] EAa, EAb, EAc: first to third luminescent regions

[0439] PCU: Unit Circuit Areas

[0440] PCa, PCb, PCc: first to third pixel driving circuits

[0441] LEDa, LEDa`: first light-emitting element LEDb LEDb`: second light-emitting element

[0442] LEDc, LEDc`: third light-emitting element CEa, CEa`: first connecting electrode

[0443] CEb, CEb`: Second connection electrode CEc, CEc`: Third connection electrode

[0444] CNPa: First connection pattern CNPb: Second connection pattern

[0445] CNPc: Third connection pattern CPa, CPa`: First circuit connection

[0446] CPb, CPb`: Second circuit connection CPc, CPc`: Third circuit connection

[0447] CNa, CNa`: first luminescent connector CNb, CNb`: second luminescent connector

[0448] CNc, CNc`: third luminescent connector

[0449] CL1: First challenge layer CL2: Second challenge layer

[0450] CL3: Third Challenge Layer

[0451] SE1, DE1, SE2, DE2: first to fourth contact electrodes

[0452] IL1, IL2, IL3, IL4, IL5, IL6: first to sixth insulating layers

[0453] PDL: pixel defining layer CNT: contact hole

[0454] CNT1, CNT2, CNT3, CNT4, CNT5, CNT6: first to sixth contact holes

[0455] SO1, SO1`: first sub-aperture SO2, SO2`: second sub-aperture

[0456] OP, OP`: opening

[0457] E1, E1`, E1``, E1```, E1````: first electrode layer

[0458] E1a, E1b, E1c: first electrodes BR1: first bridges

[0459] BR2: Second bridges EL1: First electrode lines

[0460] EL2: Second electrode lines EP: Electrode patterns

[0461] ML, ML`: middle layer E2, E2`: second electrode layer

[0462] E2a, E2a`, E2b, E2b`, E2c, E2c`: second electrodes

[0463] TLG, TLG`, TLG``: Transmission line group

[0464] TL1: First transmission lines TL2: Second transmission lines

[0465] SPR, SPR`: Separator

[0466] OA1, OA2, OA3: First to third open areas

[0467] ENC: Encapsulation layer IEL1: First weapon encapsulation layer

[0468] OEL: Organic encapsulation layer IEL2: Second inorganic encapsulation layer

Claims

A pixel driving circuit including a transistor; A connecting electrode disposed on the pixel driving circuit portion and electrically connected to the transistor of the pixel driving circuit portion; A first electrode layer disposed on the above connecting electrode, receiving a power voltage, and including a plurality of first electrodes; A group of transmission lines arranged in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane; A separator disposed on the first electrode layer; and A display device comprising a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator. A display device, characterized in that in the first paragraph, the first electrode layer is connected to receive the power voltage through the transmission line group. A display device according to claim 1, characterized in that the first electrode layer has a mesh pattern in which the plurality of first electrodes extending in different directions are integrally connected. A display device characterized in that in the third paragraph, the transmission line group includes a plurality of transmission lines extending in one direction and arranged in a cross direction that is not parallel to the one direction and intersects it. In paragraph 4, The above transistor, An active pattern comprising a semiconductor material; a gate electrode disposed on the above active pattern; and a contact electrode disposed on the gate electrode and in contact with the active pattern; A display device characterized in that the plurality of transmission lines are arranged on the same layer as the contact electrode. A display device according to claim 4, characterized in that the plurality of transmission lines are arranged on the same layer as the connecting electrode. In the third paragraph, the transmission line group, A plurality of first transmission lines extending in one direction and arranged in a cross direction that is not parallel to the one direction and intersects it; and A display device characterized by including a plurality of second transmission lines extending in the cross direction and arranged in the one direction. In paragraph 7, The above transistor, An active pattern comprising a semiconductor material; a gate electrode disposed on the above active pattern; and a contact electrode disposed on the gate electrode and in contact with the active pattern; The above plurality of first transmission lines are arranged on the same layer as the contact electrode, A display device characterized in that the plurality of second transmission lines are arranged on the same layer as the connecting electrode. In the first paragraph, the first electrode layer includes electrode lines extending in one direction and arranged in a cross direction that is not parallel to the one direction and intersects with it, The above electrode lines are physically separated from each other, A display device characterized in that each of the above electrode lines has a structure in which some of the first electrodes extending in different directions are integrally connected. In the first paragraph, the first electrode layer includes a plurality of electrode patterns arranged in one direction and in a cross direction that is not parallel to the one direction and intersects with the first direction, The above plurality of electrode patterns are physically separated from each other, A display device characterized in that each of the plurality of electrode patterns has a structure in which some of the plurality of first electrodes are integrally connected. In the 10th paragraph, the transmission line group A plurality of first transmission lines extending in the above one direction and arranged in the above cross direction; and A display device characterized by including a plurality of second transmission lines extending in the cross direction and arranged in the one direction. In Article 11, The plurality of first transmission lines and the plurality of second transmission lines are connected to at least one of the plurality of electrode patterns, A display device characterized in that the plurality of first transmission lines, the plurality of second transmission lines, and the plurality of electrode patterns form the mesh structure. A display device, characterized in that in claim 11, the plurality of electrode patterns are electrically connected to each other through the plurality of first transmission lines and the plurality of second transmission lines. In Article 12, The above transistor, An active pattern comprising a semiconductor material; a gate electrode disposed on the above active pattern; and a contact electrode disposed on the gate electrode and in contact with the active pattern; The above plurality of first transmission lines are arranged on the same layer as the contact electrode, A display device characterized in that the plurality of second transmission lines are arranged on the same layer as the connecting electrode. In the first paragraph, the plurality of first electrodes are arranged in one direction and in a cross direction that is not parallel to the one direction and intersects with the one direction, A display device characterized in that the plurality of first electrodes are physically separated from each other. In the first paragraph, A display device characterized in that it further includes an intermediate layer disposed between the first electrode layer and the second electrode layer and containing a light-emitting material. A display device characterized in that in the first paragraph, at least one of the plurality of second electrodes is electrically connected to the connection electrode and is electrically connected to the transistor of the pixel driving circuit unit through the connection electrode. A pixel driving circuit including a transistor; A connecting electrode disposed on the pixel driving circuit portion and electrically connected to the transistor of the pixel driving circuit portion; A first electrode layer disposed on the above connecting electrode, receiving a power voltage, and including a plurality of first electrodes; A group of transmission lines arranged in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane; A pixel defining film disposed on the first electrode layer and defining a light-emitting area; A connection pattern electrically connected to the above connection electrode and surrounding the light-emitting area on a plane; A separator disposed on the pixel definition film and the connection pattern and covering at least a portion of the connection pattern; and A display device comprising a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator. A display device characterized in that in claim 18, at least one of the plurality of second electrodes contacts the connection pattern at a position adjacent to or overlapping the separator, and is electrically connected to the transistor of the pixel driving circuit unit through the connection electrode and the connection pattern. A pixel driving circuit including a transistor; A connecting electrode disposed on the pixel driving circuit portion and electrically connected to the transistor of the pixel driving circuit portion; A first electrode layer disposed on the above connecting electrode, receiving a power voltage, and including a plurality of first electrodes; A group of transmission lines arranged in a different layer from the first electrode layer, electrically connected to the first electrode layer, and forming a mesh structure with the first electrode layer on a plane; A separator disposed on the first electrode layer; and A display device including a second electrode layer disposed on the first electrode layer and separated into a plurality of second electrodes by the separator; and An electronic device including a power module that supplies the power voltage to the display device.

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