Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cells, which are distributed in different layers and are stacked in a direction perpendicular to a substrate (1); bit lines (30), which run through the memory cells in the different layers and extend in the direction perpendicular to the substrate (1); and a plurality of word lines (40), which are distributed in different layers, wherein the word lines (40) and the bit lines (30) are distributed in a first direction parallel to the substrate (1), and the word lines (40) extend in a second direction parallel to the substrate, the first direction intersecting the second direction; and each memory cell comprises a transistor, the transistor comprising a semiconductor layer (23), the semiconductor layer (23) surrounding each word line (40), the side wall of the semiconductor layer (23) facing the side of each bit line (30) and perpendicular to the substrate (1) being connected to said bit line (30), and a plurality of semiconductor layers (23) of a plurality of transistors at the same position in different layers being connected to the same bit line (30).

Description

A semiconductor device, a manufacturing method thereof, and an electronic device

[0001] The present application claims priority to the Chinese patent application No. 2024110179399, filed on July 26, 2024, and entitled "A semiconductor device, a manufacturing method thereof, and an electronic device", the content of which should be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising:

[0008] a plurality of memory cells distributed along a vertical substrate direction and stacked in different layers;

[0009] a bit line extending along a vertical substrate direction through the memory cells in different layers;

[0010] a plurality of word lines distributed in different layers, the word lines and the bit line being distributed along a first direction parallel to the substrate, the word lines extending along a second direction parallel to the substrate, the first direction and the second direction intersecting;

[0011] The memory cells comprise transistors, the transistors comprise a semiconductor layer, the semiconductor layer surrounds the word line, a side of the semiconductor layer facing the bit line and perpendicular to the substrate is connected to the bit line, and a plurality of semiconductor layers of a plurality of transistors at the same position in different layers are connected to the same bit line.

[0012] In some embodiments, the transistor further comprises a first electrode disposed on a side of the word line away from the bit line and connected with a side wall of the semiconductor layer away from the bit line and perpendicular to the substrate;

[0013] The first electrode forms an annular recess comprising a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall comprises an inner bottom wall located inside the annular recess and an outer bottom wall located outside the annular recess, and the semiconductor layer is connected with a partial area of the outer bottom wall.

[0014] In some embodiments, the memory cell further comprises a capacitor, and the capacitor and the transistor of the same memory cell are distributed along the first direction.

[0015] The capacitor comprises a first capacitor electrode and a second capacitor electrode; the first electrode is multiplexed as the first capacitor electrode of the capacitor; the second capacitor electrode comprises a first sub-electrode, the first capacitor electrode surrounds the first sub-electrode, and a first dielectric layer is disposed between the first capacitor electrode and the first sub-electrode; the first sub-electrode is distributed on the inner wall of the annular recess formed by the first electrode; and the first sub-electrodes of the memory cells at the same position of different layers are connected to form an integrated structure.

[0016] In some embodiments, the side wall of the annular recess comprises an inner side wall located inside the annular recess and an outer side wall located outside the annular recess, and the first sub-electrode is further distributed on the outer side wall of the annular recess.

[0017] In some embodiments, the outer bottom wall of the annular recess comprises a first area, a second area, and two intermediate areas respectively disposed on both sides of the first area and spaced from the first area and the second area along the circumferential direction of the annular recess, the first area is located on a side of the annular recess facing the bit line, the word line is distributed on the first area, and the semiconductor layer is connected with a partial area of the first area; and the second capacitor electrode further comprises a second sub-electrode, and the second sub-electrode is distributed on the second area of the outer bottom wall of the annular recess.

[0018] In some embodiments, a second dielectric layer is disposed between the first capacitor electrode and the second sub-electrode, and the second dielectric layers of the capacitors at the same position of different layers are spaced along a direction perpendicular to the substrate.

[0019] In some embodiments, the memory cells of the same layer are arrayed along the first direction and the second direction, and the second sub-electrodes of the plurality of memory cells of the same layer and the same column distributed along the second direction are connected to form an integrated structure.

[0020] In some embodiments, the second sub-electrode, two first capacitor electrodes adjacent in the second direction, and the region defined by the word line adjacent to the first electrode are filled with a first isolation layer, and the first isolation layers in the same position of different layers are connected to form an integrated structure extending in a direction perpendicular to the substrate direction, and the first isolation layer is connected to the middle region of the outer bottom wall of the two first capacitor electrodes adjacent in the second direction.

[0021] In some embodiments, the first isolation layer is also distributed on the region where the first region is not connected to the semiconductor layer.

[0022] In some embodiments, the semiconductor device further comprises:

[0023] insulating layers and conductive layers alternately distributed along a direction perpendicular to the substrate;

[0024] a first hole penetrating through the insulating layers and the conductive layers; the first hole comprises a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the second sub-hole has a groove extending in a direction parallel to the substrate direction relative to the first sub-hole;

[0025] The first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer, and the first sub-electrode are sequentially distributed from the outside to the inside in the first hole.

[0026] In some embodiments, the semiconductor layers of the same column of the plurality of storage units distributed in the second direction in the same layer are arranged in the second direction and surround the same word line.

[0027] In some embodiments, two storage units adjacent in the first direction in each column are connected to the same bit line.

[0028] In some embodiments, the semiconductor layers of the same column of storage units distributed in the second direction in the same layer are respectively connected to different bit lines distributed in the second direction.

[0029] In some embodiments, a second isolation layer penetrating through the storage units of different layers and extending along a direction perpendicular to the substrate direction is arranged between different bit lines distributed in the second direction.

[0030] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0031] forming a stack structure comprising alternately arranged first insulating layers and first sacrificial layers on a substrate;

[0032] forming a plurality of second holes penetrating through the stack structure in a direction perpendicular to the substrate direction and distributed in a second direction, and filling a plurality of bit lines in the plurality of second holes;

[0033] forming a plurality of first holes spaced along a second direction through the stack structure along a direction perpendicular to the substrate, and the first holes are spaced along a first direction from the second holes, based on the first holes, etching the first sacrificial layer along a direction parallel to the substrate, forming first lateral recesses; forming first electrodes distributed on inner walls of the first lateral recesses; the first direction and the second direction intersect;

[0034] forming a first trench extending along the second direction through the stack structure on a side of the first holes away from the second holes;

[0035] based on the first trench, forming word lines extending along the second direction between the fourth insulating layers adjacent to each other, and a plurality of semiconductor layers spaced along the second direction around the word lines, the semiconductor layers are connected to the first electrodes and the bit lines respectively.

[0036] In some embodiments, based on the first trench, forming word lines extending along the second direction between the fourth insulating layers adjacent to each other, and a plurality of semiconductor layers spaced along the second direction around the word lines, includes:

[0037] based on the first trench, etching and removing the first insulating layer, replacing the first insulating layer with a fourth insulating layer and a second sacrificial layer, the second sacrificial layer is located between the first sacrificial layers adjacent to each other, and is located between the bit lines adjacent to each other along the second direction, and connects the bit lines adjacent to each other along the second direction;

[0038] based on the first trench, etching and removing the first sacrificial layer, forming a third sacrificial layer connected to the second sacrificial layer between the second sacrificial layers adjacent to each other along a direction perpendicular to the substrate, and between the bit lines adjacent to each other along the second direction;

[0039] sequentially depositing a semiconductor thin film, a gate insulating thin film and a first conductive thin film, etching and removing the semiconductor thin film, the gate insulating thin film and the first conductive thin film covering a side of the first electrode away from the bit line, a side of the first electrode facing the first electrode adjacent to each other along the second direction, retaining the semiconductor thin film, the gate insulating thin film and the first conductive thin film covering a side of the first electrode facing the bit line, forming a plurality of semiconductor layers and a plurality of gate insulating layers of a plurality of transistors, and word lines, the gate insulating layers surrounding the word lines, and the semiconductor layers surrounding the gate insulating layers;

[0040] forming a fourth sacrificial layer connecting the word lines and the first electrodes adjacent to each other along the second direction between the fourth insulating layers adjacent to each other; forming a fifth sacrificial layer connected to the fourth sacrificial layer between the fourth sacrificial layers adjacent to each other along a direction perpendicular to the substrate;

[0041] etching and removing the second and third sacrificial layers to form third holes; etching and removing the fourth and fifth sacrificial layers to form fourth holes; etching the plurality of semiconductor layers along a direction parallel to the substrate based on the third and fourth holes, such that the plurality of semiconductor layers are broken apart.

[0042] In some embodiments, the method further comprises: exposing the first hole and the first lateral recess to form a first sub-electrode within the first hole and the first lateral recess.

[0043] In some embodiments, before forming the first sub-electrode within the first hole and the first lateral recess, the method further comprises: exposing the first electrode to form a second lateral recess on a side of the first electrode facing away from the substrate and a side of the first electrode facing toward the substrate.

[0044] Forming the first sub-electrode within the first hole and the first lateral recess comprises: forming the first sub-electrode within the first hole, the first lateral recess, and the second lateral recess.

[0045] In some embodiments, after forming the fourth sacrificial layer connecting the word line and the first electrode adjacent to the second direction between adjacent fourth insulating layers, and before forming the fifth sacrificial layer connected to the fourth sacrificial layer between the fourth sacrificial layers adjacent to the direction perpendicular to the substrate, the method further comprises:

[0046] forming a second sub-electrode distributed on a side of the first electrode facing away from the bit line;

[0047] After forming the fifth sacrificial layer connected to the fourth sacrificial layer between the fourth sacrificial layers adjacent to the direction perpendicular to the substrate, the method further comprises:

[0048] forming a connection electrode filling the first trench and connected to the second sub-electrode.

[0049] Embodiments of the present disclosure provide an electronic device comprising the semiconductor device of any of the above embodiments, or a semiconductor device formed according to the manufacturing method of any of the above embodiments.

[0050] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly described herein.

[0051] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0052] BRIEF DESCRIPTION OF DRAWINGS

[0053] The accompanying drawings are used to provide an understanding of the technical solutions of the present application, constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0054] Fig. 1A is a sectional view of a semiconductor device along AA' direction parallel to the substrate according to some embodiments, Fig. 1B is a sectional view of a semiconductor device along BB' direction parallel to the substrate according to some embodiments, Fig. 1C is a sectional view along CC' direction in Fig. 1A, Fig. 1D is a sectional view along DD' direction in Fig. 1A, Fig. 1E is a sectional view along EE' direction in Fig. 1A, Fig. 1F is a sectional view along FF' direction in Fig. 1A, and Fig. 1G is a schematic view of a first capacitor electrode according to some embodiments;

[0055] Fig. 2A is a sectional view along AA' direction of forming a bit line trailing edge according to some embodiments, Fig. 2B is a sectional view along CC' direction of forming a bit line trailing edge according to some embodiments, and Fig. 2C is a sectional view along DD' direction of forming a bit line trailing edge according to some embodiments;

[0056] Fig. 3A is a sectional view along AA' direction of forming a first capacitor electrode according to some embodiments, Fig. 3B is a sectional view along CC' direction of forming a first capacitor electrode according to some embodiments, and Fig. 3C is a sectional view along FF' direction of forming a first capacitor electrode according to some embodiments;

[0057] Fig. 4A is a sectional view along AA' direction of forming a first trench according to some embodiments, Fig. 4B is a sectional view along CC' direction of forming a first trench according to some embodiments, and Fig. 4C is a sectional view along FF' direction of forming a first trench according to some embodiments;

[0058] Fig. 5A is a sectional view along AA' direction of forming a second sacrificial layer according to some embodiments, Fig. 5B is a sectional view along CC' direction of forming a second sacrificial layer according to some embodiments, Fig. 5C is a sectional view along DD' direction of forming a second sacrificial layer according to some embodiments, and Fig. 5D is a sectional view along FF' direction of forming a second sacrificial layer according to some embodiments;

[0059] Fig. 6A is a sectional view along AA' direction of forming a semiconductor layer, a gate insulating layer and a word line according to some embodiments, Fig. 6B is a sectional view along CC' direction of forming a semiconductor layer, a gate insulating layer and a word line according to some embodiments, Fig. 6C is a sectional view along DD' direction of forming a semiconductor layer, a gate insulating layer and a word line according to some embodiments, and Fig. 6D is a sectional view along EE' direction of forming a semiconductor layer, a gate insulating layer and a word line according to some embodiments;

[0060] FIG. 7A is a cross-sectional view in the direction of AA' of forming a second dielectric layer and a second sub-electrode according to some embodiments, FIG. 7B is a cross-sectional view in the direction of CC' of forming a second dielectric layer and a second sub-electrode according to some embodiments, and FIG. 7C is a cross-sectional view in the direction of EE' of forming a second dielectric layer and a second sub-electrode according to some embodiments;

[0061] FIG. 8A is a cross-sectional view in the direction of AA' of forming a connection electrode according to some embodiments, FIG. 8B is a cross-sectional view in the direction of CC' of forming a connection electrode according to some embodiments, and FIG. 8C is a cross-sectional view in the direction of EE' of forming a connection electrode according to some embodiments;

[0062] FIG. 9A is a cross-sectional view in the direction of AA' of disconnecting the semiconductor layer of different transistors in the same column according to some embodiments, FIG. 9B is a cross-sectional view in the direction of CC' of disconnecting the semiconductor layer of different transistors in the same column according to some embodiments, and FIG. 9C is a cross-sectional view in the direction of EE' of disconnecting the semiconductor layer of different transistors in the same column according to some embodiments;

[0063] FIG. 10A is a cross-sectional view in the direction of AA' of forming an isolation layer according to some embodiments, FIG. 10B is a cross-sectional view in the direction of CC' of forming an isolation layer according to some embodiments, and FIG. 10C is a cross-sectional view in the direction of EE' of forming an isolation layer according to some embodiments;

[0064] FIG. 11A is a cross-sectional view in the direction of AA' of forming a first dielectric layer and a first sub-electrode according to some embodiments, FIG. 11B is a cross-sectional view in the direction of CC' of forming a first dielectric layer and a first sub-electrode according to some embodiments, and FIG. 11C is a cross-sectional view in the direction of EE' of forming a first dielectric layer and a first sub-electrode according to some embodiments.

[0065] DETAILED DESCRIPTION

[0066] The embodiments of the present disclosure will be described in detail with reference to the drawings in the following. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as there is no conflict.

[0067] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0068] The embodiments of the present disclosure are not necessarily limited to the shapes or values shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0069] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are provided in order to avoid confusion of components, and do not indicate any order, number, or importance.

[0070] In the present disclosure, in order to facilitate the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0071] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connect", and "connect" should be broadly understood. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0072] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0073] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using transistors with opposite polarities, or in the case of changing the direction of current in circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0074] In the present disclosure, "connection" includes the case where the components are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission of electrical signals between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0075] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, thus, it also includes the angle greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, thus, it also includes the angle greater than or equal to 85° and less than or equal to 95°.

[0076] In the present disclosure, "A and B are integrated structure" can mean that there is no obvious fault or gap, etc. in the microstructure. Generally, the connected film layers are integrated on a film layer. For example, A and B use the same material to form a film layer and are formed by the same patterning process.

[0077] In the present disclosure, "the orthographic projection of B is located within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0078] FIG. 1A is a cross-sectional view of a semiconductor device along the AA' direction parallel to the substrate 1, FIG. 1B is a cross-sectional view of a semiconductor device along the BB' direction parallel to the substrate 1, FIG. 1C is a cross-sectional view along the CC' direction perpendicular to the substrate 1 in FIG. 1A, FIG. 1D is a cross-sectional view along the DD' direction perpendicular to the substrate 1 in FIG. 1A, FIG. 1E is a cross-sectional view along the EE' direction perpendicular to the substrate 1 in FIG. 1A, and FIG. 1F is a cross-sectional view along the FF' direction perpendicular to the substrate 1 in FIG. 1A. As shown in FIGS. 1A-1F, the present disclosure provides a semiconductor device including a vertically stacked multi-layered memory cell array on a substrate 1.

[0079] The memory cell array can include a plurality of memory cells, a plurality of bit lines 30, and a plurality of word lines 40. Each layer of the memory cell array can include a plurality of memory cells arrayed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0080] The bit lines 30 can extend along a direction perpendicular to the substrate 1, and the plurality of memory cells at the same position of different layers stacked in the direction perpendicular to the substrate 1 are connected to the same bit line 30.

[0081] In some embodiments, the memory cells adjacent along the first direction X are connected to the same bit line 30. Every two vertical columns of memory cells can be a group, and the memory cells in the same group are connected to the same bit line 30. The plurality of memory cells at the same position of different layers is referred to as a vertical column of memory cells.

[0082] The word lines 40 can extend along a second direction Y parallel to the substrate 1, a plurality of word lines 40 of the same memory cell array can be spaced apart from each other, and the plurality of word lines 40 of the same memory cell array can be spaced apart along the first direction X. The word lines 40 of different layer memory cell arrays can be stacked along a direction perpendicular to the substrate 1.

[0083] The memory cell can be a 1T1C memory cell, or can be a memory cell of other structures.

[0084] Taking the 1T1C memory cell as an example, the memory cell can include a transistor and a capacitor connected to the transistor. The transistor and the capacitor of the same memory cell can be distributed along the first direction X. The capacitor, the word line 40, and the bit line 30 can be distributed along the first direction X. The transistor can include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 can be part of the word line 40, and the gate electrodes 26 of the same column of transistors in the same layer can be connected to form an integrated structure of the word line 40.

[0085] The second electrode 52 can be connected to the bit line 30, or the second electrode 52 can be part of the bit line 30. The second electrodes 52 of the transistors of the memory cells in the same position of different layers can be connected to the same bit line 30. The second electrodes 52 of the transistors in the same position of different layers can be connected to form an integrated structure of the bit line 30 extending along a direction perpendicular to the substrate 1.

[0086] The following is described taking a semiconductor device including a plurality of vertically stacked transistors in the same position as an example, and taking a memory cell as a 1T1C as an example.

[0087] As shown in FIGS. 1A-1F, the embodiments of the present disclosure provide a semiconductor device, which includes:

[0088] A plurality of memory cells distributed in different layers stacked along a direction perpendicular to the substrate 1;

[0089] A bit line 30 extending along a direction perpendicular to the substrate 1 through the memory cells in different layers;

[0090] A plurality of word lines 40 distributed in different layers, the word lines 40 and the bit line 30 being distributed along a first direction X parallel to the substrate 1, the word lines 40 extending along a second direction Y parallel to the substrate 1, and the first direction X and the second direction Y intersecting;

[0091] The storage unit includes a transistor including a semiconductor layer 23, the semiconductor layer 23 is connected with the bit line 30 on the side of the semiconductor layer 23 facing the bit line 30 and perpendicular to the sidewall of the substrate 1, and the semiconductor layers 23 of the transistors in the same column and different layers are connected with the same bit line 30.

[0092] Compared with the scheme in which the bit line extends horizontally and the word line extends vertically, the thickness of the bit line is greater than the thickness of the word line when the bit line extends horizontally (the area where the bit line is located is occupied by the word line, the semiconductor layer, and the gate insulating layer between the word line and the semiconductor layer, and the thickness of the word line is smaller than the thickness of the bit line when the bit line extends horizontally under the condition that the thickness of the transistor is the same), so that the parasitic capacitance between the word line and the bit line is smaller.

[0093] In some embodiments, the semiconductor layers 23 of the storage units in the same column and distributed along the second direction Y are respectively connected to different bit lines 30 distributed along the second direction Y at intervals.

[0094] In some embodiments, a second isolation layer 602 extending through the storage units in different layers and extending along the direction perpendicular to the substrate 1 is arranged between adjacent bit lines 30 distributed along the second direction Y at intervals. That is, the adjacent bit lines 30 along the second direction Y are spaced apart by the second isolation layer 602.

[0095] In some embodiments, the semiconductor layers 23 of the storage units in the same column and distributed along the second direction Y at the same layer are arranged at intervals along the second direction Y and surround the same word line 40. That is, the semiconductor layers 23 of the transistors in the same column are distributed in different areas of the sidewall of the same word line 40.

[0096] In some embodiments, the transistor can further include a gate insulating layer 24 arranged between the word line 40 and the semiconductor layer 23, the gate insulating layers 24 of the transistors in the same column and at the same layer can be connected to form an integrated structure, and the gate insulating layer 24 continuously extends on the side of the word line 40 facing the bit line 30, and there is an opening on the side of the word line 40 away from the bit line 30, exposing the word line 40.

[0097] In some embodiments, the first electrode 51 of the transistor is arranged on the side of the word line 40 away from the bit line 30 and is connected with the sidewall of the semiconductor layer 23 away from the bit line 30 and perpendicular to the substrate 1.

[0098] In some embodiments, the first electrode 51 can form a ring-shaped recess, which can include a bottom wall perpendicular to the substrate 1 and two side walls parallel to the substrate 1, the bottom wall including an inner bottom wall located inside the ring-shaped recess and an outer bottom wall located outside the ring-shaped recess, and the semiconductor layer 23 is connected to a partial region of the outer bottom wall. In some embodiments, the ring-shaped recess can be a closed ring in the orthographic projection of the substrate 1.

[0099] In some embodiments, the capacitor can include a first capacitor electrode 41 and a second capacitor electrode 42, and the first electrode 51 can be multiplexed as the first capacitor electrode 41.

[0100] In some embodiments, the second capacitor electrode 42 can include a first sub-electrode 421, the first capacitor electrode 41 surrounds the first sub-electrode 421, and a first dielectric layer 431 is arranged between the first capacitor electrode 41 and the first sub-electrode 421; the first sub-electrode 421 extends along a direction perpendicular to the substrate 1 and fills the ring-shaped recess formed by the first electrode 51; and the first sub-electrode 421 of the storage unit at the same position of different layers can be connected to form an integrated structure extending along a direction perpendicular to the substrate 1. That is, the first sub-electrode 421 is arranged in the region surrounded by the first electrode 51. The scheme provided by the embodiment can form the first sub-electrode 421 of multiple capacitors through one manufacturing process, simplify the process, and reduce the cost.

[0101] In some embodiments, the first dielectric layer 431 of the capacitors at the same position of different layers can be connected to form an integrated structure. The scheme provided by the embodiment can form the first dielectric layer 431 of multiple capacitors through one manufacturing process, simplify the process, and reduce the cost.

[0102] In some embodiments, the side wall of the ring-shaped recess can include an inner side wall located inside the ring-shaped recess and an outer side wall located outside the ring-shaped recess, and the first sub-electrode 421 is also distributed on the outer side wall of the ring-shaped recess. That is, the first sub-electrode 421 can be distributed on the inner wall (including the inner bottom wall and the inner side wall) of the ring-shaped recess, and can also be distributed on the outer side wall of the ring-shaped recess, so that the facing area with the first capacitor electrode 41 can be increased as much as possible, and the capacitance of the capacitor can be increased. However, the embodiments of the present disclosure are not limited thereto, and the first sub-electrode 421 can not be distributed on the outer side wall of the ring-shaped recess.

[0103] In some embodiments, the second capacitor electrode 42 can further include a second sub-electrode 422 distributed on the outer bottom wall of the annular groove, and a second dielectric layer 432 is arranged between the first capacitor electrode 41 and the second sub-electrode 422. The scheme provided in this embodiment can further increase the capacitance of the capacitor by arranging the electrode outside the first capacitor electrode 41.

[0104] In some embodiments, the second sub-electrodes 422 of the plurality of memory cells distributed in the same layer and the same column in the second direction Y can be connected to form an integrated structure. The scheme provided in this embodiment can form the second sub-electrodes 422 of the plurality of capacitors through one manufacturing process, simplify the process, and reduce the cost.

[0105] In some embodiments, the second sub-electrode 422 can fill the area between the first capacitor electrodes 41 adjacent in the second direction Y.

[0106] In some embodiments, the second sub-electrodes 422 of the plurality of memory cells in the same position in different layers are connected. The plurality of second sub-electrodes 422 can be connected through a connection electrode 424 extending in a direction perpendicular to the substrate 1. The connection electrode 424 can be arranged in a trench extending in the second direction Y and perpendicular to the substrate 1. The connection electrode 424 can be a planar film layer extending in a direction perpendicular to the substrate 1 and the second direction Y, connecting the second sub-electrodes 422 of the plurality of memory cells in the same layer and the same column, and connecting the second sub-electrodes 422 of the plurality of memory cells in the same position in different layers.

[0107] In some embodiments, the second dielectric layers 432 of the capacitors distributed in the same layer and the same column in the second direction Y can be connected to form an integrated structure. The scheme provided in this embodiment can form the second dielectric layers 432 of the plurality of capacitors in the same layer through one manufacturing process, simplify the process, and reduce the cost.

[0108] In some embodiments, the second dielectric layers 432 of the capacitors in the same position in different layers can be disconnected, such as physically disconnected.

[0109] FIG. 1G is a schematic view of the first capacitor electrode 41 or the first electrode 51 according to some embodiments. In some embodiments, as shown in FIG. 1G, the outer bottom wall of the annular recess includes a first region 511, a second region 512, and two intermediate regions 513 and 514 respectively arranged on both sides of the first region 511 and separating the first region 511 and the second region 512, the first region 511 is located on the side of the annular recess facing the bit line 30, the word line 40 is distributed on the first region 511, and the semiconductor layer 23 is connected to part of the first region 511.

[0110] In some embodiments, the second sub-electrode 422 can be distributed on the second region 512 of the outer bottom wall of the annular recess.

[0111] In some embodiments, the second sub-electrode 422 can be connected to form an integrated structure, the first isolation layer 601 is arranged between the word line 40 and the region defined by the first capacitor electrode 41 of the two capacitors adjacent in the second direction Y. And the first isolation layer 601 in the same position of different layers can be connected to form an integrated structure extending in a direction perpendicular to the substrate 1. Under this structure, the word line can be realized without a mask, thereby reducing the mask, reducing the cost, in addition, the device can be more compact, improving the device density.

[0112] The two intermediate regions of the outer bottom wall of the annular recess and the word line 40 are respectively filled with the first isolation layer 601, and the first isolation layer 601 is also distributed on the region of the first region 511 which is not connected to the semiconductor layer 23. That is, the first intermediate region 513 and the word line 40 are filled with the first isolation layer 601, and the second intermediate region 514 and the word line 40 are filled with the first isolation layer 601. The first isolation layer 601 is connected to the word line 40, which can be connected through the opening of the gate insulating layer 24.

[0113] In some embodiments, the first isolation layer 601 is connected to the adjacent intermediate regions of the annular recess of the first capacitor electrode 41 of the capacitors of the two memory cells adjacent in the second direction Y, that is, the first isolation layer 601 is connected to the first intermediate region 513 of the first capacitor electrode 41 of one of the capacitors and the second intermediate region 514 of the first capacitor electrode 41 of the other capacitor. The first isolation layer 601 is also connected to the second dielectric layer 432.

[0114] In some embodiments, the first isolation layer 601 connects the middle regions on the same side of the outer bottom walls of the first capacitor electrodes 41 of the plurality of capacitors at the same position of different layers. That is, the first isolation layer 601 can connect the first middle regions 513 of the outer bottom walls of the first capacitor electrodes 41 of the plurality of capacitors at the same position of different layers, or connect the second middle regions 514 of the outer bottom walls of the first capacitor electrodes 41 of the plurality of capacitors at the same position of different layers.

[0115] In some embodiments, the end surface of the word line 40 connected with the first isolation layer 601 comprises a recessed region recessed towards the bit line 30.

[0116] In some embodiments, the semiconductor device can further comprise:

[0117] The insulating layer and the conductive layer are alternately distributed along the direction of the substrate 1; the conductive layer can comprise the first electrode 51;

[0118] The first hole penetrating through the insulating layer and the conductive layer; the first hole comprises a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, the second sub-hole has a groove extending along the direction parallel to the substrate 1 relative to the first sub-hole; that is, the first sub-hole in the orthographic projection of the substrate 1 falls within the orthographic projection of the second sub-hole in the substrate 1;

[0119] The first electrode 51 is distributed on the inner wall of the groove, and the first electrode 51, the first dielectric layer 431 and the first sub-electrode 421 are sequentially distributed from the outside to the inside in the first hole. The scheme provided by the present embodiment can form a plurality of first electrodes 51 at one time, form a plurality of first dielectric layers 431 of capacitors at one time, and form a plurality of first sub-electrodes 421 of capacitors at one time, thereby simplifying the process.

[0120] The technical scheme of the embodiment is further illustrated by a manufacturing process of the semiconductor device in the embodiment. The "patterning process" in the embodiment includes deposition of a film, coating of photoresist, mask exposure, development, etching, stripping of photoresist, and the like, which are mature manufacturing processes in the related art. The "lithography process" in the embodiment includes coating of a film, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can be performed by using known processes such as sputtering, evaporation, chemical vapor deposition, and the like, coating can be performed by using known coating processes, and etching can be performed by using known methods, and thus specific limitations are not made herein. In the description of the embodiment, it is to be understood that "film" refers to a film of a certain material formed on a substrate by using deposition or coating processes. If the "film" does not need to be subjected to a patterning process or a lithography process in the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be subjected to a patterning process or a lithography process in the entire manufacturing process, the "film" is referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process or the lithography process includes at least one "pattern".

[0121] In an exemplary embodiment, the manufacturing process of the semiconductor device can include:

[0122] 1) forming a bit line 30;

[0123] A substrate 1 is provided, and a first insulating film and a first sacrificial layer film are alternately deposited on the substrate 1 to form a stack structure including a plurality of first insulating layers 11 and first sacrificial layers 10 alternately arranged;

[0124] The stack structure is etched from the top layer to the bottom layer in a direction perpendicular to the substrate 1 (the etching is stopped on the substrate 1) to form a plurality of columns of second holes K2, each column can include a plurality of second holes K2 spaced apart in a second direction Y; the plurality of columns of second holes K2 can be spaced apart in a first direction X;

[0125] After the deposition of the first conductive film, the first conductive film is polished to form a bit line 30 filling the second holes K2; as shown in FIGS. 2A, 2B, and 2C. FIG. 2A is a cross-sectional view along the AA' direction after the formation of the bit line 30 according to some embodiments, FIG. 2B is a cross-sectional view along the CC' direction after the formation of the bit line 30 according to some embodiments, and FIG. 2C is a cross-sectional view along the DD' direction after the formation of the bit line 30 according to some embodiments. Only one column of second holes K2 is shown in FIGS. 2A, 2B, and 2C.

[0126] In some embodiments, the first conductive film can be one or more of the following different types of materials:

[0127] For example, the first conductive film can contain tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, and the like; the first conductive film can be an alloy containing one of the aforementioned metals;

[0128] Alternatively, it can be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), an oxide of indium (InO), a highly conductive metal oxide material such as aluminum doped zinc oxide (AZO), etc.; a metal nitride material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.

[0129] Alternatively, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0130] The materials of the second conductive film to the sixth conductive film are similar to the first conductive film, and will not be described again.

[0131] In some embodiments, the bit line 30 can include a first sub-layer 31 and a second sub-layer 32, the first sub-layer 31 can be a conductive material such as TiN, etc. that has good adhesion to other film layers, and the second sub-layer 32 can be a conductive material such as tungsten, etc. that has a low resistivity. The first sub-layer 31 covers the bottom wall and the sidewall of the second hole K2, and the second sub-layer 32 fills the second hole K2.

[0132] In some embodiments, the substrate 1 can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0133] In some embodiments, the first insulating film can be a low-K dielectric layer including but not limited to silicon oxide such as silicon dioxide (SiO2), etc., and the materials of the second insulating film to the fifth insulating film are similar, and will not be described again.

[0134] In some embodiments, the first sacrificial layer film can be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN), etc.

[0135] In some embodiments, the second hole K2 can be circular, square, etc. along a cross section parallel to the substrate 1.

[0136] 2) Forming the first capacitor electrode 41;

[0137] Depositing a second insulating film to form a second insulating layer 12, the second insulating layer 12 covers the bit line 30 and the topmost first sacrificial layer 10.

[0138] etching the stack structure from top to bottom along a direction perpendicular to the substrate 1 (stopping on the substrate 1), a plurality of first initial holes K1 are formed, which are spaced along the second direction Y; the first initial holes K1 are spaced along the first direction X from the second holes K2;

[0139] Based on the first initial holes K1, the first sacrificial layer 10 is laterally etched (i.e., etching along a direction parallel to the substrate 1), forming first lateral recesses V1, the first initial holes K1 and the first lateral recesses V1 constitute first holes, the first holes are located in the first holes located in the first sacrificial layer 10. The projection of the sub-hole on the substrate 1 falls within the projection of the sub-hole on the substrate 1;

[0140] The second conductive film and the first dummy layer film are deposited in sequence to form the first capacitor electrode 41 and the first dummy layer 9, the second conductive film covers the inner wall of the first initial hole K1 and the inner wall of the first lateral recess V1, and the first dummy layer film fills the first initial hole K1 and the first lateral recess V1;

[0141] The first capacitor electrode 41 and the first dummy layer 9 in the first initial hole K1 are etched and removed, and the first capacitor electrode 41 and the first dummy layer 9 in the first lateral recess V1 are reserved, as shown in FIGS. 3A, 3B and 3C. Among them, FIG. 3A is a cross-sectional view along the AA' direction provided by some embodiments after forming the first capacitor electrode 41, FIG. 3B is a cross-sectional view along the CC' direction provided by some embodiments after forming the first capacitor electrode 41, and FIG. 3C is a cross-sectional view along the FF' direction provided by some embodiments after forming the first capacitor electrode 41.

[0142] In some embodiments, the first dummy layer film can be a film layer such as polysilicon and first insulating film, first sacrificial layer film with etching selectivity.

[0143] In some embodiments, the first initial hole K1 can be circular, square, etc. along a cross section parallel to the substrate 1.

[0144] 3) Forming a first trench T1;

[0145] Depositing a second dummy layer film to form a second dummy layer 8 filling the first initial hole K1;

[0146] wet etching the second dummy layer film, removing a portion of the second dummy layer film on top of the first initial hole K1, depositing a third insulating film, grinding to remove the second insulating layer 12, forming a third insulating layer 13, the third insulating layer 13 being flush with the topmost first sacrificial layer 10; the third insulating layer 13 forms a top cover of the first initial hole K1, covering the second dummy layer 8, i.e. the second dummy layer 8 is covered by the third insulating layer 13 and has no connection with the first hard mask layer 7 formed subsequently.

[0147] depositing a first hard mask layer film, forming a first hard mask layer 7 covering the bit line 30, the third insulating layer 13, and the first sacrificial layer 10; the first hard mask layer 7 serves as a hard mask layer for subsequent etching.

[0148] etching the stack structure in a direction perpendicular to the substrate 1, forming a plurality of first trenches T1 penetrating through the stack structure; the first trenches T1 extend along the second direction Y and penetrate through the stack structure along the second direction Y, adjacent first trenches T1 define a group of memory cells, each group of memory cells including two columns of memory cells;

[0149] removing the first insulating layer 11 based on lateral etching of the first trenches T1, as shown in FIGS. 4A, 4B, and 4C. FIG. 4A is a cross-sectional view along the AA' direction after forming the first trenches T1 according to some embodiments, FIG. 4B is a cross-sectional view along the CC' direction after forming the first trenches T1 according to some embodiments, and FIG. 4C is a cross-sectional view along the FF' direction after forming the first trenches T1 according to some embodiments.

[0150] In some embodiments, the second dummy layer film and the first hard mask layer film can be polysilicon or the like.

[0151] 4) forming a second sacrificial layer 61;

[0152] depositing a second sacrificial layer film, the second sacrificial layer film filling the regions between adjacent first sacrificial layers 10, laterally etching the second sacrificial layer film, leaving the second sacrificial layer film between adjacent bit lines 30 along the second direction Y, forming a second sacrificial layer 61; the second sacrificial layer 61 can provide support after subsequent etching of the first sacrificial layer 10;

[0153] depositing a fourth insulating film, the fourth insulating film filling the regions between adjacent first sacrificial layers 10 and the first trenches T1, etching to remove the fourth insulating film in the first trenches T1, exposing the sidewalls of the first sacrificial layer 10 on the side facing the first trenches T1, forming a fourth insulating layer 14;

[0154] The first sacrificial layer 10 is removed by lateral etching based on the first trench T1, as shown in FIGS. 5A, 5B, 5C and 5D. FIG. 5A is a cross-sectional view along the direction AA' after forming a second sacrificial layer 61 according to some embodiments, FIG. 5B is a cross-sectional view along the direction CC' after forming the second sacrificial layer 61 according to some embodiments, FIG. 5C is a cross-sectional view along the direction DD' after forming the second sacrificial layer 61 according to some embodiments, and FIG. 5D is a cross-sectional view along the direction FF' after forming the second sacrificial layer 61 according to some embodiments.

[0155] In some embodiments, the second sacrificial layer film can be a film layer having etching selectivity with the first sacrificial layer film, the first insulating film, such as aluminum oxide, etc. The third, fourth and fifth sacrificial layer films have similar materials, and thus are not described again.

[0156] 5) forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40;

[0157] depositing a third sacrificial layer film, the third sacrificial layer film filling the regions between the adjacent fourth insulating layers 14, laterally etching the third sacrificial layer film, and retaining the third sacrificial layer film between the adjacent bit lines 30 along the second direction Y to form a third sacrificial layer 62;

[0158] The semiconductor thin film, the gate insulating thin film and the third conductive thin film are sequentially deposited, the semiconductor thin film, the gate insulating thin film and the third conductive thin film in the first trench T1 are etched and removed, the semiconductor thin film, the gate insulating thin film and the third conductive thin film are etched laterally based on the first trench T1, the semiconductor thin film, the gate insulating thin film and the third conductive thin film between the first initial holes K1 adjacent in the second direction Y are removed, and the semiconductor thin film, the gate insulating thin film and the third conductive thin film covering the side of the first capacitor electrode 41 facing the first trench T1 are reserved, the semiconductor thin film, the gate insulating thin film and the third conductive thin film covering the side of the first capacitor electrode 41 facing the bit line 30 are removed, and the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed; as shown in FIGS. 6A, 6B, 6C and 6D. FIG. 6A is a sectional view along the AA' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed according to some embodiments, FIG. 6B is a sectional view along the CC' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed according to some embodiments, FIG. 6C is a sectional view along the DD' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed according to some embodiments, and FIG. 6D is a sectional view along the EE' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed according to some embodiments. As can be seen, the semiconductor layer 23 covers the side of the first capacitor electrode 41 facing the bit line 30. At this time, the semiconductor layers 23 of the plurality of transistors in the same column are connected to each other. The etching amount of the semiconductor thin film, the gate insulating thin film and the third conductive thin film can be set as needed.

[0159] In some embodiments, the material of the semiconductor thin film can be silicon or polycrystalline silicon or the like material with a band gap less than 1.65 eV, or can be a wide band gap material such as a metal oxide material with a band gap greater than 1.65 eV.

[0160] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, and the like; and can also include other small amounts of doped elements.

[0161] In some embodiments, the material of the metal oxide semiconductor layer or channel can include one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor meets the requirements, and the specific material can be adjusted according to the actual situation.

[0162] The band gap of these materials is wide, and the leakage current is low. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0163] The material of the metal oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0164] In some embodiments, the material of the gate insulating layer 24 can include one or more layers of high-K dielectric material. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. can be included. For example, high-K materials such as, but not limited to, at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. can be included.

[0165] 6) forming a second dielectric layer 432 and a second sub-electrode 422;

[0166] A fourth sacrificial layer film is deposited to fill the area between adjacent fourth insulating layers 14; the fourth sacrificial layer film is laterally etched to leave a fourth sacrificial layer film with a predetermined width, forming a fourth sacrificial layer 63 distributed on the side of the word line 40 away from the bit line 30 and covering the area of the word line 40 not covered by the gate insulating layer 24;

[0167] Depositing a second dielectric thin film and a fourth conductive thin film in sequence, etching to remove the second dielectric thin film and the fourth conductive thin film in the first trench T1, forming a second dielectric layer 432 and a second sub-electrode 422; at this time, the fourth sacrificial layer 63 separates the second sub-electrode 422 and the word line 40; as shown in FIG. 7A, FIG. 7B, FIG. 7C. Among them, FIG. 7A is a cross-sectional view along the AA' direction after forming the second dielectric layer 432 and the second sub-electrode 422 provided by some embodiments, FIG. 7B is a cross-sectional view along the CC' direction after forming the second dielectric layer 432 and the second sub-electrode 422 provided by some embodiments, and FIG. 7C is a cross-sectional view along the EE' direction after forming the second dielectric layer 432 and the second sub-electrode 422 provided by some embodiments.

[0168] In some embodiments, the second dielectric thin film can be a High-K dielectric material. In some embodiments, it can include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, such as, but not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. High-K material. The subsequent first dielectric thin film is similar to the second dielectric thin film and will not be repeated here.

[0169] 7) forming a connection electrode 424;

[0170] Based on the lateral etching of the fourth insulating layer 14 in the first trench T1, etching to expose the fourth sacrificial layer 63 side facing the substrate 1;

[0171] Depositing a fifth sacrificial layer thin film, the fifth sacrificial layer thin film fills the area where the fourth insulating layer 14 is etched; laterally etching the fifth sacrificial layer thin film, retaining a fifth sacrificial layer thin film with a predetermined width, forming a fifth sacrificial layer 64, the fifth sacrificial layer 64 and the fourth sacrificial layer 63 are connected to form a film layer extending in a direction perpendicular to the substrate 1;

[0172] Depositing a fifth insulating thin film, etching to remove the fifth insulating thin film in the first trench T1, exposing the second sub-electrode 422 side facing the first trench T1, forming a fifth insulating layer 15; the fifth insulating layer 15 fills the area where the fourth insulating layer 14 is etched, that is, the fifth sacrificial layer 64 is formed in part of the area where the fourth insulating layer 14 is etched, and the fifth insulating layer 15 is formed in another part of the area;

[0173] Depositing a fifth conductive film to form a connecting electrode 424, which fills the first trench T1, connects the second sub-electrode 422, and connects the second sub-electrodes 422 of the capacitors in the same position of different layers, as shown in FIGS. 8A, 8B, and 8C. FIG. 8A is a cross-sectional view along the direction of AA' after forming the connecting electrode 424 according to some embodiments, FIG. 8B is a cross-sectional view along the direction of CC' after forming the connecting electrode 424 according to some embodiments, and FIG. 8C is a cross-sectional view along the direction of EE' after forming the connecting electrode 424 according to some embodiments.

[0174] 8) disconnecting the semiconductor layers 23 of different transistors in the same column;

[0175] Wet etching to remove the second and third sacrificial layers 61 and 62, and the fourth and fifth sacrificial layers 63 and 64, to form a plurality of third holes K3 and a plurality of fourth holes K4; the third hole K3 is the region formed after the second and third sacrificial layers 61 and 62 are etched, and the fourth hole K4 is the region formed after the fifth and fourth sacrificial layers 64 and 63 are etched;

[0176] Based on the third and fourth holes K3 and K4, wet etching the semiconductor layers 23 so as to disconnect the semiconductor layers 23 of a plurality of transistors in the same layer and the same column; the semiconductor layers 23 exposed in the third hole K3 can be etched away, and the semiconductor layers 23 located in the second hole K2 and adjacent to the semiconductor layers 23 located in the third hole K3 can be etched away, and the semiconductor layers 23 located in the first hole can be etched away; as shown in FIGS. 9A, 9B, and 9C. FIG. 9A is a cross-sectional view along the direction of AA' after disconnecting the semiconductor layers 23 of different transistors in the same column according to some embodiments, FIG. 9B is a cross-sectional view along the direction of CC' after disconnecting the semiconductor layers 23 of different transistors in the same column according to some embodiments, and FIG. 9C is a cross-sectional view along the direction of EE' after disconnecting the semiconductor layers 23 of different transistors in the same column according to some embodiments.

[0177] 9) forming an isolation layer 6;

[0178] After depositing the isolation layer film, polishing to form the isolation layer 6, which fills the third and fourth holes K3 and K4, and the region formed after the semiconductor layers 23 are etched in step 8;

[0179] Etching to remove the first dummy layer 9, the second dummy layer 8, and the third insulating layer 13 in the first initial hole K1 and the first lateral groove V1;

[0180] Based on the first initial hole K1 and the first lateral recess V1, the isolation layer 6, the fourth insulating layer 14, and the fifth insulating layer 15 are etched laterally to expose the inner wall of the first capacitor electrode 41, the outer wall on the side facing the substrate 1, and the outer wall on the side facing away from the substrate 1, and to form a second lateral recess between the first capacitor electrodes 41 adjacent in the direction perpendicular to the substrate 1; as shown in FIGS. 10A, 10B, and 10C. FIG. 10A is a cross-sectional view along the AA' direction after forming the isolation layer 6 according to some embodiments, FIG. 10B is a cross-sectional view along the CC' direction after forming the isolation layer 6 according to some embodiments, and FIG. 10C is a cross-sectional view along the EE' direction after forming the isolation layer 6 according to some embodiments. In this step, the first capacitor electrode 41 is exposed except for the area in contact with the semiconductor layer 23, thereby increasing the facing area of the first capacitor electrode 41 and the first sub-electrode 421 to be formed subsequently, and increasing the capacitance of the capacitor. However, the embodiments of the present disclosure are not limited thereto, for example, the outer wall of the first capacitor electrode 41 on the side facing the substrate 1 and the outer wall on the side facing away from the substrate 1 can not be exposed, that is, the first sub-electrode 421 can be distributed only on the inner wall of the first capacitor electrode 41. The isolation layer 6 includes a first isolation layer 601 and a second isolation layer 602.

[0181] In some embodiments, the isolation layer film can be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc.

[0182] 10) forming a first dielectric layer 431 and a first sub-electrode 421;

[0183] 10) forming a first dielectric layer 431 and a first sub-electrode 421;

[0184] In some embodiments, the first sub-electrode 421 can include a third sub-layer 33 and a fourth sub-layer 34. The third sub-layer 33 can be a film layer with good adhesion, such as TiN, and the fourth sub-layer 34 can be a conductive material with low resistivity, such as tungsten. The third sub-layer 33 is distributed on the bottom wall and the inner side wall of the first capacitor electrode 41, and on the outer side wall facing the substrate 1 and the outer side wall facing away from the substrate 1. The fourth sub-layer 34 fills the first initial hole K1, the first lateral groove V1, and the second lateral groove. As shown in FIGS. 11A, 11B, and 11C, FIG. 11A is a cross-sectional view of the semiconductor device along the AA' direction after forming the first dielectric layer 431 and the first sub-electrode 421, FIG. 11B is a cross-sectional view of the semiconductor device along the CC' direction after forming the first dielectric layer 431 and the first sub-electrode 421, and FIG. 11C is a cross-sectional view of the semiconductor device along the EE' direction after forming the first dielectric layer 431 and the first sub-electrode 421. In FIGS. 11A, 11B, and 11C, the first lateral groove V1 and the second lateral groove have been filled with the first dielectric layer 431, so that the first sub-electrode 421 is not distributed in the first lateral groove V1 and the second lateral groove. However, when the thickness of the first dielectric layer 431 is small and the first lateral groove V1 and the second lateral groove are not filled, the first sub-electrode 421 fills the first lateral groove V1 and the second lateral groove. That is, the first sub-electrode 421 fills the area formed by the first initial hole K1, the first lateral groove V1, and the second lateral groove with the first dielectric layer 431.

[0185] The manufacturing method of the semiconductor device provided in the embodiments only needs a mask when forming the first initial hole, the second hole, and the first groove, and does not need a mask when manufacturing the word line. Therefore, the number of masks required is small, the process is simple, and the cost is low. In addition, the manufacturing of the word line does not need a mask, so the device is not limited by the size of the mask, the size of the device can be reduced, and the storage array density can be improved. In addition, the thickness of the word line in the semiconductor device formed is small, and the parasitic capacitance between the word line and the bit line is small.

[0186] The embodiments of the present disclosure also provide an electronic device including the semiconductor device described in any of the preceding embodiments or the semiconductor device formed by the manufacturing method of the semiconductor device described in any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0187] Although the present application has been described with reference to the above embodiments, the contents described are merely employed embodiments for facilitating the understanding of the present application, and are not intended to limit the present application. Any modification and change in the form and details can be made by any person skilled in the art without departing from the spirit and scope of the present application, and the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a plurality of memory cells stacked along a vertical substrate direction at different layers; a bit line extending along a vertical direction of the substrate through the memory cells at different layers; a plurality of word lines distributed at different layers, the word lines and the bit line being distributed along a first direction parallel to the substrate, the word lines extending along a second direction parallel to the substrate, the first direction and the second direction intersecting; the memory cell comprising a transistor, the transistor comprising a semiconductor layer, the semiconductor layer surrounding the word line, a side of the semiconductor layer facing the bit line and perpendicular to the substrate being connected to the bit line, a plurality of the semiconductor layers of a plurality of transistors at the same position at different layers being connected to the same bit line.

2. The semiconductor device of claim 1, wherein, the transistor further comprising a first electrode, the first electrode being disposed at a side of the word line facing away from the bit line and connected to a side of the semiconductor layer facing away from the bit line and perpendicular to the substrate; the first electrode forming a ring-shaped recess, the ring-shaped recess comprising a bottom wall perpendicular to the substrate and two side walls parallel to the substrate, the bottom wall comprising an inner bottom wall inside the ring-shaped recess and an outer bottom wall outside the ring-shaped recess, the semiconductor layer being connected to a part of the outer bottom wall.

3. The semiconductor device of claim 2, wherein, the memory cell further comprising a capacitor, the capacitor and the transistor of the same memory cell being distributed along the first direction; the capacitor comprising a first capacitor electrode and a second capacitor electrode, the first electrode being multiplexed as the first capacitor electrode of the capacitor, the second capacitor electrode comprising a first sub-electrode, the first capacitor electrode surrounding the first sub-electrode, a first dielectric layer being disposed between the first capacitor electrode and the first sub-electrode, the first sub-electrode being distributed on an inner wall of the ring-shaped recess formed by the first electrode, the first sub-electrodes of the memory cells at the same position at different layers being connected to form an integrated structure.

4. The semiconductor device of claim 3, wherein, a side wall of the ring-shaped recess comprising an inner side wall inside the ring-shaped recess and an outer side wall outside the ring-shaped recess, the first sub-electrode being further distributed on the outer side wall of the ring-shaped recess.

5. The semiconductor device of claim 3, wherein, the outer bottom wall of the ring-shaped recess comprising a first region, a second region and two intermediate regions disposed at two sides of the first region respectively, the first region being located at a side of the ring-shaped recess facing the bit line, the word line being distributed on the first region, the semiconductor layer being connected to a part of the first region, the second capacitor electrode further comprising a second sub-electrode, the second sub-electrode being distributed on the second region of the outer bottom wall of the ring-shaped recess.

6. The semiconductor device of claim 5, wherein, a second dielectric layer being disposed between the first capacitor electrode and the second sub-electrode, the second dielectric layers of the capacitors at the same position at different layers being spaced apart along a direction perpendicular to the substrate.

7. The semiconductor device of claim 5, wherein, the memory cells at the same layer being arrayed along the first direction and the second direction, the second sub-electrodes of the memory cells at the same column and the same layer along the second direction being connected to form an integrated structure.

8. The semiconductor device of claim 5, wherein, The second sub-electrode is connected to form an integrated structure, two first capacitor electrodes adjacent in the second direction, and the area defined by the first electrode and the word line adjacent to the first electrode is filled with a first isolation layer, and the first isolation layers at the same position of different layers are connected to form an integrated structure extending in a direction perpendicular to the substrate, and the first isolation layer is connected to the middle area of the outer bottom wall of the two first capacitor electrodes adjacent in the second direction.

9. The semiconductor device of claim 8, wherein, The first isolation layer is also distributed on the area of the first region not connected to the semiconductor layer.

10. The semiconductor device of claim 5, wherein, The semiconductor device further comprises: insulating layers and conductive layers alternately distributed along the direction perpendicular to the substrate; a first hole penetrating through the insulating layer and the conductive layer; the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and the second sub-hole has a groove extending in a direction parallel to the substrate relative to the first sub-hole; The first electrode is distributed on the inner wall of the groove, and the first electrode, the first dielectric layer and the first sub-electrode are sequentially distributed from outside to inside in the first hole.

11. The semiconductor device of claim 7, wherein, The plurality of semiconductor layers of the plurality of memory cells in the same column distributed in the second direction of the same layer are arranged in the second direction and surround the same word line.

12. The semiconductor device of claim 11, wherein, Two memory cells adjacent in the first direction in each column are connected to the same bit line.

13. The semiconductor device of claim 11, wherein, The plurality of semiconductor layers of the memory cells in the same column distributed in the second direction of the same layer are respectively connected to different bit lines distributed in the second direction.

14. The semiconductor device of claim 13, wherein, The second isolation layer penetrating through the memory cells of different layers and extending along the direction perpendicular to the substrate is arranged between different bit lines distributed in the second direction.

15. A semiconductor device manufacturing method, comprising: forming a stack structure comprising alternately arranged first insulating layers and first sacrificial layers on a substrate; forming a plurality of second holes spaced apart in the second direction penetrating through the stack structure in a direction perpendicular to the substrate, and a plurality of bit lines filling the plurality of second holes; forming a plurality of first holes spaced apart in the second direction penetrating through the stack structure in a direction perpendicular to the substrate, and the first holes are spaced apart in the first direction from the second holes, based on etching the first sacrificial layer in a direction parallel to the substrate based on the first holes, forming a first lateral groove; forming a first electrode distributed on the inner wall of the first lateral groove; the first direction and the second direction intersect; forming a first trench penetrating through the stack structure and extending in the second direction on the side of the first hole away from the second hole; based on the first trench, forming a word line extending in the second direction between adjacent fourth insulating layers and between a plurality of first holes and a plurality of second holes, and a plurality of semiconductor layers spaced apart in the second direction surrounding the word line, the semiconductor layers are respectively connected to the first electrode and the bit line.

16. The method of manufacturing a semiconductor device according to claim 15, wherein based on the first trench, forming a word line extending in the second direction between adjacent fourth insulating layers and between a plurality of first holes and a plurality of second holes, and a plurality of semiconductor layers spaced apart in the second direction surrounding the word line comprises: etching the first trench based on the first trench, the first insulating layer is removed, the first insulating layer is replaced by a fourth insulating layer and a second sacrificial layer, the second sacrificial layer is located between adjacent first sacrificial layers, and is located between adjacent bit lines along the second direction, and connects adjacent bit lines along the second direction; etching the first trench based on the first trench, the first insulating layer is removed, the first insulating layer is replaced by a fourth insulating layer and a second sacrificial layer, the second sacrificial layer is located between adjacent first sacrificial layers, and is located between adjacent bit lines along the second direction, and connects adjacent bit lines along the second direction; sequentially depositing a semiconductor thin film, a gate insulating thin film and a first conductive thin film, etching and removing the semiconductor thin film, the gate insulating thin film and the first conductive thin film covering the first electrode away from the bit line side, the first electrode towards the side of the first electrode adjacent along the second direction, retaining the semiconductor thin film, the gate insulating thin film and the first conductive thin film covering the first electrode towards the bit line side, forming a plurality of semiconductor layers and a plurality of gate insulating layers of a plurality of transistors, and a word line, the gate insulating layer surrounding the word line, and the semiconductor layer surrounding the gate insulating layer; forming a fourth sacrificial layer connecting the word line and the first electrode adjacent along the second direction between adjacent fourth insulating layers; forming a fifth sacrificial layer connected with the fourth sacrificial layer between the fourth sacrificial layers adjacent along the direction perpendicular to the substrate direction; etching and removing the second sacrificial layer and the third sacrificial layer to form a third hole; etching and removing the fourth sacrificial layer and the fifth sacrificial layer to form a fourth hole; based on the third hole and the fourth hole, etching the plurality of semiconductor layers along the direction parallel to the substrate direction, so that the plurality of semiconductor layers are disconnected.

17. The method of manufacturing a semiconductor device according to claim 16, further comprising: exposing the first hole and the first lateral recess, and forming a first sub-electrode in the first hole and the first lateral recess.

18. The semiconductor device manufacturing method according to claim 17, wherein, before forming the first sub-electrode in the first hole and the first lateral recess, further comprising: exposing the first electrode away from the substrate side and towards the substrate side, and forming a second lateral recess; forming the first sub-electrode in the first hole, the first lateral recess, and the second lateral recess.

19. The method of manufacturing a semiconductor device according to Claim 16, wherein after forming the fourth sacrificial layer connecting the word line and the first electrode adjacent along the second direction between adjacent fourth insulating layers, and before forming the fifth sacrificial layer connected with the fourth sacrificial layer between the fourth sacrificial layers adjacent along the direction perpendicular to the substrate direction, further comprising: forming a second sub-electrode distributed on the first electrode away from the bit line side; after forming the fifth sacrificial layer connected with the fourth sacrificial layer between the fourth sacrificial layers adjacent along the direction perpendicular to the substrate direction, further comprising: forming a connection electrode filling the first trench and connected with the second sub-electrode.

20. An electronic device comprising the semiconductor device according to any one of claims 1 to 14, or a semiconductor device formed according to the semiconductor device manufacturing method according to any one of claims 15 to 19.

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