Pixel driving circuit and display apparatus

Abstract

A pixel driving circuit and a display apparatus. The pixel driving circuit comprises: a first transistor (T1), which switches a current path between a reference voltage signal (Vref) and a second node (N2) in response to a first scan signal (Sn1); a second transistor (T2), which switches a current path between a third node (N3) and a first node (N1); a third transistor (T3), which switches a current path between a data signal (Data) and the second node (N2) in response to a third scan signal (Sn3); a fourth transistor (T4), which switches a current path between a positive electrode of a power supply and the first node (N1); a fifth transistor (T5), which switches a current path between the third node (N3) and an anode (Anode) of a light-emitting diode (E), wherein a cathode of the light-emitting diode (E) is connected to a negative electrode of the power supply; a sixth transistor (T6), which switches a current path between the anode (Anode) of the light-emitting diode (E) and an initialization voltage (Vint) in response to a second scan signal (Sn2); a first voltage-stabilizing capacitor (C1), which stabilizes the voltage at the third node (N3); and a storage capacitor (Cst), which is used for storing a fixed voltage delivered to a gate electrode of the second transistor (T2). The display non-uniformity between different pixels can be compensated for, thereby improving the display quality.

Description

Pixel driving circuit and display device Technical Field

[0001] This invention relates to the field of OLED devices, and particularly to pixel driving circuits and display devices. Background Technology

[0002] Recently, various flat panel displays, including liquid crystal displays, field emission displays, plasma display panels, and organic light-emitting displays, have been developed that have a smaller weight and volume compared to cathode ray tube displays.

[0003] In flat panel displays, organic light-emitting displays (OLEDs) use organic light-emitting diodes (OLEDs) to display images, which generate light through the recombination of electrons and holes. OLEDs have a fast response time and are driven with low power consumption. A typical OLED uses transistors formed in pixels to supply current to the OLED light-emitting device according to a data signal, thereby causing the OLED light-emitting device to emit light.

[0004] Organic light-emitting displays can be classified into passive-matrix OLED (PMOLED) and active-matrix OLED (AMOLED) based on their driving type. Passive-matrix OLEDs do not use thin-film transistor substrates, while active-matrix OLEDs do.

[0005] Each pixel in an actively driven organic light-emitting diode (OLED) display is equipped with a low-temperature polycrystalline silicon thin-film transistor (LTS) that functions as a switch, and each pixel also has a storage capacitor. The peripheral driving circuitry and display components are integrated on the same glass substrate. Each pixel generates a driving current based on a data signal, and the brightness of the organic light-emitting diode is controlled by adjusting the driving current of the OLED light-emitting device. Due to inevitable fluctuations in the manufacturing process, the threshold voltages of the driving transistors in different pixel circuits differ, which can easily lead to uneven display.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this invention, and therefore may contain information that is unknown to those skilled in the art and does not constitute prior art.

[0007] Summary of the Invention

[0008] In view of the problems in the prior art, the purpose of the present invention is to provide a pixel driving circuit and display device, which overcomes the difficulties of the prior art, can compensate for the differences between different pixels due to threshold voltage, improve the display unevenness caused by process fluctuations, and improve the display quality.

[0009] An embodiment of the present invention provides a pixel driving circuit, comprising:

[0010] The first transistor is used to switch the current path between the reference voltage signal and the second node in response to the voltage signal of the first scan signal.

[0011] The second transistor is used to switch the current path between the third node and the first node in response to the voltage signal of the second node;

[0012] The third transistor is used to switch the current path between the data signal and the second node in response to the voltage signal of the third scan signal.

[0013] The fourth transistor is used to switch the current path between the positive power supply voltage signal and the first node in response to the voltage signal of the second enable signal.

[0014] The fifth transistor is used to switch the current path between the third node and the anode of the light-emitting diode in response to the voltage signal of the first enable signal, wherein the cathode of the light-emitting diode is connected to the negative voltage signal of the power supply.

[0015] The sixth transistor is used to switch the current path between the anode and the initialization voltage of the light-emitting diode in response to the voltage signal of the second scan signal; and

[0016] A first voltage-regulating capacitor is connected to the third node and the positive voltage signal of the power supply to regulate the voltage of the third node; and

[0017] A storage capacitor, connecting the second node and the third node, is used to store a fixed voltage supplied to the gate of the second transistor.

[0018] In some embodiments, the first end of the first voltage regulator capacitor is connected to the third node, and the second end is connected to the positive voltage signal of the power supply.

[0019] In some embodiments, the waveforms of the first scan signal and the second scan signal are the same.

[0020] In some embodiments, the first end of the first voltage-stabilizing capacitor is connected to the third node, and the second end is connected to the initialization voltage.

[0021] In some embodiments, at least one of the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor has a back gate, and the at least one back gate is connected to the gate of the transistor.

[0022] In some embodiments, at least one of the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor has a back gate, and at least one of the back gates is connected to one of the power supply positive voltage, initialization voltage, and power supply negative voltage signal.

[0023] In some embodiments, the frame period of the first enable signal includes an early first low level and a later first high level, with a first high level during the first low level period;

[0024] The frame period of the second enable signal includes an early second low level and a later second high level. The second low level is time-aligned with the first low level, and the second high level is time-aligned with the first high level. A second high level is provided during the second low level period, and the second high level is located after the timing of the first high level.

[0025] The first scan signal is a first pulse signal, the rising edge of the first pulse signal is aligned with the rising edge of the first high level, and the falling edge of the first pulse signal is aligned with the falling edge of the second high level.

[0026] The second scan signal is a second pulse signal, the rising edge of the second pulse signal is aligned with the rising edge of the first high level, and the falling edge of the second pulse signal is aligned with the falling edge of the first high level.

[0027] The third scan signal is a third pulse signal, wherein the rising edge of the third pulse signal is after the falling edge of the first pulse signal, and the falling edge of the third pulse signal is before the rising edge of the first high level.

[0028] Preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all N-type thin-film transistors.

[0029] Embodiments of the present invention provide another pixel driving circuit, comprising:

[0030] The first transistor is used to switch the current path between the reference voltage signal and the second node in response to the voltage signal of the first scan signal.

[0031] The second transistor is used to switch the current path between the third node and the first node in response to the voltage signal of the second node;

[0032] The third transistor is used to switch the current path between the data signal and the second node in response to the voltage signal of the third scan signal.

[0033] The fourth transistor is used to switch the current path between the positive power supply voltage signal and the first node in response to the voltage signal of the first enable signal.

[0034] The fifth transistor is used to switch the current path between the third node and the anode of the light-emitting diode in response to the voltage signal of the first enable signal, wherein the cathode of the light-emitting diode is connected to the negative voltage signal of the power supply.

[0035] The sixth transistor is used to switch the current path between the third node and the initialization voltage in response to the voltage signal of the second scan signal; and

[0036] A first voltage-regulating capacitor is connected to the third node and the positive voltage signal of the power supply to regulate the voltage of the third node; and

[0037] A storage capacitor, connecting the second node and the third node, is used to store a fixed voltage supplied to the gate of the second transistor.

[0038] Preferably, the waveforms of the first scan signal and the second scan signal are the same.

[0039] Embodiments of the present invention provide yet another pixel driving circuit, comprising:

[0040] The first transistor is used to switch the current path between the reference voltage signal and the second node in response to the voltage signal of the first scan signal.

[0041] The second transistor is used to switch the current path between the third node and the first node in response to the voltage signal of the second node;

[0042] The third transistor is used to switch the current path between the data signal and the second node in response to the voltage signal of the third scan signal.

[0043] The fourth transistor is used to switch the current path between the positive power supply voltage signal and the first node in response to the voltage signal of the first enable signal.

[0044] The fifth transistor is used to switch the current path between the third node and the anode of the light-emitting diode in response to the voltage signal of the first enable signal, wherein the cathode of the light-emitting diode is connected to the negative voltage signal of the power supply.

[0045] The sixth transistor is used to switch the current path between the anode and the initialization voltage of the light-emitting diode in response to the voltage signal of the second scan signal;

[0046] The seventh transistor is used to switch the current path between the charging voltage and the first node in response to the voltage signal of the second enable signal; and

[0047] A first voltage-regulating capacitor is connected to the third node and the positive voltage signal of the power supply to regulate the voltage of the third node; and

[0048] A storage capacitor, connecting the second node and the third node, is used to store a fixed voltage supplied to the gate of the second transistor.

[0049] Embodiments of the present invention also provide a display device, including: a pixel driving circuit as described above.

[0050] This invention can compensate for differences in threshold voltage between different pixels, improve display unevenness caused by process fluctuations, and enhance display quality. Based on common knowledge in the field, the above-mentioned preferred conditions can be arbitrarily combined to obtain various preferred embodiments of this invention. Attached Figure Description

[0051] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0052] Figure 1 is a circuit diagram of the pixel driving circuit according to the first embodiment of the present invention.

[0053] Figure 2 is a timing diagram of the pixel driving circuit of the first embodiment of the present invention.

[0054] Figure 3 is a schematic diagram of the conduction state of the pixel driving circuit under the first timing of the first embodiment of the present invention.

[0055] Figure 4 is a timing diagram of the pixel driving circuit of the first embodiment of the present invention under the first timing condition.

[0056] Figure 5 is a schematic diagram of the conduction state of the pixel driving circuit under the second timing according to the first embodiment of the present invention.

[0057] Figure 6 is a timing diagram of the pixel driving circuit of the first embodiment of the present invention under the second timing.

[0058] Figure 7 is a schematic diagram of the conduction state of the pixel driving circuit under the third timing of the first embodiment of the present invention.

[0059] Figure 8 is a timing diagram of the pixel driving circuit of the first embodiment of the present invention under the third timing.

[0060] Figure 9 is a schematic diagram of the conduction state of the pixel driving circuit in the fourth timing of the first embodiment of the present invention.

[0061] Figure 10 is a timing diagram of the pixel driving circuit of the first embodiment of the present invention under the fourth timing.

[0062] Figure 11 is a preferred timing diagram of the pixel driving circuit according to the second embodiment of the present invention.

[0063] Figure 12 is a preferred timing diagram of the pixel driving circuit according to the third embodiment of the present invention.

[0064] Figure 13 is a circuit diagram of the pixel driving circuit according to the fourth embodiment of the present invention.

[0065] Figure 14 is a timing diagram of the pixel driving circuit according to the fourth embodiment of the present invention.

[0066] Figure 15 is a circuit diagram of the pixel driving circuit according to the fifth embodiment of the present invention.

[0067] Figure 16 is a circuit diagram of the pixel driving circuit according to the sixth embodiment of the present invention.

[0068] Figure 17 is a circuit diagram of the pixel driving circuit of the seventh embodiment of the present invention.

[0069] Figure 18 is a circuit diagram of the pixel driving circuit of the eighth embodiment of the present invention.

[0070] Figure 19 is a circuit diagram of the pixel driving circuit of the ninth embodiment of the present invention. Detailed Implementation

[0071] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0072] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0073] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0074] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0075] For the purpose of clearly describing this application, devices that are not relevant to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0076] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0077] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0078] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of a feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

[0079] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0080] Figure 1 is a circuit diagram of the pixel driving circuit according to the first embodiment of the present invention. Figure 2 is a timing diagram of the pixel driving circuit according to the first embodiment of the present invention. As shown in Figures 1 and 2, the present invention provides a pixel driving circuit, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first voltage regulating capacitor C1, and a storage capacitor Cst. The first transistor T1 is used to switch the current path between the reference voltage signal Vref and the second node N2 in response to the voltage signal of the first scan signal Sn1. The second transistor T2 is used to switch the current path between the third node N3 and the first node N1 in response to the voltage signal of the second node N2. The third transistor T3 is used to switch the current path between the data signal Data and the second node N2 in response to the voltage signal of the third scan signal Sn3. The fourth transistor T4 is used to switch the current path between the positive power supply voltage signal ELVDD and the first node N1 in response to the voltage signal of the second enable signal En2. The fifth transistor T5 responds to the voltage signal of the first enable signal En1, switching the current path between the third node N3 and the anode of the light-emitting diode E. The cathode of the light-emitting diode E is connected to the negative power supply voltage signal ELVSS. The sixth transistor T6 responds to the voltage signal of the second scan signal Sn2, switching the current path between the anode of the light-emitting diode E and the initialization voltage Vint. The storage capacitor Cst connects the second node N2 and the third node N3, storing the fixed voltage (i.e., the positive power supply voltage signal ELVDD) supplied to the gate of the second transistor T2. The first voltage regulator capacitor C1 connects the third node N3 and the positive power supply voltage signal ELVDD, regulating the voltage of the third node N3. This invention can be applied to OLED self-emissive pixel circuits composed of N-type TFTs, achieving compensation for the Vth of the second transistor T2 (driving transistor), eliminating display unevenness caused by Vth fluctuations between different pixels.

[0081] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all N-type thin-film transistors, but are not limited thereto.

[0082] In an alternative embodiment, referring to FIG2, the frame period of the first enable signal En1 includes an early first low level and a later first high level, with a first high level during the first low level period.

[0083] The frame period of the second enable signal En2 includes an early second low level and a later second high level. The second low level is time-aligned with the first low level, and the second high level is time-aligned with the first high level. A second high level is provided during the second low level period, and the second high level is located after the first high level.

[0084] The first scan signal Sn1 is a first pulse signal. The rising edge of the first pulse signal is aligned with the rising edge of the first high level, and the falling edge of the first pulse signal is aligned with the falling edge of the second high level.

[0085] The second scan signal Sn2 is a second pulse signal. The rising edge of the second pulse signal is aligned with the rising edge of the first high level, and the falling edge of the second pulse signal is aligned with the falling edge of the first high level.

[0086] The third scan signal Sn3 is a third pulse signal. The rising edge of the third pulse signal is after the falling edge of the first pulse signal, and the falling edge of the third pulse signal is before the rising edge of the first high level.

[0087] In one alternative embodiment, the first terminal of the first voltage-regulating capacitor C1 is connected to the third node N3, and the second terminal is connected to the positive voltage signal ELVDD of the power supply to regulate the voltage of the third node N3, but this is not a limitation.

[0088] The following uses Figures 3 to 10 to specifically illustrate the transmission relationship of the conduction states of each transistor in the pixel driving circuit under different timing sequences within a frame period, to introduce the specific implementation of the present invention: Figure 3 is a schematic diagram of the conduction states of the pixel driving circuit under the first timing sequence of the first embodiment of the present invention. Figure 4 is a timing diagram of the pixel driving circuit under the first timing sequence of the first embodiment of the present invention. As shown in Figures 3 and 4, taking the same frame period as an example, in the first timing sequence F1, the first scan signal Sn1 is at a high level, the second scan signal Sn2 is at a high level, the third scan signal Sn3 is at a low level, the first enable signal En1 is at a high level, and the second enable signal En2 is at a low level. At this time, after the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, the second node N2 = Vref, and the voltage of the first node N1 = the voltage of the third node N3 = the voltage of the anode Anode = the initialization voltage Vint, so that the second transistor T2 is turned on, the Vint signal resets the anode potential, and the anode charge is discharged through T7. (Transistors T1, T2, T5, and T6 are turned on; transistors T3 and T4 are turned off.) The light-emitting diode E is an OLED device and has its own capacitance, storing the anode potential and charge from the previous frame. Releasing these charges helps to ensure a consistent brightness trend during brightness transitions. The Vref signal is relatively positive to ensure the OLED device does not light up at this time.

[0089] Figure 5 is a schematic diagram of the conduction state of the pixel driving circuit under the second timing sequence of the first embodiment of the present invention. Figure 6 is a timing diagram of the pixel driving circuit under the second timing sequence of the first embodiment of the present invention. As shown in Figures 5 and 6, taking the same frame period as an example, in the second timing sequence F2, the first scan signal Sn1 is high, the second scan signal Sn2 is low, the third scan signal Sn3 is low, and the first enable signal En1 is low, causing the fifth transistor T5 to be turned off. The second enable signal En2 is high, and the fourth transistor T4 is turned on. The second node N2 = Vref, and the first node N1 = ELVDD. The third node N3 = Vref - Vth - T2. The anode Anode = initialization voltage Vint. At this time, Vgs of T2 = Vth, and Vth of T2 is compensated. (The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, and the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off.)

[0090] Figure 7 is a schematic diagram of the conduction state of the pixel driving circuit in the third timing sequence of the first embodiment of the present invention. Figure 8 is a timing diagram of the pixel driving circuit in the third timing sequence of the first embodiment of the present invention. As shown in Figures 7 and 8, taking the same frame period as an example, in the third timing sequence F3, the first scan signal Sn1 and the second scan signal Sn2 are both low level, and the first transistor T1 and the sixth transistor T6 are turned off. The third scan signal Sn3 is high level, and the third transistor T3 is turned on. The first enable signal En1 is low level, and the second enable signal En2 is low level. At this time, the second node N2 = Data, and ΔV(N2) = Data - Vref.

[0091] The third node N3 = Vref_T2 - Vth_T2 + (Data - Vref) * Cst / (Cst + C1).

[0092] Anode = Vint.

[0093] Vgs_T2 of T2 = [1-Cst / (Cst+C1)]*(Data-Vref)+Vth_T2. (The second transistor T2 and the third transistor T3 are turned on, while the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.)

[0094] Figure 9 is a schematic diagram of the conduction state of the pixel driving circuit in the fourth timing sequence of the first embodiment of the present invention. Figure 10 is a timing diagram of the pixel driving circuit in the fourth timing sequence of the first embodiment of the present invention. As shown in Figures 9 and 10, taking the same frame period as an example, in the third timing sequence F4, the first scan signal Sn1 and the second scan signal Sn2 are both at low level, the third scan signal Sn3 is at high level, and the third transistor T3 is turned off. The first enable signal En1 and the second enable signal En2 are both at high level, and light emission begins.

[0095] The third node N3 = Anode = ELVSS + Voled.

[0096] △V(N3)=ELVSS+Voled-Vref+Vth_T2-(Data-Vref)*Cst / (Cst+C1).

[0097] The second node N2 = Data + △V(N3)

[0098] =ELVSS+Voled+[1-Cst / (Cst+C1)]*(Data-Vref)+Vth_T2

[0099] At this point, Vgs_T2 of T2 = [1-Cst / (Cst+C1)]*(Data-Vref)+Vth_T2

[0100] Furthermore, the current flowing through the light-emitting diode E during the light-emitting stage is:

[0101] Ioled=1 / 2Cox·W / L·μ[1-Cst / (Cst+C1)] 2 ×(Data-Vref) 2

[0102] (The second transistor T2, the fourth transistor T4, and the fifth transistor T5 are turned on, while the first transistor T1, the third transistor T3, and the sixth transistor T6 are turned off.)

[0103] Figure 11 is an optional timing diagram of the pixel driving circuit according to the second embodiment of the present invention. As shown in Figure 11, the difference between the second embodiment and the first embodiment is that the timing of the second scanning signal Sn2 can be adjusted to improve the release capability and degree of residual charge on the anode node in one frame. As shown by the dashed line in Figure 12, the high-level time of the second scanning signal Sn2 can be adjusted to increase or decrease. The timing principle is the same as described above, but it is not limited thereto.

[0104] Figure 12 is an optional timing diagram of the pixel driving circuit according to the third embodiment of the present invention. As shown in Figure 12, the difference between the third embodiment and the first embodiment is that the second scanning signal Sn2 can be high-level multiple times within a frame, causing the sixth transistor T6 to conduct in order to reset the anode. Because the anode potential is reset multiple times within a frame, the anode potential is continuously pulled low and reset. Each time light is emitted, it needs to reach the emission potential again. Optically, this is manifested as cutting off the continuous change trend of brightness, achieving a dimming effect, but it is not limited to this.

[0105] Figure 13 is a circuit diagram of the pixel driving circuit according to the fourth embodiment of the present invention. Figure 14 is a timing diagram of the pixel driving circuit according to the fourth embodiment of the present invention. As shown in Figures 13 and 14, the difference between the fourth embodiment and the first embodiment is that Sn1 and Sn2 can also be combined into a single control signal (i.e., the first scan signal Sn1 signal is equal to the second scan signal Sn2, as shown in 1 and 3). This reduces one signal line and a set of gate driving circuits, thereby reducing the bezel width and facilitating the implementation of narrow bezel mobile phone panels, but is not a limitation thereof.

[0106] Figure 15 is a circuit diagram of the pixel driving circuit of the fifth embodiment of the present invention. As shown in Figure 15, the difference between the fifth embodiment and the fourth embodiment of the present invention is that the first terminal of the first voltage regulator capacitor C1 is connected to the third node N3, and the second terminal is connected to a fixed voltage signal such as the initialization voltage Vint (or ELVSS), but this is not a limitation.

[0107] Figure 16 is a circuit diagram of the pixel driving circuit according to the sixth embodiment of the present invention. As shown in Figure 16, the difference between the sixth embodiment and the fourth embodiment is that at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 has a back gate. This back gate is connected to the gate of the transistor, or at least one back gate is connected to one of the positive power supply voltage ELVDD, the initialization voltage Vint, and the negative power supply voltage signal ELVSS. In this embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 has a back gate, with a portion of the back gate connected to the gate of the transistor, and the remaining back gates connected to one of the positive power supply voltage ELVDD, the initialization voltage Vint, and the negative power supply voltage signal ELVSS. In the pixel circuit of the present invention, all TFTs can have a back gate added. The back gate can be connected to a fixed voltage signal such as ELVDD, Vint, or ELVSS, or to the top gate, thereby transmitting the same voltage signal, but this is not a limitation.

[0108] Figure 17 is a circuit diagram of the pixel driving circuit according to the seventh embodiment of the present invention. As shown in Figure 17, the pixel driving circuit of the seventh embodiment of the present invention includes: a first transistor T1, used to switch the current path between the reference voltage signal Vref and the second node N2 in response to the voltage signal of the first scan signal Sn; a second transistor T2, used to switch the current path between the third node N3 and the first node N1 in response to the voltage signal of the second node N2; a third transistor T3, used to switch the current path between the data signal Data and the second node N2 in response to the voltage signal of the third scan signal Sn3; a fourth transistor T4, used to switch the current path between the positive power supply voltage signal ELVDD and the first node N1 in response to the voltage signal of the first enable signal En1; a fifth transistor T5, used to switch the current path between the third node N3 and the anode of the light-emitting diode E in response to the voltage signal of the first enable signal En1, wherein the cathode of the light-emitting diode E is connected to the negative power supply voltage signal ELVSS; and a sixth transistor T6, used to switch the current path between the third node N3 and the initialization voltage Vint in response to the voltage signal of the second scan signal Sn2. A storage capacitor Cst, connected to the second node N2 and the third node N3, is used to store the fixed voltage supplied to the gate of the second transistor T2. A first voltage-regulating capacitor C1, with its first terminal connected to the third node N3 and its second terminal connected to the positive power supply voltage signal ELVDD, regulates the voltage at the third node N3. When the first enable signal En1 is high, the fifth transistor T5 is turned on, and the anode charge is discharged, achieving the same effect as in the circuit diagram of Figure 1.

[0109] Figure 18 is a circuit diagram of the pixel driving circuit of the eighth embodiment of the present invention. As shown in Figure 18, the difference between the eighth embodiment and the seventh embodiment is that Sn1 and Sn2 can also be combined into a single control signal (i.e., the first scan signal Sn1 signal in 1 and 3 is equal to the second scan signal Sn2). This reduces one signal line and a set of gate driving circuits, thereby reducing the bezel width and making it more advantageous for achieving narrow bezel mobile phone panels, but it is not a limitation thereto.

[0110] Figure 19 is a circuit diagram of the pixel driving circuit according to the ninth embodiment of the present invention. As shown in Figure 19, the pixel driving circuit of the ninth embodiment of the present invention includes: a first transistor T1, used to switch the current path between the reference voltage signal Vref and the second node N2 in response to the voltage signal of the first scan signal Sn; a second transistor T2, used to switch the current path between the third node N3 and the first node N1 in response to the voltage signal of the second node N2; a third transistor T3, used to switch the current path between the data signal Data and the second node N2 in response to the voltage signal of the third scan signal Sn3; a fourth transistor T4, used to switch the current path between the positive power supply voltage signal ELVDD and the first node N1 in response to the voltage signal of the first enable signal En1; a fifth transistor T5, used to switch the current path between the third node N3 and the anode of the light-emitting diode E in response to the voltage signal of the first enable signal En1, wherein the cathode of the light-emitting diode E is connected to the negative power supply voltage signal ELVSS; and a sixth transistor T6, used to switch the current path between the anode of the light-emitting diode E and the initialization voltage Vint in response to the voltage signal of the second scan signal Sn2. The seventh transistor T7 is used to switch the current path between the charging voltage Vcharge and the first node N1 in response to the voltage signal of the second enable signal En2. The storage capacitor Cst, connected to the second node N2 and the third node N3, is used to store the fixed voltage supplied to the gate of the second transistor T2. The first voltage regulator capacitor C1, with its first terminal connected to the third node N3 and its second terminal connected to the positive power supply voltage signal ELVDD, regulates the voltage at the third node N3.

[0111] In this embodiment, a seventh transistor T7, controlled by the second enable signal En2, is added, and the gate control signal of the fourth transistor T4 is changed from En2 to En1. ELVDD, as the positive signal of the light-emitting circuit, generates a resistive voltage drop (IR drop) within the panel when light is emitted. IR drop causes a decrease in the ELVDD voltage from the near-IC end to the far-IC end of the panel; a situation may occur where some rows are emitting light while others are compensating. When the IR drop is large, it may affect the uniformity of compensation. Adding T7 and the charging voltage Vcharge signal, used only for compensation and not involved in light emission, can improve the uniformity of compensation.

[0112] This embodiment also provides a display device, such as an OLED panel, including the pixel driving circuit described above. The display device of the present invention incorporates the structural features, techniques, and effects of the pixel driving circuit described above, which will not be repeated here.

[0113] In summary, the present invention can compensate for the differences in threshold voltage between different pixels, improve the display unevenness caused by process fluctuations, and improve display quality.

[0114] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A pixel driving circuit, characterized by comprising: The application relates to a display device, comprising: a first transistor (T1) for switching a current path between a reference voltage signal (Vref) and a second node (N2) in response to a voltage signal of a first scan signal (Sn1); a second transistor (T2) for switching a current path between a third node (N3) and a first node (N1) in response to a voltage signal of the second node (N2); a third transistor (T3) for switching a current path between a data signal (Data) and the second node (N2) in response to a voltage signal of a third scan signal (Sn3); a fourth transistor (T4) for switching a current path between a power supply positive voltage signal (ELVDD) and the first node (N1) in response to a voltage signal of a second enable signal (En2); a fifth transistor (T5) for switching a current path between the third node (N3) and an anode of a light emitting diode (E) in response to a voltage signal of a first enable signal (En1), a cathode of the light emitting diode (E) being connected to a power supply negative voltage signal (ELVSS); a sixth transistor (T6) for switching a current path between the anode of the light emitting diode (E) and an initialization voltage (Vint) in response to a voltage signal of a second scan signal (Sn2); a first voltage stabilizing capacitor (C1) connected between the third node (N3) and the power supply positive voltage signal (ELVDD) for stabilizing the voltage of the third node (N3); and a storage capacitor (Cst) connected between the second node (N2) and the third node (N3) for storing a fixed voltage supplied to a gate of the second transistor (T2). The first scan signal (Sn1) has the same waveform as the second scan signal (Sn2).

2. The pixel driving circuit according to claim 1, wherein A first end of the first voltage stabilizing capacitor (C1) is connected to the third node (N3), and a second end is connected to the initialization voltage (Vint).

3. The pixel driving circuit of claim 1, wherein, At least one of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5) and the sixth transistor (T6) is provided with a back gate, and at least one of the back gates is connected to a gate of the transistor.

4. The pixel driving circuit of claim 1, wherein, At least one of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5) and the sixth transistor (T6) is provided with a back gate, and at least one of the back gates is connected to one of the power supply positive voltage (ELVDD), the initialization voltage (Vint) and the power supply negative voltage signal (ELVSS).

5. The pixel driving circuit of claim 1, wherein, The first enable signal (En1) comprises a first low level in an early stage and a first high level in a later stage in a frame period, and the first low level has a first high level.

6. The pixel driving circuit of claim 1, wherein, ​ The frame period of the second enable signal (En2) includes a previous second low level and a subsequent second high level, the second low level is time-aligned with the first low level, the second high level is time-aligned with the first high level, and a second high level is provided in the second low level, and the second high level is time-later than the first high level; The first scan signal (Sn1) is a first pulse signal, the rising edge of the first pulse signal is time-aligned with the rising edge of the first high level, and the falling edge of the first pulse signal is time-aligned with the falling edge of the second high level; The second scan signal (Sn2) is a second pulse signal, the rising edge of the second pulse signal is time-aligned with the rising edge of the first high level, and the falling edge of the second pulse signal is time-aligned with the falling edge of the first high level; The third scan signal (Sn3) is a third pulse signal, the rising edge of the third pulse signal is time-later than the falling edge of the first pulse signal, and the falling edge of the third pulse signal is time-earlier than the rising edge of the first high level.

7. The pixel driving circuit of claim 1, wherein, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) are N-type thin film transistors.

8. A pixel driving circuit, characterized by comprising: Comprising: The first transistor (T1) is configured to switch a current path between a reference voltage signal (Vref) and a second node (N2) in response to a voltage signal of a first scan signal (Sn); The second transistor (T2) is configured to switch a current path between a third node (N3) and a first node (N1) in response to a voltage signal of the second node (N2); The third transistor (T3) is configured to switch a current path between a data signal (Data) and the second node (N2) in response to a voltage signal of a third scan signal (Sn3); The fourth transistor (T4) is configured to switch a current path between a power supply positive voltage signal (ELVDD) and the first node (N1) in response to a voltage signal of a first enable signal (En1); The fifth transistor (T5) is configured to switch a current path between the third node (N3) and an anode of a light emitting diode (E) in response to a voltage signal of the first enable signal (En1), a cathode of the light emitting diode (E) being connected to a power supply negative voltage signal (ELVSS); The sixth transistor (T6) is configured to switch a current path between the third node (N3) and an initialization voltage (Vint) in response to a voltage signal of a second scan signal (Sn2); The first voltage stabilizing capacitor (C1) is connected between the third node (N3) and the power supply positive voltage signal (ELVDD) and is configured to stabilize the voltage of the third node (N3); And The storage capacitor (Cst) is connected between the second node (N2) and the third node (N3) and is configured to store a fixed voltage to be supplied to a gate of the second transistor (T2). The first scan signal (Sn1) and the second scan signal (Sn2) have the same waveform.

9. The pixel driving circuit of claim 8, wherein, Comprising:

10. A pixel driving circuit, characterized by comprising: ​ a first transistor (T1) for switching a current path between a reference voltage signal (Vref) and a second node (N2) in response to a voltage signal of a first scan signal (Sn); a second transistor (T2) for switching a current path between a third node (N3) and a first node (N1) in response to a voltage signal of the second node (N2); a third transistor (T3) for switching a current path between a data signal (Data) and the second node (N2) in response to a voltage signal of a third scan signal (Sn3); a fourth transistor (T4) for switching a current path between a power supply positive voltage signal (ELVDD) and the first node (N1) in response to a voltage signal of a first enable signal (En1); a fifth transistor (T5) for switching a current path between the third node (N3) and an anode of a light emitting diode (E) in response to a voltage signal of the first enable signal (En1), a cathode of the light emitting diode (E) being connected to a power supply negative voltage signal (ELVSS); a sixth transistor (T6) for switching a current path between the anode of the light emitting diode (E) and an initialization voltage (Vint) in response to a voltage signal of a second scan signal (Sn2); a seventh transistor (T7) for switching a current path between a charging voltage (Vcharge) and the first node (N1) in response to a voltage signal of a second enable signal (En2); and a first stabilizing capacitor (C1) connected between the third node (N3) and the power supply positive voltage signal (ELVDD) for stabilizing the third node (N3); and a storage capacitor (Cst) connected between the second node (N2) and the third node (N3) for storing a fixed voltage delivered to a gate of the second transistor (T2).

11. A display device, characterized by comprising: The pixel driving circuit according to any one of claims 1 to 10. The pixel driving circuit according to any one of claims 1 to 10.

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