Processor, and method for prefetching data

Abstract

A processor and a method for prefetching data, relating to the field of computers. The processor comprises a prefetcher and a cache controller; the prefetcher is used for: obtaining a first target address, the first target address being an address accessed by the processor (801); when the first target address is within a preset first address range, generating a second index address on the basis of a pre-stored first index address and a preset step size of the index address (802); reading a value in the second index address, and generating a first element address on the basis of the value in the second index address and a pre-acquired element base address, the value in the second index address being used for indicating first address offset information of the element base address (803); and sending first information to the cache controller, the first information being used for instructing to prefetch first data in a storage area in a memory corresponding to the first element address (804).

Description

Processor, and method for prefetching data

[0001] This application claims priority to Chinese Patent Application No. 202411018211.8, filed on July 26, 2024, entitled "Processor and Method for Prefetching Data", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and more particularly to a processor and a method for prefetching data. Background Technology

[0003] With the rise of neural networks, big data, and cloud computing, the performance requirements for data processing devices such as processors and servers are becoming increasingly demanding. This necessitates high computing speeds for these devices to perform more and more complex calculations and inferences. Processors typically contain computing units and caches. The computing units execute various operations by reading instructions and data from the cache.

[0004] Existing processors used in scenarios such as neural networks and cloud computing typically employ memory access patterns with multi-level memory addresses (e.g., level-one and level-two memory addresses), such as Gather Copy operations, to read data from memory. Furthermore, to improve data retrieval speed, the data required by the computing unit is pre-fetched from memory and stored in the cache. When using a multi-level memory access pattern, the processor maintains a non-contiguous linked list of physical storage areas, and data is transferred sequentially by traversing this linked list. However, with multi-level memory access patterns, traditional prefetching algorithms often result in data being pre-fetched too early or too late. Moreover, existing prefetching algorithms can only estimate level-one memory addresses, not level-two addresses, meaning the predicted addresses have high randomness. This prevents the processor from pre-fetching the necessary data into the cache, thus reducing prefetch coverage. Consequently, the processor cannot find the required data in the cache and must wait for the data in memory to be transferred to the cache, reducing the processor's data access efficiency and thus its overall operating efficiency. Therefore, when using a memory access mode with multi-level memory addresses, reducing memory access latency and improving the processor's data access efficiency becomes a problem that needs to be solved. Summary of the Invention

[0005] The processor and data prefetching method provided in this application can reduce memory access latency and improve the processor's data reading efficiency. To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a processor, the processor comprising: a prefetcher and a cache controller; the prefetcher is configured to: obtain a first target address, wherein the first target address is an address accessed by the processor; when the first target address is within a preset first address range, generate a second index address based on a pre-stored first index address and a preset step size of the index address; read a value from the second index address, and generate a first element address based on the value from the second index address and a pre-obtained element base address, wherein the value from the second index address is used to indicate first address offset information of the element base address; and send first information to the cache controller, the first information being used to indicate the prefetching of first data in the storage area corresponding to the first element address in memory.

[0007] The processor provided in this application embodiment, by setting a prefetcher, tracks the address (first target address) accessed by the processor. When the prefetcher tracks the address accessed by the processor (that is, when the prefetcher detects that the first target address is within a preset first address range), it triggers data prefetching. This avoids the problem of low data coverage caused by data prefetching too early or too late (for example, when data is prefetched too early, the prefetched data is data that the processor will use after running for a long time, and the data needed by the processor is not in the cache, i.e., low data coverage; or, for example, when data is prefetched too late, the prefetched data is data that the processor has already accessed, resulting in low data coverage). In addition, the prefetcher uses pre-obtained index addresses and element base addresses to prefetch data from memory. Compared with data prefetching algorithms in the prior art, this reduces the randomness of the estimated address, thereby improving the coverage of the prefetched data and reducing the time the processor waits for data to be transferred from memory to the cache. Therefore, compared with the prior art, the processor provided in this application embodiment can reduce memory access latency and improve the processor's data reading efficiency.

[0008] Based on the first aspect, in one possible implementation, the processor further includes a register for storing data prefetch instructions, which include a first index address and an element base address; the prefetcher is also used to: read the data prefetch instructions from the register before obtaining the first target address.

[0009] By setting data prefetch instructions in registers, the index address and element base address in memory are pre-written into the data prefetch instructions. The prefetcher reads data from memory using the index address, element base address, and a pre-set step size for the index address. Since the index address and element base address are pre-provided in the data prefetch instructions, the prefetcher performs data prefetching based on the pre-provided index address and element base address. This ensures that the data read is limited to a certain range based on the element base address. Compared with existing data prefetching algorithms, this reduces the randomness of the estimated address, thereby reducing the number of invalid data reads and improving the processor's cache hit rate.

[0010] Based on the first aspect, in one possible implementation, the prefetcher is also used to: generate a third index address based on the first index address and a preset index address pointer, and to save the third index address.

[0011] Saving the third index address can also be understood as updating the first index address to the third index address. By updating the first index address to the third index address, the address in the prefetcher can be kept synchronized and consistent with the address accessed by the processor, which can make the subsequent prefetched data more accurate and improve the processor's cache hit rate.

[0012] Based on the first aspect, in one possible implementation, after saving the third index address, the prefetcher is further configured to: obtain a second target address; when the second target address is within a preset second address range, generate a fourth index address based on the third index address and the step size of the index address; generate a second element address based on the value in the fourth index address and the element base address, wherein the value in the fourth index address is used to indicate the second address offset information of the element base address; and send second information to the cache controller, the second information being used to indicate the prefetching of second data in the storage area corresponding to the second element address in memory.

[0013] Based on the first aspect, in one possible implementation, the processor further includes a load memory unit; the load memory unit is used to send a first target address and a second target address to the prefetcher.

[0014] Based on the first aspect, in one possible implementation, before reading the value at the second index address, the prefetcher is further configured to: generate a second element address based on the value at the fourth index address and the element base address, wherein the fourth index address is any index address in the range from the first index address to the second index address, and the value at the fourth index address is used to indicate the second address offset information of the element base address; and send second information to the cache controller, the second information being used to indicate the prefetching of the second data in the storage area corresponding to the second element address in memory.

[0015] By setting the fourth index address to any index address within the range from the first index address to the second index address, the prefetcher can prefetch data corresponding to a range of index addresses based on the triggering of the first target address, thereby increasing the amount of data prefetched and improving cache coverage.

[0016] Based on the first aspect, in one possible implementation, the prefetcher further includes an index buffer; before generating the address of the first element, the prefetcher is also used to: detect whether the value at the second index address is stored in the index buffer; when the value at the second index address is not stored in the index buffer, send a request to the cache controller to retrieve the value at the second index address.

[0017] By setting up an index buffer, the value at the index address can be pre-stored in the index buffer. Thus, when the prefetcher performs the data prefetching process, it can directly read the value at the index address from the index buffer without having to read it from memory through the cache controller. This can improve the reading speed of the value at the index address, which is beneficial to further improving the processor's operating speed.

[0018] Based on the first aspect, in one possible implementation, the prefetcher is also used to: receive third information from the cache controller, the third information indicating that the storage area corresponding to the address of the first element has been accessed; and adjust the step size of the index address based on the third information.

[0019] When the second information refers to the address of the second element being accessed, it indicates that the prefetcher prefetched the data too late, causing the data required by the processor to be unable to be read directly from the cache. By adjusting the step size of the index address, such as increasing the step size of the index address, the data can be prefetched earlier, thereby improving the coverage of the processor's data read.

[0020] Based on the first aspect, in one possible implementation, the processor further includes a cache; the cache controller is used to: read first data from memory and store the first data in the cache.

[0021] Based on the first aspect, in one possible implementation, the cache includes a first-level cache and a second-level cache, and the index buffer includes a first index buffer and a second index buffer. The first index buffer is dedicated to storing the value in the index address corresponding to the first-level cache, and the second index buffer is dedicated to storing the value in the index address corresponding to the second-level cache.

[0022] Based on the first aspect, in one possible implementation, the cache includes a first-level cache and a second-level cache, and the index buffer is used to store one of the following: the value at the index address corresponding to the first-level cache, or the value at the index address corresponding to the second-level cache.

[0023] Secondly, embodiments of this application provide a method for prefetching data, the method comprising: obtaining a first target address, wherein the first target address is an address accessed by a processor; when the first target address is within a preset first address range, generating a second index address based on a pre-stored first index address and a preset step size of the index address; reading a value from the second index address, generating a first element address based on the value from the second index address and a pre-acquired element base address, wherein the value from the second index address is used to indicate first address offset information of the element base address; and sending first information to a cache controller, the first information being used to indicate the prefetching of first data in the memory region corresponding to the first element address.

[0024] Based on the second aspect, in one possible implementation, before obtaining the first target address, the method further includes: reading a data prefetch instruction from a register; wherein the data prefetch instruction is used to instruct data to be prefetched, and the data prefetch instruction includes a first index address and an element base address.

[0025] Based on the second aspect, in one possible implementation, when the first target address is within the first address range, the method further includes: generating a third index address based on the first index address and a preset index address pointer, and saving the third index address.

[0026] Based on the second aspect, in one possible implementation, after saving the third index address, the method further includes: obtaining a second target address; when the second target address is within a preset second address range, generating a fourth index address based on the third index address and the step size of the index address; generating a second element address based on the value in the fourth index address and the element base address, wherein the value in the fourth index address is used to indicate the second address offset information of the element base address; and sending second information to the cache controller, the second information being used to indicate the prefetching of second data in the storage area corresponding to the second element address in memory.

[0027] Based on the second aspect, in one possible implementation, before the prefetcher reads the value at the second index address, the method further includes: generating a second element address based on the value at the fourth index address and the element base address, wherein the fourth index address is any level address in the range of index addresses from the first index address to the second index address, and the value at the fourth index address is used to indicate the second address offset information of the element base address; and sending second information to the cache controller, the second information being used to indicate the second data in the storage area corresponding to the second element address in the prefetch memory.

[0028] Based on the second aspect, in one possible implementation, before generating the address of the first element, the method further includes: detecting whether the value at the second index address is stored in the index buffer; and when the value at the second index address is not stored in the index buffer, sending a request to the cache controller to retrieve the value at the second index address.

[0029] Based on the second aspect, in one possible implementation, after sending the first information to the cache controller, the method further includes: receiving third information from the cache controller, the third information being used to indicate that the storage area corresponding to the address of the first element has been accessed; and adjusting the step size of the index address based on the third information.

[0030] Thirdly, embodiments of this application also provide a data prefetching device, which includes at least one prefetcher that, when the at least one prefetcher executes program code or instructions, implements the method described in the second aspect or any possible implementation thereof.

[0031] Optionally, the data prefetching device may further include at least one memory for storing the program code or instructions.

[0032] Fourthly, embodiments of this application also provide a computer-readable storage medium for storing a computer program that includes methods for implementing the second aspect described above or any possible implementation thereof.

[0033] Fifthly, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the computer to implement the method described in the second aspect or any possible implementation thereof.

[0034] It should be understood that the second to fifth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description

[0035] Figure 1 is a schematic diagram of an electronic device provided in an embodiment of this application;

[0036] Figure 2 is a schematic diagram of the kernel provided in an embodiment of this application;

[0037] Figure 3 is a schematic diagram of the workflow of the pre-extractor provided in an embodiment of this application;

[0038] Figure 4 is a schematic diagram of a storage area in memory provided in an embodiment of this application;

[0039] Figure 5 is a structural schematic diagram of a data prefetch instruction provided in an embodiment of this application;

[0040] Figure 6 is a schematic diagram of a prefetcher provided in an embodiment of this application;

[0041] Figure 7 is another schematic diagram of the prefetcher provided in the embodiment of this application;

[0042] Figure 8 is a flowchart of a data prefetching method provided in an embodiment of this application;

[0043] Figure 9 is a schematic diagram of a data prefetching device provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0045] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0046] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0047] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0048] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0049] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0050] Please refer to Figure 1, which is a schematic diagram of the hardware architecture of an electronic device 100 provided in an embodiment of this application. As shown in Figure 1, the electronic device 100 includes a processor 10 and memory 20. This electronic device can be a server or located within a server. The server can be, for example, a server for performing cloud computing or a server for training artificial intelligence models (e.g., deep neural networks, decision trees, etc.). Furthermore, the electronic device 100 can also be located within a terminal, which can be, for example, a smartphone or a smart car. It should be noted that Figure 1 is only an example of the electronic device 100. Alternatively, the electronic device 100 can be any type of device, such as a chip or chipset or a circuit board carrying a chip or chipset, etc. This embodiment does not limit this. The chip or chipset or the circuit board carrying a chip or chipset can operate under suitable software drivers. Optionally, the processor 10 and memory 20 can be integrated into one or more chips. These one or more chips can be considered as a chipset. When one or more processors are integrated into the same chip, the chip is also called a system on a chip (SOC).

[0051] Processor 10 includes, but is not limited to, a central processing unit (CPU) or a dedicated processor. For example, a dedicated processor includes an artificial intelligence processor, a neural network processor, a digital signal processor, or an image signal processing processor. Processor 10 may include at least one core 11, a cache 12, and a cache controller 13. The figure schematically shows processor 10 including three cores 11. It is understood that processor 10 may also include more or fewer cores. Furthermore, processor 10 may also include a cache 12 and a cache controller 13. In one possible implementation, cache 12 and cache controller 13 may be located within the cores of processor 10 or outside the cores; this application embodiment does not specifically limit this. This application embodiment schematically shows the case where cache 12 and cache controller 13 are located outside the cores of processor 10. Cache controller 13 is used to manage the cache, and the core interacts with cache controller 13 to read instructions or data from cache 12. In one possible implementation of this application embodiment, cache 12 may include multi-level caches, such as cache L1, cache L2, and cache L3. In cache 12, the operating speeds of caches L1, L2, and L3 decrease sequentially, but their capacities increase sequentially. Cache L1 in cache 12 is used to cache the most frequently hit instructions and data in kernel 11. Cache L1 operates quickly, but its capacity is generally very small due to its high cost. Each core 11 in processor 10 corresponds to a cache L2, which can cache data exclusive to kernel 11. There is usually one cache L3. The data stored in cache L1 is shared by multiple cores 11, mainly used to reduce the latency between kernel 11 and memory 20. As shown in processor 10 in Figure 1, each core 11 may be equipped with a prefetcher 113. The prefetcher 113 is used to interact with cache controller 13 to request cache controller 13 to prefetch at least one of the instructions or data from memory 20. Specifically, the prefetcher 113 can determine the address of the instruction or data to be read based on the location of the software program running in the kernel 11, and then send a request carrying the address to the cache controller 13; the cache controller 13 prefetches data from memory 20 into cache 12 based on the received address. In addition, the processor 10 may also include more components, such as a decoder.

[0052] Memory 20 may, exemplarily, include components such as volatile memory for storing instructions and data; volatile memory may include, but is not limited to, dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR), etc. Memory 20 may store various operating system programs (e.g., general-purpose operating system programs and trusted operating system programs), application programs, instruction code and data required for operation, etc. Processor 10 executes various functional applications and data processing of electronic device 100 by loading programs and instructions and acquiring data. In this embodiment, memory 20 may include a memory management unit (MMU) and a memory array. The memory management unit can control the memory array to establish a connection with the processor, so that the processor can read data from or write data to the memory array in memory 20.

[0053] It is understood that the electronic device 100 shown in FIG1 may also include other devices, including but not limited to input / output devices (such as screens, keyboards, and mice) and sensors (such as image sensors, infrared sensors, gyroscope sensors, and accelerometers). The input / output devices and sensors can be connected to the processor 10 via a bus. The user interacts with the processor 10 through the input / output devices to instruct the processor 10 to control the electronic device to perform various functions. The user can also store data in and retrieve data from the memory 20 through the input / output devices. Sensors can collect data (e.g., image sensors collect image data, gyroscope sensors collect three-axis component data of the electronic device), store the collected data in the memory 20, or directly provide it to the processor 10. The processor 10 can control the electronic device to perform certain functions based on the data collected in the memory 20 (e.g., screen unlocking based on facial image data collected by an image sensor). It should be noted that the electronic device 100 shown in FIG1 may also include more or fewer devices or equipment (e.g., it may also include communication devices to achieve short-range communication or cellular communication), and this embodiment does not specifically limit this.

[0054] In this embodiment, the processor 10 implements various functions through multiple workflows, including reading instructions from memory 20, decoding instructions, and executing instruction content. When the processor 10 starts running, it executes a read instruction, that is, it reads the instructions that the processor 10 needs to execute from memory 20. Next, in the instruction decoding stage, the processor 10 translates the read instructions into machine code. Then, the arithmetic logic unit in the processor 10 executes the instruction content. For example, if the instruction is an addition instruction, the operands are added; if it is a subtraction instruction, the operands are subtracted. During the instruction content execution stage, the processor 10 typically needs to access data stored in memory 20 (including reading data from memory 20 and writing intermediate data generated during the operation to memory 20) and write the completed data back to memory 20. In the above workflow, the processor 10 needs to interact with memory 20 during the instruction read stage and the instruction content execution stage to read instructions or data from memory 20.

[0055] In this embodiment, the processor 10 can access memory 20 through a multi-level address access method. The multi-level address access method may include element-level address access, three-level address access, or four-level address access, etc., and this embodiment does not specifically limit the method. When the processor 10 uses element-level address access, the first-level address can be called the index address, and the element address can be called the element address, where the value in the index is the offset from the element's base address. It can be understood that when the processor 10 accesses memory 20 through a three-level (or four-level) address access method, the first-level address (or index address) can also be called the preceding address, and the element address (or element address) can also be called the following address. This embodiment describes an example using element-level address access, with the first-level address being the index address and the element address being the element address, but this is not intended to limit the solution. When reading data from memory 20, the index is first retrieved from memory based on the index address. Then, based on the offset of the element's base address recorded in the index, the element's base address and the offset are calculated to generate an element address. This generated element address is the virtual address to be accessed. Thus, the virtual address can be translated into a physical address, and data can be retrieved from that physical address in memory 20. It should be noted that data in memory 20 is stored in the form of data blocks. That is, a data block is the smallest unit of data storage. Data is typically read in units of data blocks. The data retrieved using the index address and element address is usually a data block.

[0056] Typically, memory 20 is located outside the processor 10. When the processor 10 reads instructions or data from memory 20, it needs to wait, which leads to memory access latency and reduces the processor 10's operating speed. To solve the memory access latency problem caused by directly reading data from memory 20, the processor 10 shown in Figure 1 further includes a cache 12. Part of the cache area in cache 12 can be located within the kernel. A prefetching method can be used to prefetch the data needed by the processor 10 from memory 20 and store it in cache 12. Existing prefetching methods typically employ a data prefetching algorithm to predict the data that the processor 10 needs to read, thereby estimating the storage address of the data to be read in memory 20 based on the prediction result, and generating a prefetch instruction based on this storage address. The prefetch instruction then prefetches the predicted data from memory 20 into cache 12. The address estimated by existing data prefetching algorithms is usually a contiguous physical address range in memory or physical addresses with a preset interval. However, processors used in applications such as artificial intelligence, big data, or cloud computing typically employ memory access patterns with multi-level memory addresses (e.g., level 1 and level 2 memory addresses), such as Gather Copy, to read data from memory. When using a multi-level memory access pattern, the processor pre-maintains a non-contiguous linked list of physical storage areas, and data is transferred sequentially by traversing this linked list. When using this multi-level memory access method, existing data prefetching algorithms often result in data being prefetched too early or too late. Furthermore, existing data prefetching algorithms can only estimate a contiguous range of level 1 memory addresses, not level 2 addresses, meaning the predicted addresses have high randomness. This prevents the processor from prefetching the necessary data into cache 12, reducing prefetch coverage. Consequently, the processor cannot find the required data in the cache and must wait for data in memory 20 to be transferred to cache 12, reducing the processor's data read efficiency and thus its overall operating efficiency. Therefore, when using a memory access mode with multi-level memory access addresses, how to reduce memory access latency and improve the processor's data reading efficiency becomes a problem that needs to be solved.

[0057] The processor provided in this application embodiment, by setting a prefetcher, tracks the address (first target address) accessed by the processor. When the prefetcher tracks the address accessed by the processor (that is, when the prefetcher detects that the first target address is within a preset first address range), it triggers data prefetching, thereby avoiding the problem of low data coverage caused by data prefetching too early or too late (for example, when data prefetching is too early, the prefetched data is data that the processor will use after running for a long time, and the data needed by the processor is not in the cache, that is, the data coverage is low; for another example, when data prefetching is too late, the prefetched data is data that the processor has already accessed, resulting in low data coverage). In addition, by using the pre-obtained index address and element base address to prefetch data from memory, the prefetcher can reduce the randomness of the estimated address compared with the data prefetching algorithm in the prior art, thereby improving the coverage of the prefetched data and reducing the time the processor waits for data to be transferred from memory 20 to cache 12. Therefore, compared with the prior art, the processor provided in this application embodiment can reduce memory access latency and improve the processor's data reading efficiency. The processor and data prefetching method provided in this application embodiment will be described in more detail below with reference to the embodiments shown in Figures 2 to 7.

[0058] Based on the hardware architecture diagram of the electronic device 100 shown in Figure 1, please refer to Figure 2, which is a hardware structure diagram of the core 11 of the processor 10 provided in this application embodiment. As shown in Figure 2, the core 11 may include a register group 110, an arithmetic and logic unit (ALU) 111, a load store unit (LSU) 112, and a hardware prefetcher (HWP) 113. It is understood that the core 11 may include more or fewer components or modules, and this application does not make specific limitations. In the core 11 shown in Figure 2, LSU 112 and HWP 113 are set as two independent modules. In other scenarios or other possible implementations, LSU 112 and HWP 113 may be set in the same hardware, which may also be called a prefetcher, and this same hardware can implement the logical functions performed by LSU 112 and HWP 113. This application embodiment describes LSU 112 and HWP 113 as two independent hardware components, but it is not intended to limit the solution. As shown in Figure 2, register group 110 includes, but is not limited to, data registers and instruction registers. It is understood that register group 110 may include more registers, the number of which is set based on the needs of the application scenario, and this embodiment does not impose a specific limitation. Register group 110 communicates with arithmetic logic unit 111 and LSU 112 respectively. Arithmetic logic unit 111 performs various logical operations by reading data from registers in register group 110, and stores the results of logical operations in register group 110.

[0059] In addition to communicating with the registers in register set 110, LSU112 also communicates with prefetcher 113 and cache controller 13. LSU112 is a dedicated component in processor 10 for executing load and store instructions. LSU112 generates addresses for load or store operations and sends these addresses to cache controller 12. Cache controller 12 then loads data from memory 20 or cache 12 into register set 110, or stores data from register set 110 into memory 20. The addresses generated by LSU112 include index addresses and element addresses. Loading data from memory 20 or cache 12 refers to reading data from memory 20 or cache 12. It should be noted that the data loaded by LSU112 is all data required by processor 10 to execute instructions. LSU112 can send the target address M1 that the processor 10 wants to access to the prefetcher 113. The target address sent by the LSU to the prefetcher 113 can be the address that the processor 10 will access or the address that the processor has already accessed. This access can be reading data from the address. As shown in the kernel 11 in Figure 2, one LSU112 is schematically shown. It can be understood that the kernel 11 can include more LSU112s. Each LSU112 can communicate with the same prefetcher 113 to trigger the prefetcher 113 to prefetch instructions or data. The number of LSU112s is not specifically limited in this embodiment.

[0060] The prefetcher 113 communicates with the LSU 112 and the cache controller 13 to prefetch instructions or data from memory 20 into cache 12. In this embodiment, the prefetcher 113 executes the instruction or data prefetching process based on the trigger of the LSU 112; the prefetcher 113 interacts with the cache controller 13 to prefetch data from memory 20 into cache 12; the prefetcher 113 sends a request to the cache controller 13 to prefetch the value of the first-level address. The prefetcher 113 can be of various forms, including but not limited to discrete devices or programmable logic devices. The prefetcher 113 can be configured with an address step size dh1 for the index address. In addition, the prefetcher 113 can also store an index address I1, which can be obtained based on the data prefetch instruction or based on the trigger update of the target address sent by the LSU 112. A detailed description of the data prefetch instruction is given in Figure 5. The prefetcher 113 can also generate a first address range F1 based on the pre-stored index address I1. This first address range F1 can be an address range including the index address I1. For example, if the index address I1 is 0x82001000, the first address range F1 can be 0x82000940 to 0x82001040. Additionally, the prefetcher 113 can also store a pre-obtained element base address E0, which can be obtained based on data prefetch instructions (see Figure 5 for a detailed description).

[0061] After receiving the target address M1 from LSU112, the prefetcher 113 can perform the following steps: First, compare the received target address M1 with the first address range F1 to determine whether the target address M1 is within the first address range F1. If the target address M1 is within the first address range F1, add the index address I1 to the preset index address step size dh1 to obtain the index address I2. Then, read the value in the index address I2 and generate the element address E1 based on the pre-obtained element base address E0 and the value in the index address I2. The value in the index address I2 is used to indicate the address offset information EP1 of the element base address E0. Finally, send information In1 to the cache controller 13. Information In1 is used to indicate the data Data1 in the storage area corresponding to the element address E1 in the prefetch memory 20. It should be noted that in this embodiment, the size of the element can usually be preset, such as 64 bits, 4KB, etc. This embodiment does not make specific limitations.

[0062] Generating element address E1 based on the values ​​at element base address E0 and index address I2 can be implemented in several ways. In a first possible implementation, the value at the index address is the offset from element base address E0. In this implementation, the starting address of the generated element address E1 is: element base address E0 + value at index address I2. Assuming an element size is 64 bits (8 bytes), the ending address of element address E1 is: element base address E0 + value at index address I2 + 7 (bytes). For example, assuming the preset element size is 8 bytes and the value at index address I2 is 0x6780, the address range of the generated element address E1 is: (element base address E0 + 0x6780) ~ element base address E0 + 0x6787. In a second possible implementation, the product of the value at the index address and the element size is the offset from element base address E0. For example, if an element is 8 bytes in size, then the starting address of element address E1 is: element base address E0 + value in index address I2 * 8; the ending address of element address E1 is: element base address E0 + value in index address I2 * 8 + 7. For instance, assuming the preset element size is 8 bytes and the value in index address I2 is 0x6780, the generated address range of element address E1 is: (element base address E0 + 0x6780 * 8) ~ element base address E0 + 0x678 * 8 + 7).

[0063] The embodiments of this application will be described below using a pre-set element size of 8 bytes as an example. In the embodiments of this application, the prefetcher 113 performs the data prefetching process only when it receives the same first address as the first address I1 from the LSU, which can avoid data prefetching too early or too late, thereby improving the hit rate of the processor reading data from the cache.

[0064] The following description, using a scenario shown in Figure 3, illustrates the data prefetching performed by prefetcher 113. Figure 4 schematically shows the storage space of memory 20, assuming that 0x80000000~0x83000000 are index addresses and 0x84000000~0x89000000 are element addresses. Assume that the index address I1 stored in prefetcher 113 is 0x82001000, the element base address E0 obtained in advance through the prefetch instruction is 0x85000000, the step size dh1 of the index address pre-set in prefetcher 113 is 0x500, and the pre-set element size is 8 bytes; furthermore, the first address range set in prefetcher 113 is 0x82000940~0x82001040. Prefetcher 113 receives target address M1 from LSU 112. Assuming the target address M1 received from LSU 112 is 0x82001020, and address 0x82001020 falls within the first address range of 0x82000940 to 0x82001040, prefetcher 113 adds the stored index address I1 to the index address step size dh1 to obtain index address I2, which is 0x82001500. Assuming the value in index address I2 is 0x6780, this value represents the address offset information of element base address E0. Then, based on element base address E0 and address offset information EP2, prefetcher 113 obtains element address E1 as 0x85006780 to 0x85006787. Finally, the prefetcher 113 can send information In1 to the cache controller 12, which indicates that data Data1 in the memory area corresponding to element address E1 in memory 20 should be prefetched.

[0065] It should be noted that in this embodiment, element address E1 is a virtual address (VA). The address sent to cache controller 12 can be either a virtual address or a physical address (PA). When the address sent by prefetcher 113 to cache controller 12 is a virtual address, cache controller 12 can translate the virtual address into a physical address to read data from memory 20 into the cache. When the address sent by prefetcher 113 to cache controller 12 is a physical address, prefetcher 113 can translate the virtual address into a physical address; or, in one possible implementation, kernel 11 may also include an address translator used to translate virtual addresses into physical addresses, and prefetcher 113 sends information In1 to cache controller 12 through the address translator.

[0066] Therefore, the cache controller 12 can prefetch the data stored in the storage area corresponding to addresses 0x85006780 to 0x85006787 in memory 20 into cache 12 based on the size of an element (e.g., 64 bits) when reading data from memory 20 as specified in the data prefetch instruction.

[0067] The processor 10 provided in this application embodiment, by setting a prefetcher 113, tracks the address (target address M1) accessed by the processor 10. When the prefetcher 113 tracks the address accessed by the processor 10 (that is, when the prefetcher detects that the target address M1 is within the first address range), it triggers data prefetching, thereby avoiding the problem of low data coverage caused by data prefetching too early or too late (for example, when data prefetching is too early, the prefetched data is data that the processor will use after running for a long time, and the data needed by the processor is not in the cache, that is, the data coverage is low; as another example, when data prefetching is too late, the prefetched data is data that the processor has already accessed, resulting in low data coverage); thus, it can improve the coverage of the prefetched data and reduce the time the processor waits for data to be transferred from memory 20 to cache 12. Therefore, compared with the prior art, the processor 10 provided in this application embodiment can reduce memory access latency and improve the data reading efficiency of the processor 10.

[0068] In one possible implementation of this application, after generating index address I2 or completing the data prefetching process, prefetcher 113 can update the stored index address, for example, updating index address I1 to index address I3. For instance, the pointer to index address I1 can be incremented by one, that is, the stored index address I1 can be shifted one position to the right, and the updated index address I3 can be saved. Taking the scenario shown in Figure 3 as an example, assuming the index address I1 indicated by the data prefetching instruction is 0x82001000, then the updated first-level address I3 is 0x82001004. Therefore, prefetcher 113 can continue to receive the target address from the LSU based on the updated first-level address I3. When it detects that the target address M2 sent by LSU 112 is within a second address range, prefetcher 113 is triggered to perform a new round of data prefetching. This second address range is a segment of addresses including index address I3.

[0069] In this embodiment, the index address I1 and element base address E0 pre-stored by the prefetcher 113 can be obtained from the prefetch instruction. Specifically, the register group 110 can pre-store the prefetch instruction, which is used to indicate the index address I1 and element base address E0 during data prefetching. The data prefetch instruction can be pre-written into the program by experts or developers. When the kernel 11 runs, the prefetch instruction is stored in the register group 110 by loading the program. The data prefetch instruction stored in the register group 110 can include the index address I1 and element base address E0 in memory. The value in the index address I1 is used to indicate the offset information EP1 of the element base address E0. In addition, the index address I1 in the instruction stored in the register group 110 can be the first-level address starting address of the prefetched data. After the data prefetch instruction is stored in the register group 110, the prefetcher 113 can be triggered to obtain the parameters in the data prefetch instruction from the register group 110. The prefetcher 113 can save the parameters in the data prefetch instruction. The prefetcher 113 detects the status of the prefetcher 113 indicated by the data prefetch instruction based on the status identification information in the data prefetch instruction. When the status identification information indicates that the prefetcher 113 should perform data prefetching, the prefetcher 113 can detect whether the target address M1 received from LSU 112 is within the first address range. When the target address M1 is within the first address range, the prefetcher 113 is triggered to perform the prefetching process shown in the scenario of Figure 3.

[0070] In this embodiment, the data prefetch instruction stored in register group 110 may include more information than just index address I1 and element base address E0. In one possible implementation, the information in the data prefetch instruction may also include at least one of the following: the length of the value of an index address, the number of index addresses of the prefetched data, the size of the data in an element (e.g., 32-bit data), and the distance between elements. The data prefetch instruction may consist of one or more instructions, and this embodiment does not impose specific limitations. For example, the data prefetch instruction includes two instructions, instruction 1 and instruction 2, as shown in Figure 5, which illustrates a possible implementation of the data prefetch instruction. It is understood that the data prefetch instruction shown in Figure 5 is merely an example and is not intended to limit the scheme. As shown in Figure 5, the parameter information included in instruction 1 may include, but is not limited to, the index count, index length, and index base address. The index length indicates the size of the index value, and the index count indicates the number of indices corresponding to the prefetched data. For example, with an index number of 5, prefetcher 113 can read the values ​​of 5 index addresses based on the trigger of the target address, and perform data prefetching based on the values ​​of these 5 index addresses. The parameter information included in instruction 2 may include, but is not limited to: the size base of an element, the distance between elements, and the element base address.

[0071] As can be seen from the above embodiments, the processor 10 provided in this application provides a data prefetch instruction. The data prefetch instruction prewrites an index address I1 and an element base address E0 in memory. Index address I1 is a first-level base address, and element base address E0 is a second-level base address. The prefetcher 113 in the processor 10 reads data from memory 20 using index address I1, element base address E0, and a pre-set index address step size dh1. Since the data prefetch instruction pre-provides index address I1 and element base address E0, the prefetcher 113 performs data prefetching based on these pre-provided index address I1 and element base address E0. This ensures that the read data is limited to a certain range based on element base address E0. Compared with existing data prefetching algorithms, this reduces the randomness of the estimated address, thereby reducing the number of invalid prefetched data and improving the hit rate of the processor reading data from the cache. Therefore, compared with the prior art, the processor 10 provided in this application provides reduced memory access latency and improved data reading efficiency.

[0072] In the above embodiments, the step size dh1 of the index address in the prefetcher 113 is shown to be a fixed value. In one possible implementation of this application embodiment, the prefetcher 113 can also adjust the step size of the index address. Specifically, when the prefetcher 113 sends an instruction to the cache controller 13 to read the storage area corresponding to element address E1 based on the data prefetch instruction and the triggering of LSU 112, instructing the cache controller 13 to store the data in memory 20 into cache 12, if LSU 112 or other modules have already read the data in the storage area from memory 20, the cache controller 13 can send an instruction to the prefetcher 113 indicating that the data in the storage area corresponding to element address E1 has been read. If the data in the storage area corresponding to E1 has been read, it means that the prefetcher 113 prefetched the data too late or prefetched too little data, causing the data required for the processor 10 to run to be unable to be directly read from cache 12, and memory 20 needs to be accessed. In this case, prefetcher 113 can adjust the index address step size, for example, by increasing the index address step size (e.g., changing the step size from 0x500 to 0x1000), that is, updating the index address step size dh1 to the index address step size dh2, to improve the data read coverage of processor 10. Furthermore, if the target address M1 received by prefetcher 113 from LSU 112 within a preset time period is different from all addresses in the first address range, it indicates that prefetcher 113 prefetched data too early. Prefetcher 113 can also adjust the index address step size, for example, by decreasing the index address step size (e.g., changing the step size from 0x500 to 0x0200), that is, updating the index address step size dh1 to the index address step size dh3, to improve the hit rate of processor 10 reading cache 12.

[0073] Based on the processor 10 shown in Figure 2, and continuing to refer to Figure 6, Figure 6 is a structural schematic diagram of the prefetcher 113 provided in this embodiment. As shown in Figure 6, the prefetcher 113 includes an index tracker 1131, an index buffer 1132, and an address generator 1133. The index buffer 1132 is coupled to both the index tracker 1131 and the address generator 1133. The index buffer 1132 is used to store the value of the index address. The index buffer 1132 may include one or more, for example, one, two, or three, etc., which is not specifically limited in this embodiment. The index buffer 1132 included in the prefetcher 113 will be described below. As shown in Figure 1, the cache 12 typically includes multi-level caches, such as cache L1, cache L2, and cache L3. For the case of multi-level caches, the number of index buffers 1132 can be implemented in various ways. In the first possible implementation, the number of index buffers 1132 is the same as the number of cache levels 12. Multiple index buffers 1132 can correspond one-to-one with multiple cache levels, with one index buffer 1132 used to store the value of the index address in the corresponding cache level. For example, index buffers 1132 include three: index buffer 0, index buffer 1, and index buffer 2. Index buffer 0 stores the value of the index address in cache L1, index buffer 1 stores the value of the index address in cache L2, and index buffer 2 stores the value of the index address in cache L3. In the second possible implementation, index buffers 1132 only store the values ​​of the index addresses in cache L2 and cache L3, and no longer store the values ​​of the index addresses in cache L1. This second possible implementation can further include the following possible implementations. Method 1: Index buffer 1132 may include two index buffers, index buffer 1 and index buffer 2. Index buffer 1 is used to store the value of the index address in cache L2, and index buffer 2 is used to store the value of the index address in cache L3. Method 2: Index buffer 1132 may include one index buffer. This index buffer 1132 may be divided into two storage spaces, which respectively store the values ​​of the index addresses in cache L2 and cache L3. Method 3: Index buffer 1132 may include one index buffer. Cache L2 and cache L3 share this one index buffer 1132. For example, when index buffer 1132 pre-stores the value of the index address in cache L2, when index buffer 1132 needs to store the value of the index address in cache L3, it can partially or completely overwrite the previously stored value of the index address in cache L2 to store the value of the index address in cache L3.

[0074] Referring to Figure 6, Figure 6 schematically illustrates the case where the index buffer 1132 includes two index buffers, index buffer 1 and index buffer 2. Index buffer 1 stores the value of the index address in cache L2, and index buffer 2 stores the value of the index address in cache L3. In one possible implementation of this application embodiment, since cache L3 and cache L2 have different latency and bandwidth, the prefetcher 113 and index tracker 1131 can be configured with a step size dh3 for the index address of cache L3 and a step size dh4 for the index address of cache L2, respectively. Both the step size dh3 and the step size dh4 are stored in the index tracker 1131.

[0075] Index tracker 1131 stores index address I4 and a third address range generated based on index address I4. Index address I4 can be the base address of the index in a stored data prefetch instruction, or a new index address generated during runtime. Additionally, index tracker 1131 stores the index address step sizes dh3 and dh4. Index tracker 1131 also communicates with LSU 112 shown in Figure 2 to receive the target address M3 from LSU 112. Assume that the index address I4 stored in index tracker 1131 is 0x82001100, the third address range is 0x82001060 to 0x82001140, and the target address M3 is 0x82001120. Index tracker 1131 detects that target address M3 is within the third address range, triggering it to add index address I4 to the index address step size dh3 to generate index address I6, which is then sent to index buffer 1. Additionally, index tracker 1131 adds index address I4 to the index address step size dh4 to generate index address I7, which is then sent to index buffer 2. Furthermore, index tracker 1131 can also update index address I4 to index address I5 and save index address I5, update the third address range to a fourth address range, and save the fourth address range.

[0076] The index address value cached in index buffer 1132 can be retrieved from memory 20 in advance by prefetcher 113, or it can be retrieved from memory 20 by prefetcher 113 during data prefetching. Furthermore, each index buffer in index buffer 1132 can maintain a page table, which records the index address corresponding to the value stored in the index buffer. After receiving an index address from index tracker 1131, each index buffer in index buffer 1132 can query the page table to see if the received index address is recorded. Taking index buffer 1 as an example, the logic executed by index buffer 2 is similar to that of index buffer 1. Index buffer 1 queries the page table to see if index address I6 is recorded. If the page table records the received index address I6, it means that index buffer 1 stores the value of index address I6; if the page table does not record index address I6, it means that index buffer 1 does not store the value of index address I6. If index buffer 1 stores the value of index address I6, index buffer 1 sends the value of index address I6 to address generator 1133; if index buffer 1 does not store the value of index address I6, index buffer 1 reads the value of index address I6 from memory 20 through cache controller 13, and then sends the read value of index address I6 to address generator 1133. The value of index address I6 is used to indicate the offset information of the element base address E0. Assuming that index buffer 1 stores the value of index address I6 (0x5750), and index buffer 2 stores the value of index address I7 (0x6750), then index buffer 1132 sends both the values ​​of index address I6 and index address I7 to address generator 1133.

[0077] The address generator 1133 can store the element base address E0, which can be read and stored from the data prefetch instruction. The address generator 1133 generates element address E3 based on the element base address E0 and the value of index address I6; and generates element address E4 based on the element base address E0 and the value of index address I7. For example, element address E3 can be 0x85005750 to 0x85005757; element address E4 can be 0x85006750 to 0x85006757. It should be noted that both element address E3 and element address E4 are virtual addresses. In one possible implementation, the address generator 1133 can also convert the generated virtual address into a physical address and send it to the cache controller 13, so that the cache controller 13 can store the data in the storage area corresponding to element address E3 in memory 20 into cache L2; and store the data in the storage area corresponding to element address E4 in memory 20 into cache L3. In another possible implementation, the address generator 1133 is not used to generate physical addresses. Instead, the address generator 1133 provides the generated virtual address to an external address converter, which converts the virtual address into a physical address and sends it to the cache controller 13 to achieve data prefetching.

[0078] In the above embodiments, it is shown that the prefetcher 113, based on the data prefetch instruction and the triggering of LSU, adds the index address (which can be the index base address read from the data prefetch instruction or the index address updated by the index tracker 1131) stored in the prefetcher 113 to the step size of the index address to generate an index address, and prefetches data based on the value in this index address. That is to say, in the above embodiments, the prefetcher 113 prefetches the data corresponding to one index address based on the data prefetch instruction and the triggering of LSU. In a possible implementation of the embodiments of this application, the prefetcher 113 can prefetch the data corresponding to multiple index addresses based on the data prefetch instruction and the triggering of LSU. In this case, the index address In obtained by adding the index address I1 stored in the index tracker 1131 to the step size of the index address is used as the end address, so that the prefetcher 113 can pre-read the values ​​of multiple index addresses between index address I1 and index address In. Specifically, the process includes the following steps: Step 1, the prefetcher 113 obtains the index address Ii based on the index address I1 and a preset pointer, where i is an integer greater than 0 and less than n; Step 2, it determines whether the index buffer 1132 stores the value of the index address Ii. If the index buffer 1132 stores the value of the index address Ii, Step 3 is executed. If the index buffer 1132 does not store the value of the index address Ii, the value of the index address Ii is read from memory 20, and then Step 3 is executed; Step 3, the index buffer 1132 sends the value of the index address Ii to the address generator 1133; Step 4, the address generator 1133 generates a virtual address based on the value of the index address Ii and the element base address E0; Step 5, the virtual address is converted into a physical address. Starting from the index address I1, steps 1 to 5 are repeated until all virtual addresses corresponding to the index address Ii are converted.

[0079] Furthermore, based on the prefetcher 113's ability to pre-read the values ​​of multiple index addresses between index address I1 and index address In, assuming it reads the value of index address I5, where index address I5 is an index address between index address I1 and index address In (e.g., index address 0x82000500), and the index tracker 1131 receives an index address from LSU 112 that is the same as the index address stored in the index tracker 1131, then the start and end addresses of the index address of the data to be prefetched need to be reset. For example, the start address pointer of the index address is incremented by 100, meaning the start address of the index address is reset from 0x82000000 to 0x82000100, and the end address of the index address is reset from 0x82001000 to 0x82001100. Since the values ​​of the index addresses corresponding to index addresses 0x82000100 to 0x82000500 have all been read before the start and end addresses of the index addresses are reset, after the start and end addresses of the index addresses are reset, it is only necessary to read the values ​​of index addresses 0x82000501 to 0x82001100.

[0080] Based on the embodiments described above, the workflow of the prefetcher 113 is described below with reference to the flowchart shown in FIG7. As shown in FIG7, the workflow of the prefetcher 113 includes the following steps:

[0081] Step 701: Based on the triggering of the data prefetch instruction, obtain the index address and element address from register 101, and save the obtained index address.

[0082] Step 702: Receive the target address from LSU112.

[0083] Step 703: Detect whether the target address sent by LSU112 is within the first-level address range. If the target address is outside the first-level address range, proceed to step 702; if the target address is within the first-level address range, proceed to steps 704-705.

[0084] Step 704: Add the saved index address to the step size of the index address to generate the index address I2, and update the saved index address.

[0085] Step 705: Determine whether the index buffer stores the value of index address I2. If not, proceed to step 706; if so, proceed to step 707.

[0086] Step 706: Read the value at index address I2 from memory 20. Then execute step 707.

[0087] Step 707: Read the value of index address I2, and generate the element address based on the value of index address I2 and the element base address.

[0088] Step 708: Send indication information 1 to cache controller 13. Indication information 1 is used to indicate the prefetching of data 1 in the storage area corresponding to the element address in memory.

[0089] Step 709: Receive indication information 2 from cache controller 13, and determine whether indication information 2 is used to indicate whether data 1 has been accessed. If indication information 2 indicates that data 1 has been accessed, proceed to step 711; if indication information 2 indicates that data 1 has not been accessed, proceed to step 702.

[0090] Step 710: Increase the step size of the index address.

[0091] Therefore, after receiving a data prefetch instruction, the prefetcher 113 can repeatedly execute the steps 702 to 710 to perform data prefetching until the next data prefetch instruction arrives. When the next data prefetch instruction arrives, if the status flag in the data prefetch instruction indicates that the prefetcher 113 should stop data prefetching, then the prefetcher 113 will stop executing the above steps 702 to 710; if the status flag in the data prefetch instruction indicates that the prefetcher 113 should perform a new data prefetch, then the prefetcher 113 can start from step 701 and re-execute the above steps 701 to 710.

[0092] Based on the same inventive concept, this application also provides a method for prefetching data, which is applied to the processor 10 shown in FIG1. ​​Please continue to refer to FIG8, which shows a flow 800 of the method for prefetching data provided in this application. The flow 800 of the method for prefetching data can be executed by the prefetcher 113, including the following steps: Step 801, obtaining a first target address, wherein the first target address is an address accessed by the processor; Step 802, when the first target address is within a preset first address range, generating a second index address based on a pre-stored first index address and a preset step size of the index address; Step 803, reading the value in the second index address, generating a first element address based on the value in the second index address and a pre-obtained element base address, wherein the value in the second index address is used to indicate the first address offset information of the element base address; Step 804, sending first information to the cache controller, the first information being used to indicate the prefetching of first data in the memory corresponding to the first element address.

[0093] In one possible implementation, before obtaining the first target address, the method further includes: reading a data prefetch instruction from a register; wherein the data prefetch instruction is used to instruct data to be prefetched, and the data prefetch instruction includes a first index address and an element base address.

[0094] In one possible implementation, when the first target address is within the first address range, the method further includes: generating a third index address based on the first index address and a preset index address pointer, and saving the third index address.

[0095] In one possible implementation, after saving the third index address, the method further includes: obtaining a second target address; when the second target address is within a preset second address range, generating a fourth index address based on the third index address and the step size of the index address; generating a second element address based on the value in the fourth index address and the element base address, wherein the value in the fourth index address is used to indicate the second address offset information of the element base address; and sending second information to the cache controller, the second information being used to indicate the prefetching of second data in the storage area corresponding to the second element address in memory.

[0096] In one possible implementation, before the prefetcher reads the value at the second index address, the method further includes: generating a second element address based on the value at the fourth index address and the element base address, wherein the fourth index address is any level address in the range of index addresses from the first index address to the second index address, and the value at the fourth index address is used to indicate the second address offset information of the element base address; and sending second information to the cache controller, the second information being used to indicate the second data in the memory corresponding to the second element address.

[0097] In one possible implementation, before generating the address of the first element, the method further includes: detecting whether the value at the second index address is stored in the index buffer; and when the value at the second index address is not stored in the index buffer, sending a request to the cache controller to retrieve the value at the second index address.

[0098] In one possible implementation, after sending the first information to the cache controller, the method further includes: receiving third information from the cache controller, the third information indicating that the storage area corresponding to the address of the first element has been accessed; and adjusting the step size of the index address based on the third information.

[0099] It is understood that, in order to achieve the above-mentioned functions, the prefetcher 113 includes hardware and / or software modules corresponding to the execution of each function. Based on the steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in a manner that drives hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0100] This embodiment can divide the prefetcher 113 into functional modules according to the above method example. For example, different functional modules can be divided for each function, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0101] With each functional module divided according to its corresponding function, Figure 9 shows a possible schematic diagram of the data prefetching device 900 involved in the above embodiments. The previously mentioned device can be further extended. For example, the data prefetching device 900 corresponding to Figure 9 can be a software device running on the prefetcher 113, or the data prefetching device 900 can be a combination of software and hardware devices embedded in the prefetcher 113. As shown in Figure 9, the data prefetching device 900 may include: an acquisition module 901, used to acquire a first target address, wherein the first target address is an address accessed by the processor; a generation module 902, used to generate a second index address based on a pre-stored first index address and a preset step size of the index address when the first target address is within a preset first address range; a first reading module 903, used to read the value in the second index address and generate a first element address based on the value in the second index address and a pre-acquired element base address, wherein the value in the second index address is used to indicate the first address offset information of the element base address; and a sending module 904, used to send first information to the cache controller, wherein the first information is used to indicate the first data in the memory corresponding to the first element address.

[0102] In one possible implementation, the data prefetching device 900 further includes: a second read module (not shown in the figure) for reading a data prefetch instruction from a register; wherein the data prefetch instruction is used to instruct data to be prefetched, and the data prefetch instruction includes a first index address and an element base address.

[0103] In one possible implementation, the data prefetching device 900 further includes a third index address generation module (not shown in the figure), which generates a third index address based on the first index address and a preset index address pointer, and saves the third index address.

[0104] In one possible implementation, the data prefetching device 900 further includes a second element generation module (not shown in the figure), configured to: obtain a second target address; when the second target address is within a preset second address range, generate a fourth index address based on a third index address and the step size of the index address; generate a second element address based on the value in the fourth index address and the element base address, wherein the value in the fourth index address is used to indicate the second address offset information of the element base address; and send second information to the cache controller, the second information being used to indicate the prefetching of second data in the storage area corresponding to the second element address in memory.

[0105] In one possible implementation, the data prefetching device 900 further includes a second element generation module (not shown in the figure), used to: generate a second element address based on the value in the fourth index address and the element base address, wherein the fourth index address is any level address in the range of index addresses from the first index address to the second index address, and the value in the fourth index address is used to indicate the second address offset information of the element base address; and send second information to the cache controller, the second information being used to indicate the prefetching of second data in the storage area corresponding to the second element address in memory.

[0106] In one possible implementation, the data prefetching device 900 further includes an index address acquisition module (not shown in the figure), used to: detect whether the value at the second index address is stored in the index buffer; and when the value at the second index address is not stored in the index buffer, send a request to the cache controller to acquire the value at the second index address.

[0107] In one possible implementation, the data prefetching device 900 further includes a step size adjustment module (not shown in the figure), which is used to: receive third information from the cache controller, the third information indicating that the storage area corresponding to the first element address has been accessed; and adjust the step size of the index address based on the third information.

[0108] The data prefetching device 900 provided in this embodiment is used to execute the data prefetching method performed by the prefetcher 113, and can achieve the same effect as the above-described implementation method or device. Specifically, each module corresponding to FIG9 above can be implemented by software, hardware, or a combination of both. For example, each module can be implemented in software form to drive the prefetcher 113 to work. Alternatively, each module can include a corresponding processor and corresponding driver software, that is, implemented by a combination of software or hardware.

[0109] Exemplarily, the prefetcher 113 may further include at least one processor and a memory. The at least one processor can invoke all or part of the computer program stored in the memory to control and manage the operation of the prefetcher 113, for example, it can be used to support the prefetcher 113 in executing the steps performed by the various modules described above. The memory can be used to support the prefetcher 113 in executing stored program code and data, and the memory includes, but is not limited to, at least a portion of the storage space, cache, or registers of the memory 103 described above. The at least one processor can implement or execute various exemplary multiple logic modules described in conjunction with the disclosure of this application, which may be a combination of one or more microprocessors implementing computational functions. Furthermore, the at least one processor may also include other programmable logic devices, transistor logic devices, or discrete hardware components, etc.

[0110] This embodiment also provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the computer performs the aforementioned method steps to implement the data prefetching method in the above embodiment.

[0111] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the data prefetching method described in the above embodiment.

[0112] In this embodiment, the computer-readable storage medium or computer program product is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0113] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0114] Furthermore, the functional units in the various embodiments of this application can be integrated into a single product, or each unit can exist physically separately, or two or more units can be integrated into a single product. Corresponding to Figure 9, if the above modules are implemented as software functional units and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A processor, comprising: The processor comprises a prefetcher and a cache controller; the prefetcher is configured to: obtain a first target address, wherein the first target address is an address accessed by the processor; when the first target address is within a preset first address range, generate a second index address based on a preset first index address and a step of the index address; read a value in the second index address, and generate a first element address based on the value in the second index address and a previously obtained element base address, wherein the value in the second index address is used to indicate first address offset information of the element base address; send first information to the cache controller, wherein the first information is used to indicate first data in a storage region corresponding to the first element address in a prefetch memory.

2. The processor of claim 1, wherein, The processor further comprises a register configured to store a data prefetch instruction, wherein the data prefetch instruction comprises the first index address and the element base address. The prefetcher is further configured to, before obtaining the first target address, read the data prefetch instruction from the register.

3. The processor of claim 1 or 2, wherein, The prefetcher is further configured to: generate a third index address based on the first index address and a preset index address pointer, and save the third index address.

4. The processor of claim 3, wherein, After saving the third index address, the prefetcher is further configured to: obtain a second target address, and when the second target address is within a preset second address range, generate a fourth index address based on the third index address and the step of the index address; generate a second element address based on a value in the fourth index address and the element base address, wherein the value in the fourth index address is used to indicate second address offset information of the element base address; send second information to the cache controller, wherein the second information is used to indicate second data in a storage region corresponding to the second element address in the prefetch memory.

5. The processor of claim 4, wherein, The processor further comprises a load store unit configured to send the first target address and the second target address to the prefetcher.

6. The processor of claim 3, wherein, The prefetcher is further configured to, before reading the value in the second index address: generate a second element address based on a value in the fourth index address and the element base address, wherein the fourth index address is any index address in a segment of index addresses from the first index address to the second index address, and the value in the fourth index address is used to indicate second address offset information of the element base address; send second information to the cache controller, wherein the second information is used to indicate second data in a storage region corresponding to the second element address in the prefetch memory.

7. The processor of claim 1, wherein, The prefetcher further comprises an index buffer, and the prefetcher is further configured to, before generating the first element address: detect whether the value in the second index address is stored in the index buffer; when the value in the second index address is not stored in the index buffer, send a request for obtaining the value in the second index address to the cache controller.

8. The processor of claim 1, wherein, The prefetcher is further configured to: receiving third information from the cache controller, the third information being used to indicate that a storage region corresponding to the first element address has been accessed; adjusting a step size of the index address based on the third information.

9. The processor of claim 7, wherein, The processor further comprises a cache; and the cache controller is configured to: read the first data from the memory and store the first data into the cache.

10. The processor of claim 9, wherein, The cache comprises a level one cache and a level two cache, and the index buffer comprises a first index buffer and a second index buffer, the first index buffer being used to store values in index addresses corresponding to the level one cache, and the second index buffer being used to store values in index addresses corresponding to the level two cache.

11. The processor of claim 9, wherein, The cache comprises a level one cache and a level two cache, and the index buffer is used to store values in one of the following: index addresses corresponding to the level one cache, or index addresses corresponding to the level two cache.

12. A method for prefetching data, characterized by, The method comprises: obtaining a first target address, wherein the first target address is an accessed address; when the first target address is within a preset first address range, generating a second index address based on a pre-stored first index address and a preset step size of index addresses; reading a value in the second index address, and generating a first element address based on the value in the second index address and a pre-acquired element base address, wherein the value in the second index address is used to indicate first address offset information of the element base address; sending first information to a cache controller, the first information being used to indicate that first data in a storage region corresponding to the first element address in a pre-fetch memory is to be pre-fetched.

13. The method of claim 12, wherein, Before the obtaining of the first target address, the method further comprises: reading a data pre-fetch instruction from a register, wherein the data pre-fetch instruction is used to indicate pre-fetched data, and the data pre-fetch instruction comprises the first index address and the element base address.

14. The method according to claim 12 or 13, characterized in that, When the first target address is within the first address range, the method further comprises: generating a third index address based on the first index address and a preset index address pointer, and saving the third index address.

15. The method of claim 14, wherein, After the saving of the third index address, the method further comprises: obtaining a second target address, and when the second target address is within a preset second address range, generating a fourth index address based on the third index address and the step size of index addresses; generating a second element address based on a value in the fourth index address and the element base address, wherein the value in the fourth index address is used to indicate second address offset information of the element base address; sending second information to the cache controller, the second information being used to indicate that second data in a storage region corresponding to the second element address in the pre-fetch memory is to be pre-fetched.

16. The method of claim 14, wherein, Before the pre-fetcher reads the value in the second index address, the method further comprises: generating a second element address based on a value in a fourth index address and the element base address, wherein the fourth index address is any one of the first index address to the second index address, and the value in the fourth index address is used to indicate second address offset information of the element base address; sending second information to the cache controller, the second information being used to indicate second data in a storage region corresponding to the second element address in the prefetch memory.

17. The method of claim 12, wherein, Before the first element address is generated, the method further comprises: detecting whether the value in the second index address is stored in the index buffer; when the value in the second index address is not stored in the index buffer, sending a request to the cache controller to acquire the value in the second index address.

18. The method of claim 15, wherein, After the first information is sent to the cache controller, the method further comprises: receiving third information from the cache controller, the third information being used to indicate that a storage region corresponding to the first element address has been accessed; adjusting a step size of the index address based on the third information.

19. A data prefetching apparatus comprising at least one prefetcher and a memory, characterized in that, The at least one prefetcher executes a program or instructions stored in the memory, so that the data prefetching apparatus implements the method of any one of claims 12 to 18.

20. A computer readable storage medium for storing a computer program, characterized in that, The computer program, when running on a computer or a processor, causes the computer or the processor to implement the method of any one of claims 12 to 18.

21. A computer program product comprising instructions therein, the computer program product comprising instructions therein, characterized in that, The instructions, when running on a computer or a processor, cause the computer or the processor to implement the method of any one of claims 12 to 18.

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