Inter-chip communication circuit and method, communication interval time determination circuit and method, and chip

Abstract

Provided are an inter-chip communication circuit and method, a communication interval time determination circuit and method, and a chip. The inter-chip communication circuit may comprise: a receiving circuit, used for receiving data frames; a memory, used for storing the received data frames; a counter circuit, used for determining a frame reception duration for receiving a data frame; a decoder circuit, used for obtaining a negative feedback adjustment value on the basis of the amount of data to be transmitted, which is stored in the memory; an adder circuit, used for determining an interval time on the basis of the frame reception duration and the negative feedback adjustment value; and a transmission circuit, used for transmitting the data frames by using the determined interval time as a transmission interval between the data frames.

Description

Inter-chip communication circuits and methods, communication interval determination circuits and methods, chips

[0001] This invention claims priority to Chinese Patent Application No. 202410987632.5, filed with the Chinese Patent Office on July 22, 2024, entitled "Inter-chip Communication Circuit and Method, Communication Interval Time Determination Circuit and Method, Chip", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to inter-chip communication circuits and methods, communication interval determination circuits and methods, and chips. Background Technology

[0003] In inter-chip communication, clock discrepancies between different chips can lead to communication failures. A circuit or method that can effectively enable inter-chip communication is desired. Summary of the Invention

[0004] According to one aspect of this disclosure, an inter-chip communication circuit is provided, comprising: a receiving circuit for receiving data frames; a memory for storing the received data frames; a counter circuit for determining the duration of the received data frames; a decoder circuit for obtaining a negative feedback adjustment value based on the amount of data to be transmitted stored in the memory; an adder circuit for determining an interval time based on the duration of the received data frames and the negative feedback adjustment value; and a transmitting circuit for transmitting data frames by using the determined interval time as the transmission interval between data frames.

[0005] According to another aspect of this disclosure, an interval time determination circuit for inter-chip communication is provided, comprising: a counter circuit for obtaining the duration of a received frame after which a received data frame has elapsed; a decoder circuit for obtaining a negative feedback adjustment value based on the amount of data to be transmitted stored in a memory; and an adder circuit for determining an interval time based on the received frame duration and the negative feedback adjustment value, the interval time being used as the transmission interval between data frames.

[0006] According to another aspect of this disclosure, a chip is provided, including an inter-chip communication circuit according to various embodiments of this disclosure or an interval time determination circuit for inter-chip communication according to various embodiments of this disclosure.

[0007] According to another aspect of this disclosure, an inter-chip communication method is provided, comprising: receiving a data frame; storing the received data frame; determining the duration of the received data frame; obtaining a negative feedback adjustment value based on the stored amount of data to be transmitted; determining an interval time based on the received frame duration and the negative feedback adjustment value; and transmitting the data frame by using the determined interval time as the transmission interval between data frames.

[0008] According to another aspect of this disclosure, a method for determining the interval time for inter-chip communication is provided, comprising: obtaining the duration of a received frame over which a received data frame has elapsed; obtaining a negative feedback adjustment value based on the amount of data to be transmitted stored in a memory; and determining an interval time based on the received frame duration and the negative feedback adjustment value, wherein the interval time is used as the transmission interval between data frames.

[0009] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0010] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic diagram illustrating the topology of a distributed battery management system;

[0012] Figure 2 is a schematic diagram illustrating the forwarding of communication frames;

[0013] Figure 3 is a schematic diagram illustrating the failure of daisy chain forwarding communication caused by frequency offset in related technologies;

[0014] Figure 4 is a schematic circuit diagram illustrating one or more embodiments of the present disclosure for inter-chip communication or for determining communication interval time;

[0015] Figure 5 is a flowchart illustrating a method for determining the interval time for inter-chip communication according to an exemplary embodiment of the present disclosure;

[0016] Figure 6 is a schematic diagram illustrating the adjustment of the interval time between data frames according to an embodiment of the present disclosure;

[0017] Figure 7 is a flowchart illustrating a method for determining the interval time for inter-chip communication according to a variant of the present disclosure;

[0018] Figure 8 is a schematic diagram illustrating a communication frame format according to an exemplary embodiment of the present disclosure;

[0019] Figure 9 is a schematic diagram illustrating the signal clock timing according to an exemplary embodiment of the present disclosure;

[0020] Figure 10 is a flowchart illustrating an inter-chip communication method according to an exemplary embodiment of the present disclosure;

[0021] Figure 11 is a schematic diagram illustrating the adjustment capability according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0022] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0023] Spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “above,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below,” “below,” or “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary terms “below” and “below” can cover both orientations above and below. Terms such as “before” or “in front” and “after” or “follow” can similarly be used, for example, to indicate the order in which light passes through the elements. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or there can be one or more intermediate layers.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items, and the phrase “at least one of A and B” includes only A, only B, and both A and B.

[0025] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0026] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0028] In inter-chip communication, clock discrepancies, also known as clock mismatch, can occur between different chips, potentially leading to communication failure. For example, consider a data communication scenario from chip 1 to chip 2 to chip 3, where chip 1's clock is faster than chip 2's. For instance, chip 1 takes 9µs to send one bit of a communication frame, while chip 2 takes 11µs. In this case, chip 2's receiving rate corresponds to chip 1's clock, while its sending rate corresponds to its own clock. For example, chip 2 might still receive data at 1 bit / 9µs and send data at 1 bit / 11µs. Because chip 2 is slower at retrieving data from its FIFO and sending it, its communication FIFO may overflow, causing errors in the data sent. Consequently, chip 3 receives incorrect data, resulting in communication failure between chip 1, chip 2, and chip 3.

[0029] Data communication between chips is widely used. As a specific, non-limiting embodiment, the following describes a chip communication scenario applicable to daisy-chain communication, and more specifically applicable to the field of electric vehicles, with reference to Figure 1.

[0030] Figure 1 illustrates a schematic diagram of a distributed battery management system (BMS) topology. In electric vehicle (EV) applications, stackable battery cells can be used as the energy source. The EV battery management system can utilize a distributed BMS architecture, where each set of battery cells is paired with a monitoring IC to measure the voltage and temperature of each cell. Since the battery cells are stackable, the monitoring ICs can also be stackable monitoring ICs, such as stack 1, stack 2, ..., stack N. The monitoring stack chips can be daisy-chained and use asynchronous communication to transmit voltage and temperature measurement results. Finally, the measurement results from all monitoring chips are aggregated and transmitted back to the BMS controller via a communication bridge IC. Referring to Figure 2, in a distributed BMS system, chip m forwards communication frames from the previous chip m+1. In this example, frequency offset may cause daisy-chain communication failure between monitoring stack chips. It is understood that the above are just example scenarios, and the scenarios of inter-chip communication and the resulting communication problems are not limited to this scenario.

[0031] In related technologies, solutions to the inter-chip communication mismatch problem include high-precision clocking and large-capacity buffering. High-precision clocking reduces the relative frequency offset between monitoring stack chips by using an on-chip high-precision clock. However, this solution requires high precision in the design of the on-chip clock module, resulting in high cost. Large-capacity buffering addresses the frequency offset problem by placing a large-capacity FIFO between the receiver and transmitter. Since the amount of data returned by the BMS can be large, this solution requires a large FIFO capacity, still resulting in high cost. Furthermore, these solutions cannot improve the communication system's tolerance to frequency offset and are insufficient to substantially solve the problem of inter-chip link communication failure caused by clock frequency deviation. Therefore, according to one or more embodiments of this disclosure, a solution is proposed that adjusts the interval time of inter-chip communication to achieve tolerance to frequency offset, thereby preventing inter-chip link communication failure caused by clock frequency deviation between devices.

[0032] Figure 3 illustrates a schematic diagram of inter-chip data forwarding communication failure caused by inter-chip clock skew. Data communication occurs at least between the first chip STACK1, the second chip STACK2, and the third chip STACK3, and there is a clock skew between at least the first and second chips. As shown in Figure 3, the frequency skew causes the FIFO of the second chip to overflow, thus leading to the failure of forwarding communication.

[0033] Based on this, according to embodiments of the present disclosure, a method for determining the interval time for inter-chip communication, an inter-chip communication method, and corresponding circuits and chips are proposed.

[0034] The following describes, with reference to FIG4, a circuit implementation of an interval time determination scheme or an inter-chip communication scheme according to one or more embodiments of the present disclosure. As shown in FIG4, the inter-chip communication circuit 400 may include an interval time determination circuit 410, which can be used to determine or adjust the interval time. For example, the interval time determination circuit 410 can be used to implement the interval time determination method described with reference to FIG5 or FIG7. It is understood that the interval time determination circuit 410 may also be referred to as an interval time determination module, an interval time adjustment module, an interval adjustment module, a feedback circuit, a feedback module, etc., and it is understood that it does not necessarily need to be implemented as a separate or integrated module.

[0035] As shown in Figure 4, the interval determination circuit 410 may include a counter circuit 411, a decoder circuit 412, and an adder circuit 413. The counter circuit 411 can be used to obtain the duration of the received data frame. The decoder circuit 412 can be used to obtain a negative feedback adjustment value based on the amount of data to be transmitted stored in the memory. The adder circuit 413 can be used to determine the interval time based on the received frame duration and the negative feedback adjustment value, the interval time being used as the transmission interval between data frames.

[0036] The interval determination circuit 410 can be used to implement the interval determination method 500 for inter-chip communication according to one or more embodiments of the present disclosure. Referring to FIG5, various steps of the interval determination method 500 for inter-chip communication are illustrated. It will be understood that, as will be further described below in conjunction with FIG4, the various steps of the interval determination method 500 can be implemented using corresponding portions or elements of the circuit described below, and the description of other embodiments or variations of the interval determination circuit 410 can also be applied to the interval determination method 500, which will not be repeated herein.

[0037] At step 510, the duration of the received data frame is obtained.

[0038] At step 520, a negative feedback adjustment value is obtained based on the amount of data to be transmitted stored in the memory. For example, the amount of data in the memory can be monitored, and the amount of correction to the interval between data frames can be determined based on the amount of data to perform negative feedback adjustment.

[0039] At step 530, an interval time is determined based on the duration of the received frame and the negative feedback adjustment value, and the interval time is used as the transmission interval between data frames.

[0040] According to one or more embodiments of this disclosure, the transmission interval between data frames can be controllably adjusted to achieve tolerance to inter-chip frequency offset. It is understood that using a term like "negative feedback adjustment value" indicates that when the amount of data to be transmitted stored in memory is large, it means that the current chip's transmission rate is slower than the reception rate (or the previous chip's transmission rate), resulting in more data accumulating in memory. Therefore, negative feedback adjustment of the transmission interval is needed to use a smaller transmission interval, thereby achieving a faster transmission rate and preventing memory overflow.

[0041] Figure 6 illustrates a data forwarding diagram following the implementation of a data frame interval adjustment mechanism according to an embodiment of this disclosure. It shows a first chip STACK1, a second chip STACK2, and a third chip STACK3, with at least a clock offset between the first and second chips. By adjusting the interval, it is ensured that the memory (e.g., a FIFO memory) does not overflow, thereby guaranteeing accurate inter-chip data transmission. It can be seen that after employing the dynamic adjustment of the data frame interval according to an embodiment of this disclosure, normal communication is possible even with a certain frequency offset.

[0042] Referring back to Figure 4, circuit 400 may also include memory 420, receiving circuit 430, and transmitting circuit 440.

[0043] The transmitting circuit 440 can be used to transmit data frames by using a determined interval time as the transmission interval between data frames. The interval time determination circuit 410 can be used to provide the generated or determined interval time value to the transmitting circuit (TXPHY) 440 for transmission.

[0044] The receiving circuit 430 can be used to receive data frames. For example, the interval determination circuit 410 can read signals related to the duration of the received frame from the receiving circuit (RXPHY) 430, such as the idle_filter_out signal that marks the start of the received frame.

[0045] The memory 420 can be used to store the received data frames. The interval time determination circuit 410 can read the current amount of data in the memory from the memory 420, such as the memory depth fifo_cnt[4:0]. As shown in Figure 4, the memory 420 can be a first-in-first-out FIFO memory, but this disclosure is not limited to this.

[0046] According to some embodiments, the adder circuit also determines the interval time based on an inherent time adjustment value, which is based on the frame structure of the data frame.

[0047] The method 700 for determining the interval time for inter-chip communication according to a variant of this disclosure will now be described with reference to FIG. 7. It will be understood that in FIG. 7, similar reference numerals as in FIG. 5 indicate similar steps; for example, step 510 may correspond to 710, step 520 may substantially correspond to 720, and step 530 may substantially correspond to step 730, and so on, and therefore repeated descriptions may be omitted. It will be understood that method 700 can also be implemented using the circuit shown in FIG. 4 or a variant thereof, and its details will not be repeated here.

[0048] At step 710, the duration of the received data frame can be obtained. Exemplarily, the time of each bit in the daisy chain during reception can be counted. Exemplarily, and for the convenience of the following description, the count result of the received frame duration can be denoted as A.

[0049] At step 715, a positive feedback adjustment value, also known as an intrinsic time adjustment value, can be obtained based on the frame structure of the data frame. The bit / bit interval time at transmission should be calculated as (A - intrinsic time), denoted as B, i.e., B = (A - intrinsic time), where the intrinsic time is the intrinsic time defined in the communication frame format. For example, this step can be referred to as the coarse adjustment positive feedback step.

[0050] At step 720, a negative feedback adjustment value can be obtained based on the amount of data to be transmitted stored in the memory. For example, the amount of data in the memory (e.g., FIFO) can be monitored, and a fine-tuning correction amount for the bit / bit interval time during transmission, denoted as C, can be calculated based on the amount of data. Exemplarily, this step can be referred to as the fine-tuning negative feedback step. As described above, "negative feedback" here means that when the amount of data to be transmitted stored in the memory is large, a smaller transmission interval will be used, thereby speeding up the transmission rate and preventing memory overflow.

[0051] At step 730, the interval time can be determined based on the received frame duration, the positive feedback adjustment value, and the negative feedback adjustment value, and this interval time can be used as the transmission interval between data frames. Continuing the example above, the coarse-adjustment positive feedback and fine-adjustment negative feedback algorithms can be combined to calculate the final bit / bit interval time at transmission as D, i.e., D = BC = A - inherent time - C.

[0052] It is understood that although the steps in Figures 5 and 7 are described in a specific order, this does not require that the steps be performed in that order. For example, step 715 may be performed after step 720. Alternatively, step 715 may be combined with step 720, and in such a case, the combined step 715 and step 720 may be analogous to step 520 described in Figure 5. As a specific non-limiting example, step 715 may be performed by adder 413 in Figure 4, but this disclosure is not limited thereto.

[0053] For example, the inherent time adjustment value may represent the standard data frame time defined in the frame format. In such an example, adder circuitry may be used to subtract the inherent time adjustment value from the received frame duration. For example, when the frame structure of the data frame is fixed, this feedback value may be built into the adder in the circuit, or it may be built into other parts of the circuit. As another embodiment, when the frame structure of the data frame is adjustable or partially adjustable, the feedback value may be input into the circuit through various circuit elements or structures (not shown) that can be understood by those skilled in the art, such as input into the adder.

[0054] According to some embodiments, the standard data frame time includes header time, valid data time, and tail time.

[0055] Figure 8 illustrates an exemplary communication frame format. In this exemplary communication frame format, each bit has a 1.375µs bus idle time (idle time 1) at the beginning, a 6.5µs nominal time in the middle, and a 0.5µs data short time at the end; in addition, there is an interval between each data frame, i.e., between bits. Various embodiments of this disclosure propose a scheme for adjusting the idle time 2, including corresponding methods, circuits, and chips. By dynamically adjusting this interval between data frames, tolerance to asynchronous communication frequency offset can be achieved. It is understood that the communication frame format shown herein is merely an example, and the embodiments of this disclosure can be applied to various data frame formats, as long as there is an interval between data frames.

[0056] Table 1 illustrates an improved communication frame format according to exemplary embodiments of the present disclosure, including fixed time and adjustable interval time.

[0057]

[0058] As a specific, non-limiting example, the steps of "determining the interval time based on the inherent time adjustment value" or the "coarse-adjustment positive feedback algorithm" as referred to in this paper can be implemented using the following formula.

[0059]

[0060] Wherein, interval time is the interval time, input delay cnt is the duration of the received frame, clk period is the clock cycle, bus idle time is the bus idle time defined in the data frame, nominal time is the nominal bit time, and bus short time is the data tail time.

[0061] In some embodiments, the above formula can be modified as follows:

[0062]

[0063] Referring to Figure 4, The clock cycle clk_8M in the diagram is... The duration of the received frame can be indicated by inputting counter 411 into adder 413. In such an example, the nominal bit time and data tail time can be fixed, for example, 56 clock cycles, and can be written to the adder at a fixed value. In such an example, The clock cycle corresponding to the bus idle time, which may be adjustable or not written to the circuit for other reasons, may be input to the interval time register 415. It is understood that the above is merely an example, and this disclosure is not limited thereto. For example, in other embodiments, the time corresponding to the entire data frame format may be written to the adder, input to the adder via circuitry, or input, stored, or calculated via other elements of the circuitry.

[0064] Referring back to Figure 4, exemplarily, the counter circuit can be configured to convert the duration of receiving a single data frame into a clock count, based on the current clock of the receiving chip, as the duration of the received frame.

[0065] Referring to Figure 9, the waveform of the circuit implementation of the inter-frame interval adjustment algorithm is shown. Figure 9 shows the communication received signal com_rx. As shown in Figure 4, the receiving circuit 430 can receive the communication received signal com_rx. The duration of the received frame can be obtained by counting com_rx.

[0066] According to some embodiments, circuit 400 may further include an edge detector configured to: obtain a delayed idle signal by delaying a received idle signal representing idle time in the receiving circuit; and obtain an idle edge pulse signal based on the idle signal and the delayed idle signal. In such an embodiment, a counter circuit may be configured to obtain the duration of the received frame by accumulating counts of two adjacent idle edge pulse signals.

[0067] Referring back to Figure 4, a negative edge detector 414 is shown, which receives the idle signal idle_filter_out from the receiving circuit RXPHY and outputs a falling edge pulse signal idle_neg. As shown in Figure 9, idle_filter_out can correspond to the idle time in the communication received signal com_rx. The interval time determination circuit can delay the received idle_filter_out signal by one clock cycle to obtain the delayed idle signal idle_d1. The falling edge pulse signal idle_neg is obtained by performing combinational logic operations on idle_filter_out and idle_d1. Then, by accumulating the two idle_neg signals, input_delay_cnt[7:0] can be obtained, which reflects the time of each bit of the received (RX) communication frame.

[0068] For example, the data to be transmitted can be stored in the memory first, and the interval determination circuit will also monitor the data storage depth in the memory. Taking a FIFO memory with a depth of 16 as an example, the fifo_cnt[4:0] signal can be read, for example, stored in buffer 416, and used to output the fifo_max_tmp[4:0] signal to the decoder 412. Referring back to Figure 9, the value of the fifo_cnt[4:0] signal reflects the amount of data in the FIFO. The larger the amount of data, the faster the RX and the slower the TX. At this time, the TX interval should be reduced.

[0069] As shown in Figure 4, the decoder circuit can receive the amount of data to be transmitted from the memory 420, such as the FIFO depth count values ​​fifo_cnt[4:0]. The FIFO depth count values ​​fifo_cnt[4:0] can be stored in the buffer fifo_max_tmp[4:0], and then read by the decoder and converted into negative feedback adjustment values ​​fifo_tune[7:0] based on predetermined rules. According to some embodiments, the decoder circuit is configured to determine the negative feedback adjustment value based on the amount of data to be transmitted stored in the memory using a decoding table.

[0070] Continuing with the exemplary formula above, the following formula can be used to further adjust based on the negative feedback adjustment value:

[0071]

[0072] in, This indicates the duration of the received frame, as shown in Figure 4 or Figure 9. The clock cycles corresponding to the bus idle time are 56, which represents the number of clock cycles corresponding to the nominal bit time and the data tail time. fifo_tune[7:0] can be obtained by decoding fifo_max_tmp. For example, input delay cnt and fifo tune are calculated values ​​under the current chip clock cycle of, for example, 8 MHz.

[0073] Table 2 provides exemplary decoded values ​​for negative feedback adjustment, still using a FIFO memory with a depth of 16 as an example. The left column gives the amount of data currently stored in the memory (FIFO depth) fifo_max_tmp[4:0], and the right column gives the negative feedback adjustment value -fifo_tune[7:0], where the negative sign indicates that the absolute value of the represented value will be subtracted from it. It is understood that the following table may be derived empirically, and the following values ​​are merely examples, and this disclosure is not limited thereto.

[0074]

[0075] According to other embodiments, the decoder circuit is configured to determine a negative feedback adjustment value based on the amount of data to be transmitted stored in the memory using a piecewise function, the piecewise function being used to characterize that: when the amount of data to be transmitted stored in the memory does not exceed a predetermined proportion of the capacity of the memory, the negative feedback adjustment value is a fixed value; and when the amount of data to be transmitted exceeds the predetermined proportion, the absolute value of the negative feedback adjustment value is positively correlated with the amount of data to be transmitted.

[0076] In some embodiments, the fixed value is 0. In such examples, negative feedback adjustment is not required when the amount of data to be sent stored in the memory does not exceed a predetermined proportion of the memory's capacity.

[0077] According to some embodiments, the predetermined ratio is 50%. In such an example, when the amount of data to be sent stored in the memory exceeds half the capacity of the memory, the absolute value of the negative feedback adjustment value is further increased as the amount increases, thereby more effectively avoiding memory overflow and ensuring correct and efficient data communication.

[0078] As a specific, non-limiting embodiment, when using a piecewise function to characterize the negative feedback adjustment value, a function of the form of the following (still taking a memory depth of 16 as an example) can be used to calculate the negative feedback adjustment value, where x is the amount stored in the memory, and y is the adjustment value (a negative value indicates a reduction in the interval time):

[0079]

[0080] Referring back to Figure 9, since the clock of the receiving chip is faster than the clock of the transmitting chip, both input_delay_cnt[7:0] and FIFO_cnt[4:0] are relatively large. In this case, the interval_time_trans[7:0] output by the interval determination circuit is reduced from 24 to 18, and the TXPHY module will transmit the bits of the communication frame at a smaller interval.

[0081] Referring back to Figure 4, circuit 400 may, by way of example, further include an interval time register 415. The interval time register 415 can be used to temporarily store the currently calculated interval time. In such an embodiment, the transmitting circuit can be configured to read the currently stored interval time interval_time_trans[7:0] from the interval time register based on the transmitting status signal tstate[4:0] for transmitting a data frame.

[0082] In addition, Figure 4 also includes a register module REG for storing and transmitting data, a delay response signal comm_conf_stk_resp_dly[1:0], a push data or control signal tx_ipush_dc, a read data signal read_data_dc[7:0], a first multiplexer MUX1, a second decoder, and a second multiplexer MUX2. The first multiplexer MUX1 can be used to receive the local time interval signal interval_time_local[7:0] and the transmission time interval signal interval_time_trans[7:0] and generate the interval signal interval_time[7:0]. The second multiplexer MUX2 can be used to receive the read_data_dc[7:0] signal and generate the dc_data_sbit signal. Those skilled in the art will understand that these circuit portions are shown for the purpose of circuit integrity, but do not imply that the claimed solution requires these circuit portions. These circuit portions may be replaced by various similar circuit elements or circuit structures that can be understood by those skilled in the art, or these circuit portions may be omitted without affecting the circuit or method proposed according to one or more embodiments of this disclosure.

[0083] According to one or more embodiments of this disclosure, an inter-chip communication method 1000 is also provided. Referring to FIG10, exemplary steps of the inter-chip communication method 1000 are illustrated. It will be understood that the inter-chip communication method 1000 can be implemented using circuit 400 or various variations thereof, and the various details or variations described with respect to circuit 400, method 500 or method 700 also apply to method 1000, and therefore, for the sake of brevity, they will not be repeated herein.

[0084] At step 1010, a data frame is received.

[0085] In step 1020, the received data frame is stored.

[0086] At step 1030, the duration of the received frame is determined.

[0087] At step 1040, a negative feedback adjustment value is obtained based on the amount of stored data to be sent.

[0088] At step 1050, the interval time is determined based on the duration of the received frame and the negative feedback adjustment value.

[0089] At step 1060, data frames are transmitted by using the determined interval time as the transmission interval between data frames.

[0090] According to one or more embodiments of the present disclosure, a chip is also provided, including an inter-chip communication circuit according to various embodiments of the present disclosure or an interval time determination circuit for inter-chip communication according to various embodiments of the present disclosure.

[0091] According to one or more embodiments of this disclosure, communication can be made to cope with frequency offset by dynamically adjusting the interval between bits in the transmitted frame. The adjustment algorithm of the embodiments of this disclosure is simple, and the implementation circuit has a small area and low cost.

[0092] According to one or more embodiments of this disclosure, it is possible to ensure that communication has a certain frequency offset tolerance by adjusting the time interval between bits of the communication frame.

[0093] According to one or more embodiments of this disclosure, the interval time of inter-chip communication or data communication with an adjustable interval time can be achieved through coarse-adjustment positive feedback and fine-adjustment negative feedback algorithms. The coarse-adjustment positive feedback algorithm determines the bit interval at the TX end by monitoring the bit interval at the communication RX end. The fine-adjustment negative feedback algorithm determines the bit interval at the TX end by monitoring the number of data items in the memory.

[0094] According to one or more embodiments of this disclosure, asynchronous communication between chips can be made to have a certain frequency offset tolerance. The maximum adjustment capability of the adjustment algorithm is described below with reference to FIG11.

[0095] When the receiver is slow and the transmitter is fast, assuming the transmitting mechanism is that the transmitter waits for 5 bits of data to be stored in the FIFO before transmitting the first bit of data, the risk of the FIFO being empty is very small, and normal communication is possible. When the receiver is fast and the transmitter is slow, the interval time can be dynamically adjusted to ensure that the FIFO does not overflow, relying on the interval time determination circuit or method or communication circuit or method according to the embodiments of this disclosure. Continuing with the hypothetical example of frequency in Figures 3 and 6 above, if interval_time_trans[7:0] is at least 0, then the fastest data rate transmitted by the transmitter is 1 bit / (1.375us + 6.5us + 0.5us + 0us) = per bit / 8.375us. In other words, in such an example, the tolerable frequency deviation can reach (10.875 - 8.375) / 8.375 = 18.4%.

[0096] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practice with respect to the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "a plurality" means two or more, and the term "based on" should be interpreted as "at least partially based on". The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

Claims

An inter-chip communication circuit comprising: a receiving circuit for receiving data frames; a memory for storing the received data frames; a counter circuit for determining a reception frame duration elapsed for receiving a data frame; a decoder circuit for obtaining a negative feedback adjustment value based on an amount of data to be transmitted stored in the memory; an adder circuit for determining an interval time based on the reception frame duration and the negative feedback adjustment value; and a transmitting circuit for transmitting data frames by using the determined interval time as a transmission interval between data frames. The adder circuit determines the interval time further based on an intrinsic time adjustment value, which is based on a frame structure of the data frames. The inter-chip communication circuit according to claim 1, wherein The adder circuit is configured to subtract the intrinsic time adjustment value from the reception frame duration. The inter-chip communication circuit according to claim 2, the inherent time adjustment value represents a standard data frame time defined in a frame format, and wherein, The standard data frame time comprises a header time, a payload data time, and a trailer time. The inter-chip communication circuit according to claim 3, wherein The decoder circuit is configured to determine the negative feedback adjustment value based on the amount of data to be transmitted stored in the memory by a decoding table. The inter-chip communication circuit according to any one of claims 1 to 4, wherein The decoder circuit is configured to determine the negative feedback adjustment value based on the amount of data to be transmitted stored in the memory by a piecewise function, which is configured to characterize: The inter-chip communication circuit according to any one of claims 1 to 4, wherein a fixed value for the negative feedback adjustment value when the amount of data to be transmitted stored in the memory does not exceed a predetermined proportion of a capacity of the memory; and an absolute value of the negative feedback adjustment value positively correlating with the amount of data to be transmitted when the amount of data to be transmitted exceeds the predetermined proportion. The fixed value is 0. The inter-chip communication circuit according to claim 6, wherein The predetermined proportion is 50%. The inter-chip communication circuit according to claim 6, wherein The memory is a first-in-first-out (FIFO) memory. The inter-chip communication circuit according to any one of claims 1 to 4, wherein The counter circuit is configured to convert a duration of receiving a single data frame into a clock count based on a clock of a current receiving chip as the reception frame duration. The inter-chip communication circuit according to any one of claims 1 to 4, wherein The inter-chip communication circuit according to any one of claims 1-4, further comprising: an edge detector configured to: obtain a delayed idle signal by delaying a received idle signal representing an idle time in the receiving circuit; and obtain an idle edge pulse signal based on the idle signal and the delayed idle signal, and wherein the counter circuit is configured to obtain the reception frame duration by cumulatively counting two adjacent idle edge pulse signals. The inter-chip communication circuit according to any one of claims 1-4, further comprising: an interval time register for temporarily storing a currently calculated interval time; and wherein the transmitting circuit is configured to read a currently stored interval time from the interval time register based on a transmission state signal for use in transmitting data frames. An interval time determination circuit for inter-chip communication, comprising: a counter circuit for obtaining a reception frame duration elapsed for receiving a data frame; a decoder circuit for obtaining a negative feedback adjustment value based on an amount of data to be transmitted stored in a memory; and an adder circuit for determining an interval time based on the reception frame duration and the negative feedback adjustment value, which is used as a transmission interval between data frames. ​ ​ ​ A chip comprising the chip-to-chip communication circuit according to any one of claims 1-12 or the interval time determination circuit for chip-to-chip communication according to claim 13. A chip-to-chip communication method comprising: receiving a data frame; storing the received data frame; determining a reception frame duration elapsed for receiving the data frame; obtaining a negative feedback adjustment value based on an amount of data to be transmitted stored in a memory; determining an interval time based on the reception frame duration and the negative feedback adjustment value; and transmitting data frames with the determined interval time as a transmission interval between the data frames. An interval time determination method for chip-to-chip communication comprising: obtaining a reception frame duration elapsed for receiving a data frame; obtaining a negative feedback adjustment value based on an amount of data to be transmitted stored in a memory; and determining an interval time based on the reception frame duration and the negative feedback adjustment value, the interval time being used as a transmission interval between data frames. ​ ​

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