Information indication method, information determination method, apparatus, network element and device

Abstract

The present application provides an information indication method, an information determination method, an apparatus, a network element, and a device. The information indication method comprises: a first network element indicates first information to an A-IoT device in a first manner, the first manner comprising at least one of the following: a first field of a PRDCH, the chip rate of a first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH.

Description

Information indication method, information determination method, device, network element and equipment

[0001] The present disclosure claims priority to the Chinese patent publication with the publication number 202411015466.9 and the publication name "Information indication method, information determination method, device, network element and equipment" filed with the China Patent Office on July 26, 2024, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of communication, and particularly refers to an information indication method, an information determination method, a device, a network element and equipment. BACKGROUND

[0003] In order to support the interconnection of hundreds of billions of things and solve the network construction cost when a large number of things are interconnected and the high operating cost brought by the replacement of batteries and other later maintenance, a new Internet of Things (IoT) device type, Ambient IoT (A-IoT), is designed in the 5G system. A-IoT devices do not have or only have limited energy storage capabilities, have low complexity, low cost and low power consumption, which will help to realize the perception and interconnection of all things.

[0004] In A-IoT communication, a reader such as a base station or a terminal sends an A-IoT downlink channel to an A-IoT device to indicate different types of A-IoT devices to complete the backscattering of incident signals or to autonomously send an uplink response signal. The A-IoT device receives the information such as the chip length used by the reader to send the PRDCH.

[0005] Since there is no broadcast channel in the A-IoT system, these information cannot be notified to the A-IoT device in the form of broadcast. Therefore, how the reader notifies the transmission parameters of the A-IoT downlink channel to the A-IoT device so that the A-IoT device can receive and demodulate the A-IoT downlink channel based on the chip length information used by the A-IoT downlink channel becomes an important problem to be solved. SUMMARY

[0006] Embodiments of the present disclosure aim to provide an information indication method, an information determination method, a device, a network element and equipment to solve the problem that the related parameters of the A-IoT downlink channel cannot be transmitted due to the lack of a broadcast channel in the A-IoT system.

[0007] To solve the above problem, an information indication method is provided in the embodiments of the present disclosure, and the method comprises:

[0008] The first network element indicates the first information to the environment Internet of Things A-IoT device through a first mode, the first mode comprising at least one of the following:

[0009] a first field of a physical reader to device channel (PRDCH);

[0010] a chip rate of the first signal;

[0011] a chip length of the first signal;

[0012] a chip rate of the first field of the PRDCH;

[0013] a chip length of the first field of the PRDCH;

[0014] wherein the first signal is any one of the following: a reader to device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, a clock acquisition component;

[0015] wherein the first information comprises at least one of the following: an R2D chip length, an on-off keying (OOK) chip length, a device to reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of the PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of a physical device to reader channel (PDRCH), a chip length of the PDRCH, a chip length of the PDRCH; the chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

[0016] wherein the first network element comprises at least one of the following: a base station, a terminal, a reader, an intermediate node.

[0017] wherein the start indication component comprises at least one of the following: a start indication component in the R2D preamble, a start indication component in the R2D time acquisition signal, a start indication component in the R2D timing acquisition signal;

[0018] or

[0019] the clock acquisition component comprises at least one of the following: a clock acquisition component in the R2D preamble, a clock acquisition component in the R2D time acquisition signal, a clock acquisition component in the R2D timing acquisition signal.

[0020] The second field of the PRDCH is any of the following:

[0021] The other field of the PRDCH except the first field;

[0022] The data field of the PRDCH;

[0023] The control field of the PRDCH;

[0024] The other control field of the control field of the PRDCH except the first field.

[0025] The first information has different values, and the patterns of the first signals corresponding to the different values are the same.

[0026] The first information has different values, and the patterns of the first signals corresponding to the different values are the same, including at least one of the following:

[0027] Different R2D chip lengths correspond to the same pattern of the first signal;

[0028] Different OOK chip lengths correspond to the same pattern of the first signal;

[0029] Different D2R chip lengths correspond to the same pattern of the first signal;

[0030] Different chip rates of the second field of the PRDCH correspond to the same pattern of the first signal;

[0031] Different chip lengths of the second field of the PRDCH correspond to the same pattern of the first signal.

[0032] The pattern of the start indication component is a first pattern; and / or,

[0033] The pattern of the clock acquisition component is a second pattern.

[0034] The chip rate of the clock acquisition component is a first preconfigured value;

[0035] Or,

[0036] The chip rate of the first field of the PRDCH is a second preconfigured value;

[0037] Or,

[0038] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0039] The first field of the PRDCH is used to indicate the ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0040] Or,

[0041] The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0042] The patterns of the first signals are the same, including:

[0043] The time domain lengths of the first signals are the same;

[0044] Or,

[0045] The time domain lengths of the first signals and the used sequences are the same;

[0046] Or,

[0047] The time domain lengths of the first signals and the used sequences are the same, and the combination of the high voltage and the low voltage of the first signals is the same.

[0048] The combination of the high voltage and the low voltage of the first signals is the same, including:

[0049] The number of the high voltage and the low voltage of the first signals is the same, and the appearance order of the high voltage and the low voltage of the first signals is the same.

[0050] The start indicating component and the clock obtaining component satisfy the following conditions:

[0051] The total length of the start indicating component and the clock obtaining component is 1 Orthogonal Frequency Division Multiplexing (OFDM) symbol;

[0052] The length of the start indicating component is 1 / 4 OFDM symbol, and the length of the clock obtaining component is 3 / 4 OFDM symbol;

[0053] The start indicating component is composed of a low voltage with a duration of 1 chip and a high voltage with a duration of 3 chips, and the chip rate of the start indicating component is 16;

[0054] The clock obtaining component is composed of different sequences, and the chip rate of the clock obtaining component is 8;

[0055] The last bit of the clock obtaining component is 1;

[0056] The cyclic prefix (CP) of the clock acquisition component is high voltage;

[0057] Different sequences of the clock acquisition component are used to indicate different chip rates.

[0058] The start indication component and the clock acquisition component satisfy the following conditions:

[0059] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0060] The length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0061] The start indication component is composed of low voltage with a duration of 1 chip and high voltage with a duration of 3 chips, and the chip rate of the start indication component is 16;

[0062] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16;

[0063] The cyclic prefix (CP) of the clock acquisition component is a combination of low voltage and high voltage;

[0064] Different sequences of the clock acquisition component are used to indicate different chip rates.

[0065] The embodiments of the present disclosure also provide an information determination method, which comprises:

[0066] The A-IoT device determines first information according to a first mode; the first mode comprises at least one of the following:

[0067] A first field of a PRDCH;

[0068] The chip rate of the first signal;

[0069] The chip length of the first signal;

[0070] The chip rate of the first field of the PRDCH;

[0071] The chip length of the first field of the PRDCH;

[0072] The first signal is any one of the following signals: a R2D preamble, a R2D time acquisition signal, a R2D timing acquisition signal, a start indication component, and a clock acquisition component;

[0073] The first information includes at least one of the following: a reader-to-device (R2D) chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of a PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of the PDRCH, a chip length of the PRDCH, and a chip length of the PDRCH. The chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

[0074] The first network element includes a memory, a transceiver, and a processor.

[0075] The memory is configured to store a computer program. The transceiver is configured to transceive data under control of the processor. The processor is configured to read the computer program in the memory and perform the following operations:

[0076] The first information is indicated to an ambient Internet of Things (A-IoT) device by a first mode. The first mode includes at least one of the following:

[0077] A first field of a physical reader-to-device channel (PRDCH);

[0078] A chip rate of the first signal;

[0079] A chip length of the first signal;

[0080] A chip rate of the first field of the PRDCH;

[0081] A chip length of the first field of the PRDCH;

[0082] The first signal is any one of the following: a reader-to-device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, and a clock acquisition component.

[0083] The first information includes at least one of the following: a reader-to-device (R2D) chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of a PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of the PDRCH, a chip length of the PRDCH, and a chip length of the PDRCH. The chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

[0084] The first network element includes at least one of the following: a base station, a terminal, a reader, and an intermediate node.

[0085] The start indication component includes at least one of the following: a start indication component in the R2D preamble, a start indication component in the R2D time acquisition signal, a start indication component in the R2D timing acquisition signal.

[0086] Alternatively,

[0087] The clock acquisition component includes at least one of the following: a clock acquisition component in the R2D preamble, a clock acquisition component in the R2D time acquisition signal, a clock acquisition component in the R2D timing acquisition signal.

[0088] The second field of the PRDCH is any of the following:

[0089] A field other than the first field in the PRDCH;

[0090] A data domain field of the PRDCH;

[0091] A control domain field of the PRDCH;

[0092] A control domain field other than the first field in the control domain field of the PRDCH.

[0093] Different values of the first information correspond to the same pattern of the first signal.

[0094] Different values of the first information correspond to the same pattern of the first signal, including at least one of the following:

[0095] Different R2D chip lengths correspond to the same pattern of the first signal;

[0096] Different OOK chip lengths correspond to the same pattern of the first signal;

[0097] Different D2R chip lengths correspond to the same pattern of the first signal;

[0098] Different chip rates of the second field of the PRDCH correspond to the same pattern of the first signal;

[0099] Different chip lengths of the second field of the PRDCH correspond to the same pattern of the first signal.

[0100] The pattern of the start indication component is a first pattern; and / or,

[0101] The pattern of the clock acquisition component is a second pattern.

[0102] The chip rate of the clock acquisition component is a first preconfigured value;

[0103] Alternatively,

[0104] The chip rate of the first field of the PRDCH is a preconfigured second value.

[0105] Alternatively,

[0106] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0107] The first field of the PRDCH is used to indicate proportion information, which is used to indicate the proportion of the chip rate of the second field of the PRDCH relative to the chip rate of the first signal, or to indicate the proportion of the chip rate of the second field of the PRDCH relative to the chip rate of the first field of the PRDCH.

[0108] Alternatively,

[0109] The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0110] The first signal has the same pattern, including:

[0111] The first signal has the same time domain length;

[0112] Alternatively,

[0113] The first signal has the same time domain length and the same used sequence;

[0114] Alternatively,

[0115] The first signal has the same time domain length and the same used sequence, and the combination of high voltage and low voltage of the first signal is the same.

[0116] The combination of high voltage and low voltage of the first signal is the same, including:

[0117] The number of high voltage and low voltage of the first signal is the same, and the appearance order of high voltage and low voltage of the first signal is the same.

[0118] The start indication component and the clock acquisition component satisfy the following conditions:

[0119] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0120] The length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0121] The start indication component is composed of low voltage with a duration of 1 chip and high voltage with a duration of 3 chips, and the chip rate of the start indication component is 16;

[0122] The clock acquisition component is composed of different sequences, and a chip rate of the clock acquisition component is 8;

[0123] The last bit of the clock acquisition component is 1;

[0124] The cyclic prefix CP of the clock acquisition component is high voltage;

[0125] Different chip rates are indicated using different sequences of the clock acquisition component.

[0126] The start indication component and the clock acquisition component satisfy the following conditions:

[0127] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0128] The length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0129] The start indication component is composed of low voltage with a duration of 1 chip and high voltage with a duration of 3 chips, and a chip rate of the start indication component is 16;

[0130] The clock acquisition component is composed of different sequences, and a chip rate of the clock acquisition component is 16;

[0131] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0132] Different chip rates are indicated using different sequences of the clock acquisition component.

[0133] The embodiments of the present disclosure further provide an environmental Internet of Things (A-IoT) device, comprising a memory, a transceiver, and a processor:

[0134] The memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; and the processor is configured to read the computer program in the memory and perform the following operations:

[0135] According to a first mode, first information is determined; the first mode includes at least one of the following:

[0136] A first field of a physical reader-to-device channel (PRDCH);

[0137] A chip rate of the first signal;

[0138] A chip length of the first signal;

[0139] A chip rate of the first field of the PRDCH;

[0140] The chip length of the first field of PRDCH;

[0141] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0142] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0143] This disclosure also provides an information indicating device, including:

[0144] The indicating unit is configured to indicate first information to an environmental Internet of Things (A-IoT) device via a first method, wherein the first method includes at least one of the following:

[0145] The first field of the Physical Reader to Device Channel (PRDCH);

[0146] Chip rate of the first signal;

[0147] Chip length of the first signal;

[0148] The chip rate of the first field of PRDCH;

[0149] The chip length of the first field of PRDCH;

[0150] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0151] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0152] This disclosure also provides an information determining device, the device comprising:

[0153] The determining unit is configured to determine first information according to a first method; the first method includes at least one of the following:

[0154] The first field of the Physical Reader to Device Channel (PRDCH);

[0155] Chip rate of the first signal;

[0156] Chip length of the first signal;

[0157] The chip rate of the first field of PRDCH;

[0158] The chip length of the first field of PRDCH;

[0159] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0160] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0161] This disclosure also provides a processor-readable storage medium storing a program for causing the processor to perform the method described above.

[0162] The above-disclosed technical solution has at least the following beneficial effects:

[0163] In the information indication method, information determination method, apparatus, network element, and device of this disclosure, the first network element indicates first information to the A-IoT device through at least one of the following: the first field of PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of PRDCH, and the chip length of the first field of PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, the chip rate of the second field of PRDCH, the chip length of the second field of PRDCH, the chip rate of PRDCH, the chip rate of PDRCH, the chip length of PRDCH, and the chip length of PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode PRDCH based on the obtained transmission parameters such as chip length or chip rate, improving the flexibility of PRDCH transmission parameter configuration and also improving the transmission spectrum efficiency of the A-IoT system. Attached Figure Description

[0164] Figure 1 shows a block diagram of a wireless communication system to which embodiments of the present disclosure may be applied;

[0165] Figure 2 is a schematic diagram illustrating the steps of the information indication method provided in an embodiment of this disclosure;

[0166] Figure 3 is a schematic diagram illustrating the steps of the information determination method provided in an embodiment of this disclosure;

[0167] Figure 4 shows a schematic diagram of the principle of Example 1 provided in the embodiments of this disclosure;

[0168] Figure 5 shows a schematic diagram of the principle of Example 2 provided in the embodiments of this disclosure;

[0169] Figure 6 shows a schematic diagram of the principle of Example 3 provided in the embodiments of this disclosure;

[0170] Figure 7 shows a schematic diagram of Example 4 provided in the embodiments of this disclosure;

[0171] Figure 8 illustrates the interaction diagram of Example 5 provided in the embodiments of this disclosure;

[0172] Figure 9 shows a schematic diagram of Example Six provided in the embodiments of this disclosure;

[0173] Figure 10 shows a schematic diagram of Example Seven provided in the embodiments of this disclosure;

[0174] Figure 11 shows a schematic diagram of the structure of the first network element provided in an embodiment of this disclosure;

[0175] Figure 12 shows a schematic diagram of the structure of the A-IoT device provided in an embodiment of this disclosure;

[0176] Figure 13 shows a schematic diagram of the structure of the information indication device provided in an embodiment of this disclosure;

[0177] Figure 14 shows a schematic diagram of the information determination device provided in an embodiment of this disclosure. Detailed Implementation

[0178] To make the technical problems, solutions, and advantages of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0179] Figure 1 shows a block diagram of a wireless communication system applicable to an embodiment of this disclosure. The wireless communication system includes a terminal device 11 and a network-side device 12. The terminal device 11 can also be referred to as a terminal or user equipment (UE). It should be noted that the specific type of terminal 11 is not limited in this embodiment. The network-side device 12 can be a base station or a core network. It should be noted that this embodiment only uses a base station in an NR system as an example, but does not limit the specific type of base station.

[0180] In this disclosure, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0181] In this disclosure, the term "multiple" refers to two or more, and other quantifiers are similar.

[0182] The technical solutions provided in this disclosure can be applied to a variety of systems. For example, applicable systems may include Long Term Evolution (LTE) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, Long Term Evolution Advanced (LTE-A) systems, Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX) systems, 5th Generation (5G) New Radio (NR) systems and their evolution communication systems, and 6th Generation (6G) systems. These systems may include terminal equipment and network equipment. The systems may also include a core network component, such as an Evolved Packet Core (EPC) or a 5G Core (5GC).

[0183] The terminal devices involved in the embodiments of this disclosure can be devices that provide voice and / or data connectivity to users, handheld devices with wireless connectivity, or other processing devices connected to a wireless modem. The names of the terminal devices may differ in different systems; for example, in a 5G system, a terminal device can be called User Equipment (UE). Wireless terminal devices can communicate with one or more core networks (CNs) via a Radio Access Network (RAN). Wireless terminal devices can be mobile terminal devices, such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, for example, portable, pocket-sized, handheld, computer-embedded, or vehicle-mounted mobile devices that exchange voice and / or data with the RAN. Examples include Personal Communication Service (PCS) phones, cordless phones, Session Initiated Protocol (SIP) phones, Wireless Local Loop (WLL) stations, and Personal Digital Assistants (PDAs). Wireless terminal equipment can also be referred to as a system, subscriber unit, subscriber station, mobile station, mobile station, remote station, access point, remote terminal, access terminal, user terminal, user agent, or user device, but is not limited to these terms in the embodiments disclosed herein.

[0184] The network device disclosed in this embodiment may be a base station, which may include multiple cells providing services to terminals. Depending on the specific application, the base station may also be called an access point, or a device in the access network that communicates with the wireless terminal device through one or more sectors on the air interface, or other names. The network device may be used to exchange received air frames with Internet Protocol (IP) packets, acting as a router between the wireless terminal device and the rest of the access network, where the rest of the access network may include an Internet Protocol (IP) communication network. The network device may also coordinate the attribute management of the air interface. For example, the network equipment involved in this disclosure can be a base transceiver station (BTS) in a Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA) system, a NodeB in a wide-band Code Division Multiple Access (WCDMA) system, an evolved Node B (eNB or e-NodeB) in a long term evolution (LTE) system, a 5G base station (gNB) in a next generation system, a Home evolved Node B (HeNB), a relay node, a femto, a pico, etc., and is not limited in this disclosure. In some network structures, the network equipment may include centralized unit (CU) nodes and distributed unit (DU) nodes, and the centralized unit and distributed unit may be geographically separated.

[0185] Network devices and terminal devices can each use one or more antennas for Multiple Input Multiple Output (MIMO) transmission. MIMO transmission can be Single User MIMO (SU-MIMO) or Multiple User MIMO (MU-MIMO). Depending on the configuration and number of antenna combinations, MIMO transmission can be 2D MIMO, 3D MIMO, Full Dimension MIMO (FD-MIMO), or Massive MIMO, or it can be diversity transmission, pre-coded transmission, or beamforming transmission, etc.

[0186] Currently, A-IoT devices can be divided into the following three types:

[0187] Type 1 devices: Peak power consumption is approximately 1 μW, with energy storage capability, initial sampling frequency offset (SFO) up to 10X ppm, and the devices lack both downlink (DL) and uplink (UL) amplification. The device's UL transmission is achieved through backscattering on an externally provided carrier.

[0188] Type 2a devices: Peak power consumption ≤ several hundred μW, with energy storage capability, initial sampling frequency offset (SFO) up to 10X ppm, and DL and / or UL amplification capabilities. The device's UL transmission is backscattered on an externally provided carrier.

[0189] Type 2b devices: Peak power consumption ≤ several hundred μW, with energy storage capability, initial sampling frequency offset (SFO) up to 10X ppm, and DL and / or UL amplification capabilities. The UL transmission of the device is generated internally.

[0190] As shown in Figure 2, this embodiment of the present disclosure provides an information indication method, the method comprising:

[0191] Step 201: The first network element indicates first information to the environmental Internet of Things (A-IoT) device through a first method, wherein the first method includes at least one of the following:

[0192] The first field of the Physical Reader to Device Channel (PRDCH);

[0193] Chip rate of the first signal;

[0194] Chip length of the first signal;

[0195] The chip rate of the first field of PRDCH;

[0196] The chip length of the first field of PRDCH;

[0197] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0198] The first information includes at least one of the following: reader-to-device R2D chip length, on / off keying OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an orthogonal frequency division multiplexing (OFDM) symbol.

[0199] In this embodiment of the disclosure, the first network element indicates first information to the A-IoT device through at least one of the following methods: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of the PRDCH, chip length of the second field of the PRDCH, chip rate of the PRDCH, chip rate of the PDRCH, chip length of the PRDCH, and chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0200] As an optional embodiment, the first network element includes at least one of the following: a base station, a terminal, a reader, and an intermediate node.

[0201] As another optional embodiment, the start indication component includes at least one of the following: a start indication component in an R2D preamble, a start indication component in an R2D time acquisition signal, and a start indication component in an R2D timing acquisition signal;

[0202] Alternatively, the clock acquisition component may include at least one of the following: a clock acquisition component in an R2D preamble, a clock acquisition component in an R2D time acquisition signal, or a clock acquisition component in an R2D timing acquisition signal.

[0203] In at least one embodiment of this disclosure, the second field of the PRDCH is any one of the following:

[0204] Other fields in PRDCH besides the first field;

[0205] PRDCH data field;

[0206] PRDCH control field;

[0207] The control field fields of PRDCH, excluding the first field.

[0208] In at least one embodiment of this disclosure, the patterns of the first signals corresponding to different values ​​of the first information are the same.

[0209] Optionally, the patterns of the first signal corresponding to different values ​​of the first information are the same, including at least one of the following:

[0210] The pattern of the first signal is the same for different R2D chip lengths;

[0211] The pattern of the first signal is the same for different OOK chip lengths;

[0212] The pattern of the first signal is the same for different D2R chip lengths;

[0213] The patterns of the first signal are the same for different chip rates in the second field of PRDCH;

[0214] The pattern of the first signal is the same for different chip lengths of the second field of PRDCH.

[0215] As an optional embodiment, the pattern of the first signal includes:

[0216] The first signal has the same time domain length;

[0217] or,

[0218] The first signal has the same time domain length and uses the same sequence.

[0219] or,

[0220] The first signal has the same time domain length and uses the same sequence, and the combination of high and low voltages in the first signal is the same.

[0221] Optionally, the combination of high voltage and low voltage in the first signal is the same, including:

[0222] The first signal has the same number of high voltage and low voltage signals, and the high voltage and low voltage signals appear in the same order.

[0223] In at least one alternative embodiment of this disclosure, the pattern of the start indicator component is a first pattern; and / or, the pattern of the clock acquisition component is a second pattern.

[0224] For example, the first pattern and the second pattern are both fixed patterns. That is, the start indicator and the clock acquisition component both have fixed patterns.

[0225] In at least one alternative embodiment of this disclosure,

[0226] The chip rate of the clock acquisition component is a pre-configured first value;

[0227] or,

[0228] The chip rate of the first field of the PRDCH is a pre-configured second value;

[0229] or,

[0230] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0231] For example, the first and second values ​​are pre-configured fixed values, such as the chip rate of the clock acquisition component being 8 or other values; or, the chip rate of the first field of the PRDCH can be the same as or different from the chip rate of the clock acquisition component.

[0232] As an optional embodiment, the first field of the PRDCH is used to indicate ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0233] For example, the first field of PRDCH indicates the ratio of the chip rate used in the PRDCH data field to the chip rate of the clock acquisition signal, such as 1 / 8, 1 / 4, 1 / 2, 1, 2, 3, etc.

[0234] For example, the first field of PRDCH indicates the ratio of the chip rate of the PRDCH data field to the chip rate of the first field of PRDCH, such as 1 / 8, 1 / 4, 1 / 2, 1, 2, 3, etc.

[0235] As another optional embodiment, the first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0236] For example, the first field of PRDCH indicates the chip rate used by the PRDCH data field, such as 1, 2, 4, 8, 16, 24, etc.

[0237] In one implementation of this disclosure, the start indication component and the clock acquisition component satisfy the following conditions:

[0238] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0239] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0240] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0241] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8.

[0242] The last bit of the clock acquisition component is 1;

[0243] The cyclic prefix CP of the clock acquisition component is high voltage;

[0244] Different sequences of the clock acquisition component indicate different chip rates.

[0245] In another implementation of this disclosure, the start indication component and the clock acquisition component satisfy the following conditions:

[0246] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0247] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0248] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0249] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16.

[0250] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0251] Different sequences of the clock acquisition component indicate different chip rates.

[0252] In this embodiment of the disclosure, the first network element indicates first information to the A-IoT device through at least one of the following methods: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of the PRDCH, chip length of the second field of the PRDCH, chip rate of the PRDCH, chip rate of the PDRCH, chip length of the PRDCH, and chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0253] As shown in Figure 3, this embodiment of the present disclosure also provides an information determination method, the method comprising:

[0254] An environmental Internet of Things (A-IoT) device determines first information according to a first method; the first method includes at least one of the following:

[0255] The first field of the Physical Reader to Device Channel (PRDCH);

[0256] Chip rate of the first signal;

[0257] Chip length of the first signal;

[0258] The chip rate of the first field of PRDCH;

[0259] The chip length of the first field of PRDCH;

[0260] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0261] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0262] In this embodiment of the disclosure, the A-IoT device determines first information based on at least one of the following: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, the chip rate of the second field of the PRDCH, the chip length of the second field of the PRDCH, the chip rate of the PRDCH, the chip rate of the PDRCH, the chip length of the PRDCH, and the chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0263] As another optional embodiment, the start indication component includes at least one of the following: a start indication component in an R2D preamble, a start indication component in an R2D time acquisition signal, and a start indication component in an R2D timing acquisition signal;

[0264] Alternatively, the clock acquisition component may include at least one of the following: a clock acquisition component in an R2D preamble, a clock acquisition component in an R2D time acquisition signal, or a clock acquisition component in an R2D timing acquisition signal.

[0265] In at least one embodiment of this disclosure, the second field of the PRDCH is any one of the following:

[0266] Other fields in PRDCH besides the first field;

[0267] PRDCH data field;

[0268] PRDCH control field;

[0269] The control field fields of PRDCH, excluding the first field.

[0270] In at least one embodiment of this disclosure, the patterns of the first signals corresponding to different values ​​of the first information are the same.

[0271] Optionally, the patterns of the first signal corresponding to different values ​​of the first information are the same, including at least one of the following:

[0272] The pattern of the first signal is the same for different R2D chip lengths;

[0273] The pattern of the first signal is the same for different OOK chip lengths;

[0274] The pattern of the first signal is the same for different D2R chip lengths;

[0275] The patterns of the first signal are the same for different chip rates in the second field of PRDCH;

[0276] The pattern of the first signal is the same for different chip lengths of the second field of PRDCH.

[0277] As an optional embodiment, the pattern of the first signal includes:

[0278] The first signal has the same time domain length;

[0279] or,

[0280] The first signal has the same time domain length and uses the same sequence.

[0281] or,

[0282] The first signal has the same time domain length and uses the same sequence, and the combination of high and low voltages in the first signal is the same.

[0283] Optionally, the combination of high voltage and low voltage in the first signal is the same, including:

[0284] The first signal has the same number of high voltage and low voltage signals, and the high voltage and low voltage signals appear in the same order.

[0285] In at least one alternative embodiment of this disclosure, the pattern of the start indicator component is a first pattern; and / or, the pattern of the clock acquisition component is a second pattern.

[0286] For example, the first pattern and the second pattern are both fixed patterns. That is, the start indicator and the clock acquisition component both have fixed patterns.

[0287] In at least one alternative embodiment of this disclosure, the chip rate of the clock acquisition component is a pre-configured first value;

[0288] or,

[0289] The chip rate of the first field of the PRDCH is a pre-configured second value;

[0290] or,

[0291] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0292] For example, the first and second values ​​are pre-configured fixed values, such as the chip rate of the clock acquisition component being 8 or other values; or, the chip rate of the first field of the PRDCH can be the same as or different from the chip rate of the clock acquisition component.

[0293] As an optional embodiment, the first field of the PRDCH is used to indicate ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0294] For example, the first field of PRDCH indicates the ratio of the chip rate used in the PRDCH data field to the chip rate of the clock acquisition signal, such as 1 / 8, 1 / 4, 1 / 2, 1, 2, 3, etc.

[0295] For example, the first field of PRDCH indicates the ratio of the chip rate of the PRDCH data field to the chip rate of the first field of PRDCH, such as 1 / 8, 1 / 4, 1 / 2, 1, 2, 3, etc.

[0296] As another optional embodiment, the first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0297] For example, the first field of PRDCH indicates the chip rate used by the PRDCH data field, such as 1, 2, 4, 8, 16, 24, etc.

[0298] In one implementation of this disclosure, the start indication component and the clock acquisition component satisfy the following conditions:

[0299] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0300] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0301] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0302] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8.

[0303] The last bit of the clock acquisition component is 1;

[0304] The cyclic prefix CP of the clock acquisition component is high voltage;

[0305] Different sequences of the clock acquisition component indicate different chip rates.

[0306] In another implementation of this disclosure, the start indication component and the clock acquisition component satisfy the following conditions:

[0307] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0308] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0309] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0310] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16.

[0311] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0312] Different sequences of the clock acquisition component indicate different chip rates.

[0313] In this embodiment of the disclosure, the A-IoT device determines first information based on at least one of the following: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, the chip rate of the second field of the PRDCH, the chip length of the second field of the PRDCH, the chip rate of the PRDCH, the chip rate of the PDRCH, the chip length of the PRDCH, and the chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0314] To more clearly describe the information indication method provided in the embodiments of this disclosure, several examples are given below.

[0315] Example 1

[0316] The first network element indicates first information to the environmental Internet of Things (A-IoT) device through a first method, wherein the first method includes at least one of the following:

[0317] The first field of the Physical Reader to Device Channel (PRDCH);

[0318] Chip rate of the first signal;

[0319] Chip length of the first signal;

[0320] The chip rate of the first field of PRDCH;

[0321] The chip length of the first field of PRDCH;

[0322] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0323] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH.

[0324] Before receiving the PRDCH sent by the first network element, the A-IoT device first needs to know the transmission information such as the chip length or chip rate used by the PRDCH. Since there is no broadcast channel in the A-IoT system, this information cannot be broadcast to the A-IoT device. Therefore, this embodiment of the present disclosure notifies the A-IoT device of this information through a first method, so that the device can demodulate and decode the PRDCH based on knowing the chip length or chip rate information used by the PRDCH.

[0325] In this example, as shown in Figure 4:

[0326] The start indicator and clock acquisition components both have fixed patterns.

[0327] The chip rate M1 value of the clock acquisition unit is pre-configured to a fixed value (M1=8).

[0328] The chip rate M2 in the first field of PRDCH is also pre-configured to a fixed value (M2=8).

[0329] The first field of PRDCH indicates the ratio of M3 to M1 used in the PRDCH data field, including 1 / 8, 1 / 4, 1 / 2, 1, 2, 3, etc., to indicate the M3 value of the PRDCH data field (M3 = 16).

[0330] The A-IoT device obtains the duration of high or low levels in the clock acquisition pattern by acquiring the M1 value of the pre-configured clock component. This helps in achieving precise clock synchronization and estimating the sampling frequency error (SFO). Then, the A-IoT device detects the information in the first field of the PRDCH by using the M2 value of the pre-configured first field. Combining this information with the information in the first field of the PRDCH, the device can obtain the M3 value of the PRDCH data field.

[0331] As shown in Table 1, the first network element can use different values ​​of the three bits of the first field of PRDCH to represent the ratio of M3 to M1 used in the PRDCH data field. Combined with the chip rate M1 value of the clock acquisition component, the A-IoT device can obtain the chip rate M3 value of the PRDCH data field. That is, different values ​​of the three bits of the first field of PRDCH correspond to different chip rate M3 values ​​in the PRDCH data field, but the pattern of the clock acquisition component is fixed. In Figure 4, the three bits of the first field of PRDCH are 100. According to the correspondence in Table 1, this corresponds to a chip rate M3 value of 16 in the PRDCH data field, and the chip length C3 of the corresponding PRDCH data field is 8 sampling points.

[0332] Table 1

[0333] The PRDCH field is used to indicate the first information to the A-IoT device. Different values ​​of the first PRDCH field can be used to indicate the first information. Using this method, the first network element can indicate transmission information such as chip length or chip rate to the A-IoT device, so that the A-IoT device can receive and decode the PRDCH according to the obtained transmission information such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also improves the transmission spectrum efficiency of the A-IoT system.

[0334] Example 2

[0335] The first network element indicates first information to the environmental Internet of Things (A-IoT) device through a first method, wherein the first method includes at least one of the following:

[0336] The first field of the Physical Reader to Device Channel (PRDCH);

[0337] Chip rate of the first signal;

[0338] Chip length of the first signal;

[0339] The chip rate of the first field of PRDCH;

[0340] The chip length of the first field of PRDCH;

[0341] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0342] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH.

[0343] Before receiving the PRDCH sent by the first network element, the A-IoT device first needs to know the transmission information such as the chip length or chip rate used by the PRDCH. Since there is no broadcast channel in the A-IoT system, this information cannot be broadcast to the A-IoT device. Therefore, this embodiment of the present disclosure notifies the A-IoT device of this information through a first method, so that the A-IoT device can demodulate and decode the PRDCH based on knowing the chip length or chip rate information used by the PRDCH.

[0344] In this example, as shown in Figure 5:

[0345] The start indicator and clock acquisition components both have fixed patterns.

[0346] The chip rate M1 value of the clock acquisition unit is pre-configured to a fixed value (M1=8).

[0347] The chip rate M2 in the first field of PRDCH is also pre-configured to a fixed value (M2=8).

[0348] The first field of PRDCH indicates the chip rate M3 value used in the PRDCH data field, such as 1, 2, 4, 8, 16, 24, etc.

[0349] The A-IoT device obtains the duration of high or low levels in the clock acquisition pattern by acquiring the M1 value of the pre-configured clock component. This helps in achieving precise clock synchronization and estimating the sampling frequency error (SFO). Then, the A-IoT device detects the information in the first field of the PRDCH by using the M2 value of the pre-configured first field. Combining this information with the information in the first field of the PRDCH, the device can obtain the M3 value of the PRDCH data field.

[0350] As shown in Table 2, the first network element can use different values ​​of the three bits of the first field of PRDCH to represent the M3 value used in the PRDCH data field. That is, different values ​​of the three bits of the first field of PRDCH correspond to different chip rate M3 values ​​in the PRDCH data field, but the pattern of the clock acquisition component is fixed. The A-IoT device obtains clock precision synchronization and estimates of sampling frequency error SFO through the clock acquisition component. In Figure 5, the value of the three bits of the first field of PRDCH is 100. According to the correspondence in Table 2, the corresponding chip rate M3 value of the PRDCH data field is 16, and the corresponding chip length C3 of the PRDCH data field is 8 sampling points.

[0351] Table 2

[0352] The PRDCH field is used to indicate the first information to A-IoT devices. Different values ​​of the first PRDCH field can be used to indicate the first information. Using this method, the reader can indicate transmission information such as chip length or chip rate to A-IoT devices, so that A-IoT devices can receive and decode PRDCH based on the obtained transmission information such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also improves the transmission spectrum efficiency of A-IoT systems.

[0353] Example 3

[0354] The first network element indicates first information to the environmental Internet of Things (A-IoT) device through a first method, wherein the first method includes at least one of the following:

[0355] The first field of the Physical Reader to Device Channel (PRDCH);

[0356] Chip rate of the first signal;

[0357] Chip length of the first signal;

[0358] The chip rate of the first field of PRDCH;

[0359] The chip length of the first field of PRDCH;

[0360] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0361] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH.

[0362] Before receiving the PRDCH sent by the first network element, the A-IoT device first needs to know the transmission information such as the chip length or chip rate used by the PRDCH. Since there is no broadcast channel in the A-IoT system, this information cannot be broadcast to the A-IoT device. Therefore, this embodiment of the present disclosure notifies the A-IoT device of this information through a first method, so that the A-IoT device can demodulate and decode the PRDCH based on knowing the chip length or chip rate information used by the PRDCH.

[0363] In this example, as shown in Figure 6:

[0364] The start indicator and clock acquisition components both have fixed patterns.

[0365] The chip rate M1 value of the clock acquisition unit is pre-configured to a fixed value (M1=8).

[0366] The chip rate M2 value of the first field of PRDCH is the same as the M1 value of the clock acquisition unit (M2 = 8).

[0367] The first field of PRDCH indicates the ratio of chip rate M3 to M1 used in the PRDCH data field, including 1 / 8, 1 / 4, 1 / 2, 1, 2, 3, etc., to indicate the M3 value of the PRDCH data field (M3 = 16).

[0368] A-IoT devices obtain the chip rate M1 value of the clock acquisition component through a pre-configured clock acquisition unit. This allows them to determine the duration of high or low levels in the clock acquisition component's pattern, aiding in precise clock synchronization and estimation of the sampling frequency error (SFO). Then, if the chip rate M2 value of the first field of the PRDCH matches the M1 value of the clock acquisition component, the information in the first field of the PRDCH can be detected. Combining this information with the first field information, the chip rate M3 value of the PRDCH data field can be obtained.

[0369] As shown in Table 3, the first network element can use different values ​​of the three bits of the first field of PRDCH to represent the ratio of M3 to M1 used in the PRDCH data field. Combined with the M1 value from the clock acquisition component, the A-IoT device can obtain the chip rate M3 value of the PRDCH data field. That is, different values ​​of the three bits of the first field of PRDCH correspond to different chip rate M3 values ​​in the PRDCH data field, but the pattern of the clock acquisition component is fixed. In Figure 6, the three bits of the first field of PRDCH are 100. According to the correspondence in Table 3, this corresponds to a chip rate M3 value of 16 in the PRDCH data field, and the chip length C3 of the corresponding PRDCH data field is 8 sampling points.

[0370] Table 3

[0371] The PRDCH field is used to indicate the first information to the device. Different values ​​of the first PRDCH field can be used to indicate the first information. Using this method, the reader can indicate transmission information such as chip length or chip rate to the A-IoT device, so that the A-IoT device can receive and decode the PRDCH according to the obtained transmission information such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also improves the transmission spectrum efficiency of the A-IoT system.

[0372] Example 4

[0373] The first network element indicates first information to the environmental Internet of Things (A-IoT) device through a first method, wherein the first method includes at least one of the following:

[0374] The first field of the Physical Reader to Device Channel (PRDCH);

[0375] Chip rate of the first signal;

[0376] Chip length of the first signal;

[0377] The chip rate of the first field of PRDCH;

[0378] The chip length of the first field of PRDCH;

[0379] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0380] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH.

[0381] Before receiving the PRDCH sent by the first network element, the A-IoT device first needs to know the transmission information such as the chip length or chip rate used by the PRDCH. Since there is no broadcast channel in the A-IoT system, this information cannot be broadcast to the A-IoT device. Therefore, this embodiment of the present disclosure notifies the A-IoT device of this information through a first method, so that the device can demodulate and decode the PRDCH based on knowing the chip length or chip rate information used by the PRDCH.

[0382] In this example, as shown in Figure 7:

[0383] The start indicator and clock acquisition components both have fixed patterns.

[0384] The chip rate M1 value of the clock acquisition unit is pre-configured to a fixed value (M1=8).

[0385] The chip rate M2 value of the first field of PRDCH is the same as the M1 value of the clock acquisition unit (M2 = 8).

[0386] The first field of PRDCH indicates the chip rate M3 value used in the PRDCH data field, such as 1, 2, 4, 8, 16, 24, etc.

[0387] A-IoT devices obtain the duration of high or low levels in the clock acquisition pattern by acquiring the M1 value of a pre-configured clock component. This helps in precise clock synchronization and estimation of the sampling frequency error (SFO). Then, if the M2 value of the first field of the PRDCH matches the M1 value of the clock acquisition component, the information in the first field of the PRDCH can be detected. Combining this information with the first field information, the M3 value of the PRDCH data field can be obtained.

[0388] As shown in Table 4, the first network element can use different values ​​of the three bits of the first field of PRDCH to represent the M3 value used in the PRDCH data field. That is, different values ​​of the three bits of the first field of PRDCH correspond to different chip rate M3 values ​​in the PRDCH data field, but the pattern of the clock acquisition component is fixed. The A-IoT device obtains clock precision synchronization and estimates of sampling frequency error SFO through the clock acquisition component. In Figure 7, the value of the three bits of the first field of PRDCH is 100. According to the correspondence in Table 4, the corresponding chip rate M3 value of the PRDCH data field is 16, and the chip length C3 of the corresponding PRDCH data field is 8 sampling points.

[0389] Table 4

[0390] The PRDCH field is used to indicate the first information to the device. Different values ​​of the first PRDCH field can be used to indicate the first information. Using this method, the first network element can indicate transmission information such as chip length or chip rate to the A-IoT device. This allows the A-IoT device to receive and decode the PRDCH based on the obtained transmission information such as chip length or chip rate, which improves the flexibility of PRDCH transmission parameter configuration and also improves the transmission spectrum efficiency of the A-IoT system.

[0391] Example 5

[0392] As shown in Figure 8, the information interaction process between the reader and the A-IoT device is as follows:

[0393] Step 8.1: The reader first determines the chip rate or chip length of the PRDCH data field, etc.

[0394] Step 8.2: The A-IoT device receives pre-configuration information and obtains the chip rate information of the clock acquisition component.

[0395] Step 8.3: The reader sends the R2D time acquisition signal and the first field of the PRDCH. The R2D time acquisition signal includes a start indication component and a clock acquisition component.

[0396] Step 8.4: The A-IoT device receives the R2D time acquisition signal and the first field of PRDCH, and obtains the first information, that is, the chip length used in the PRDCH data field.

[0397] Step 8.5: The reader sends the PRDCH data field.

[0398] Step 8.6, the A-IoT device receives the PRDCH data field with the first information.

[0399] Using the first field of the PRDCH to indicate the first information, the first information can be indicated to the device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained chip bandwidth and other transmission information. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0400] Example 6

[0401] In this example, as shown in Figure 9:

[0402] The start indicator component and clock acquire the component with a total length of 1 OFDM symbol.

[0403] The start indicator part length is 1 / 4 OFDM symbol, and the clock acquires part length 3 / 4 OFDM symbol.

[0404] The start indicator consists of a low level lasting one chip and a high level lasting three chips, with a chip rate M = 16.

[0405] The clock acquisition unit consists of different sequences, with a chip rate M1 = 8.

[0406] The last bit of the clock acquisition unit is fixed at 1, which ensures that after adding the cyclic prefix CP, it is fixed at a high level before the start of the indicator unit.

[0407] The cyclic prefix CP is high.

[0408] To simplify system design, the same clock acquisition component pattern design is used for the M3 value of different PRDCH data fields. This eliminates the need for A-IoT devices to blindly detect different clock acquisition components to obtain the M3 value of the PRDCH data field. By using the pre-configured M1 value of the clock acquisition component, the A-IoT device can determine the duration of high or low levels in the clock acquisition component pattern, which assists in clock synchronization and estimation of the sampling frequency error (SFO). Then, combined with information from the first field of the PRDCH, the M3 value of the PRDCH data field can be obtained.

[0409] Example 7

[0410] In this example, as shown in Figure 10:

[0411] The start indicator component and clock acquire the component with a total length of 1 OFDM symbol.

[0412] The start indicator part length is 1 / 4 OFDM symbol, and the clock acquires part length 3 / 4 OFDM symbol.

[0413] The start indicator consists of a low level lasting one chip and a high level lasting three chips, with a chip rate M = 16.

[0414] The clock acquisition unit consists of different sequences, with a chip rate M1 = 16.

[0415] The cyclic prefix CP is high.

[0416] To simplify system design, the same clock acquisition component pattern design is used for the M3 value of different PRDCH data fields. This eliminates the need for A-IoT devices to blindly detect different clock acquisition components to obtain the M3 value of the PRDCH data field. By using the pre-configured M1 value of the clock acquisition component, the A-IoT device can determine the duration of high or low levels in the clock acquisition component pattern, which assists in clock synchronization and estimation of the sampling frequency error (SFO). Then, combined with information from the first field of the PRDCH, the M3 value of the PRDCH data field can be obtained.

[0417] As shown in Figure 11, this embodiment of the present disclosure also provides a first network element, including a memory 1120, a transceiver 1110, and a processor 1100:

[0418] The memory 1120 is used to store computer programs; the transceiver 1110 is used to send and receive data under the control of the processor 1100; the processor 1100 is used to read the computer program in the memory 1120 and perform the following operations:

[0419] The first information is indicated to the environmental Internet of Things (A-IoT) device through a first method, wherein the first method includes at least one of the following:

[0420] The first field of the Physical Reader to Device Channel (PRDCH);

[0421] Chip rate of the first signal;

[0422] Chip length of the first signal;

[0423] The chip rate of the first field of PRDCH;

[0424] The chip length of the first field of PRDCH;

[0425] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0426] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0427] As an optional embodiment, the first network element includes at least one of the following: a base station, a terminal, a reader, and an intermediate node.

[0428] As an optional embodiment, the start indication component includes at least one of the following: a start indication component in an R2D preamble, a start indication component in an R2D time acquisition signal, and a start indication component in an R2D timing acquisition signal;

[0429] or,

[0430] The clock acquisition component includes at least one of the following: a clock acquisition component in an R2D preamble, a clock acquisition component in an R2D time acquisition signal, and a clock acquisition component in an R2D timing acquisition signal.

[0431] As an optional embodiment, the second field of the PRDCH is any one of the following:

[0432] Other fields in PRDCH besides the first field;

[0433] PRDCH data field;

[0434] PRDCH control field;

[0435] The control field fields of PRDCH, excluding the first field.

[0436] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same.

[0437] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same, including at least one of the following:

[0438] The pattern of the first signal is the same for different R2D chip lengths;

[0439] The pattern of the first signal is the same for different OOK chip lengths;

[0440] The pattern of the first signal is the same for different D2R chip lengths;

[0441] The patterns of the first signal are the same for different chip rates in the second field of PRDCH;

[0442] The pattern of the first signal is the same for different chip lengths of the second field of PRDCH.

[0443] As an optional embodiment, the pattern of the start indicator component is a first pattern; and / or,

[0444] The pattern of the clock acquisition component is the second pattern.

[0445] As an optional embodiment, the chip rate of the clock acquisition unit is a pre-configured first value;

[0446] or,

[0447] The chip rate of the first field of the PRDCH is a pre-configured second value;

[0448] or,

[0449] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0450] As an optional embodiment, the first field of the PRDCH is used to indicate ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0451] or,

[0452] The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0453] As an optional embodiment, the pattern of the first signal includes:

[0454] The first signal has the same time domain length;

[0455] or,

[0456] The first signal has the same time domain length and uses the same sequence.

[0457] or,

[0458] The first signal has the same time domain length and uses the same sequence, and the combination of high and low voltages in the first signal is the same.

[0459] As an optional embodiment, the combination of high voltage and low voltage in the first signal is the same, including:

[0460] The first signal has the same number of high voltage and low voltage signals, and the high voltage and low voltage signals appear in the same order.

[0461] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0462] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0463] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0464] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0465] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8.

[0466] The last bit of the clock acquisition component is 1;

[0467] The cyclic prefix CP of the clock acquisition component is high voltage;

[0468] Different sequences of the clock acquisition component indicate different chip rates.

[0469] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0470] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0471] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0472] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0473] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16.

[0474] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0475] Different sequences of the clock acquisition component indicate different chip rates.

[0476] In Figure 11, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits of one or more processors represented by processor 1100 and memory represented by memory 1120. The bus architecture may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. Transceiver 1110 may be multiple elements, including transmitters and receivers, providing units for communicating with various other devices over transmission media, including wireless channels, wired channels, optical fibers, etc. Processor 1100 is responsible for managing the bus architecture and general processing, and memory 1120 may store data used by processor 1100 during operation.

[0477] The processor 1100 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor can also adopt a multi-core architecture.

[0478] In this embodiment of the disclosure, the first network element indicates first information to the A-IoT device through at least one of the following methods: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of the PRDCH, chip length of the second field of the PRDCH, chip rate of the PRDCH, chip rate of the PDRCH, chip length of the PRDCH, and chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0479] It should be noted that the first network element provided in this embodiment is a network element capable of executing the above information indication method. Therefore, all embodiments of the above information indication method are applicable to this network element and can achieve the same or similar beneficial effects, which will not be repeated here.

[0480] As shown in Figure 12, this embodiment of the present disclosure also provides an environmental Internet of Things (A-IoT) device, including a memory 1220, a transceiver 1210, and a processor 1200.

[0481] The memory 1220 is used to store computer programs; the transceiver 1210 is used to send and receive data under the control of the processor 1200; the processor 1200 is used to read the computer program in the memory 1220 and perform the following operations:

[0482] The first information is determined according to the first method; the first method includes at least one of the following:

[0483] The first field of the Physical Reader to Device Channel (PRDCH);

[0484] Chip rate of the first signal;

[0485] Chip length of the first signal;

[0486] The chip rate of the first field of PRDCH;

[0487] The chip length of the first field of PRDCH;

[0488] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0489] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0490] As an optional embodiment, the start indication component includes at least one of the following: a start indication component in an R2D preamble, a start indication component in an R2D time acquisition signal, and a start indication component in an R2D timing acquisition signal;

[0491] or,

[0492] The clock acquisition component includes at least one of the following:

[0493] Clock acquisition component in R2D preamble, clock acquisition component in R2D time acquisition signal, clock acquisition component in R2D timing acquisition signal.

[0494] As an optional embodiment, the second field of the PRDCH is any one of the following:

[0495] Other fields in PRDCH besides the first field;

[0496] PRDCH data field;

[0497] PRDCH control field;

[0498] The control field fields of PRDCH, excluding the first field.

[0499] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same.

[0500] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same, including at least one of the following:

[0501] The pattern of the first signal is the same for different R2D chip lengths;

[0502] The pattern of the first signal is the same for different OOK chip lengths;

[0503] The pattern of the first signal is the same for different D2R chip lengths;

[0504] The patterns of the first signal are the same for different chip rates in the second field of PRDCH;

[0505] The pattern of the first signal is the same for different chip lengths of the second field of PRDCH.

[0506] As an optional embodiment, the pattern of the start indicator component is a first pattern; and / or,

[0507] The pattern of the clock acquisition component is the second pattern.

[0508] As an optional embodiment, the chip rate of the clock acquisition unit is a pre-configured first value;

[0509] or,

[0510] The chip rate of the first field of the PRDCH is a pre-configured second value;

[0511] or,

[0512] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0513] As an optional embodiment, the first field of the PRDCH is used to indicate ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0514] or,

[0515] The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0516] As an optional embodiment, the pattern of the first signal includes:

[0517] The first signal has the same time domain length;

[0518] or,

[0519] The first signal has the same time domain length and uses the same sequence.

[0520] or,

[0521] The first signal has the same time domain length and uses the same sequence, and the combination of high and low voltages in the first signal is the same.

[0522] As an optional embodiment, the combination of high voltage and low voltage in the first signal is the same, including:

[0523] The first signal has the same number of high voltage and low voltage signals, and the high voltage and low voltage signals appear in the same order.

[0524] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0525] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0526] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0527] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0528] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8.

[0529] The last bit of the clock acquisition component is 1;

[0530] The cyclic prefix CP of the clock acquisition component is high voltage;

[0531] Different sequences of the clock acquisition component indicate different chip rates.

[0532] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0533] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0534] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0535] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0536] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16.

[0537] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0538] Different sequences of the clock acquisition component indicate different chip rates.

[0539] In Figure 12, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits of one or more processors represented by processor 1200 and memory represented by memory 1220. The bus architecture may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. Transceiver 1210 may be multiple elements, including transmitters and receivers, providing units for communicating with various other devices over transmission media, including wireless channels, wired channels, optical fibers, etc. Processor 1200 is responsible for managing the bus architecture and general processing, and memory 1220 may store data used by processor 1200 during operation.

[0540] The processor 1200 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor can also adopt a multi-core architecture.

[0541] In this embodiment of the disclosure, the A-IoT device determines first information based on at least one of the following: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, the chip rate of the second field of the PRDCH, the chip length of the second field of the PRDCH, the chip rate of the PRDCH, the chip rate of the PDRCH, the chip length of the PRDCH, and the chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0542] It should be noted that the A-IoT device provided in this disclosure is a device capable of executing the above information determination method. Therefore, all embodiments of the above information determination method are applicable to this device and can achieve the same or similar beneficial effects, which will not be repeated here.

[0543] As shown in Figure 13, this embodiment of the present disclosure also provides an information indicating device, including:

[0544] Indication unit 1301 is configured to indicate first information to an environmental Internet of Things (A-IoT) device via a first method, wherein the first method includes at least one of the following:

[0545] The first field of the Physical Reader to Device Channel (PRDCH);

[0546] Chip rate of the first signal;

[0547] Chip length of the first signal;

[0548] The chip rate of the first field of PRDCH;

[0549] The chip length of the first field of PRDCH;

[0550] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0551] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0552] As an optional embodiment, the first network element includes at least one of the following: a base station, a terminal, a reader, and an intermediate node.

[0553] As an optional embodiment, the start indication component includes at least one of the following: a start indication component in an R2D preamble, a start indication component in an R2D time acquisition signal, and a start indication component in an R2D timing acquisition signal;

[0554] or,

[0555] The clock acquisition component includes at least one of the following: a clock acquisition component in an R2D preamble, a clock acquisition component in an R2D time acquisition signal, and a clock acquisition component in an R2D timing acquisition signal.

[0556] As an optional embodiment, the second field of the PRDCH is any one of the following:

[0557] Other fields in PRDCH besides the first field;

[0558] PRDCH data field;

[0559] PRDCH control field;

[0560] The control field fields of PRDCH, excluding the first field.

[0561] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same.

[0562] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same, including at least one of the following:

[0563] The pattern of the first signal is the same for different R2D chip lengths;

[0564] The pattern of the first signal is the same for different OOK chip lengths;

[0565] The pattern of the first signal is the same for different D2R chip lengths;

[0566] The patterns of the first signal are the same for different chip rates in the second field of PRDCH;

[0567] The pattern of the first signal is the same for different chip lengths of the second field of PRDCH.

[0568] As an optional embodiment, the pattern of the start indicator component is a first pattern; and / or,

[0569] The pattern of the clock acquisition component is the second pattern.

[0570] As an optional embodiment, the chip rate of the clock acquisition unit is a pre-configured first value;

[0571] or,

[0572] The chip rate of the first field of the PRDCH is a pre-configured second value;

[0573] or,

[0574] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0575] As an optional embodiment, the first field of the PRDCH is used to indicate ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0576] or,

[0577] The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0578] As an optional embodiment, the pattern of the first signal includes:

[0579] The first signal has the same time domain length;

[0580] or,

[0581] The first signal has the same time domain length and uses the same sequence.

[0582] or,

[0583] The first signal has the same time domain length and uses the same sequence, and the combination of high and low voltages in the first signal is the same.

[0584] As an optional embodiment, the combination of high voltage and low voltage in the first signal is the same, including:

[0585] The first signal has the same number of high voltage and low voltage signals, and the high voltage and low voltage signals appear in the same order.

[0586] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0587] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0588] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0589] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0590] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8.

[0591] The last bit of the clock acquisition component is 1;

[0592] The cyclic prefix CP of the clock acquisition component is high voltage;

[0593] Different sequences of the clock acquisition component indicate different chip rates.

[0594] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0595] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0596] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0597] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0598] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16.

[0599] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0600] Different sequences of the clock acquisition component indicate different chip rates.

[0601] In this embodiment of the disclosure, the first network element indicates first information to the A-IoT device through at least one of the following methods: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of the PRDCH, chip length of the second field of the PRDCH, chip rate of the PRDCH, chip rate of the PDRCH, chip length of the PRDCH, and chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0602] It should be noted that the information indicating device provided in this disclosure is a device capable of executing the above information indicating method. Therefore, all embodiments of the above information indicating method are applicable to this device and can achieve the same or similar beneficial effects, which will not be repeated here.

[0603] As shown in Figure 14, this embodiment of the present disclosure also provides an information determining device, the device comprising:

[0604] The determining unit 1401 is configured to determine first information according to a first method; the first method includes at least one of the following:

[0605] The first field of the Physical Reader to Device Channel (PRDCH);

[0606] Chip rate of the first signal;

[0607] Chip length of the first signal;

[0608] The chip rate of the first field of PRDCH;

[0609] The chip length of the first field of PRDCH;

[0610] The first signal can be any one of the following: reader-to-device R2D preamble, R2D time acquisition signal, R2D timing acquisition signal, start indicator component, or clock acquisition component;

[0611] The first information includes at least one of the following: reader-to-device R2D chip length, on / off key control OOK chip length, device-to-reader D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, chip rate of the second field of PRDCH, chip length of the second field of PRDCH, chip rate of PRDCH, chip rate of PDRCH, chip length of PRDCH, and chip length of PDRCH; wherein the chip rate is used to indicate the number of chips contained in an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

[0612] As an optional embodiment, the start indication component includes at least one of the following: a start indication component in an R2D preamble, a start indication component in an R2D time acquisition signal, and a start indication component in an R2D timing acquisition signal;

[0613] or,

[0614] The clock acquisition component includes at least one of the following:

[0615] Clock acquisition component in R2D preamble, clock acquisition component in R2D time acquisition signal, clock acquisition component in R2D timing acquisition signal.

[0616] As an optional embodiment, the second field of the PRDCH is any one of the following:

[0617] Other fields in PRDCH besides the first field;

[0618] PRDCH data field;

[0619] PRDCH control field;

[0620] The control field fields of PRDCH, excluding the first field.

[0621] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same.

[0622] As an optional embodiment, the patterns of the first signals corresponding to different values ​​of the first information are the same, including at least one of the following:

[0623] The pattern of the first signal is the same for different R2D chip lengths;

[0624] The pattern of the first signal is the same for different OOK chip lengths;

[0625] The pattern of the first signal is the same for different D2R chip lengths;

[0626] The patterns of the first signal are the same for different chip rates in the second field of PRDCH;

[0627] The pattern of the first signal is the same for different chip lengths of the second field of PRDCH.

[0628] As an optional embodiment, the pattern of the start indicator component is a first pattern; and / or,

[0629] The pattern of the clock acquisition component is the second pattern.

[0630] As an optional embodiment, the chip rate of the clock acquisition unit is a pre-configured first value;

[0631] or,

[0632] The chip rate of the first field of the PRDCH is a pre-configured second value;

[0633] or,

[0634] The chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

[0635] As an optional embodiment, the first field of the PRDCH is used to indicate ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH.

[0636] or,

[0637] The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

[0638] As an optional embodiment, the pattern of the first signal includes:

[0639] The first signal has the same time domain length;

[0640] or,

[0641] The first signal has the same time domain length and uses the same sequence.

[0642] or,

[0643] The first signal has the same time domain length and uses the same sequence, and the combination of high and low voltages in the first signal is the same.

[0644] As an optional embodiment, the combination of high voltage and low voltage in the first signal is the same, including:

[0645] The first signal has the same number of high voltage and low voltage signals, and the high voltage and low voltage signals appear in the same order.

[0646] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0647] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0648] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0649] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0650] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8.

[0651] The last bit of the clock acquisition component is 1;

[0652] The cyclic prefix CP of the clock acquisition component is high voltage;

[0653] Different sequences of the clock acquisition component indicate different chip rates.

[0654] As an optional embodiment, the start indication component and the clock acquisition component satisfy the following conditions:

[0655] The total length of the start indication component and the clock acquisition component is 1 OFDM symbol;

[0656] The length of the start indicator component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol;

[0657] The start indicator component consists of a low voltage lasting for 1 chip and a high voltage lasting for 3 chips, and the chip rate of the start indicator component is 16.

[0658] The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16.

[0659] The cyclic prefix CP of the clock acquisition component is a combination of low voltage and high voltage;

[0660] Different sequences of the clock acquisition component indicate different chip rates.

[0661] In this embodiment of the disclosure, the A-IoT device determines first information based on at least one of the following: the first field of the PRDCH, the chip rate of the first signal, the chip length of the first signal, the chip rate of the first field of the PRDCH, and the chip length of the first field of the PRDCH. The first information includes at least one of the following: R2D chip length, OOK chip length, D2R chip length, R2D chip rate, OOK chip rate, D2R chip rate, the chip rate of the second field of the PRDCH, the chip length of the second field of the PRDCH, the chip rate of the PRDCH, the chip rate of the PDRCH, the chip length of the PRDCH, and the chip length of the PDRCH. Using this method, the first network element can indicate transmission parameters such as chip length or chip rate to the A-IoT device, thereby enabling the A-IoT device to receive and decode the PRDCH based on the obtained transmission parameters such as chip length or chip rate. This improves the flexibility of PRDCH transmission parameter configuration and also enhances the transmission spectrum efficiency of the A-IoT system.

[0662] It should be noted that the information determination device provided in this disclosure is a device capable of executing the above information determination method. Therefore, all embodiments of the above information determination method are applicable to this device and can achieve the same or similar beneficial effects, which will not be repeated here.

[0663] It should be noted that the division of units in the embodiments of this disclosure is illustrative and only represents one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0664] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to related technologies, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0665] This disclosure also provides a processor-readable storage medium storing a computer program that causes the processor to execute the various processes described in the method embodiments above, achieving the same technical effects. To avoid repetition, these processes will not be repeated here. The processor-readable storage medium can be any available medium or data storage device accessible to the processor, including but not limited to magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (e.g., compact discs (CDs), digital video discs (DVDs), Blu-ray discs (BD), high-definition versatile discs (HVD), etc.), and semiconductor storage (e.g., ROMs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), non-volatile memory (NAND flash), solid-state drives (SSDs), etc.).

[0666] This disclosure also provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, they implement the various processes in the method embodiments described above and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0667] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0668] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0669] These processor-executable instructions may also be stored in a processor-readable memory that can instruct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0670] These processor-executable instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0671] Furthermore, it should be noted that in the apparatus and method of this disclosure, it is obvious that the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered equivalent solutions of this disclosure. Moreover, the steps performing the above series of processes can naturally be executed in the order described, but are not necessarily required to be executed in chronological order; some steps can be executed in parallel or independently of each other. Those skilled in the art will understand that all or any step or component of the method and apparatus of this disclosure can be implemented in any computing device (including processors, storage media, etc.) or network of computing devices, in hardware, firmware, software, or a combination thereof, which can be achieved by those skilled in the art using their basic programming skills after reading the description of this disclosure.

[0672] It should be noted that the above division of modules is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a module can be a separate processing element, or it can be integrated into a chip in the aforementioned device. Alternatively, it can be stored as program code in the memory of the aforementioned device, and its function can be called and executed by a processing element of the device. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element mentioned here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0673] For example, each module, unit, subunit, or submodule can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0674] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A method for indicating information, the method comprising: indicating, by a first network element, first information to an Ambient Internet of Things (A-IoT) device through a first manner, the first manner comprising at least one of: a first field of a Physical Reader-to-Device Channel (PRDCH); a chip rate of a first signal; a chip length of the first signal; a chip rate of the first field of the PRDCH; a chip length of the first field of the PRDCH; wherein the first signal is any one of: a Reader-to-Device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, a clock acquisition component; wherein the first information comprises at least one of: an R2D chip length, an On-Off Keying (OOK) chip length, a Device-to-Reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of the PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of the PDRCH, a chip length of the PRDCH, a chip length of the PDRCH; the chip rate being used to indicate a number of chips contained in one Orthogonal Frequency-Division Multiplexing (OFDM) symbol.

2. The method of claim 1, wherein, the start indication component comprises at least one of: a start indication component in the R2D preamble, a start indication component in the R2D time acquisition signal, a start indication component in the R2D timing acquisition signal; or, the clock acquisition component comprises at least one of: a clock acquisition component in the R2D preamble, a clock acquisition component in the R2D time acquisition signal, a clock acquisition component in the R2D timing acquisition signal.

3. The method of claim 1, wherein, the second field of the PRDCH is any one of: a field other than the first field in the PRDCH; a data field of the PRDCH; a control field of the PRDCH; a control field other than the first field in the control field of the PRDCH.

4. The method of claim 1, wherein, patterns of the first signals corresponding to different values of the first information are the same.

5. The method of claim 4, wherein, patterns of the first signals corresponding to different values of the first information are the same, comprising at least one of: patterns of the first signals corresponding to different R2D chip lengths are the same; patterns of the first signals corresponding to different OOK chip lengths are the same; patterns of the first signals corresponding to different D2R chip lengths are the same; patterns of the first signals corresponding to different chip rates of the second field of the PRDCH are the same; patterns of the first signals corresponding to different chip lengths of the second field of the PRDCH are the same.

6. The method of claim 1, wherein: a pattern of the start indication component is a first pattern; and / or, a pattern of the clock acquisition component is a second pattern.

7. The method of claim 1, wherein: a chip rate of the clock acquisition component is a first preconfigured value; or, a chip rate of the first field of the PRDCH is a second preconfigured value; or, the chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

8. The method of claim 1, wherein: The first field of the PRDCH is used to indicate the ratio information, which is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first signal, or is used to indicate the ratio of the chip rate of the second field of the PRDCH to the chip rate of the first field of the PRDCH. Or, The first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

9. The method of claim 4 or 5, wherein, The patterns of the first signals are the same, including: The time domain lengths of the first signals are the same; Or, The time domain lengths of the first signals and the used sequences are the same; Or, The time domain lengths of the first signals and the used sequences are the same, and the combination of the high voltage and the low voltage of the first signals is the same.

10. The method of claim 9, wherein, The combination of the high voltage and the low voltage of the first signals is the same, including: The number of the high voltage and the low voltage of the first signals is the same, and the appearance order of the high voltage and the low voltage of the first signals is the same.

11. The method of claim 1, wherein, The start indication component and the clock acquisition component satisfy the following conditions: The total length of the start indication component and the clock acquisition component is 1 OFDM symbol; The length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol; The start indication component is composed of a low voltage with a duration of 1 chip and a high voltage with a duration of 3 chips, and the chip rate of the start indication component is 16; The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8; The last bit of the clock acquisition component is 1; The cyclic prefix CP of the clock acquisition component is a high voltage; Different sequences of the clock acquisition component are used to indicate different chip rates.

12. The method of claim 1, wherein, The start indication component and the clock acquisition component satisfy the following conditions: The total length of the start indication component and the clock acquisition component is 1 OFDM symbol; The length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol; The start indication component is composed of a low voltage with a duration of 1 chip and a high voltage with a duration of 3 chips, and the chip rate of the start indication component is 16; The clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 16; The cyclic prefix CP of the clock acquisition component is a combination of a low voltage and a high voltage; Different sequences of the clock acquisition component are used to indicate different chip rates.

13. The method of claim 1, wherein, The first network element includes at least one of the following: a base station, a terminal, a reader, and an intermediate node.

14. An information determination method, the method comprising: An ambient Internet of Things (A-IoT) device determines first information according to a first mode, and the first mode includes at least one of the following: A first field of a physical reader-to-device channel (PRDCH); A chip rate of a first signal; A chip length of a first signal; A chip rate of a first field of a PRDCH; A chip length of a first field of a PRDCH; The first signal is any one of the following signals: a reader-to-device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, and a clock acquisition component. The first information includes at least one of the following: an R2D chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of a physical reader-to-device channel (PRDCH), a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of a PDRCH, a chip length of the PRDCH, and a chip length of the PDRCH. The chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

15. A first network element, comprising a memory, a transceiver, and a processor: The memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; and the processor is configured to read the computer program in the memory and perform the following operations: indicating first information to an ambient Internet of Things (A-IoT) device by a first mode, the first mode including at least one of the following: a first field of a physical reader-to-device channel (PRDCH); a chip rate of the first signal; a chip length of the first signal; a chip rate of the first field of the PRDCH; a chip length of the first field of the PRDCH; wherein, The first signal is any one of the following signals: a reader-to-device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, and a clock acquisition component. The first information includes at least one of the following: an R2D chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of a physical reader-to-device channel (PRDCH), a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of a PDRCH, a chip length of the PRDCH, and a chip length of the PDRCH. The chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

16. The first network element of claim 15, wherein The start indication component includes at least one of the following: a start indication component in the R2D preamble, a start indication component in the R2D time acquisition signal, and a start indication component in the R2D timing acquisition signal. Alternatively, The clock acquisition component includes at least one of the following: a clock acquisition component in the R2D preamble, a clock acquisition component in the R2D time acquisition signal, and a clock acquisition component in the R2D timing acquisition signal.

17. The first network element of claim 15, wherein, The second field of the PRDCH is any one of the following: a field other than the first field in the PRDCH; a data domain field of the PRDCH; a control domain field of the PRDCH; a control domain field other than the first field in the control domain field of the PRDCH.

18. The first network element of claim 15, wherein, Different values of the first information correspond to the same pattern of the first signal.

19. The first network element of claim 18, wherein, Different values of the first information correspond to the same pattern of the first signal, including at least one of the following: the patterns of the first signals corresponding to different R2D chip lengths are the same; the patterns of the first signals corresponding to different OOK chip lengths are the same; the patterns of the first signals corresponding to different D2R chip lengths are the same; the patterns of the first signals corresponding to different chip rates of the second field of the PRDCH are the same; the patterns of the first signals corresponding to different chip lengths of the second field of the PRDCH are the same.

20. The first network element of claim 15, wherein, the pattern of the start indication component is a first pattern; and / or, the pattern of the clock acquisition component is a second pattern.

21. The first network element of claim 15, wherein, the chip rate of the clock acquisition component is a first preconfigured value; or, the chip rate of the first field of the PRDCH is a second preconfigured value; or, the chip rate of the clock acquisition component is the same as the chip rate of the first field of the PRDCH.

22. The first network element of claim 15, wherein, the first field of the PRDCH is used to indicate scaling information, the scaling information is used to indicate a scaling of the chip rate of the second field of the PRDCH relative to a chip rate of the first signal, or to indicate a scaling of the chip rate of the second field of the PRDCH relative to the chip rate of the first field of the PRDCH; or, the first field of the PRDCH is used to indicate the chip rate of the second field of the PRDCH.

23. The first network element of claim 18 or 19, wherein, the patterns of the first signals being the same includes: the time domain lengths of the first signals being the same; or, the time domain lengths of the first signals and the sequences used being the same; or, the time domain lengths of the first signals and the sequences used being the same, and the combinations of high and low voltages of the first signals being the same.

24. The first network element of claim 23, wherein, the combinations of high and low voltages of the first signals being the same includes: the numbers of high and low voltages of the first signals being the same, and the orders of appearance of high and low voltages of the first signals being the same.

25. The first network element of claim 15, wherein, the start indication component and the clock acquisition component satisfy the following conditions: the total length of the start indication component and the clock acquisition component is 1 OFDM symbol; the length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol; the start indication component is composed of a low voltage with a duration of 1 chip and a high voltage with a duration of 3 chips, and the chip rate of the start indication component is 16; the clock acquisition component is composed of different sequences, and the chip rate of the clock acquisition component is 8; the last bit of the clock acquisition component is 1; the cyclic prefix (CP) of the clock acquisition component is a high voltage; different sequences of the clock acquisition component are used to indicate different chip rates.

26. The first network element of claim 15, wherein, the start indication component and the clock acquisition component satisfy the following conditions: the total length of the start indication component and the clock acquisition component is 1 OFDM symbol; the length of the start indication component is 1 / 4 OFDM symbol, and the length of the clock acquisition component is 3 / 4 OFDM symbol; The start indication component is composed of a low voltage with a duration of 1 chip and a high voltage with a duration of 3 chips, and a chip rate of the start indication component is 16; The clock acquisition component is composed of different sequences, and a chip rate of the clock acquisition component is 16; A cyclic prefix (CP) of the clock acquisition component is a combination of a low voltage and a high voltage; Different sequences of the clock acquisition component are used to indicate different chip rates.

27. The first network element of claim 15, wherein, The first network element includes at least one of the following: a base station, a terminal, a reader, and an intermediate node.

28. An environmental Internet of Things (A-IoT) device, comprising a memory, a transceiver, and a processor: The memory is configured to store a computer program; the transceiver is configured to transceive data under control of the processor; and the processor is configured to read the computer program in the memory and perform the following operations: According to a first mode, determining first information; the first mode includes at least one of the following: A first field of a physical reader-to-device channel (PRDCH); A chip rate of the first signal; A chip length of the first signal; A chip rate of the first field of the PRDCH; A chip length of the first field of the PRDCH; wherein, The first signal is any one of the following signals: a reader-to-device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, and a clock acquisition component; The first information includes at least one of the following: an R2D chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of the PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of the PDRCH, a chip length of the PRDCH, and a chip length of the PDRCH; the chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

29. An information indication apparatus, comprising: An indication unit configured to indicate first information to an environmental Internet of Things (A-IoT) device by a first mode, the first mode including at least one of the following: A first field of a physical reader-to-device channel (PRDCH); A chip rate of the first signal; A chip length of the first signal; A chip rate of the first field of the PRDCH; A chip length of the first field of the PRDCH; The first signal is any one of the following signals: a reader-to-device (R2D) preamble, an R2D time acquisition signal, an R2D timing acquisition signal, a start indication component, and a clock acquisition component; The first information includes at least one of the following: an R2D chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, an R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of the PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of the PDRCH, a chip length of the PRDCH, and a chip length of the PDRCH; the chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

30. An information determining apparatus, the apparatus comprising: a determining unit configured to determine first information according to a first manner; the first manner comprises at least one of: a first field of a physical reader-to-device channel (PRDCH); a chip rate of the first signal; a chip length of the first signal; a chip rate of the first field of the PRDCH; a chip length of the first field of the PRDCH; wherein the first signal is any one of: a reader-to-device (R2D) preamble, a R2D time acquisition signal, a R2D timing acquisition signal, a start indication component, a clock acquisition component; wherein the first information comprises at least one of: a reader-to-device (R2D) chip length, an on-off keying (OOK) chip length, a device-to-reader (D2R) chip length, a R2D chip rate, an OOK chip rate, a D2R chip rate, a chip rate of a second field of the PRDCH, a chip length of the second field of the PRDCH, a chip rate of the PRDCH, a chip rate of the PDRCH, a chip length of the PRDCH, a chip length of the PDRCH; the chip rate is used to indicate a number of chips contained in one orthogonal frequency division multiplexing (OFDM) symbol.

31. A processor-readable storage medium, the processor-readable storage medium storing a program for causing the processor to perform the method of any one of claims 1 to 13, or the program for causing the processor to perform the method of claim 14.

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