Display device

Abstract

The present invention suppresses the occurrence of display failures caused by changes in TFT characteristics in an upper-edge portion of a panel in a display device using current-driven display elements.　In a unit circuit constituting a shift register as a scan signal line drive circuit, back gates 61 to 63 are provided in three transistors M1 to M3 for controlling the voltage of a first internal node N1 connected via a transistor M6 to the gate of a transistor M7 that functions as a buffer transistor. A DC voltage (first high-level power supply voltage GVDD) is continuously applied to the back gates 62, 63 of the transistors M2, M3, said DC voltage being of opposite polarity to the gate voltage for turning on the transistors M2, M3. A voltage (high-level voltage of a set signal S) is applied to the back gate 61 of the transistor M1 during an off period of a shift pulse, said voltage being of opposite polarity to the gate voltage for turning on the transistor M1.

Description

display device

[0001] The following disclosure relates to a display device, and more particularly to a current-driven display device including display elements such as organic EL elements that are driven by current.

[0002] In recent years, organic EL display devices equipped with pixel circuits including organic EL elements have been put to practical use. Organic EL elements, also known as OLEDs (organic light-emitting diodes), are self-luminous display elements that emit light at a brightness corresponding to the current flowing through them. Because organic EL elements are self-luminous display elements, organic EL display devices can be easily made thinner, consume less power, and have higher brightness than liquid crystal display devices that require a backlight and a color filter.

[0003] The display section of an organic EL display device is provided with multiple data signal lines that transmit data signals, multiple scanning signal lines that transmit scanning signals that control the writing of data signals to pixel circuits, and multiple emission control lines that transmit emission control signals that control the emission of organic EL elements in the pixel circuits. The multiple scanning signal lines and multiple emission control lines intersect perpendicularly with the multiple data signal lines. The organic EL display device also includes a data signal line drive circuit that drives the multiple data signal lines, a scanning signal line drive circuit that drives the multiple scanning signal lines, and an emission control circuit that drives the multiple emission control lines. Hereinafter, the scanning signal line drive circuit and the emission control circuit will be collectively referred to as the "scanning side drive circuit." Generally, the scanning side drive circuit is composed of a shift register consisting of multiple stages. Each stage of the shift register (hereinafter referred to as a "unit circuit") includes a large number of TFTs (thin film transistors).

[0004] In the organic EL display device described above, display defects may occur due to changes in the characteristics of the TFTs in the unit circuits. Therefore, Japanese Patent Application Laid-Open No. 2017-084435 describes a method for alleviating stress on the transistors by providing back gates to some of the transistors in the unit circuits and swapping the potentials of the gate and back gates with each other during a non-selection period, in order to prevent a decrease in reliability due to deterioration of the transistor characteristics.

[0005] In addition, the following prior art documents are also known in relation to the following disclosures: WO 2019 / 123089 describes applying a voltage to the back gates of some transistors in a unit circuit to change the threshold voltage of the transistors and thereby suppress an increase in off-state current in order to suppress an increase in power consumption; WO 2017 / 150443 describes providing a back gate to a clear transistor and controlling the back gate voltage to reduce the threshold voltage of the clear transistor and increase the off-state leakage current so that charge on a floating node in the unit circuit is quickly removed when the device is powered off.

[0006] Japanese Patent Publication No. 2017-084435 International Publication No. 2019 / 123089 Pamphlet International Publication No. 2017 / 150443 Pamphlet

[0007] As described above, the characteristics of TFTs in a unit circuit can change. In particular, TFT characteristics are more susceptible to change at the upper edge of the panel. This is because the pattern density at the upper edge of the panel varies significantly, making it susceptible to process effects such as plasma damage due to the microloading effect (a phenomenon in which the etching rate decreases or the processed shape changes depending on the pattern density) and ESD (electrostatic discharge). If the characteristics of TFTs in a unit circuit at the upper edge of the panel change significantly, bright lines may appear at the upper edge of the panel. For example, in FIG. 19, the outer edge of the housing of an organic EL display device is represented by a dashed line labeled 95, and the display unit is represented by a solid line labeled 96. Bright lines may appear in the dotted line labeled 97. Furthermore, organic EL elements that should be lit at the upper edge of the panel may not be lit. The principles behind such display defects are explained below.

[0008] FIG. 20 is a circuit diagram showing an example of the configuration of a conventional unit circuit constituting a shift register as a scanning-side driver circuit. This unit circuit includes ten transistors Q1 to Q10 and one capacitor C91. Transistors Q1 to Q3, Q5 to Q8, and Q10 are P-channel TFTs, while transistors Q4 and Q9 are N-channel TFTs. This unit circuit also includes input terminals for power supply voltages (first high-level power supply voltage GVDD, second high-level power supply voltage GVDD2, and low-level power supply voltage GVSS), as well as three input terminals 91 to 93 and two output terminals 98 and 99. The output signal from the unit circuit constituting the preceding stage is applied to input terminal 91 as a set signal S. One of multiple clock signals that operate the shift register is applied to input terminal 92 as a first control clock signal CK1. The other of the multiple clock signals is applied to input terminal 93 as a second control clock signal CK2. Output terminals 98 and 99 output output signals OUT1 and OUT2 for controlling the on / off of transistors in the pixel circuits.

[0009] In the above-described configuration, during the period during which a series of operations for outputting active output signals OUT1 and OUT2 from this unit circuit are performed (a period roughly corresponding to the non-emission period described below), the voltages of the first internal node N91 and the third internal node N93 must be maintained at a low level so that the transistors Q7 and Q10 remain on. However, as described above, the TFT characteristics are prone to change at the upper edge of the panel. Regarding the plasma damage described above, analysis results show that negative charges on the TFT gates shift the characteristics of P-channel TFTs toward depletion and N-channel TFTs toward enhancement. Therefore, leakage currents are likely to occur in the P-channel TFTs in the unit circuits at the upper edge of the panel. As a result, during the period during which the voltages of the first internal node N91 and the third internal node N93 must be maintained at a low level, leakage currents flow, as indicated by the arrows (thick solid lines) labeled 901 and 902 in FIG. 20 . That is, the voltages of the first internal node N91 and the third internal node N93 cannot be maintained at a low level. This causes the output signals OUT1 and OUT2 from the unit circuits at the upper end of the panel to become abnormal. Incidentally, two dummy unit circuits, for example, are provided at the first stage of the shift register. However, because the gate start pulse signal is directly input to the dummy unit circuits as the set signal S, the dummy unit circuits operate almost normally. This allows the pixel circuits in the first and second rows to be initialized normally. However, as described above, the output signals OUT1 and OUT2 from the unit circuits at the upper end of the panel become abnormal, preventing data voltages (voltages of data signals) from being written to the pixel circuits in the first and second rows. As a result, the organic EL elements in the pixel circuits in the first and second rows emit light based on the voltages written by initialization, resulting in the bright lines appearing at the upper end of the panel as described above. Note that neither initialization nor writing of data voltages is performed on the pixel circuits in the third and subsequent rows, and the displayed image is not updated.

[0010] Therefore, the following disclosure relates to a display device using a display element driven by current, and aims to suppress the occurrence of display defects caused by changes in the characteristics of TFTs at the upper end of the panel.

[0011] a plurality of pixel circuits each including the display element and configuring a pixel matrix of n rows and m columns, where n and m are integers of 2 or greater; a data side driving circuit applying data signals to the plurality of data signal lines; a scanning side driving circuit including at least one shift register that drives the plurality of scanning signal lines or the plurality of emission control lines; a plurality of clock wirings for supplying the scanning side driving circuit with a plurality of clock signals required for operation of the at least one shift register; and a plurality of power supply wirings for supplying the scanning side driving circuit with a plurality of power supply voltages required for operation of the at least one shift register, wherein the at least one shift register is configured by at least n unit circuits, and each unit circuit The device includes: a buffer transistor, one of which is a first conduction terminal and a second conduction terminal, which are two terminals that function as a source and a drain, connected to one of the plurality of clock wirings or one of the plurality of power supply wirings, and the other of which is connected to a corresponding scanning signal line or a corresponding light emission control line; and a plurality of control transistors, one of which is a first conduction terminal and a second conduction terminal, which are two terminals that function as a source and a drain, connected to a gate of the buffer transistor directly or via another transistor, and at least one of the plurality of control transistors is provided with a back gate to which a DC voltage of opposite polarity to a gate voltage that turns the control transistor on is continuously applied.

[0012] a plurality of pixel circuits each including the display element and configuring a pixel matrix of n rows and m columns, where n and m are integers of 2 or greater; a data side driving circuit applying data signals to the plurality of data signal lines; a scanning side driving circuit including at least one shift register that drives the plurality of scanning signal lines or the plurality of emission control lines; a plurality of clock wirings for supplying the scanning side driving circuit with a plurality of clock signals required for operation of the at least one shift register; and a plurality of power supply wirings for supplying the scanning side driving circuit with a plurality of power supply voltages required for operation of the at least one shift register, wherein the at least one shift register is configured by at least n unit circuits, and each unit circuit a buffer transistor, one of two terminals functioning as a source and a drain, namely a first conduction terminal and a second conduction terminal, connected to one of the plurality of clock wirings or one of the plurality of power supply wirings, and the other of the first conduction terminal and the second conduction terminal connected to a corresponding scanning signal line or a corresponding light-emitting control line; and a plurality of control transistors, one of the two terminals functioning as a source and a drain, namely the first conduction terminal and the second conduction terminal, connected to a gate of the buffer transistor directly or via another transistor, wherein the plurality of control transistors include a first control transistor having a gate to which one of the plurality of clock signals is applied, a first conduction terminal to which a shift pulse is applied, a second conduction terminal connected to the gate of the buffer transistor directly or via another transistor, and a back gate to which the shift pulse is applied, and throughout the off period of the shift pulse, a voltage of opposite polarity to the gate voltage that turns the first control transistor into an on state is applied to the back gate.

[0013] According to some embodiments of the present disclosure, a unit circuit constituting at least one shift register included in a scanning-side driving circuit includes a plurality of control transistors, each of whose source and drain are connected to the gate of a buffer transistor, either directly or via another transistor. A backgate is provided to at least one of the control transistors. A DC voltage of opposite polarity to the gate voltage that turns the control transistor on is continuously applied to the backgate. Therefore, even if the characteristics (Ids-Vgs characteristics) of the control transistor shift toward depletion due to plasma damage during the manufacturing of the display device, the backgate voltage shifts the characteristics of the control transistor toward enhancement. This suppresses leakage current in the control transistor and reduces display defects such as bright lines appearing at the upper edge of the panel. As described above, display devices using current-driven display elements are able to reduce display defects caused by changes in transistor characteristics at the upper edge of the panel.

[0014] According to some other embodiments of the present disclosure, in a unit circuit constituting at least one shift register included in a scanning-side driving circuit, at least one of the plurality of control transistors is provided with a back gate, and a voltage of opposite polarity to the gate voltage that turns the control transistor on is applied to the back gate during the off period of the shift pulse. Therefore, even if the characteristics (Ids-Vgs characteristics) of the control transistor are shifted toward depletion due to plasma damage during the manufacturing of the display device, the back gate voltage shifts the characteristics of the control transistor toward enhancement during the off period of the shift pulse. This suppresses the occurrence of leakage current in the control transistor and suppresses display defects such as the appearance of bright lines at the upper edge of the panel. As described above, in a display device using a display element driven by current, display defects caused by changes in the characteristics of the transistor at the upper edge of the panel are suppressed.

[0015] 1 is a circuit diagram showing a configuration of a unit circuit in the first embodiment. FIG. 2 is a block diagram showing an overall configuration of an organic EL display device according to the first embodiment. FIG. 3 is a timing chart for explaining a schematic operation of the organic EL display device according to the first embodiment. FIG. 4 is a circuit diagram showing a configuration of a pixel circuit in the first embodiment. FIG. 5 is a timing chart for explaining the operation of the pixel circuit in the first embodiment. FIG. 6 is a block diagram showing a schematic configuration of a scanning side drive circuit in the first embodiment. FIG. 7 is a block diagram showing a configuration of a scanning signal line drive circuit in the first embodiment. FIG. 8 is a timing chart for explaining the operation of a unit circuit in the first embodiment. FIG. 9 is a partial cross-sectional view of a unit circuit in the first embodiment. FIG. 10 is a diagram showing Ids-Vgs characteristics for an N-channel TFT. FIG. 11 is a diagram showing Ids-Vgs characteristics for a P-channel TFT. FIG. 12 is a diagram for explaining the effect of the first embodiment. FIG. 13 is a diagram for explaining a circuit configuration in a modified example of the first embodiment. FIG. 14 is a partial cross-sectional view of a unit circuit in the modified example of the first embodiment. FIG. 15 is a block diagram showing a schematic configuration of a scanning side drive circuit in the second embodiment. FIG. 16 is a block diagram showing the configuration of a scanning signal line drive circuit in the second embodiment. FIG. 17 is a circuit diagram showing a configuration of a unit circuit in the second embodiment. FIG. 18 is a timing chart for explaining the operation of a unit circuit in the second embodiment. 1 is a circuit diagram illustrating an example of a configuration of a conventional unit circuit, and FIG.

[0016] Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that among the TFTs described below, the drain and source are interchangeable during operation. Therefore, for each TFT, one of the two terminals that function as the drain and source is fixedly referred to as the "drain," and the other of the two terminals is fixedly referred to as the "source." Each timing chart shows an ideal waveform that ignores delays.

[0017] 2 is a block diagram showing the overall configuration of an organic EL display device 10 according to a first embodiment. The organic EL display device 10 has a function of performing compensation processing to compensate for variations and fluctuations in the threshold voltage of a drive transistor (described later) in a pixel circuit. The compensation processing method used is an internal compensation method in which a capacitor for storing information about the threshold voltage of the drive transistor is provided in the pixel circuit.

[0018] 2, the organic EL display device 10 includes a display unit 11, a display control circuit 20, a data-side drive circuit (data signal line drive circuit) 30, and a scanning-side drive circuit 40. The scanning-side drive circuit 40 functions as a scanning signal line drive circuit and a light-emission control circuit. At least a portion of the scanning-side drive circuit 40 and the data-side drive circuit 30 may be formed integrally with the display unit 11. The organic EL display device 10 also includes a power supply circuit (not shown) that generates various power supply voltages.

[0019] The display unit 11 is provided with (n+2) first scanning signal lines NS(-1) to NS(n), n second scanning signal lines PS(1) to PS(n), n light-emission control lines EM(1) to EM(n), and m data signal lines D(1) to D(m), where m and n are integers equal to or greater than 2. The first scanning signal lines NS(-1) to NS(n), the second scanning signal lines PS(1) to PS(n), and the light-emission control lines EM(1) to EM(n) are typically parallel to one another. The first scanning signal lines NS(-1) to NS(n) are perpendicular to the data signal lines D(1) to D(m). Each first scanning signal line NS transmits a first scanning signal, each second scanning signal line PS transmits a second scanning signal, each light-emission control line EM transmits a light-emission control signal, and each data signal line D transmits a data signal. The display unit 11 also has n×m pixel circuits 15. The n×m pixel circuits 15 form a pixel matrix of n rows and m columns. Hereinafter, when distinguishing between the n×m pixel circuits 15, the pixel circuit corresponding to the ith second scanning signal line PS(i) and the jth data signal line D(j) will be referred to as the "pixel circuit in the ith row and jth column." The pixel circuit in the ith row and jth column will be given the symbol 15(i, j). Furthermore, hereinafter, as necessary, the first scanning signals respectively supplied to the first scanning signal lines NS(-1) to NS(n) will also be assigned the symbols NS(-1) to NS(n), the second scanning signals respectively supplied to the second scanning signal lines PS(1) to PS(n) will also be assigned the symbols PS(1) to PS(n), the light emission control signals respectively supplied to the light emission control lines EM(1) to EM(n) will also be assigned the symbols EM(1) to EM(n), and the data signals respectively supplied to the data signal lines D(1) to D(m) will also be assigned the symbols D(1) to D(m).

[0020] Furthermore, the display unit 11 is provided with power supply wiring (not shown) that is common to each pixel circuit 15. More specifically, a power supply line (hereinafter referred to as a "high-level power supply line") that supplies a high-level power supply voltage ELVDD for driving the organic EL elements, a power supply line (hereinafter referred to as a "low-level power supply line") that supplies a low-level power supply voltage ELVSS for driving the organic EL elements, and a power supply line (hereinafter referred to as an "initialization power supply line") that supplies an initialization voltage Vini are provided.

[0021] The operation of each component shown in Fig. 2 will now be described. The display control circuit 20 receives an input signal Sin from outside the organic EL display device 10, which includes image information representing an image to be displayed and timing control information for image display, and outputs a data-side control signal Scd that controls the operation of the data-side drive circuit 30 and a scan-side control signal Scs that controls the operation of the scan-side drive circuit 40.

[0022] The data side drive circuit 30 drives the data signal lines D(1) to D(m) based on the data side control signal Scd output from the display control circuit 20. That is, the data side drive circuit 30 generates m data signals representing an image to be displayed based on the data side control signal Scd and applies them to the data signal lines D(1) to D(m).

[0023] The scanning-side drive circuit 40 drives the first scanning signal lines NS(-1) to NS(n), the second scanning signal lines PS(1) to PS(n), and the light-emission control lines EM(1) to EM(n) based on the scanning-side control signal Scs output from the display control circuit 20. That is, based on the scanning-side control signal Scs, the scanning-side drive circuit 40 applies first scanning signals to the first scanning signal lines NS(-1) to NS(n), applies second scanning signals to the second scanning signal lines PS(1) to PS(n), and applies light-emission control signals to the light-emission control lines EM(1) to EM(n).

[0024] In this manner, data signals are applied to the data signal lines D(1) to D(m), first scanning signals are applied to the first scanning signal lines NS(-1) to NS(n), second scanning signals are applied to the second scanning signal lines PS(1) to PS(n), and light emission control signals are applied to the light emission control lines EM(1) to EM(n), whereby an image based on the input signal Sin is displayed on the display unit 11.

[0025] <1.2 General Operation> The general operation of the organic EL display device 10 will be described with reference to the timing chart shown in Figure 3. The scanning control signal Scs provided from the display control circuit 20 to the scanning drive circuit 40 includes a two-phase clock signal consisting of a first gate clock signal GCK1 and a second gate clock signal GCK2. Based on this two-phase clock signal, the scanning drive circuit 40 outputs second scanning signals PS(1) to PS(n), first scanning signals NS(-1) to NS(n), and light-emission control signals EM(1) to EM(n). Meanwhile, the data drive circuit 30 outputs data signals D(1) to D(m) based on the data-side control signal Scd provided from the display control circuit 20. Note that Figure 3 shows the waveforms of the second scanning signals PS(i-2) to PS(i+2), the first scanning signals NS(i-2) to NS(i+2), the light-emission control signals EM(i-2) to EM(i+2), and the data signal D(j). As can be seen from FIG. 3 , during each frame period, the n second scanning signal lines PS(1) to PS(n), the (n+2) first scanning signal lines NS(−1) to NS(n), and the n light-emitting control lines EM(1) to EM(n) are sequentially selected for a predetermined period. In each row, the period during which the corresponding light-emitting control signal EM is maintained at a high level is the non-light-emitting period, and the period during which the corresponding light-emitting control signal EM is maintained at a low level is the light-emitting period. The first scanning signal NS goes high for a predetermined period during the non-light-emitting period, and the second scanning signal PS goes low for a portion of the period during which the first scanning signal NS is maintained at a high level, thereby writing a data voltage (the voltage of the data signal D) to the pixel circuit 15. During the light-emitting period, the pixel circuit 15 emits light at a brightness corresponding to the written data voltage.

[0026] 1.3 Pixel Circuit Configuration Figure 4 is a circuit diagram showing the configuration of a pixel circuit 15(i,j) in row i and column j. As shown in Figure 4, the pixel circuit 15(i,j) includes one organic EL element (organic light-emitting diode) 151 as a display element, seven transistors T1 to T7 (a first initialization transistor T1, a threshold compensation transistor T2, a write control transistor T3, a drive transistor T4, a first light-emission control transistor T5, a second light-emission control transistor T6, and a second initialization transistor T7), and one storage capacitor Cst. In this embodiment, the first initialization transistor T1, the threshold compensation transistor T2, and the second initialization transistor T7 are N-channel TFTs, and the write control transistor T3, the drive transistor T4, the first light-emission control transistor T5, and the second light-emission control transistor T6 are P-channel TFTs. For example, an oxide TFT using an oxide semiconductor for the channel layer (more specifically, an IGZO-TFT in which the channel layer is formed from an oxide semiconductor containing indium, gallium, zinc, and oxygen) is used as an N-channel TFT, and an LTPS-TFT using low-temperature polysilicon for the channel layer is used as a P-channel TFT. The storage capacitor Cst is a capacitive element consisting of two electrodes (a first electrode and a second electrode).

[0027] The pixel circuit 15(i, j) is connected to the first scanning signal line NS(i), the first scanning signal line NS(i-2), the second scanning signal line PS(i), the light-emitting control line EM(i), the data signal line D(j), the high-level power supply line, the low-level power supply line, and the initialization power supply line.

[0028] The first initialization transistor T1 has a gate connected to the first scanning signal line NS(i-2), a drain connected to the second electrode of the storage capacitor Cst, the gate of the driving transistor T4, and the source of the threshold compensation transistor T2, and a source connected to the initialization power supply line. The threshold compensation transistor T2 has a gate connected to the first scanning signal line NS(i), a drain connected to the drain of the driving transistor T4 and the source of the second light-emitting control transistor T6, and a source connected to the second electrode of the storage capacitor Cst, the drain of the first initialization transistor T1, and the gate of the driving transistor T4. The write control transistor T3 has a gate connected to the second scanning signal line PS(i), a drain connected to the source of the driving transistor T4 and the drain of the first light-emitting control transistor T5, and a source connected to the data signal line D(j). As for the driving transistor T4, its gate is connected to the second electrode of the storage capacitor Cst, the drain of the first initialization transistor T1, and the source of the threshold compensation transistor T2, its drain is connected to the drain of the threshold compensation transistor T2 and the source of the second light-emitting control transistor T6, and its source is connected to the drain of the write control transistor T3 and the drain of the first light-emitting control transistor T5.

[0029] The first light-emission control transistor T5 has a gate connected to the light-emission control line EM(i), a drain connected to the drain of the write control transistor T3 and the source of the drive transistor T4, and a source connected to a high-level power supply line. The second light-emission control transistor T6 has a gate connected to the light-emission control line EM(i), a drain connected to the drain of the second initialization transistor T7 and the anode electrode of the organic EL element 151, and a source connected to the drain of the threshold compensation transistor T2 and the drain of the drive transistor T4. The second initialization transistor T7 has a gate connected to the light-emission control line EM(i), a drain connected to the drain of the second light-emission control transistor T6 and the anode electrode of the organic EL element 151, and a source connected to the initialization power supply line. The storage capacitor Cst has a first electrode connected to the high-level power supply line, and a second electrode connected to the drain of the first initialization transistor T1, the source of the threshold compensation transistor T2, and the gate of the drive transistor T4. As for the organic EL element 151, the anode electrode is connected to the drain of the second light emission control transistor T6 and the drain of the second initialization transistor T7, and the cathode electrode is connected to the low-level power supply line.

[0030] <1.4 Operation of Pixel Circuit> Next, the operation of pixel circuit 15(i,j) will be described with reference to the timing chart shown in Fig. 5. Note that with reference to Fig. 5, it is assumed that the period before time t1 and the period after time t8 are light-emitting periods (periods during which organic EL element 151 in pixel circuit 15(i,j) should be maintained in an emitting state), and the period from time t1 to time t8 is a non-light-emitting period (period during which organic EL element 151 in pixel circuit 15(i,j) should be maintained in an extinguished state).

[0031] Just before time t1, the first scanning signal NS(i-2), the first scanning signal NS(i), and the light-emission control signal EM(i) are at low level, and the second scanning signal PS(i) is at high level. At this time, the first initialization transistor T1, the threshold compensation transistor T2, the write control transistor T3, and the second initialization transistor T7 are in the off state, and the first light-emission control transistor T5 and the second light-emission control transistor T6 are in the on state. Therefore, the organic EL element 151 emits light in accordance with the magnitude of the drive current.

[0032] At time t1, the light emission control signal EM(i) changes from low to high. This causes the first light emission control transistor T5 and the second light emission control transistor T6 to turn off. As a result, the supply of current to the organic EL element 151 is cut off, and the organic EL element 151 turns off. In addition, the second initialization transistor T7 turns on. As a result, the anode voltage of the organic EL element 151 is initialized.

[0033] At time t2, the first scanning signal N(i-2) changes from low level to high level. This turns on the first initialization transistor T1. As a result, the holding capacitor Cst is initialized, and the gate voltage Vg of the drive transistor T4 becomes the initialization voltage Vini. At time t3, the first scanning signal N(i-2) changes from high level to low level. This turns off the first initialization transistor T1.

[0034] At time t4, the first scanning signal NS(i) changes from low to high, which turns on the threshold compensation transistor T2 and puts the drive transistor T4 into a diode-connected state.

[0035] At time t5, the second scanning signal PS(i) changes from high to low. This turns on the write control transistor T3. At this time, the threshold compensation transistor T2 is on, and the drive transistor T4 is in a diode-connected state. Therefore, the voltage of the data signal D(j) is applied as the data voltage Vdata to the storage capacitor Cst via the diode-connected drive transistor T4. As a result, the threshold-compensated data voltage is written to the storage capacitor Cst, and the gate voltage Vg of the drive transistor T4 is maintained at the voltage of the second electrode of the storage capacitor Cst. At this time, if the threshold voltage of the drive transistor T4 is represented by Vth (<0), the gate voltage Vg is expressed by the following equation (1): Vg = Vdata + Vth (1) In this way, during the period from time t5 to time t6, when the write control transistor T3 turns off, the data voltage is written while performing internal compensation.

[0036] At time t6, the second scanning signal PS(i) changes from low to high, turning off the write control transistor T3. At time t7, the first scanning signal NS(i) changes from high to low, turning off the threshold compensation transistor T2.

[0037] At time t8, the light-emission control signal EM(i) changes from high to low. This causes the first light-emission control transistor T5 and the second light-emission control transistor T6 to turn on. As a result, a drive current corresponding to the gate voltage Vg of the drive transistor T4 is supplied to the organic EL element 151, and the organic EL element 151 emits light according to the magnitude of the drive current.

[0038] 6 is a block diagram showing a schematic configuration of the scanning side driving circuit 40 in this embodiment. The scanning side driving circuit 40 comprises a scanning signal line driving circuit 401 and a light emission control circuit 409. The scanning signal line driving circuit 401 applies a first scanning signal NS to the first scanning signal line and a second scanning signal PS to the second scanning signal line. The light emission control circuit 409 applies a light emission control signal EM to the light emission control line. The configuration and operation of the scanning signal line driving circuit 401 will be described in detail below. The light emission control circuit 409 can have, for example, a known configuration.

[0039] <1.5.1 Configuration of Scanning Signal Line Drive Circuit> Fig. 7 is a block diagram showing the configuration of the scanning signal line drive circuit 401. The scanning signal line drive circuit 401 in this embodiment is configured by a shift register consisting of (n+2) stages (in other words, (n+2) unit circuits). Note that Fig. 7 only shows the unit circuits 4(i-2), 4(i-1), 4(i), 4(i+1), and 4(i+2) in the (i-2)th stage, (i-1)th stage, i-th stage, (i+1)th stage, and (i+2)th stage, where i is an even number.

[0040] The shift register serving as the scanning signal line driving circuit 401 is supplied with the scanning-side control signal Scs, which includes two-phase clock signals, a first gate clock signal GCK1 and a second gate clock signal GCK2, and a gate start pulse signal (not shown). The shift register is also supplied with a first high-level power supply voltage GVDD, a second high-level power supply voltage GVDD2, and a low-level power supply voltage GVSS as operating power supply voltages. The first high-level power supply voltage GVDD is a voltage at a level that turns on the N-channel TFTs in the pixel circuits 15 and turns off the P-channel TFTs in the pixel circuits 15. The low-level power supply voltage GVSS is a voltage at a level that turns off the N-channel TFTs in the pixel circuits 15 and turns on the P-channel TFTs in the pixel circuits 15. 7, the first clock wiring for supplying the first gate clock signal GCK1 is denoted by reference numeral 461, the second clock wiring for supplying the second gate clock signal GCK2 is denoted by reference numeral 462, the first power supply wiring for supplying the first high-level power supply voltage GVDD is denoted by reference numeral 471, the second power supply wiring for supplying the low-level power supply voltage GVSS is denoted by reference numeral 472, and the third power supply wiring for supplying the second high-level power supply voltage GVDD2 is denoted by reference numeral 473.

[0041] Each unit circuit 4 includes input terminals for receiving the first control clock signal CK1, the second control clock signal CK2, the set signal S, the first high-level power supply voltage GVDD, the second high-level power supply voltage GVDD2, and the low-level power supply voltage GVSS, respectively, and output terminals for outputting the first output signal OUT1 and the second output signal OUT2, respectively.

[0042] The even-numbered unit circuits 4 are supplied with the first gate clock signal GCK1 as the first control clock signal CK1 and the second gate clock signal GCK2 as the second control clock signal CK2. The odd-numbered unit circuits 4 are supplied with the second gate clock signal GCK2 as the first control clock signal CK1 and the first gate clock signal GCK1 as the second control clock signal CK2. The first high-level power supply voltage GVDD, the second high-level power supply voltage GVDD2, and the low-level power supply voltage GVSS are commonly supplied to all the unit circuits 4. Furthermore, the second output signal OUT2 output from the unit circuit 4 of the previous stage is supplied to the unit circuit 4 of each stage as a set signal S. The first output signal OUT1 output from the unit circuit 4 of each stage is supplied to the corresponding first scanning signal line NS as a first scanning signal. The second output signal OUT2 output from the unit circuit 4 of each stage is given as a set signal S to the unit circuit 4 of the next stage, and is given as a second scanning signal to the corresponding second scanning signal line PS.

[0043] 1 is a circuit diagram showing the configuration of a unit circuit 4 (the configuration of one stage of a shift register) in this embodiment. The unit circuit 4 includes ten transistors M1 to M10 and one capacitor C1. The transistors M1 to M3, M5 to M8, and M10 are P-channel TFTs, and the transistors M4 and M9 are N-channel TFTs. The unit circuit 4 also has an input terminal connected to a first power supply wiring 471 that supplies a first high-level power supply voltage GVDD, an input terminal connected to a third power supply wiring 473 that supplies a second high-level power supply voltage GVDD2, and an input terminal connected to a second power supply wiring 472 that supplies a low-level power supply voltage GVSS, as well as three input terminals 41 to 43 and two output terminals 48 and 49. 1, the input terminal for receiving the set signal S is denoted by reference numeral 41, the input terminal for receiving the first control clock signal CK1 is denoted by reference numeral 42, the input terminal for receiving the second control clock signal CK2 is denoted by reference numeral 43, the output terminal for outputting the first output signal OUT1 is denoted by reference numeral 48, and the output terminal for outputting the second output signal OUT2 is denoted by reference numeral 49. In the following, the output terminal 48 for outputting the first output signal OUT1 is referred to as the "first output terminal," and the output terminal 49 for outputting the second output signal OUT2 is referred to as the "second output terminal."

[0044] The source of transistor M1, the drain of transistor M2, the gate of transistor M4, the gate of transistor M5, the source of transistor M6, the gate of transistor M9, and the gate of transistor M10 are connected to one another. The node where these are connected is called the "first internal node." The first internal node is denoted by the symbol N1. The source of transistor M2 and the drain of transistor M3 are connected to one another. The node where these are connected is called the "second internal node." The second internal node is denoted by the symbol N2. The drain of transistor M6, the gate of transistor M7, and one end of capacitor C1 are connected to one another. The node where these are connected is called the "third internal node." The third internal node is denoted by the symbol N3. The gate of transistor M3, the drain of transistor M4, the drain of transistor M5, and the gate of transistor M8 are connected to one another. The node where these are connected is called the "fourth internal node." The fourth internal node is denoted by the symbol N4.

[0045] The unit circuit 4 includes a first control circuit 411 that controls the voltage of the first internal node N1, a second control circuit 412 that controls the voltage of the fourth internal node N4, a third control circuit 413 that controls the voltage of the first internal node N1, a first output circuit 421 that controls the output of the first output signal OUT1, and a second output circuit 422 that controls the output of the second output signal OUT2. The first control circuit 411 includes a transistor M1. The second control circuit 412 includes transistors M4 and M5. The third control circuit 413 includes a stabilization circuit 430 and a transistor M6. The stabilization circuit 430 includes transistors M2 and M3. The first output circuit 421 includes transistors M9 and M10. The second output circuit 422 includes transistors M7 and M8 and a capacitor C1.

[0046] The transistor M1 has a gate connected to the input terminal 42, a drain connected to the input terminal 41, and a source connected to the first internal node N1. The transistor M1 is also provided with a back gate (back gate electrode) 61, which is connected to the input terminal 41. Note that a configuration in which the first high-level power supply voltage GVDD is applied to the back gate 61 may also be employed. The transistor M2 has a gate connected to the input terminal 43, a drain connected to the first internal node N1, and a source connected to the second internal node N2. The transistor M2 is also provided with a back gate (back gate electrode) 62, which is connected to the first power supply wiring 471. That is, the first high-level power supply voltage GVDD is applied to the back gate 62 of the transistor M2. The transistor M3 has a gate connected to the fourth internal node N4, a drain connected to the second internal node N2, and a source connected to the first power supply wiring 471. The transistor M3 is provided with a back gate (back gate electrode) 63, which is connected to the first power supply wiring 471. That is, the first high-level power supply voltage GVDD is applied to the back gate 63 of the transistor M3. As described above, the transistors M1 to M3 are provided with the back gates 61 to 63.

[0047] The transistor M4 has a gate connected to the first internal node N1, a drain connected to the fourth internal node N4, and a source connected to the second power supply wiring 472. The transistor M5 has a gate connected to the first internal node N1, a drain connected to the fourth internal node N4, and a source connected to the first power supply wiring 471. The transistor M6 has a gate connected to the second power supply wiring 472, a drain connected to the third internal node N3, and a source connected to the first internal node N1. The transistor M7 has a gate connected to the third internal node N3, a drain connected to the input terminal 43, and a source connected to the second output terminal 49. The transistor M8 has a gate connected to the fourth internal node N4, a drain connected to the second output terminal 49, and a source connected to the first power supply wiring 471. The transistor M9 has a gate connected to the first internal node N1, a drain connected to the first output terminal 48, and a source connected to the second power supply wiring 472. The transistor M10 has a gate connected to the first internal node N1, a drain connected to the first output terminal 48, and a source connected to the third power supply wiring 473. The capacitor C1 has one end connected to the third internal node N3 and the other end connected to the second output terminal 49.

[0048] In this embodiment, the transistors M1 to M6 constitute control transistors, and the transistors M7 to M10 constitute buffer transistors. The transistors M1 to M6 constitute first to sixth control transistors, respectively. The transistor M7 constitutes a first buffer transistor, and the transistor M8 constitutes a second buffer transistor. The first high-level power supply voltage GVDD constitutes a first power supply voltage, and the low-level power supply voltage GVSS constitutes a second power supply voltage.

[0049] 8, the operation of the unit circuit 4 will be described. During the period before time t11, the voltages of the first internal node N1, the second internal node N2, and the third internal node N3 are maintained at a high level, the voltage of the fourth internal node N4 is maintained at a low level, the first output signal OUT1 is maintained at a low level, and the second output signal OUT2 is maintained at a high level. Note that, since the fourth internal node N4 is maintained at a low level, the transistors M3 and M8 are maintained in an on state.

[0050] At time t11, the first control clock signal CK1 changes from high to low. This turns on the transistor M1. Also at time t11, the set signal S changes from high to low (in other words, a shift pulse is input). As a result, the voltage of the first internal node N1 drops to low, the transistors M5 and M10 are on, and the transistors M4 and M9 are off. With the transistor M4 in the off state and the transistor M5 in the on state, the voltage of the fourth internal node N4 changes from low to high. With the transistor M9 in the off state and the transistor M10 in the on state, the first output signal OUT1 changes from low to high. Even though the voltage of the first internal node N1 drops to low, the transistor M6 remains on, and the voltage of the third internal node N3 also drops to low. This turns on the transistor M7.

[0051] At time t12, the first control clock signal CK1 changes from low to high, turning off the transistor M1. Also at time t12, the set signal S changes from low to high.

[0052] At time t13, the second control clock signal CK2 changes from high to low. At this time, because transistor M7 is on, the voltage at the input terminal 43 drops, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) drops. Because capacitor C1 is provided between the third internal node N3 and the second output terminal 49, the voltage at the third internal node N3 also drops as the voltage at the second output terminal 49 drops (the third internal node N3 enters a boosted state). As a result, a large negative voltage is applied to the gate of transistor M7. This bootstrap operation reduces the voltage of the second output signal OUT2 to a level sufficient to turn on the write control transistor T3 (see FIG. 4 ) connected to the second output terminal 49. When the voltage at the third internal node N3 drops at time t13, the drain voltage of transistor M6 becomes lower than the gate voltage. This turns transistor M6 off. Therefore, the voltage of the first internal node N1 does not change at time t13.

[0053] At time t14, the second control clock signal CK2 changes from low to high. This causes the voltage at the input terminal 43 to rise, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) to rise. When the voltage at the second output terminal 49 rises, the voltage at the third internal node N3 also rises via the capacitor C1. This turns on the transistor M6.

[0054] At time t15, the first control clock signal CK1 changes from high to low. This turns on transistor M1. At this time, the set signal S is maintained at high. This causes the voltage at the first internal node N1 to rise to high, turning off transistors M5 and M10 and turning on transistors M4 and M9. As a result, the first output signal OUT1 changes from high to low. The voltage at the fourth internal node N4 also changes from high to low. This turns on transistors M3 and M8. Furthermore, because transistor M6 is maintained in the on state, the voltage at the third internal node N3 also rises to high at time t15. This turns off transistor M7. The period after time t15 is the same as the period before time t11.

[0055] Incidentally, parasitic capacitance exists in the transistors in the unit circuit 4. Therefore, before time t11 and after time t15, fluctuations in the voltages of the first internal node N1 and the third internal node N3 may occur due to the clock operation of the second control clock signal CK2 and the presence of parasitic capacitance in the transistor M7. This may cause fluctuations in the voltages of the first output signal OUT1 and the second output signal OUT2. However, before time t11 and after time t15, the transistor M3 is maintained in the on state, and the transistor M2 is turned on every time the second control clock signal CK2 goes low. When both the transistors M2 and M3 are on, the first internal node N1 is connected to the first power supply wiring 471 that supplies the first high-level power supply voltage GVDD. Therefore, even if noise occurs due to the clock operation of the second control clock signal CK2 during the period before time t11 or the period after time t15, the voltages of the first internal node N1 and the third internal node N3 are reliably maintained at a high level.

[0056] Note that, during the period from time t11 to time t13, the second control clock signal CK2 is at a high level, so the transistor M2 is maintained in an off state. Therefore, the voltage of the second internal node N2 being maintained at a high level does not affect the voltages of the first internal node N1 and the third internal node N3. Also, since the transistor M3 is in an off state at time t13, the second control clock signal CK2 changes from a high level to a low level, and the voltage of the second internal node N2 also changes from a high level to a low level. Thereafter, as described above, the transistor M3 turns on at time t15, and the voltage of the second internal node N2 changes from a low level to a high level.

[0057] <1.5.4 Regarding the Back Gate> Here, a cross-sectional view of the portion where transistors M2 to M5 are provided is shown in FIG. 9. In FIG. 9, the regions marked with reference numerals 52 to 55 are the regions where transistors M2 to M5 are provided, respectively. Note that these transistors M2 to M5 are not arranged in a linear fashion. Also, in FIG. 9, contact holes are indicated by hatching. As shown in FIG. 9, a base coat film 112, a back gate insulating film 113, a gate insulating film 114, a first interlayer insulating film 115, a second interlayer insulating film 116, an organic interlayer insulating film 117, and a bank layer 118 are stacked on a polyimide substrate 111. For example, the back gate insulating film 113 and the gate insulating film 114 are formed using silicon dioxide (SiO2), the first interlayer insulating film 115 is formed using silicon nitride (SiNx), the second interlayer insulating film 116 is formed using silicon nitride (SiNx) or silicon oxide (SiOx), and the organic interlayer insulating film 117 and the bank layer 118 are formed using polyimide (PI). In a partial region on the base coat film 112, a back gate electrode 120 is formed using, for example, molybdenum (Mo). In a partial region on the back gate insulating film 113, a semiconductor layer is formed using, for example, low-temperature polysilicon. In this regard, the regions denoted by reference numerals 131 to 137 are p-type semiconductor layers doped with high concentrations of impurities. +The regions denoted by reference numerals 141 to 143 are channel regions. Gate electrodes 161 to 163 are formed on a portion of the gate insulating film 114 using, for example, molybdenum (Mo). For example, when attention is focused on the region 52 where the transistor M2 is provided, the p + region 131 and p acting as a source + A channel region (N-type semiconductor) 141 exists between the gate electrode 161 and the semiconductor layer (p + region 131, channel region 141, p + The top gate electrode 181 is insulated from the semiconductor layer 132 by a gate insulating film 114, and the back gate electrode 120 is insulated from the semiconductor layer 132 by a back gate insulating film 113. Furthermore, metal layers 171 and 172 are formed in a partial region of the first interlayer insulating film 115, for example, using molybdenum (Mo). Then, a transistor M4 is formed in the region 54, which is composed of a top gate electrode 181, a top gate insulating film 182, and a semiconductor layer 183. For example, the top gate electrode 181 is formed from molybdenum (Mo), the top gate insulating film 182 is formed from silicon dioxide (SiO), and the semiconductor layer 183 is formed from an oxide semiconductor containing indium, gallium, zinc, and oxygen.

[0058] 9, in this embodiment, one electrode (back gate electrode 120) functions as the back gate 62 of the transistor M2 and the back gate 63 of the transistor M3 (see FIG. 1). Therefore, the back gate 62 of the transistor M2 and the back gate 63 of the transistor M3 are supplied with the same voltage (specifically, the first high-level power supply voltage GVDD).

[0059] Incidentally, when light is irradiated onto the semiconductor layer of a TFT, a leakage current occurs. However, according to the configuration shown in Fig. 9, the back gate electrode 120 functions as a light-shielding layer that prevents light from irradiating the semiconductor layers of transistors M2 and M3. That is, the back gates 62 and 63 shown in Fig. 1 function as light-shielding layers. Similarly, the back gate 61 shown in Fig. 1 (the back gate provided in transistor M1) also functions as a light-shielding layer.

[0060] FIG. 10 shows the Ids-Vgs characteristics (hereinafter simply referred to as "characteristics") of an N-channel TFT. Here, it is assumed that the characteristics when no voltage is applied to the back gate are represented by the thick dotted line labeled 71. When a positive voltage (here, a positive voltage refers to a voltage that turns the TFT on when applied to the gate) is applied to the back gate, the TFT enters a state similar to that in which a forward bias is applied to its semiconductor layer. This narrows the depletion layer within the TFT's semiconductor layer (in other words, a state in which a channel is more likely to form). As a result, the TFT's characteristics become, for example, as represented by the solid line labeled 72 in FIG. 10. As described above, when a positive voltage is applied to the back gate of an N-channel TFT, its characteristics shift toward depletion (negative).

[0061] In contrast, when a negative voltage (a voltage of opposite polarity to the positive voltage) is applied to the back gate, the TFT enters a state similar to that of a reverse bias applied to its semiconductor layer. This widens the depletion layer within the TFT's semiconductor layer (in other words, it becomes difficult for a channel to form). As a result, the TFT's characteristics become, for example, as represented by the thick solid line labeled 73 in FIG. 10. As described above, when a negative voltage is applied to the back gate of an N-channel TFT, its characteristics shift in the enhancement direction (positive direction).

[0062] FIG. 11 shows the Ids-Vgs characteristics of a P-channel TFT. Here, we assume that the characteristics when no voltage is applied to the back gate are represented by the thick dotted line labeled 74. When a negative voltage is applied to the back gate (here, a negative voltage refers to a voltage that turns the TFT on when applied to the gate), the TFT enters a state similar to that of a forward bias applied to its semiconductor layer. This narrows the depletion layer within the TFT's semiconductor layer (in other words, a state in which a channel is more likely to form). As a result, the TFT's characteristics become, for example, as represented by the thick solid line labeled 75 in FIG. 11. As described above, when a negative voltage is applied to the back gate of a P-channel TFT, its characteristics shift toward depletion (positive).

[0063] In contrast, when a positive voltage (a voltage of opposite polarity to the negative voltage) is applied to the back gate, the TFT enters a state similar to that of a reverse bias applied to its semiconductor layer. This widens the depletion layer within the TFT's semiconductor layer (in other words, it becomes difficult for a channel to form). As a result, the TFT's characteristics become, for example, as represented by the solid line labeled 76 in FIG. 11. As described above, when a positive voltage is applied to the back gate of a P-channel TFT, its characteristics shift in the enhancement direction (negative direction).

[0064] In this embodiment, as described above, back gates 61 to 63 are provided to transistors M1 to M3, which are P-channel TFTs (see FIG. 1). A first high-level power supply voltage GVDD is applied to the back gates 62 and 63 of transistors M2 and M3. The first high-level power supply voltage GVDD is a DC voltage of opposite polarity to the gate voltage that turns on the P-channel TFT transistors M2 and M3. In this manner, a positive voltage is continuously applied to the back gates 62 and 63 of transistors M2 and M3. Therefore, the transistors M2 and M3 in this embodiment have characteristics that are shifted toward the enhancement mode compared to the characteristics of a configuration in which back gates are not provided.

[0065] A set signal S is applied to the back gate 61 of transistor M1. As shown in FIG. 8 , the set signal S is low during the period from time t11 to time t12 (one horizontal scanning period of one frame period), but is maintained high during the remaining periods. The low-level voltage of the set signal S is a voltage of the same polarity as the gate voltage that turns on transistor M1, a P-channel TFT, and the high-level voltage of the set signal S is a voltage of the opposite polarity to the gate voltage that turns on transistor M1. In each unit circuit 4, the set signal S functions as a shift pulse when its logical level is low. As described above, a positive voltage is applied to the back gate 61 of transistor M1 during the off period of the shift pulse, and a negative voltage is applied during the on period of the shift pulse. Therefore, in this embodiment, transistor M1 has characteristics shifted toward enhancement compared to the characteristics of a configuration without a back gate during the off period of the shift pulse, and has characteristics shifted toward depletion compared to the characteristics of a configuration without a back gate during the on period of the shift pulse.

[0066] In this embodiment, back gates 61 to 63 are provided in the transistors M1 to M3 for all unit circuits 4 that constitute the shift register as the scanning signal line driving circuit 401. However, this is not limiting, and back gates 61 to 63 may be provided in the transistors M1 to M3 only for unit circuits 4 located at the upper end of the panel (for example, unit circuits 4 corresponding to pixel circuits 15 in the first and second rows). Also, for example, light-shielding back gates 61 to 63 may be provided in the transistors M1 to M3 for unit circuits 4 located at the upper end of the panel, and back gates 61 to 63 not having light-shielding properties may be provided in the transistors M1 to M3 for other unit circuits 4.

[0067] <1.6 Effects> According to this embodiment, in the unit circuit 4 constituting the shift register as the scanning signal line driving circuit 401, three transistors (P-channel TFTs) M1 to M3 are provided with back gates 61 to 63 for controlling the voltage of the first internal node N1, which is connected via transistor M6 to the gate of transistor M7, which functions as a buffer transistor. A DC voltage (first high-level power supply voltage GVDD) having a polarity opposite to that of the gate voltage that turns on the transistors M2 and M3 is continuously applied as a back gate voltage to the back gates 62 and 63 of the transistors M2 and M3. Therefore, even if the characteristics of the transistors M2 and M3 shift toward depletion due to, for example, plasma damage during the manufacturing of the organic EL display device 10, the back gate voltage shifts the characteristics of the transistors M2 and M3 toward enhancement. This suppresses the generation of leakage current in the transistors M2 and M3, and prevents the voltage at the first internal node N1 from increasing via the transistors M2 and M3 during the period from time t11 to time t15 in FIG. 8 . Furthermore, throughout the OFF period of the shift pulse, a voltage (the high-level voltage of the set signal S) of opposite polarity to the gate voltage that turns on the transistor M1 is continuously applied to the back gate 61 of the transistor M1 as a back gate voltage. Therefore, even if the characteristics of the transistor M1 have shifted toward depletion due to plasma damage or the like, the back gate voltage shifts the characteristics of the transistor M1 toward enhancement. This suppresses the generation of leakage current in the transistor M1, thereby preventing the voltage of the first internal node N1 from increasing via the transistor M1 during the period from time t12 to time t15 in FIG. 8 . As a result, the voltages of the first internal node N1 and the third internal node N3 are prevented from increasing due to leakage current during the period when the voltages of the first internal node N1 and the third internal node N3 must be maintained at a low level. As a result, display defects such as the appearance of bright lines at the upper edge of the panel are suppressed. As described above, according to this embodiment, the organic EL display device 10 suppresses display defects caused by changes in the characteristics of the TFTs at the upper edge of the panel.This also has the effect of improving the yield in manufacturing the organic EL display device 10.

[0068] Furthermore, according to this embodiment, the characteristics of the transistors M1 to M3 are shifted in advance toward the enhancement mode by the back gate voltage, thereby suppressing the flow of a large amount of leakage current when the transistors M1 to M3 deteriorate due to long-term use of the organic EL display device 10. In this regard, in the conventional configuration, for example, the initial characteristics are represented by the dotted line labeled 701 in FIG. 12 , and the characteristics after deterioration are represented by the thick solid line labeled 702 in FIG. 12 . In contrast, according to the configuration of this embodiment, the initial characteristics are represented by the dotted line labeled 703 in FIG. 12 . Compared to the conventional configuration, the characteristics are shifted toward the enhancement mode. Therefore, the characteristics after deterioration are represented by the thick solid line labeled 704 in FIG. 12 . As a result, the occurrence of abnormal operation due to deterioration (shift in characteristics) of the transistors M1 to M3 due to long-term use is suppressed.

[0069] Furthermore, the back gates 61 to 63 of the transistors M1 to M3 have a light-shielding property. Generally, when a transistor is exposed to light, the leakage current increases. However, in this embodiment, the back gates 61 to 63 have a light-shielding property, so the occurrence of leakage current due to light irradiation is also suppressed. In other words, the occurrence of abnormal operation due to leakage current due to light irradiation is also suppressed.

[0070] Furthermore, a negative voltage (a voltage of the same polarity as the gate voltage that turns on the transistor M1) is applied as a back gate voltage to the back gate 61 of the transistor M1 during the on period of the shift pulse. As a result, the characteristics of the transistor M1 shift toward depletion during the on period of the shift pulse, increasing the driving capability. As described above, the first high-level power supply voltage GVDD may be applied to the back gate 61 of the transistor M1. However, considering the driving capability during the on period of the shift pulse, it is preferable to apply the set signal S to the back gate 61 of the transistor M1 rather than applying the first high-level power supply voltage GVDD.

[0071] <1.7 Comparison with Configurations Described in Prior Art Documents> The differences between the configurations described in the above-mentioned prior art documents and the configuration of this embodiment will be described.

[0072] First, let us focus on FIG. 2(A) of Japanese Patent Application Laid-Open No. 2017-084435 (hereinafter referred to as "Reference Diagram 1" for convenience). In FIG. 1, transistors 126-129 function as buffer transistors, and the other transistors are provided to control the voltages of nodes connected to the gates of the buffer transistors. Among these other transistors, transistors 125 and 132 have back gates, which are connected to terminal 117 connected to wiring 106 to which signal DTY1 is supplied (here, we focus on the 1st to k-1th stages). In this configuration, a switching period 172b is provided during each frame period in which the polarity of the voltage applied to the gates of transistors 125 and 132 is switched with the polarity of the voltage applied to the back gates of transistors 125 and 132 (see, particularly, FIGS. 8 and 13 of the publication). As a result, positive stress is applied to the gates of transistors 125 and 132 while signal DTY1 is maintained at a low level, and positive stress is applied to the back gates of transistors 125 and 132 while signal DTY1 is maintained at a high level. In this way, degradation of the characteristics of transistors 125 and 132 is suppressed. Paragraph 0115 of the same publication states, "The duty ratios of signals DTY1 to DTY4 are preferably 30% to 70%, more preferably 40% to 60%, and even more preferably 45% to 55%." This description indicates that a negative voltage is not continuously applied to the back gates of transistors 125 and 132, and that a negative voltage is not applied to the back gates of transistors 125 and 132 throughout the off period of the shift pulse. With this configuration, there is a concern that circuit operation may become unstable during the switching period 172b due to, for example, changes in the characteristics of transistors 125 and 132 or fluctuations in the voltage of internal nodes. When the circuit operation becomes unstable, for example, uneven display and afterimages occur.

[0073] Next, attention is focused on Figure 4(B) of Japanese Patent Application Laid-Open No. 2017-084435 (hereinafter referred to as "Reference Diagram 2" for convenience). In the configuration of Reference Diagram 2, in addition to the transistors having back gates in the configuration of Reference Diagram 1, back gates are provided for transistors 121, 122, 124, 131, 135, and 136.

[0074] For transistors 121, 122, 124, and 135 in the second reference diagram, the back gate is connected to the gate. That is, a double-gate structure is adopted in which channels are formed on both the front side (gate insulating film side) and the back side (back gate insulating film side) of the semiconductor layer. This has the advantage of increasing the on-current and improving drive capability, but it also increases the off-current (leakage current). Therefore, it does not achieve the effect of suppressing display defects caused by changes in transistor characteristics. Furthermore, since the back gate voltage changes in synchronization with changes in gate voltage, when the gate voltage changes, the back gate voltage also changes, causing the transistor's threshold voltage to fluctuate. This changes the transistor's characteristics (Ids-Vgs characteristics), resulting in unstable operation and, for example, display unevenness and image retention.

[0075] The back gates of transistors 131 and 136 in FIG. 2 are connected to wiring 145 to which an L potential is supplied. Because transistors 131 and 136 are N-channel transistors, the L potential corresponds to a voltage of opposite polarity to the gate voltage that turns on transistors 131 and 136. However, paragraph 0086 of the same publication states, "The other of the first gate or the second gate of transistor 131 may not be connected to wiring 145, but the first gate and the second gate may be electrically connected." and "The other of the first gate or the second gate of transistor 136 may not be connected to wiring 145, but the first gate and the second gate may be electrically connected." For example, if the gate (first gate) and back gate (second gate) of transistor 136 are electrically connected, both the gate and the back gate are connected to terminal 117, which is connected to wiring 106 to which signal DTY1 is supplied. Therefore, according to the description in paragraph 0115 of the publication, a negative voltage is not continuously applied to the back gate of transistor 136, nor is a negative voltage applied to the back gate of transistor 136 throughout the OFF period of the shift pulse. In other words, the publication does not disclose the technical idea of ​​continuously applying a DC voltage of opposite polarity to the gate voltage that turns the transistor on to the back gate of a transistor, or the technical idea of ​​applying a voltage of opposite polarity to the gate voltage that turns the transistor on to the back gate of a transistor throughout the OFF period of the shift pulse.

[0076] Next, attention is focused on FIG. 13 of WO 2019 / 123089 (hereinafter referred to as "Reference Diagram 3" for convenience). In Reference Diagram 3, transistors M13 and M14 function as buffer transistors, and transistors M3 to M12 are provided to control the voltage of nodes connected to the gates of the buffer transistors. Transistors M3 to M14 are all N-channel transistors.

[0077] For transistors M3, M6, M7, M8, M11, and M12 in Reference Diagram 3, the back gate is connected to the gate. That is, a double-gate structure is adopted. Therefore, similar to the configuration in which transistors 121, 122, 124, and 135 in Reference Diagram 2 are provided, the effect of suppressing display defects caused by changes in transistor characteristics cannot be obtained, and display unevenness and afterimages, for example, occur.

[0078] The back gates of transistors M4, M5, M9, and M10 in Reference Figure 3 are connected to a wiring BGL to which a signal VBG is applied. In this regard, paragraph 0150 of the pamphlet states, "By applying the signal VBG to the wiring BGL to the back gates of transistors M4, M5, M9, and M10, an increase in off-state current can be suppressed." However, the specific voltage value of signal VBG is only described in paragraph 0158, which states, "The signal VBG is controlled to have the same value as the threshold voltage of transistor M14 by the output voltage of output terminal 12b of voltage reference circuit 12." Since the threshold voltage of an N-channel transistor is generally greater than zero, in this example, a positive voltage is applied to the back gate of the transistor. That is, a voltage of the same polarity as the gate voltage that turns the transistor on is applied to the back gate of the transistor. This shifts the characteristics toward depletion, making it impossible to suppress leakage current, for example, when the transistor deteriorates. However, there is also a disadvantage in that a dedicated independent power supply wiring is required as the wiring BGL.

[0079] Next, let us turn our attention to Figure 9 of International Publication No. 2017 / 150443 (hereinafter referred to as "Reference Diagram 4" for convenience). In Figure 4, backgates are provided for three clear transistors (transistors TFT-A1, TFT-A2, and TFT-R) whose gates receive a clear signal CLR. All three clear transistors are N-channel TFTs, and their backgates are supplied with a positive power supply voltage VDD or GND potential. This increases the leakage current in the clear transistors, effectively removing residual charge from floating nodes (internal nodes) within the unit circuit when the power is turned off. However, because the characteristics of the clear transistors shift toward depletion, it is not possible to suppress the generation of leakage current, for example, when the transistors deteriorate.

[0080] In contrast to the configurations described in the prior art documents, the configuration of this embodiment of the present invention continuously applies a DC voltage of the opposite polarity to the gate voltage that turns on transistors M2 and M3 to the back gates 62 and 63 of transistors M2 and M3 in the unit circuit 4 (see FIG. 1 ), and applies a voltage of the opposite polarity to the gate voltage that turns on transistor M1 to the back gate 61 of transistor M1 throughout the off period of the shift pulse. This prevents the transistor characteristics from becoming unstable, and achieves the effect of suppressing leakage current by shifting the transistor characteristics toward the enhancement mode. Furthermore, in this embodiment, the gates and back gates of transistors M1 to M3 are not electrically connected. That is, in the configuration of this embodiment, a channel is formed only on the surface side (gate insulating film side) of the semiconductor layer. Therefore, the off-state current does not increase due to the transistor structure.

[0081] 1.8 Modifications In the first embodiment described above, the circuit configuration shown in part A of Fig. 13 was adopted for the configuration of the transistors M2 and M3. However, it is also possible to adopt the circuit configuration shown in part B of Fig. 13 (the configuration of this modification). In this modification, the back gate 63 of the transistor M3 is connected to the first power supply wiring 471 as in the first embodiment (i.e., the first high-level power supply voltage GVDD is applied to the back gate 63), but the back gate 62 of the transistor M2 is connected to the second internal node N2, unlike in the first embodiment.

[0082] In this modification, the cross-sectional view of the portion where transistors M2 to M5 are provided is as shown in Fig. 14. As shown in Fig. 14, a back gate electrode 121 for transistor M2 and a back gate electrode 122 for transistor M3 are provided separately. The back gate electrode 121 functions as a light-shielding layer that prevents light from being irradiated onto the semiconductor layer of transistor M2, and the back gate electrode 122 functions as a light-shielding layer that prevents light from being irradiated onto the semiconductor layer of transistor M3.

[0083] As described above, the circuit configuration shown in part B of Fig. 13 can also be used as the configuration of transistors M2 and M3. However, for the following reasons, it is preferable to use the circuit configuration shown in part A of Fig. 13 (the configuration of the first embodiment) rather than the circuit configuration shown in part B of Fig. 13 (the configuration of this modified example).

[0084] According to the configuration of the first embodiment, the first high-level power supply voltage GVDD is applied to both the back gate 62 of the transistor M2 and the back gate 63 of the transistor M3. In contrast, according to the configuration of this modification, the first high-level power supply voltage GVDD is applied to the back gate 63 of the transistor M3, but a voltage that is smaller than the first high-level power supply voltage GVDD by Vds (drain-source voltage) of the transistor M3 is applied to the back gate 62 of the transistor M2 when the transistor M3 is in the on state, and a voltage V expressed by the following equation (2) is applied when the transistor M3 is in the off state. Note that V N1is the voltage of the first internal node N1. V=GVDD-(GVDD-V N1 ) / 2 ... (2)

[0085] As described above, a larger positive voltage is applied to the back gate 62 of the transistor M2 in the configuration of the first embodiment than in the configuration of this modification, and therefore the occurrence of leakage current is more effectively suppressed in the configuration of the first embodiment than in the configuration of this modification.

[0086] Furthermore, in the configuration of the first embodiment, the back gate electrode 120 and the first power supply wiring 471 are connected by a contact hole (see FIG. 9), whereas in the configuration of this modification, the back gate electrode 122 and the first power supply wiring 471 are connected by a contact hole, and in addition, the back gate electrode 121 and the second internal node N2 are connected by a contact hole (see FIG. 14). Therefore, the configuration of the first embodiment can make the circuit layout area smaller than the configuration of this modification.

[0087] 2. Second Embodiment A second embodiment will be described. Note that differences from the first embodiment will be mainly described, and descriptions of similarities to the first embodiment will be omitted as appropriate.

[0088] 2.1 Scanning-Side Drive Circuit FIG. 15 is a block diagram showing a schematic configuration of the scanning-side drive circuit 40 in this embodiment. The scanning-side drive circuit 40 includes a first scanning signal line drive circuit 401a, a second scanning signal line drive circuit 401b, and a light-emission control circuit 409. The first scanning signal line drive circuit 401a applies a first scanning signal NS to the first scanning signal line. The second scanning signal line drive circuit 401b applies a second scanning signal PS to the second scanning signal line. The light-emission control circuit 409 applies a light-emission control signal EM to the light-emission control line. The configuration and operation of the second scanning signal line drive circuit 401b will be described in detail below. The first scanning signal line drive circuit 401a and the light-emission control circuit 409 can employ, for example, known configurations.

[0089] <2.1.1 Configuration of Second Scanning Signal Line Drive Circuit> Figure 16 is a block diagram showing the configuration of the second scanning signal line drive circuit 401b. In this embodiment, the second scanning signal line drive circuit 401b is configured by a shift register consisting of n stages (in other words, n unit circuits). Note that, assuming that i is an even number, Figure 16 only shows the unit circuits 4(i-2), 4(i-1), 4(i), 4(i+1), and 4(i+2) in the (i-2)th stage, (i-1)th stage, i-th stage, (i+1)th stage, and (i+2)th stage.

[0090] Unlike the shift register in the first embodiment (see FIG. 7), the shift register in this embodiment is not supplied with the second high-level power supply voltage GVDD2 (hence, in this embodiment, GVDD is referred to as the "high-level power supply voltage"). Also, only one output signal OUT is output from each unit circuit 4. The output signal OUT output from each unit circuit 4 is supplied as a set signal S to the unit circuit 4 of the next stage, and is supplied as a second scanning signal to the corresponding second scanning signal line PS.

[0091] 2.1.2 Unit Circuit Configuration FIG. 17 is a circuit diagram showing the configuration of a unit circuit 4 in this embodiment. The unit circuit 4 includes eight transistors M11 to M18 and two capacitors C11 and C12. All of the transistors M11 to M18 are P-channel TFTs. The unit circuit 4 also includes an input terminal connected to a first power supply wiring 471 that supplies a high-level power supply voltage GVDD and an input terminal connected to a second power supply wiring 472 that supplies a low-level power supply voltage GVSS, as well as three input terminals 81 to 83 and one output terminal 89. In FIG. 17 , the input terminal that receives the set signal S is labeled 81, the input terminal that receives the first control clock signal CK1 is labeled 82, the input terminal that receives the second control clock signal CK2 is labeled 83, and the output terminal that outputs the output signal OUT is labeled 89.

[0092] The source of transistor M11, the drain of transistor M12, the gate of transistor M14, and the source of transistor M16 are connected to one another. The node where these are connected is called the "first internal node." The first internal node is denoted by the symbol N11. The source of transistor M12 and the drain of transistor M13 are connected to one another. The node where these are connected is called the "second internal node." The second internal node is denoted by the symbol N12. The drain of transistor M16, the gate of transistor M17, and one end of capacitor C12 are connected to one another. The node where these are connected is called the "third internal node." The third internal node is denoted by the symbol N13. The gate of transistor M13, the drain of transistor M14, the drain of transistor M15, the gate of transistor M18, and one end of capacitor C11 are connected to one another. The node where these are connected is called the "fourth internal node." The fourth internal node is denoted by the symbol N14.

[0093] The transistor M11 has a gate connected to the input terminal 82, a drain connected to the input terminal 81, and a source connected to the first internal node N11. The transistor M11 is also provided with a back gate (back gate electrode) 64, which is connected to the input terminal 81. The transistor M12 has a gate connected to the input terminal 83, a drain connected to the first internal node N11, and a source connected to the second internal node N12. The transistor M13 has a gate connected to the fourth internal node N14, a drain connected to the second internal node N12, and a source connected to the first power supply wiring 471. The transistor M14 has a gate connected to the first internal node N11, a drain connected to the fourth internal node N14, and a source connected to the input terminal 82. The transistor M14 is also provided with a back gate (back gate electrode) 65, which is connected to the first power supply wiring 471. The transistor M15 has a gate connected to the input terminal 82, a drain connected to the fourth internal node N14, and a source connected to the second power supply wiring 472. The transistor M15 is also provided with a back gate (back gate electrode) 66, which is connected to the first power supply wiring 471. As described above, the transistors M11, M14, and M15 are provided with the back gates 64, 65, and 66.

[0094] The transistor M16 has a gate connected to the second power supply wiring 472, a drain connected to the third internal node N13, and a source connected to the first internal node N11. The transistor M17 has a gate connected to the third internal node N13, a drain connected to the input terminal 83, and a source connected to the output terminal 89. The transistor M18 has a gate connected to the fourth internal node N14, a drain connected to the output terminal 89, and a source connected to the first power supply wiring 471. The capacitor C11 has one end connected to the fourth internal node N14, and the other end connected to the first power supply wiring 471. The capacitor C12 has one end connected to the third internal node N13, and the other end connected to the output terminal 89.

[0095] In this embodiment, the transistors M11 to M16 constitute control transistors, and the transistors M17 and M18 constitute buffer transistors. The transistors M11 to M16 constitute first to sixth control transistors, respectively, the transistor M17 constitutes a first buffer transistor, and the transistor M18 constitutes a second buffer transistor. The high-level power supply voltage GVDD constitutes a first power supply voltage, and the low-level power supply voltage GVSS constitutes a second power supply voltage.

[0096] 18, the operation of the unit circuit 4 will be described. During the period before time t21, the voltages of the first internal node N11, the second internal node N12, and the third internal node N13 are maintained at a high level, the voltage of the fourth internal node N14 is maintained at a low level, and the output signal OUT is maintained at a high level.

[0097] At time t21, the first control clock signal CK1 changes from high to low. This causes the transistors M11 and M15 to turn on. Also at time t21, the set signal S changes from high to low (in other words, a shift pulse is input). As a result, the voltage of the first internal node N11 drops to low, and the transistor M14 turns on. Even if the voltage of the first internal node N11 drops to low, the transistor M16 remains on, and the voltage of the third internal node N13 also drops to low. This causes the transistor M17 to turn on.

[0098] At time t22, the first control clock signal CK1 changes from low to high. This causes the transistors M11 and M15 to turn off. At this time, the transistor M14 is in the on state, so the voltage at the fourth internal node N14 rises to high. Also at time t22, the set signal S changes from low to high.

[0099] At time t23, the second control clock signal CK2 changes from high to low. At this time, because the transistor M17 is on, the voltage at the input terminal 83 drops, and the voltage at the output terminal 89 (the voltage of the output signal OUT) drops. Because the capacitor C12 is provided between the third internal node N13 and the output terminal 89, the voltage at the third internal node N13 also drops as the voltage at the output terminal 89 drops (the third internal node N13 enters a boosted state). As a result, a large negative voltage is applied to the gate of the transistor M17. This bootstrap operation reduces the voltage of the output signal OUT to a level sufficient to turn on the write control transistor T3 (see FIG. 4) connected to the output terminal 89. When the voltage at the third internal node N13 drops at time t23, the drain voltage of the transistor M16 becomes lower than the gate voltage. This turns the transistor M16 off. Therefore, the voltage at the first internal node N11 does not change at time t23.

[0100] At time t24, the second control clock signal CK2 changes from low to high. This causes the voltage at the input terminal 83 to rise, and the voltage at the output terminal 89 (the voltage of the output signal OUT) to rise. When the voltage at the output terminal 89 rises, the voltage at the third internal node N13 also rises via the capacitor C12. This turns on the transistor M16.

[0101] At time t25, the first control clock signal CK1 changes from high to low. This causes the transistors M11 and M15 to turn on. At this time, the set signal S is maintained at high. This causes the voltage of the first internal node N11 to rise to high, turning the transistor M14 off. Furthermore, the voltage of the fourth internal node N14 changes from high to low, turning the transistors M13 and M18 on. With the transistor M13 turned on, the voltage of the second internal node N12 rises to high. Furthermore, since the transistor M16 is maintained in the on state, the voltage of the third internal node N13 also rises to high at time t25. This causes the transistor M17 to turn off. The period after time t25 is the same as the period before time t21.

[0102] 2.1.4 Back Gates In this embodiment, the P-channel TFT transistors M11, M14, and M15 are provided with back gates 64, 65, and 66. The first high-level power supply voltage GVDD is applied to the back gates 65, 66 of the transistors M14 and M15. Therefore, like the transistors M2 and M3 in the first embodiment, the transistors M14 and M15 have characteristics shifted toward the enhancement mode compared to the characteristics of a configuration without back gates. A set signal S is applied to the back gate 61 of the transistor M11. As shown in FIG. 18 , the set signal S is low from time t21 to time t22, but is maintained high during other periods. Therefore, similar to the transistor M1 in the first embodiment, the transistor M11 has characteristics that are shifted toward the enhancement direction during the off period of the shift pulse compared to the characteristics in a configuration in which a back gate is not provided, and has characteristics that are shifted toward the depletion direction during the on period of the shift pulse compared to the characteristics in a configuration in which a back gate is not provided.

[0103] Similarly to the back gates 61 to 63 in the first embodiment, the back gates 64 to 66 function as light-shielding layers that prevent light from being irradiated onto the semiconductor layers. That is, the back gates 64 to 66 have a light-shielding property.

[0104] 2.2 Effects According to this embodiment, in the unit circuit 4 constituting the shift register serving as the second scanning signal line driving circuit 401b, a back gate 64 is provided for the transistor M11 (a P-channel TFT) for controlling the voltage of the first internal node N11, which is connected to the gate of the transistor M17 functioning as a buffer transistor via the transistor M16. Also, back gates 65, 66 are provided for the transistors M14, M15 (P-channel TFTs) for controlling the voltage of the fourth internal node N14, which is connected to the gate of the transistor M18 functioning as a buffer transistor. A DC voltage (high-level power supply voltage GVDD) having a polarity opposite to that of the gate voltage that turns on the transistors M14, M15 is continuously applied to the back gates 65, 66 of the transistors M14, M15 as a back gate voltage. Therefore, even if the characteristics of the transistors M14, M15 have shifted toward depletion due to plasma damage or the like, the back gate voltage shifts the characteristics of the transistors M14, M15 toward enhancement. This suppresses the generation of leakage current in the transistors M14 and M15. Therefore, the voltage at the fourth internal node N14 is suppressed from increasing via the transistor M14 during the period before time t22 in FIG. 18 and the period after time t25 in FIG. 18 , and the voltage at the fourth internal node N14 is suppressed from decreasing via the transistor M15 during the period from time t22 to time t25 in FIG. 18 . Furthermore, a voltage of opposite polarity to the gate voltage that turns on the transistor M11 (the high-level voltage of the set signal S) is continuously applied as a back gate voltage to the back gate 64 of the transistor M11 throughout the off period of the shift pulse. Therefore, even if the characteristics of the transistor M11 have shifted toward depletion due to plasma damage or the like, the back gate voltage shifts the characteristics of the transistor M11 toward enhancement. This suppresses the generation of leakage current in the transistor M11 and suppresses the voltage at the first internal node N11 from increasing via the transistor M11 during the period from time t22 to time t25 in FIG. 18 .As described above, similar to the first embodiment, the organic EL display device 10 suppresses display defects due to changes in TFT characteristics at the upper edge of the panel. Also, similar to the first embodiment, the organic EL display device 10 suppresses abnormal operation due to transistor degradation (shift in characteristics) over long-term use and abnormal operation due to leakage current caused by light irradiation. Furthermore, a negative voltage (a voltage of the same polarity as the gate voltage that turns on transistor M11) is applied as a back gate voltage to the back gate 64 of transistor M11 during the on period of the shift pulse. As a result, the characteristics of transistor M11 shift toward depletion during the on period of the shift pulse, thereby improving driving capability.

[0105] 3. Others In the above embodiments (including modified examples), an organic EL display device has been described as an example, but the present invention is not limited to this. The above disclosure can also be applied to an inorganic EL display device, a QLED display device, or any other display device that uses a display element driven by current.

[0106] Furthermore, while the above embodiments have provided a back gate in a P-channel TFT, a back gate can also be provided in an N-channel TFT. In this case, a negative voltage (a voltage of the opposite polarity to the voltage that turns the TFT on when applied to the gate) is continuously applied to the back gate of the N-channel TFT. This shifts the characteristics of the N-channel TFT toward the enhancement mode, thereby suppressing the generation of leakage current.

[0107] Furthermore, with regard to the configuration in which back gates are provided to some transistors, the first embodiment exemplifies a unit circuit 4 in which N-channel TFTs and P-channel TFTs are mixed, and the second embodiment exemplifies a unit circuit 4 that includes only P-channel TFTs. However, the present invention is not limited to these, and it is also possible to employ a configuration in which back gates are provided to some transistors in a unit circuit that includes only N-channel TFTs.

[0108] Furthermore, with respect to the unit circuit constituting the shift register as the light emission control circuit 409, a back gate may be provided for at least one of the plurality of control transistors (transistors having one of their source and drain connected to the gate of the buffer transistor directly or via another transistor), and a DC voltage of opposite polarity to the gate voltage that turns on the control transistor may be continuously applied to the back gate.

[0109] 4...Unit circuit 10...Organic EL display device 15...Pixel circuit 40...Scanning side drive circuit 61 to 66...Back gate 151...Organic EL element 401...Scanning signal line drive circuit 409...Emission control circuit NS, NS(-1) to NS(n)...First scanning signal line, first scanning signal PS, PS(1) to PS(n)...Second scanning signal line, second scanning signal EM, EM(1) to EM(n)...Emission control line, emission control signal M1 to M18...Transistor (in the unit circuit)

Claims

1. A display device using display elements driven by current, comprising: a plurality of data signal lines; a plurality of scanning signal lines intersecting the plurality of data signal lines; a plurality of light emission control lines intersecting the plurality of data signal lines; n x m pixel circuits each including the display element, forming a pixel matrix of n rows x m columns, where n and m are integers of 2 or greater; a data side drive circuit that applies data signals to the plurality of data signal lines; a scanning side drive circuit including at least one shift register that drives the plurality of scanning signal lines or the plurality of light emission control lines; a plurality of clock wirings for supplying the scanning side drive circuit with a plurality of clock signals required for operation of the at least one shift register; and a plurality of power supply wirings for supplying the scanning side drive circuit with a plurality of power supply voltages required for operation of the at least one shift register, wherein the at least one shift register is composed of at least n unit circuits, and each unit circuit is a buffer transistor, one of which is a first conduction terminal and a second conduction terminal that function as a source and a drain, connected to one of the plurality of clock wirings or one of the plurality of power supply wirings, and the other of which is connected to a corresponding scanning signal line or a corresponding light emission control line; and a plurality of control transistors, one of which is a first conduction terminal and a second conduction terminal that function as a source and a drain, connected to a gate of the buffer transistor directly or via another transistor, wherein at least one of the plurality of control transistors is provided with a back gate to which a DC voltage of opposite polarity to a gate voltage that turns the control transistor on is continuously applied.

2. The display device according to claim 1, wherein the DC voltage continuously applied to the back gate is one of the plurality of power supply voltages.

3. The display device according to claim 1, wherein the back gate has a light-shielding property.

4. The plurality of clock signals are two-phase clock signals provided to the at least n unit circuits as a first control clock signal and a second control clock signal, the plurality of power supply voltages include a first power supply voltage and a second power supply voltage, each unit circuit includes a first internal node, a second internal node, a third internal node and a fourth internal node, each unit circuit includes as the buffer transistor: a first buffer transistor having a gate connected to the third internal node, a first conduction terminal to which the second control clock signal is provided and a second conduction terminal connected to the corresponding scanning signal line, and a second buffer transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the corresponding scanning signal line and a second conduction terminal to which the first power supply voltage is provided, and the plurality of control transistors include: a first control transistor having a gate to which the first control clock signal is provided, a first conduction terminal to which a shift pulse is provided and a second conduction terminal connected to the first internal node, 2. The display device according to claim 1, comprising: a second control transistor having a gate to which the second control clock signal is applied, a first conduction terminal connected to the first internal node, and a second conduction terminal connected to the second internal node; a third control transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the second internal node, and a second conduction terminal to which the first power supply voltage is applied; a fourth control transistor having a gate connected to the first internal node, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the second power supply voltage is applied; a fifth control transistor having a gate connected to the first internal node, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the first power supply voltage is applied; and a sixth control transistor having a gate to which the second power supply voltage is applied, a first conduction terminal connected to the third internal node, and a second conduction terminal connected to the first internal node, 5. The display device according to claim 4, wherein the first power supply voltage is applied as the DC voltage to the back gate provided in the second control transistor and the back gate provided in the third control transistor.

6. The plurality of clock signals are two-phase clock signals provided to the at least n unit circuits as a first control clock signal and a second control clock signal, the plurality of power supply voltages include a first power supply voltage and a second power supply voltage, each unit circuit includes a first internal node, a second internal node, a third internal node and a fourth internal node, each unit circuit includes as the buffer transistor: a first buffer transistor having a gate connected to the third internal node, a first conduction terminal to which the second control clock signal is provided and a second conduction terminal connected to the corresponding scanning signal line, and a second buffer transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the corresponding scanning signal line and a second conduction terminal to which the first power supply voltage is provided, and the plurality of control transistors include: a first control transistor having a gate to which the first control clock signal is provided, a first conduction terminal to which a shift pulse is provided and a second conduction terminal connected to the first internal node, 2. The display device according to claim 1, comprising: a second control transistor having a gate to which the second control clock signal is applied, a first conduction terminal connected to the first internal node, and a second conduction terminal connected to the second internal node; a third control transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the second internal node, and a second conduction terminal to which the first power supply voltage is applied; a fourth control transistor having a gate connected to the first internal node, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the first control clock signal is applied; a fifth control transistor having a gate to which the first control clock signal is applied, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the second power supply voltage is applied; and a sixth control transistor having a gate to which the second power supply voltage is applied, a first conduction terminal connected to the third internal node, and a second conduction terminal connected to the first internal node, 7. The display device according to any one of claims 1 to 6, wherein the at least one control transistor is a P-channel thin film transistor.

8. A display device using a display element driven by current, comprising: a plurality of data signal lines; a plurality of scanning signal lines intersecting the plurality of data signal lines; a plurality of light emission control lines intersecting the plurality of data signal lines; n×m pixel circuits each including the display element, forming a pixel matrix of n rows and m columns, where n and m are integers of 2 or greater; a data side drive circuit applying data signals to the plurality of data signal lines; a scanning side drive circuit including at least one shift register that drives the plurality of scanning signal lines or the plurality of light emission control lines; a plurality of clock wirings for supplying the scanning side drive circuit with a plurality of clock signals required for operation of the at least one shift register; and a plurality of power supply wirings for supplying the scanning side drive circuit with a plurality of power supply voltages required for operation of the at least one shift register, wherein the at least one shift register is constituted by at least n unit circuits, and each unit circuit is a buffer transistor, one of two terminals functioning as a source and a drain, a first conduction terminal and a second conduction terminal, connected to one of the plurality of clock wirings or one of the plurality of power supply wirings, and the other of the first conduction terminal and the second conduction terminal connected to a corresponding scanning signal line or a corresponding light-emitting control line; and a plurality of control transistors, one of the two terminals functioning as a source and a drain, the first conduction terminal and the second conduction terminal, connected to a gate of the buffer transistor directly or via another transistor, 9. The display device according to claim 8, wherein the back gate has a light-shielding property.

10. The plurality of clock signals are two-phase clock signals provided to the at least n unit circuits as a first control clock signal and a second control clock signal, the plurality of power supply voltages include a first power supply voltage and a second power supply voltage, each unit circuit includes a first internal node, a second internal node, a third internal node and a fourth internal node, each unit circuit includes as the buffer transistor: a first buffer transistor having a gate connected to the third internal node, a first conduction terminal to which the second control clock signal is provided and a second conduction terminal connected to the corresponding scanning signal line, and a second buffer transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the corresponding scanning signal line and a second conduction terminal to which the first power supply voltage is provided, and the plurality of control transistors include: a second control transistor having a gate to which the second control clock signal is provided, a first conduction terminal connected to the first internal node and a second conduction terminal connected to the second internal node, 9. The display device according to claim 8, comprising: a third control transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the second internal node, and a second conduction terminal to which the first power supply voltage is applied; a fourth control transistor having a gate connected to the first internal node, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the second power supply voltage is applied; a fifth control transistor having a gate connected to the first internal node, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the first power supply voltage is applied; and a sixth control transistor having a gate to which the second power supply voltage is applied, a first conduction terminal connected to the third internal node, and a second conduction terminal connected to the first internal node, 11. The plurality of clock signals are two-phase clock signals provided to the at least n unit circuits as a first control clock signal and a second control clock signal, the plurality of power supply voltages include a first power supply voltage and a second power supply voltage, each unit circuit includes a first internal node, a second internal node, a third internal node, and a fourth internal node, each unit circuit including, as the buffer transistor, a first buffer transistor having a gate connected to the third internal node, a first conduction terminal to which the second control clock signal is provided, and a second conduction terminal connected to the corresponding scanning signal line, and a second buffer transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the corresponding scanning signal line, and a second conduction terminal to which the first power supply voltage is provided, and the plurality of control transistors include a second control transistor having a gate to which the second control clock signal is provided, a first conduction terminal connected to the first internal node, and a second conduction terminal connected to the second internal node, 9. The display device according to claim 8, comprising: a third control transistor having a gate connected to the fourth internal node, a first conduction terminal connected to the second internal node, and a second conduction terminal to which the first power supply voltage is applied; a fourth control transistor having a gate connected to the first internal node, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the first control clock signal is applied; a fifth control transistor having a gate to which the first control clock signal is applied, a first conduction terminal connected to the fourth internal node, and a second conduction terminal to which the second power supply voltage is applied; and a sixth control transistor having a gate to which the second power supply voltage is applied, a first conduction terminal connected to the third internal node, and a second conduction terminal connected to the first internal node, 12. The display device according to any one of claims 8 to 11, wherein the first control transistor is a P-channel thin film transistor.

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