Design assistance system and design assistance method

Abstract

This design assistance system is for designing a semiconductor on the basis of specifications, and comprises: a design data database 71 that stores past design data of semiconductors; a partitioning unit 21 that creates a partition plan for dividing a semiconductor with specified specifications into a plurality of blocks, on the basis of the past design data stored in the design data database 71; and a design difficulty assessment unit 23 that assesses the design difficulty of each block obtained as a result of the partitioning by the partitioning unit 21, on the basis of the past design data stored in the design data database 71.

Description

Design support system and design support method

[0001] The present invention relates to a design support system and a design support method suitable for application to semiconductor design.

[0002] Conventionally, general-purpose semiconductors that can be installed in various products have been mass-produced. Examples of general-purpose semiconductors include central processing units (CPUs) installed in personal computers. General-purpose semiconductors based on the conventional von Neumann architecture are designed to have high performance in sequential processing.

[0003] According to Moore's Law, semiconductor production costs can be reduced by increasing integration density. Therefore, the main goal of conventional semiconductors has been to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing the integration density of semiconductors requires a significant investment in equipment. For this reason, the fabless production method, in which a company that primarily designs semiconductors outsources semiconductor production to an external company, has become mainstream.

[0004] Patent Document 1 discloses a technique relating to lithography-based pattern optimization.

[0005] U.S. Pat. No. 1,144,9659

[0006] As semiconductors become increasingly miniaturized, not only are semiconductor manufacturing turnaround times (TATs) becoming longer, but the complex rules and constraints of semiconductor design are also lengthening the design process, creating a need to reduce the time required for design. Hierarchical layouts are typically used when designing large-scale semiconductors. To reduce design time, different designers are tasked with designing each level. However, the division of a hierarchical layout into blocks has typically been determined based on the designer's experience. When dividing a hierarchical layout into blocks, the designer must determine the size, shape, and number of blocks, as well as the logic to be implemented in each block.

[0007] Although it is possible to predict to some extent the division of blocks, which are the units of hierarchical layout, through prior prototyping, etc., it is difficult to make major corrections once the design has begun. Therefore, even if it is determined during the design process that the hierarchical layout is inappropriate, it is difficult to make major corrections, and there have been cases where it is not possible to properly recover from problems when they occur during semiconductor design. As such, if the division of blocks, which are the units of hierarchical layout, is not performed appropriately, there is a problem that the time required for design is extended.

[0008] 18 shows an example of a procedure for executing steps from block division to placement and routing during conventional semiconductor design. When designing, an RTL (Register Transfer Level) netlist D1, an SDC (Synopsys Design Constraints) file D2, and a library D3 are first obtained as data related to the semiconductor specifications. The RTL netlist D1 describes the logic circuits to be mounted on the semiconductor, and the SDC file D2 describes information such as the operating frequency and I / O delays. The library D3 is a database that compiles basic logic gates, logic circuit blocks, cells, and the like required for semiconductor specification design.

[0009] First, the RTL netlist D1, SDC file D2, and library D3 are input into a design tool, which then executes floorplanning and partitioning (step S1). The execution of floorplanning and partitioning results in the output of the design tool being first block data, second block data, ..., nth block data (n is any integer equal to or greater than 2), and TOP data (step S2). Each block data includes the size and shape of the block, the logic circuit to be placed, and so on.

[0010] Once multiple block data are obtained, each block data is handed over to a separate designer. The individual designers then perform placement and routing trials for the assigned blocks (steps S3a, S3b, ..., S3n). The designers then determine whether the placement and routing trials in steps S3a to S3n are complete and convergence is possible (step S4). If it is determined in step S4 that convergence is not possible (No in step S4), the designer changes the parameters of the design tool and re-executes the floorplanning and partitioning in step S1 (step S5). The parameter changes here are performed manually and therefore depend on the designer's experience.

[0011] If it is determined in step S3 that convergence is possible (Yes in step S4), the overall designer adjusts the floorplan based on the trial placement and routing status of each block (step S6). Then, the designers for each block execute placement and routing design for each block (step S7). This allows the overall designer to obtain data for each block that has already been placed and routed (step S8). Once the data for each block is obtained in step S8, the designer executes placement and routing design for the semiconductor's top region and the boundary region of each block using the data for each block and the TOP data generated in step S2 (step S9).

[0012] Next, the designer determines whether the placement and routing for the TOP region and the boundary region of each block in step S9 can be converged (step S10). If it is determined that convergence is not possible in step S10 (No in step S10), the designer returns to step S5, changes the parameters of the design tool, and re-executes the floorplan and partitioning in step S1.

[0013] If it is determined in step S10 that convergence is possible (Yes in step S10), the designer verifies the timing layout using a design tool and performs timing convergence through ECO (Engineering Change Order) processing (step S11). As a result, the designer completes the semiconductor design data through work on a block-by-block basis, and the design tool outputs (tapes out) the completed semiconductor design data.

[0014] Conventionally, when designing a semiconductor device by dividing it into blocks, the design is performed according to the flow shown in the flowchart of FIG. 18. However, because partitioning into blocks relies heavily on the designer's experience, there have been cases where it has been inappropriate. For example, there has often been a large variation in the time required to design the placement and wiring for each block. In other words, when designing a semiconductor device, if it takes an extremely long time to design one block, it will ultimately take a long time to complete the semiconductor design data, which is undesirable.

[0015] Furthermore, if it is determined in step S4 or step S10 that convergence is not possible, the block division must be redone, and in that case, the placement and routing that had been attempted up to that point must be redone. This poses the problem of a long time being required to complete the semiconductor design data. In particular, the parameter change for block division in step S5 is a task that depends on the designer's experience, and it cannot always be said that the parameter change can be made appropriately, which leads to a long design time.

[0016] The present invention has been made in view of the above circumstances, and aims to provide a design support system and a design support method that can efficiently reduce the design time and effort required when designing a semiconductor by dividing it into blocks.

[0017] The design support system of the present invention is a design support system for designing semiconductors based on specifications, and includes a database that stores past design data for semiconductors, a partitioning unit that creates a partition plan for dividing a semiconductor with specified specifications into multiple blocks based on the past design data stored in the database, and a design difficulty evaluation unit that evaluates the design difficulty of each block obtained as a result of the division by the partitioning unit based on the past design data stored in the database.

[0018] In addition, the design support method of the present invention is a design support method for designing a semiconductor based on specifications through computational processing by a computer, and the computational processing performed by the computer includes a storage process for storing past design data of the semiconductor as a database, a partitioning process for creating a partition plan for dividing a semiconductor with specified specifications into multiple blocks based on the past design data stored in the database, and a design difficulty evaluation process for evaluating the design difficulty of each block obtained as a result of the division in the partitioning process based on the past design data stored in the database.

[0019] According to the present invention, when a semiconductor is designed by dividing it into multiple blocks, the blocks can be divided appropriately based on the design difficulty of each block, thereby contributing to shortening the design period of the semiconductor.

[0020] 12 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to a first embodiment of the present invention. FIG. 13 is a diagram showing an example of a post-process in a packaging process according to the first embodiment of the present invention. FIG. 14 is a block diagram showing an example of the overall configuration of a design support system according to the first embodiment of the present invention. FIG. 15 is a block diagram showing an example of the configuration of a supervising device according to the first embodiment of the present invention. FIG. 16 is a block diagram showing an example of the configuration of a design unit of the design support system according to the first embodiment of the present invention. FIG. 17 is a flowchart showing an example of block division processing performed by the design support system according to the first embodiment of the present invention. FIG. 18 is a flowchart showing an example of detailed example of block division processing performed by the design support system according to the first embodiment of the present invention. FIG. 19 is a flowchart showing an example of processing performed by a design difficulty evaluation unit of the design support system according to the first embodiment of the present invention. FIG. 19 is a diagram showing an example of evaluation of each block by the design support system according to the first embodiment of the present invention. FIG. 20 is a diagram showing an example of an image of an improvement measure by the design support system according to the first embodiment of the present invention. FIG. 21 is a flowchart showing an example of another processing performed by the design difficulty evaluation unit of the design support system according to the first embodiment of the present invention. FIG. 22 is a diagram showing an example of an image of a difference in the number of cell tracks shown in the example of FIG. 21. FIG. 23 is a diagram showing an example of an image of a difference in CPP shown in the example of FIG. 21. FIG. 24 is a diagram showing an example image (part 1) of Multi Row shown in the example of FIG. 21. Fig. 12 is a diagram showing an image example (part 2) of Multi Row shown in the example of Fig. 11. Fig. 13 is a flowchart showing an example of block division processing performed by a design support system according to a second embodiment of the present invention. Fig. 14 is a flowchart showing an example of processing performed by a design difficulty evaluation unit of a design support system according to a second embodiment of the present invention. Fig. 15 is a flowchart showing an example of conventional block division processing of a semiconductor.

[0021] First Embodiment A design support system and a design support method according to a first embodiment of the present invention will be described below with reference to FIGS.

[0022] [Example of Semiconductor Manufacturing Process] FIG. 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to a first embodiment.

[0023] The semiconductor manufacturing process is broadly divided into a design process, a wafer process for manufacturing wafers, and a packaging process for manufacturing packages from wafers. In this embodiment, the manufacturing technology for design is called MFD (Manufacturing for Design) to distinguish it from DFM (Design for Manufacturing), which is a conventional design technology for manufacturing. MFD is a methodology that supports design based on data obtained in the wafer process and packaging process.

[0024] In the design support system 10 according to the first embodiment (see FIG. 3 described later), repeating MFD and DFM enables design-manufacturing co-optimization (DMCO), which represents the coordination and optimization of semiconductor design and manufacturing. As a result, the design support system 10 according to the first embodiment makes it possible to reduce the total cycle time from semiconductor design to packaging compared to conventional methods.

[0025] In the design process, semiconductors and circuit layouts are designed. In this embodiment, a new design methodology supported by an AI (Artificial Intelligence) model is provided to semiconductor customers. For example, the AI ​​model learns silicon big data measured by various measuring devices in the wafer process and packaging process, thereby training each AI model stored in a design DB 71 (described later) shown in FIG. 4 . This improves the performance of the PDK (Process Design Kit). In this embodiment, the trained AI model is used in the design process to assist the customer's designer in their design, thereby automating semiconductor design.

[0026] The PDK contains technology information necessary for semiconductor design, such as what device models are available, what design rules should be used, and what regulatory components should be extracted. Designers import this information into the PDK tool to design semiconductors. The MFD, in which the AI ​​model learns from silicon big data as shown in Figure 1, and the MFD, in which the AI ​​model assists the designer in design by navigating them, are structured in a hierarchical structure.

[0027] [General Wafer and Packaging Processes] The wafer and packaging processes are divided into front-end and back-end processes. The front-end process includes a front-end of line (FEOL) where elements are formed, a back-end of line (BEOL) where wiring is formed, and wafer characteristic inspection.

[0028] The FEOL includes, for example, a cleaning process, a film formation process, a photolithography process, an etching process, an ion implantation process, and a wafer inspection process, and these processes are performed repeatedly. The BEOL includes, for example, a cleaning process, a film formation process, a photolithography process, an etching process, a planarization process, and a wafer inspection process, and these processes are performed repeatedly on wafers manufactured through the FEOL. In the wafer characteristic inspection in the wafer inspection process, an electrical characteristic inspection of the wafer is performed on the wafer manufactured through the BEOL. When the wafer characteristic inspection is completed, the wafer is completed.

[0029] The back-end process includes an assembly process and an inspection process. The assembly process includes a dicing process, a die bonding process, a wire bonding process, and a molding process for wafers that are determined to be non-defective as a result of the wafer characteristic inspection. The inspection process includes a final inspection process for semiconductors produced in the molding process. This back-end process consisting of the assembly and inspection processes is carried out in a simple packaging process using wire bonding of a single chip and a complex packaging process in which multiple chips are stacked. In the back-end process, once the final inspection process is completed, a packaged semiconductor (also called a chip) is completed.

[0030] [Wafer Process and Packaging Process According to the Present Embodiment] Generally, wafer processes are divided into batch processes, in which all wafers in a lot undergo the same process, and single-wafer processes, in which wafers in a lot are processed one by one and the process for each wafer can be changed. Typically, batch and single-wafer processes coexist. In contrast, in the wafer process according to the present embodiment, all processes are performed using the single-wafer process. This allows the time required to complete a lot to be reduced to less than the normal time required for completion. Furthermore, in this embodiment, by varying the conditions for each wafer individually, a larger amount of data is accumulated in the same time period compared to processes including batch processes, and silicon big data is generated. Silicon big data contributes to improving wafer yield in the wafer process. Silicon big data is also used to train AI models in the design process (MFD). Furthermore, in the wafer process, the single-wafer process allows the processing time (x) for a single wafer to be reduced to less than half of the conventional time.

[0031] The packaging process involves bonding multiple wafers, wafers, chips, and chips together to form multi-chips, which are then mounted on a substrate, resulting in a wide variety of complex combinations. The post-process, described next, conceptually involves chipping the wafers completed in the pre-process, mounting the chips on a substrate (e.g., a silicon substrate) with additional rewiring, and then mounting the resulting substrate on a final packaging substrate. In the post-process, a substrate with additional rewiring is mounted on the packaging substrate, resulting in multiple integrated chips with various functions. Therefore, according to this embodiment, even if not all functions are integrated on a single chip, equivalent functionality can be achieved by using a packaging substrate product in which multiple chips with various functions are integrated.

[0032] 2 is a diagram showing an example of a back-end process in a packaging process that supports multi-chip integration. In the back-end process, for example, a bump formation process and a dicing process are performed on the wafer manufactured in the above-mentioned front-end process. In the back-end process, a TSV process, a rewiring layer formation process, and a bump formation process are performed on the rewiring substrate. Then, in the back-end process, a chip mounting process is performed in which the chips separated by the dicing process are combined with the rewiring substrate. Then, in the back-end process, an encapsulation process and a bump formation process are performed, followed by a substrate mounting process on the packaging substrate. In the back-end process, a final inspection process is performed after the encapsulation process.

[0033] During the design process, heterogeneous (heterogeneous integration) design is possible using chiplet technology based on design support information received from a chiplet technology platform containing multiple IPs. In the semiconductor field, functional blocks that make up LSIs, such as CPUs, image processing circuits, and memories, are considered design assets and are called IP (Intellectual Property) cores or simply IPs. In this specification, IP is described as a circuit element in semiconductor design. Circuit elements can be anything, including simple standard cells, interface functional blocks, or CPU cores.

[0034] 3 is a block diagram showing an example of the overall configuration of a design support system 10 according to this embodiment. The design support system 10 includes a control device 1, a design section 2, a wafer process section 3, and a packaging section 4.

[0035] The supervisory device 1 provides a platform that can be arbitrarily accessed by the design department 2, wafer process department 3, and packaging department 4. To this end, the supervisory device 1 acquires wafer process information measured in the wafer process for manufacturing wafers from the wafer process department 3. The supervisory device 1 also acquires packaging process information measured in the packaging process from the packaging department 4. The supervisory device 1 then provides design support information calculated based on the wafer process information and packaging process information to the design department 2.

[0036] The supervision device 1 uses the wafer process information as silicon big data and the packaging process information as packaging big data to perform analysis using a design AI model (described below) to create design support information. The analysis using the design AI model determines correlations between various types of parameters based on the silicon big data and the packaging big data. The design AI model provides the design support information, including optimal parameter combinations and values, to the design unit 2.

[0037] The design unit 2 designs the wafer process and the wafer packaging process. The design support information provided by the supervision device 1 and the design support function of the AI ​​model enable optimal semiconductor design, so the design unit 2 can increase the convergence speed of the design. Note that the design unit 2 may also import information on semiconductor design created by a designer using the design support function of the AI ​​model. Alternatively, the design unit 2 may import information on semiconductor design created by the AI ​​model itself.

[0038] The wafer process section 3 has a function of managing the wafer process, and manufactures wafers based on the design information designed by the design section 2. The wafer process section 3 transmits data measured by various measuring devices in the wafer process to the supervising device 1 as wafer process information.

[0039] The packaging unit 4 has a function of managing the packaging process for wafers manufactured by the wafer process unit 3. The packaging unit 4 performs a packaging process for wafers manufactured by the wafer process unit 3, in which various chips are placed on a substrate and wiring is performed between the multiple chips based on the placement information designed by the design unit 2. The packaging unit 4 also transmits data measured by various measuring devices in the packaging process to the supervising device 1 as packaging process information.

[0040] 4 is a block diagram showing an example of the internal configuration of the supervising device 1. The supervising device 1 operates as a platform that provides the functions of each section of the design section 2. The supervising device 1 includes a wafer process information collecting section 50, a packaging process information collecting section 60, a design process learning section 70, and a separating section 73.

[0041] The wafer process information collecting unit 50 accumulates wafer process information acquired for each wafer manufactured in the wafer process, and outputs the wafer process information to the design process learning unit 70. The wafer process information collecting unit 50 includes a data acquiring unit 51, a feedback unit 52, and a wafer process database (hereinafter referred to as DB) 53.

[0042] The data acquisition unit 51 acquires a large amount of data for each wafer in the wafer process as wafer process information. The data acquired by the data acquisition unit 51 is stored in the wafer process DB 53. The feedback unit 52 outputs the data (wafer process information) read from the wafer process DB 53 to the design process learning unit 70.

[0043] The packaging process information collection unit 60 accumulates packaging process information acquired each time a chip cut out from a wafer manufactured in the packaging process is packaged, and outputs the packaging process information to the design process learning unit 70. This packaging process information collection unit 60 includes a data acquisition unit 61, a feedback unit 62, and a packaging process DB 63.

[0044] The data acquisition unit 61 acquires a large amount of data measured for each packaged product in the packaging process as packaging process information. The data acquired by the data acquisition unit 61 is stored in a packaging process DB 63. The feedback unit 62 outputs the data (packaging process information) read from the packaging process DB 63 to the design process learning unit 70.

[0045] The design process learning unit 70 obtains design support information that supports the design of the wafer process based on the wafer process information. Furthermore, the design process learning unit 70 obtains design support information that supports the design of the packaging process based on the packaging process information. The design process learning unit 70 creates a design AI model based on this design support information and supplies it to the design unit 2. The design process learning unit 70 includes a design DB 71 and a design learning unit 72.

[0046] The design DB 71 performs a storage process to store wafer process information provided from the wafer process information collection unit 50, and also stores packaging process information provided from the packaging process information collection unit 60. The design DB 71 also stores design AI models used in the design process. The design AI models have functions to support various designs in the design process, and are models obtained by learning from past design data.

[0047] Machine learning in the design AI model can be unsupervised, supervised, or reinforcement learning, depending on the DMCO application. The design learning unit 72 performs machine learning or the like based on wafer process information and packaging process information to update the design AI model. The updated design AI model is stored in the design DB 71.

[0048] The isolation unit 73 can set the isolation range between the process of the customer designer and the process of the manufacturer that produces wafers based on that design. The design unit 2 can design the wafer specifications and package specifications using the design AI model provided by the design process learning unit 70. The wafer specifications designed by the design unit 2 are transmitted to the wafer process unit 3. The package specifications designed by the design unit 2 are transmitted to the package unit 4.

[0049] [Configuration of Design Unit] Fig. 5 shows an example configuration of the design unit 2. The design unit 2 is configured with a computer. The configuration shown in Fig. 5 shows a processing function unit configured in memory by executing a program implemented in the computer. The design unit 2 is configured with an AI / ML platform that performs machine learning (ML) using an AI model.

[0050] The design unit 2 includes a partitioning unit 21. The partitioning unit 21 performs partitioning to divide a chip to be designed into multiple blocks (partitioning process). The division into multiple blocks is applied to a hierarchical layout that is used in the design of large-scale semiconductors, and the partitioning unit 21 divides the chip into blocks that serve as units of the hierarchical layout.

[0051] The partitioning by the partitioning unit 21 is performed before wiring placement, and the size, shape, and number of blocks of each block, the type of logic circuit to be incorporated, etc. The partitioning by the partitioning unit 21 is performed by machine learning using a design AI model generated based on past semiconductor design data prepared in the design DB 71.

[0052] The partitioning unit 21 includes a placement and routing execution unit 22. The placement and routing execution unit 22 executes routing and placement for each of the divided blocks. When the placement and routing execution unit 22 executes routing and placement for each block, it uses a design AI model generated based on past semiconductor design data prepared in a design DB 71.

[0053] The design unit 2 also includes a design difficulty evaluation unit 23. The design difficulty evaluation unit 23 performs a design difficulty evaluation process to evaluate the design difficulty of each block obtained by the partitioning unit 21. The design difficulty evaluation unit 23 calculates, through the design difficulty evaluation process, the convergence time, which is the time required to design the wiring layout of each block. The design difficulty evaluation unit 23 also uses a design AI model prepared in the design DB 71 when making an evaluation. Details of the design difficulty evaluation performed by the design difficulty evaluation unit 23 will be described later with reference to the flowchart in FIG. 7.

[0054] The partitioning unit 21 modifies the details of each block (such as the size and shape of the block, and what kind of logic circuit is to be incorporated) when dividing the blocks based on the evaluation results of the design difficulty evaluation unit 23, and performs a process of leveling out the evaluation results of each block by the design difficulty evaluation unit 23.

[0055] Furthermore, if the design difficulty cannot be leveled by adjusting the size, shape, etc. of the blocks, the partitioning unit 21 performs processing to increase the number of blocks to achieve leveling. Details of these processing steps performed by the partitioning unit 21 will be described later with reference to the flowchart in Figure 6. The design unit 2 also includes a timing layout verification unit 24. The timing layout verification unit 24 performs timing layout verification on the wiring placement performed by the placement and routing execution unit 22.

[0056] 6 is a flowchart showing the flow of semiconductor design processing by the design unit 2. The design unit 2 acquires an RTL netlist D1, an SDC file D2, and a library D3 as data on semiconductor specifications. The RTL netlist D1, the SDC file D2, and the library D3 are the same as the RTL netlist D1, the SDC file D2, and the library D3 shown in FIG. 18 as a conventional example.

[0057] First, the RTL netlist D1, SDC file D2, and library D3 are input to the design unit 2, and the partitioning unit 21 performs partitioning (step S101). The partitioning unit 21 obtains a partition plan by performing the partitioning in step S101 (step S102). The resulting partition plan is a plan obtained by dividing the design into an appropriate number of blocks through machine learning using a design AI model generated from past design data stored in the design DB 71. Elements of the partition plan other than the number of blocks (such as block size, shape, and the type of logic circuit to be incorporated) are also determined appropriately using the design AI model stored in the design DB 71. When generating the partition plan, the partitioning unit 21 also generates TOP data, which is data outside the blocks.

[0058] When the partitioning unit 21 obtains a partition plan in step S102, the design difficulty evaluation unit 23 evaluates the design difficulty of each block in the obtained partition plan (step S103). The design difficulty evaluation unit 23 predicts the convergence time, which is the time required to design each block, and evaluates the design difficulty based on the leveling of the convergence time. In predicting the convergence time, the design difficulty evaluation unit 23 sets in advance in the design unit 2 the resources to be invested in the design of each block (such as the personnel who will carry out the design and the equipment used for the design).

[0059] The design difficulty evaluation unit 23 then determines whether the convergence times of the blocks as evaluated in step S103 have been leveled, and judges whether the leveling status can be improved (step S104). Here, the design difficulty evaluation unit 23 determines that the leveling status can be improved when there is a large variation in convergence times, for example, the convergence time of block A is 10 days, the convergence time of block B is 5 days, etc. Conversely, the design difficulty evaluation unit 23 determines that no improvement is necessary when there is little difference in the convergence times of the blocks and the leveling status is high.

[0060] If it is determined in step S104 that improvement is possible (Yes in step S104), the design difficulty evaluation unit 23 supplies the partitioning unit 21 with predicted convergence time information and instructs the partitioning unit 21 to formulate an improvement plan for the partitioning plan so that the convergence times of each block are approximately equal (step S105). Based on this instruction, the partitioning unit 21 recreates the partition plan in step S101. When formulating this improvement plan, the partitioning unit 21 also uses the design AI model accumulated in the design DB 71.

[0061] Furthermore, when it is determined in step S104 that no improvement is necessary (No in step S104), the design difficulty evaluation unit 23 causes the placement and routing execution unit 22 to perform a trial of wiring placement for each block using the partition plan obtained in step S102 (step S106). The wiring placement for each block here is a trial to confirm that convergence is possible, and the partitioning unit 21 determines whether convergence is possible for the entire semiconductor after the trial (step S107).

[0062] The processes from step S101 to step S106 are executed by machine learning using an AI model on the AI / ML platform of the design unit 2. If it is determined in step S107 that convergence is not possible (No in step S107), the process returns to step S105, and the partitioning unit 21 recreates the partition plan based on an instruction from the design difficulty evaluation unit 23.

[0063] If it is determined in step S107 that convergence is possible (Yes in step S107), the design unit 2 proceeds to the actual design of each block. That is, the design unit 2 adjusts the floor plan, which indicates how each block is to be placed on the chip (step S108). Then, the placement and routing execution unit 22 performs a wiring placement design for each block for which the floor plan has been adjusted (step S109). As a result, the placement and routing execution unit 22 obtains block data for which wiring placement has been completed (step S110). Thereafter, the design unit 2 performs a placement and routing design for the top region of the semiconductor and the boundary region of each block using the data for each block for which wiring placement has been completed and the top data (step S111).

[0064] Furthermore, the timing layout verification unit 24 of the design unit 2 verifies the timing layout and performs timing convergence by ECO processing (step S112). As a result, the design unit 2 completes the semiconductor design data and outputs (tapes out) the completed semiconductor design data. The design data output by the design unit 2 is supplied to the wafer process unit 3 and the packaging unit 4 (both of which are shown in FIG. 4).

[0065] [Details of Design Processing by Design Unit] Figure 7 is a flowchart showing in more detail the semiconductor design processing by the design unit 2. In the flowchart of Figure 7, the same processes as in the flowchart of Figure 6 are assigned the same step numbers. First, the design unit 2 acquires the RTL netlist D1, the SDC file D2, and the library D3. Then, the partitioning unit 21 performs partitioning based on this data (step S101) and obtains a partition plan (step S102).

[0066] When performing this partitioning, the partitioning unit 21 performs logic synthesis using input data (step S101a). Then, the partitioning unit 21 creates a partition plan for each block (step S101b). The logic synthesis in step S101a and the creation of a partition plan for each block in step S101b are performed by machine learning using a design AI model generated from past design data (step S101c).

[0067] Thereafter, the design difficulty evaluation unit 23 evaluates the design difficulty of each block of the resulting partition plan by predicting the convergence time, which is the time required to design each block (step S103). Furthermore, the design difficulty evaluation unit 23 determines whether the convergence time of each block as a result of the evaluation in step S103 has been equalized, and judges whether the equalization situation can be improved (step S104).

[0068] If it is determined in step S104 that improvement is not possible (No in step S104), the design difficulty evaluation unit 23 causes the placement and routing execution unit 22 to attempt wiring placement of the blocks of the partition plan (step S106). Here, the placement and routing execution unit 22 executes wiring placement within each block individually for each block (step S106a) and executes placement and routing of the TOP data and the boundaries of each block (step S106b). The placement and routing in steps S106a and S106b are also executed by machine learning using a design AI model generated from past design data (step S106c).

[0069] Then, the partitioning unit 21 determines whether convergence is possible for the semiconductor as a whole after the trial (step S107). If it is determined that convergence is possible in step S107, the processing is the same as the processing from step S106 onwards shown in the flowchart of Fig. 6. If it is determined that improvement is possible in step S104 (Yes in step S104) or if it is determined that convergence is not possible in step S107 (No in step S107), the design difficulty evaluation unit 23 instructs the design difficulty evaluation unit 23 to formulate an improvement plan for the partition plan (step S105).

[0070] Next, the details of what happens when the design difficulty evaluation unit 23 issues an instruction in step S105 will be described. First, the design difficulty evaluation unit 23 acquires design data and a report for each block as a partition plan (step S105a). Then, the design difficulty evaluation unit 23 analyzes and diagnoses the design difficulty of each block (step S105b). The analysis data and past design data obtained in step S105b are stored in a database (step S105c).

[0071] The design difficulty evaluation unit 23 then instructs the partitioning unit 21 to recreate the partition plan based on the analysis data and past design data accumulated in the database in step S105c (step S105d). This causes the processing of step S101 to be re-executed, and the partitioning unit 21 recreates the improved partition plan based on the instruction. The design difficulty evaluation unit 23 also uses the design AI model accumulated in the design DB 71 when analyzing and diagnosing the design difficulty of each block in step S105b and when instructing the recreation of the partition plan in step S105d.

[0072] 8 is a flowchart showing an example of the design difficulty evaluation process for each block performed by the design difficulty evaluation unit 23. First, the design difficulty evaluation unit 23 extracts parameters for each block data (step S121). Here, the design difficulty evaluation unit 23 predicts the shape, pin positions within each block, logic scale (nets, number of elements), timing (number of clocks, period), wiring complexity (number of MET fan-outs), and difficulty of timing convergence (number of logic stages between elements, logic complexity, etc.) for each block, and extracts the predicted parameters.

[0073] Next, the design difficulty evaluation unit 23 performs a convergence complexity analysis for each block data and TOP data (step S122). Here, the design difficulty evaluation unit 23 predicts the convergence time expected for each modification method. For this prediction, the design difficulty evaluation unit 23 performs weighting using the parameters extracted in step S121. Furthermore, the design difficulty evaluation unit 23 re-predicts the convergence time as necessary.

[0074] Thereafter, the design difficulty evaluation unit 23 analyzes the data of all blocks and the TOP data to determine whether the design difficulty is equalized for each block (step S123). For example, the design difficulty evaluation unit 23 determines whether the design difficulty and predicted convergence time of a specific block are outstanding. If the determination in step S123 is that the design difficulty and predicted convergence time of a specific block are outstanding, the design difficulty evaluation unit 23 instructs the partitioning unit 21 to perform a merge process to move part of the corresponding block to a peripheral block. Alternatively, the design difficulty evaluation unit 23 instructs the partitioning unit 21 to divide the corresponding block.

[0075] In this way, if improvement is possible based on this judgment result, the design difficulty evaluation unit 23 feeds back information for re-partitioning to the partitioning unit 21. Also, if no further improvement is possible in step S123, that is, if the block division has been optimized, the process moves to step S108 and subsequent steps in the flowchart of FIG. 6, and the design unit 2 proceeds to floorplan adjustment and wiring placement processing.

[0076] 9 shows an example of an image in which the design difficulty evaluation unit 23 evaluates each block obtained as a partition plan. As shown in FIG. 9, assume that five blocks HLB1 to HLB5 exist in the semiconductor 100 represented by the partition plan. In this case, the design difficulty evaluation unit 23 performs processing to obtain evaluation values ​​for each of HLB1 to HLB5 using a plurality of evaluation methods.

[0077] 9 shows an example in which six types of evaluation methods are applied to block HLB4, and evaluation values ​​for each method are obtained. The design difficulty evaluation unit 23 then evaluates block HLB4 using the method with the lowest evaluation value among the six evaluation methods. In this way, the design difficulty evaluation unit 23 performs evaluation on all blocks indicated in the partition plan.

[0078] 10 shows an image in which a partition plan semiconductor 100a is evaluated and a revised partition plan semiconductor 100b is created. As shown on the left side of FIG. 10, the initially created partition plan semiconductor 100a has six partitions HLB1 to HLB6, and the estimated design time for each block is assumed to be significantly longer for block HLB3 than for the other blocks.

[0079] At this time, as shown in the semiconductor 100b of the proposed revision shown on the right side of Figure 10, the partitioning unit 21 allocates the logic of block HLB3 to other blocks, and makes the estimated design time of block HLB3 approximately the same as that of the other blocks. Note that the number of blocks is also reduced in the proposed revision shown in the example of Figure 10. However, reducing the number of blocks is just an example, and the partitioning unit 21 may also perform a revision to increase the number of blocks. Note that there are cases in which the partitioning unit 21 does not change the number of blocks.

[0080] As described above, according to this embodiment, when a semiconductor is divided into multiple blocks for design, the block division can be optimized based on the design difficulty of each block, contributing to shortening the semiconductor design period. That is, as described in FIG. 18, in the past, adjustment of block division was performed manually, which often resulted in variations in the convergence time (design time) of each block. Furthermore, the design time for the entire semiconductor was determined by the block with the longest convergence time, resulting in a long design time.

[0081] In contrast to this, in the present embodiment, the design difficulty evaluation unit 23 causes the partitioning unit 21 to re-execute the partitioning process through evaluation using the design AI model so as to equalize the convergence time of each block. Then, the design difficulty evaluation unit 23 equalizes the convergence time of each block. Therefore, according to the present embodiment, the variation in design time of each block is suppressed, which can contribute to shortening the semiconductor design period.

[0082] Furthermore, in this embodiment, not only is the convergence time of the blocks measured, but a trial placement and routing (processing in step S106 of FIG. 6 ) is performed before the placement and routing of each block is actually performed, and a judgment is made as to whether the placement and routing of each block will be performed properly. Therefore, in this embodiment, it is possible to avoid situations where the placement and routing of each block becomes difficult. This leads to avoiding the design coming to a deadlock midway and having to go back to creating the initial partition plan, and in this respect, it is possible to contribute to shortening the semiconductor design period.

[0083] [Another Example of Evaluation Processing by Design Difficulty Evaluation Unit] Note that another evaluation processing may be performed as the evaluation processing of the partition proposal in the design difficulty evaluation unit 23. FIG. 11 is a flowchart showing an example of another evaluation processing by the design difficulty evaluation unit 23. Describing the example shown in FIG. 11 , first, the design difficulty evaluation unit 23 executes parameter extraction for each block data (step S211). In step S211, the design difficulty evaluation unit 23 predicts, for each block, the shape, the position of the pins in each block, the logic scale (nets, number of elements), timing (number of clocks, period), wiring complexity (number of MET fan-outs), and difficulty of timing convergence (number of logic stages between elements, logic complexity, etc.), and extracts the predicted parameters.

[0084] Furthermore, in step 211, the design difficulty evaluation unit 23 estimates power, performance, and area in addition to these parameters, and extracts the predicted parameters for each. Power estimation is performed, for example, based on the logic scale. Performance estimation is performed, for example, based on the timing period difficulty. Area estimation is performed, for example, based on the logic scale and wiring complexity. In semiconductor design, these three items, power, performance, and area, are collectively referred to as PPA, taking the initials of each item.

[0085] Next, the design difficulty evaluation unit 23 performs a convergence complexity analysis for each block data and TOP data (step S212). During this convergence complexity analysis, the design difficulty evaluation unit 23 analyzes the convergence complexity by taking into account the requirements of the three items of PPA (power, performance, and area) in addition to the convergence complexity analysis shown in step S122 of FIG. 8. For example, the design difficulty evaluation unit 23 compares the area and power estimates with the required levels, and if necessary, applies an improvement methodology to modify the semiconductor configuration method and re-predict whether this will affect the convergence time.

[0086] Furthermore, the design difficulty evaluation unit 23 compares the performance estimate with the required value, and if necessary, applies an improvement methodology to modify the semiconductor configuration method and re-predicts whether this will affect the convergence time. Note that, although the design difficulty evaluation unit 23 compares all three items of the PPA here, it may also compare one or two items.

[0087] The design difficulty evaluation unit 23 applies an improvement methodology to make corrections, such as changing the number of cell tracks, changing the contact poly pitch (CPP), and applying multi-rows. Regarding changing the number of cell tracks, in semiconductor design, standard cells used in automatic placement and routing have a fixed height and vary in width to achieve different drive capabilities and functions. The design difficulty evaluation unit 23 can also change the drive capabilities of the entire chip and layout block by changing the height of all cells. Height is usually expressed in terms of the number of tracks in the M1 wiring (e.g., 6-track cell, 7-track cell, etc.).

[0088] Figure 12 (a), (b), and (c) show an image of an increase in the number of cell tracks as a wiring configuration. In the example of Figure 12, the number of tracks increases in order from (a) to (c). As the number of tracks increases, the area of ​​the semiconductor increases, but as the number of tracks increases, performance improves.

[0089] To explain the change in CPP, CPP is a method of changing the transistor gate size itself, rather than changing the height while keeping the same cell architecture. In this case, the spacing between the gate and poly within the cell, called CPP, or the spacing between the gate and the first wiring layer (M1), is used as a parameter and these parameters are changed. Figures 13A and 13B show an image of the spacing value corresponding to this CPP being changed. In general, in semiconductors, as the CPP increases, the gate width increases, and the cell becomes larger, but performance improves.

[0090] The multi-row modification (application) is a method of stacking cells with different cell tracks vertically, that is, arranging cells with the same track in each row, thereby improving both performance and area. For example, in semiconductors, by stacking 6-track cells and 7-track cells vertically in a row of 6-track cells and a row of 7-track cells, and arranging cells with the same track horizontally, both performance and area can be improved.

[0091] Figures 14A, 14B, 15A, and 15B are diagrams showing modified examples of multi-row. Figure 14A shows an example of a 7-track / 6-track mixed row with 2-1 fins, and Figure 14B shows an example of an 8-track / 7-track mixed row with 3-2 fins. Figure 15A shows an example of a 3-3 fin, and Figure 15B shows an example of a 3-2 fin. The 3-3 fin in Figure 15A shows a case where part of the fin (the area indicated by the dashed line) has been cut. By selecting these configurations, semiconductors can improve both performance and area.

[0092] 11, after step S212, the design difficulty evaluation unit 23 analyzes the data of all blocks and the TOP data to determine whether the design difficulty levels are equalized for each block (step S213). Here, the design difficulty evaluation unit 23 determines, for example, whether the design difficulty and predicted convergence time of a particular block are outstanding. The design difficulty evaluation unit 23 also determines whether there are any blocks that do not satisfy the requirements of the PAA.

[0093] If it is determined in step S213 that the design difficulty and predicted convergence time of a particular block are outstanding or do not satisfy the PAA requirements, the design difficulty evaluation unit 23 instructs the partitioning unit 21 to perform a merge process to move part of the relevant block to a peripheral block. Alternatively, the design difficulty evaluation unit 23 instructs the partitioning unit 21 to divide the relevant block.

[0094] In this way, if improvement is possible based on this judgment result, the design difficulty evaluation unit 23 feeds back information for re-partitioning to the partitioning unit 21. When block division is instructed, the divided blocks become smaller in design and the design difficulty decreases, but on the other hand, the difficulty of the TOP data increases. Also, if no further improvement is possible in step S213, that is, if the block division has been optimized, the design unit 2 proceeds to the processing from step S108 onwards in the flowchart of FIG. 6, and proceeds to floorplan adjustment and wiring placement processing.

[0095] 11, the design difficulty evaluation unit 23 performs analysis taking into account the requirements of the three items of PPA (power, performance, and area), thereby enabling block division that satisfies the requirements of the three items of PPA. This enables the design difficulty evaluation unit 23 to perform more appropriate block division.

[0096] <Second Embodiment> Next, a design support system and a design support method according to a second embodiment of the present invention will be described with reference to Figures 16 to 17. In Figures 16 to 17, which are described in the second embodiment, the same parts as those in Figures 1 to 15, which were described in the first embodiment, are designated by the same reference numerals, and duplicated explanations will be omitted.

[0097] In this embodiment, the partitioning process in the partitioning unit 21 of the design unit 2 and the evaluation process in the design difficulty evaluation unit 23 are different from those in the first embodiment. The configuration of the design unit 2 is the same as the configuration shown in Fig. 5 in the first embodiment. In addition, the overall configuration of the design support system 10 including the design unit 2 is the same as the configuration explained in Figs. 3 and 4 in the first embodiment.

[0098] This embodiment is a process for when there is existing design data that has already been divided into multiple block data and TOP data, and it becomes necessary to logically modify at least some of the block data of the existing design data.

[0099] [Flow of Design Processing by Design Unit] Figure 16 is a flowchart showing the flow of semiconductor design processing by the design unit 2 in this embodiment. The design unit 2 is supplied with existing design data, namely, first block data 101a, second block data 101b, ..., nth block data 101n (n is an integer equal to or greater than 2), and TOP data 102. Logic modification information D11 is also input to the design unit 2. The logic modification information D11 is, for example, a netlist, and indicates which block or TOP data is to be modified. The block to be modified may be multiple blocks. The design unit 2 then extracts parameters from the block or TOP data to be modified among the input block data 101a-101n and TOP data 102 (step S301). The following explanation will be given for the case where one of the blocks is to be modified.

[0100] As a result of the extraction process in step S301, the design unit 2 acquires parameters of the block to be corrected (step S302). From the parameters of the block to be corrected, the design difficulty evaluation unit 23 predicts the convergence time as an evaluation of the design difficulty (step S303). The design AI model stored in the design DB 71 is used to predict the convergence time.

[0101] Then, the design difficulty evaluation unit 23 determines whether the partitioning unit 21 can improve the convergence time by partitioning (step S304). If the determination in step S304 indicates that improvement is possible (Yes in step S304), the design difficulty evaluation unit 23 instructs the formulation of an improvement plan (step S305), returns to the processing in step S301, and executes the parameter extraction processing for another improvement plan.

[0102] If it is determined in step S304 that further improvement is not possible (No in step S304), the design difficulty evaluation unit 23 proposes a correction method based on the formulated improvement plan (step S306). The processes from step S301 to step S306 are executed by the AI / ML platform of the design unit 2.

[0103] Based on the proposed modification method in step S306, the design unit 2 modifies the logic to be placed in each block (step S307) and performs change processing in accordance with the modification method (step S308). The timing layout verification unit 24 of the design unit 2 then verifies the timing layout and performs timing convergence through ECO processing (step S309). This allows the design unit 2 to complete the modification of the semiconductor design data and output (tape-out) the modified semiconductor design data.

[0104] 17 is a flowchart showing an example of the design difficulty evaluation process for each block performed by the design difficulty evaluation unit 23 in this embodiment. First, the design difficulty evaluation unit 23 executes parameter extraction for each block data to be corrected (step S311). Here, the design difficulty evaluation unit 23 predicts the shape, pin positions within each block, logic scale (nets, number of elements), timing (number of clocks, period), wiring complexity (number of MET fan-outs), and difficulty of timing convergence (number of logic stages between elements, logic complexity, etc.) for each block, and extracts the predicted parameters.

[0105] Next, the design difficulty evaluation unit 23 performs a convergence time prediction as a design difficulty evaluation for each block data to be corrected (step S312). Here, the design difficulty evaluation unit 23 predicts the convergence time expected for each correction method. For this prediction, the design difficulty evaluation unit 23 also performs weighting using the parameters extracted in step S311. Then, if necessary, it performs a re-prediction of the convergence time.

[0106] Thereafter, the design difficulty evaluation unit 23 evaluates the convergence period and determines whether improvement is possible for each block data to be corrected (step S313). Here, the design difficulty evaluation unit 23 compares and analyzes the past performance values ​​in the design DB with the current correction content to determine the appropriateness of the correction method. If the determination of appropriateness in step S313 indicates that the correction method is not appropriate, the design difficulty evaluation unit 23 reanalyzes the correction method and formulates improvement measures. Improvement measures include changing the correction method or providing more detailed correction instructions.

[0107] As described above, according to this embodiment, correction of already created block data can also be executed in the shortest convergence time.

[0108] <Modifications> In the above-described embodiments, the design unit 2 in the design support system 10 shown in Fig. 3 is equipped with the partitioning unit 21 and design difficulty evaluation unit 23 shown in Fig. 5. In contrast, the computer serving as the design unit 2 may be equipped with a program serving as a design support method for executing the processes shown in the flowcharts of Fig. 6 and Fig. 7 in the first embodiment or the processing procedures shown in the flowcharts of Fig. 16 and Fig. 17 in the second embodiment, thereby functioning as the design support system 10. In this case, the program can be installed in the computer via various recording media.

[0109] DESCRIPTION OF SYMBOLS 1...Supervising device, 2...Design department, 3...Wafer process department, 4...Packaging department, 10...Design support system, 21...Partitioning department, 22...Placement and wiring execution department, 23...Design difficulty evaluation department, 24...Timing layout verification department, 50...Wafer process information collection department, 51...Data acquisition department, 52...Feedback department, 53...Wafer process DB, 60...Packaging process information collection department, 61...Data acquisition department, 62...Feedback department, 63...Packaging process DB, 71...Design DB, 72...Design learning department, 101a to 101n...Block data, 102...TOP data

Claims

1. A design support system for designing semiconductors based on specifications, comprising: a database that stores past design data for semiconductors; a partitioning unit that creates a partition plan for dividing the semiconductor, according to the specified specifications, into multiple blocks based on the past design data stored in the database; and a design difficulty evaluation unit that evaluates the design difficulty of each block obtained as a result of the division by the partitioning unit based on the past design data stored in the database.

2. The design support system according to claim 1, wherein the design difficulty assessment unit extracts predicted parameters for each block from past design data, performs convergence complexity analysis based on the extracted parameters and the specifications, predicts the convergence time required for the design of each block, and assesses the design difficulty based on the convergence time.

3. The design support system according to claim 2, wherein said partitioning section divides the design into blocks so as to equalize the convergence time of each block predicted by said design difficulty evaluation section.

4. The design support system according to claim 3, wherein when the partition plan does not improve the leveling of the convergence time of each block, the partitioning unit creates a partition plan that increases the number of blocks.

5. The design support system according to claim 1, wherein the design difficulty evaluation unit estimates at least one of power, performance, and area for each block, compares the estimate with the required value for that block, and, if there is an impact on convergence time, executes an improvement methodology for the design items to modify the method applied to the semiconductor.

6. The design support system according to claim 1, wherein the design difficulty evaluation unit evaluates the design difficulty when modifying the logic of a portion of an already blocked block, and the partitioning unit creates a partition plan with the modified logic.

7. A design support method for designing a semiconductor based on specifications through computational processing by a computer, the computational processing executed by the computer including: a storage process for storing past design data of the semiconductor as a database; a partitioning process for creating a partition plan for dividing the semiconductor, according to the specified specifications, into a plurality of blocks, based on the past design data stored in the database; and a design difficulty evaluation process for evaluating the design difficulty of each block obtained as a result of the division in the partitioning process, based on the past design data stored in the database.

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