Design assistance system and design assistance method

Abstract

The present invention comprises: a specification input unit for acquiring specifications of a wafer or a package; a language model processing unit for code generation whereby code necessary for designing the wafer or package by natural language processing using a language model is generated on the basis of the input specifications; a transmission / reception unit for transmitting confidential data-excluding learning data, in which data that requires concealment has been excluded from learning data used in the natural language processing, and inputs and outputs of the code generation language model processing unit, to an external server, and receiving a natural language processing result of the server; and a verification unit for verifying code generated as the natural language processing result of the server. When the verification unit determines that the code is valid, the verified code is output as design data of the wafer or package.

Description

Design support system and design support method

[0001] The present invention relates to a design support system and a design support method suitable for application to semiconductor design.

[0002] Conventionally, general-purpose semiconductors that can be installed in various products have been mass-produced. Examples of general-purpose semiconductors include central processing units (CPUs) installed in personal computers. Conventional general-purpose semiconductors based on the von Neumann architecture have been designed to have high performance in sequential processing.

[0003] According to Moore's Law, semiconductor production costs can be reduced by increasing integration density. Therefore, the main goal of conventional semiconductors has been to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing the production volume of semiconductors requires a large investment in equipment. For this reason, the fabless production method, in which a company that primarily designs semiconductors outsources the production of semiconductors to an external company, has become mainstream.

[0004] Patent Document 1 discloses a technique relating to lithography-based pattern optimization.

[0005] U.S. Pat. No. 1,144,9659

[0006] As semiconductors become increasingly miniaturized, not only are there issues with turnaround time (TAT) in semiconductor manufacturing, but the rules and constraints for semiconductor design have become more complex, lengthening the time required for design. As a result, if a problem is discovered in the semiconductor development process, it takes a huge amount of time and money to redo the design and manufacturing (prototype). Therefore, a design methodology that reduces the number of redoes required when designing semiconductors was needed.

[0007] In the current semiconductor manufacturing system, semiconductor design companies and semiconductor manufacturing companies exist separately. Therefore, semiconductor design companies do not share information about optimal manufacturing conditions or causes of failures, which can only be determined by semiconductor manufacturing companies manufacturing semiconductors based on design information from semiconductor design companies. Even if information about optimal manufacturing conditions and causes of failures were shared between semiconductor design companies, semiconductor design companies simply repeated trial and error, not knowing how to optimally design semiconductors. Therefore, conventional semiconductors required a lot of time to design. Furthermore, even when the technology disclosed in Patent Document 1 was used, the time required for semiconductor design remained the same.

[0008] The present invention has been made in view of the above circumstances, and has as its object to provide a design support system and a design support method that can reduce the time and effort required for semiconductor design.

[0009] The design support system of the present invention is a design support system for designing either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from wafers, and includes: a specification input unit for acquiring specifications of the wafer and / or package; a code-generation language model processing unit for generating code required for designing the wafer and / or package through natural language processing using a language model based on the specifications input to the specification input unit; a transceiver unit for transmitting confidential data-excluded learning data, which is learning data used in the natural language processing in the code-generation language model processing unit that has excluded data that needs to be kept confidential, and the input and output of the code-generation language model processing unit to an external server that performs natural language processing and receives the results of the natural language processing at the server; a verification unit for verifying the code obtained by the transceiver unit as the result of the natural language processing at the server; and if the verification unit determines that the verified code is appropriate, outputting the verified code as design data for the wafer and / or package.

[0010] Furthermore, the design support method of the present invention is a design support system that designs either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from wafers through computational processing by a computer, and the computational processing executed by the computer includes: a specification input process for acquiring specifications of the wafer and / or package; a code generation language model process for generating code required for designing the wafer and / or package through natural language processing using a language model based on the specifications input by the specification input process; a transmission and reception process for transmitting confidential data-excluded learning data, which is learning data used in the natural language processing by the code generation language model process that excludes data that needs to be kept confidential, and the input and output when performing the code generation language model processing to an external server that performs natural language processing, and receiving the natural language processing results at the server; and a verification process for verifying the code as a result of the natural language processing at the server obtained by the transmission and reception process, and if the verification process determines that the code is appropriate, the verified code is output as design data for the wafer and / or package.

[0011] According to the present invention, the time required for semiconductor design can be significantly reduced by coordinating the generation of design code in an on-premise environment that can be used by the design department and the generation of design code in a cloud environment using an external server.

[0012] FIG. 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to a first embodiment of the present invention. FIG. 2 is a diagram showing an example of a post-process in a packaging process according to the first embodiment of the present invention. FIG. 3 is a block diagram showing an example of an overall configuration of a design support system according to the first embodiment of the present invention. FIG. 4 is a block diagram showing an example of a configuration of a control device according to the first embodiment of the present invention. FIG. 5 is a block diagram showing an example of a configuration of a design unit of the design support system according to the first embodiment of the present invention. FIG. 6 is a flowchart showing an example of a program language generation process of the design unit of the design support system according to the first embodiment of the present invention. FIG. 7 is a flowchart showing an example of a process in an on-premise environment and an example of a process in a cloud environment during design in the design support system according to the first embodiment of the present invention. FIG. 8 is a block diagram showing an example of a configuration of the design unit of the design support system according to a second embodiment of the present invention. FIG. 9 is a flowchart showing an example (Example 1) of a program language generation process of the design unit of the design support system according to the second embodiment of the present invention. FIG. 10 is a flowchart showing an example (Example 2: an example of generating an intermediate language) of the program language generation process of the design unit of the design support system according to the second embodiment of the present invention. FIG. 11 is a diagram showing an example of a processing configuration of code generated by the design support system according to the second embodiment of the present invention. FIG. 12 is a diagram showing an example of code generated by the code generation LLM processing unit according to each embodiment of the present invention. 10A-10C illustrate examples of additional prompts according to exemplary embodiments of the present invention.

[0013] First Embodiment A design support system and a design support method according to a first embodiment of the present invention will be described below with reference to FIGS.

[0014] [Example of Semiconductor Manufacturing Process] FIG. 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to a first embodiment.

[0015] Semiconductor manufacturing processes are broadly divided into a design process, a wafer process for manufacturing wafers, and a packaging process for manufacturing packages from wafers. In this embodiment, the manufacturing technology for design is called MFD (Manufacturing for Design) to distinguish it from DFM (Design for Manufacturing), a conventional design technology for manufacturing. MFD is a methodology for supporting design based on data obtained in the wafer and packaging processes. In a design support system 10 according to a first embodiment (see FIG. 3 , described later), repeated MFD and DFM enable design-manufacturing co-optimization (DMCO), which represents the coordination and optimization of semiconductor design and manufacturing. As a result, the design support system 10 according to the first embodiment enables a reduction in the total cycle time from semiconductor design to packaging compared to conventional methods.

[0016] In the design process, semiconductors and circuit layouts are designed. In this embodiment, a new design methodology supported by an AI (Artificial Intelligence) model is provided to semiconductor customers. For example, the AI ​​model learns silicon big data measured by various measuring devices in the wafer process and packaging process, thereby training each AI model stored in a design DB 71 (described later) shown in FIG. 4 . This improves the performance of the PDK (Process Design Kit). In this embodiment, the trained AI model is used in the design process to assist the customer's designer in their design, thereby automating semiconductor design.

[0017] The PDK contains technology information necessary for semiconductor design, such as what device models are available, what design rules should be used, and what regulatory components should be extracted. Designers import this information into the PDK tool to design semiconductors. The MFD, in which the AI ​​model learns from silicon big data as shown in Figure 1, and the MFD, in which the AI ​​model assists the designer in design by navigating them, are structured in a hierarchical structure.

[0018] [General Wafer and Packaging Processes] The wafer and packaging processes are divided into front-end and back-end processes. The front-end process includes a front-end of line (FEOL) where elements are formed, a back-end of line (BEOL) where wiring is formed, and wafer characteristic inspection.

[0019] The FEOL includes, for example, a cleaning process, a film formation process, a photolithography process, an etching process, an ion implantation process, and a wafer inspection process, and these processes are performed repeatedly. The BEOL includes, for example, a cleaning process, a film formation process, a photolithography process, an etching process, a planarization process, and a wafer inspection process, and these processes are performed repeatedly on wafers manufactured through the FEOL. In the wafer characteristic inspection in the wafer inspection process, an electrical characteristic inspection of the wafer is performed on the wafer manufactured through the BEOL. When the wafer characteristic inspection is completed, the wafer is completed.

[0020] The back-end process includes an assembly process and an inspection process. The assembly process includes a dicing process, a die bonding process, a wire bonding process, and a molding process for wafers that are determined to be non-defective as a result of the wafer characteristic inspection. The inspection process includes a final inspection process for semiconductors produced in the molding process. This back-end process consisting of the assembly and inspection processes is carried out in a simple packaging process using wire bonding of a single chip and a complex packaging process in which multiple chips are stacked. In the back-end process, once the final inspection process is completed, a packaged semiconductor (also called a chip) is completed.

[0021] [Wafer Process and Packaging Process According to the Present Embodiment] Generally, wafer processes are divided into batch processes, in which all wafers in a lot undergo the same process, and single-wafer processes, in which wafers in a lot are processed one by one and the process for each wafer can be changed. Typically, batch and single-wafer processes coexist. In contrast, in the wafer process according to the present embodiment, all processes are performed using the single-wafer process. As a result, in this embodiment, the time required to complete one lot can be reduced to less than the time required to complete batch-based processing. Furthermore, in this embodiment, by prototyping each wafer under different conditions, a larger amount of data can be accumulated in the same time period compared to processes that include batch processing, and silicon big data can be generated. Silicon big data contributes to improving wafer yield in the wafer process. Silicon big data is also used to train AI models in the design process (MFD). Furthermore, in the wafer process, the single-wafer process can reduce the processing time (x) per wafer to less than half of the conventional process.

[0022] The packaging process involves bonding multiple wafers, wafers, chips, and chips together to form multi-chips, which are then mounted on a substrate, resulting in a wide variety of complex combinations. The post-process, described next, conceptually involves chipping the wafers completed in the pre-process, mounting the chips on a substrate (e.g., a silicon substrate) with additional rewiring, and then mounting the resulting substrate on a final packaging substrate. In the post-process, a substrate with additional rewiring is mounted on the packaging substrate, resulting in multiple integrated chips with various functions. Therefore, according to this embodiment, even if not all functions are integrated on a single chip, equivalent functionality can be achieved by using a packaging substrate product in which multiple chips with various functions are integrated.

[0023] 2 is a diagram showing an example of a back-end process in a packaging process that supports multi-chip integration. In the back-end process, for example, a bump formation process and a dicing process are performed on the wafer manufactured in the above-mentioned front-end process. In the back-end process, a TSV process, a rewiring layer formation process, and a bump formation process are performed on the rewiring substrate. Then, in the back-end process, a chip mounting process is performed in which the chips separated by the dicing process are combined with the rewiring substrate. Then, in the back-end process, an encapsulation process and a bump formation process are performed, followed by a substrate mounting process on the packaging substrate. In the back-end process, a final inspection process is performed after the encapsulation process.

[0024] During the design process, heterogeneous (heterogeneous integration) design is possible using chiplet technology based on design support information received from a chiplet technology platform containing multiple IPs. In the semiconductor field, functional blocks that make up LSIs, such as CPUs, image processing circuits, and memories, are considered design assets and are called IP (Intellectual Property) cores or simply IPs. In this specification, IP is described as a circuit element in semiconductor design. Circuit elements can be anything, including simple standard cells, interface functional blocks, or CPU cores.

[0025] 3 is a block diagram showing an example of the overall configuration of a design support system 10 according to this embodiment. The design support system 10 includes a control device 1, a design section 2, a wafer process section 3, and a packaging section 4.

[0026] The supervisory device 1 provides a platform that can be arbitrarily accessed by the design department 2, wafer process department 3, and packaging department 4. To this end, the supervisory device 1 acquires wafer process information measured in the wafer process for manufacturing wafers from the wafer process department 3. The supervisory device 1 also acquires packaging process information measured in the packaging process from the packaging department 4. The supervisory device 1 then provides design support information calculated based on the wafer process information and packaging process information to the design department 2.

[0027] The supervision device 1 uses the wafer process information as silicon big data and the packaging process information as packaging big data to perform analysis using a design AI model (described below) to create design support information. The analysis using the design AI model determines correlations between various types of parameters based on the silicon big data and the packaging big data. The design AI model provides the design support information, including optimal parameter combinations and values, to the design unit 2.

[0028] The design unit 2 designs the wafer process and the wafer packaging process. The design support information provided by the supervision device 1 and the design support function of the AI ​​model enable optimal semiconductor design, so the design unit 2 can increase the convergence speed of the design. Note that the design unit 2 may also import information on semiconductor design created by a designer using the design support function of the AI ​​model. Alternatively, the design unit 2 may import information on semiconductor design created by the AI ​​model itself.

[0029] The wafer process section 3 has a function of managing the wafer process, and manufactures wafers based on the design information designed by the design section 2. The wafer process section 3 transmits data measured by various measuring devices in the wafer process to the supervising device 1 as wafer process information.

[0030] The packaging unit 4 has a function of managing the packaging process for wafers manufactured by the wafer process unit 3. The packaging unit 4 performs a packaging process for wafers manufactured by the wafer process unit 3, in which various chips are placed on a substrate and wiring is performed between the multiple chips based on the placement information designed by the design unit 2. The packaging unit 4 also transmits data measured by various measuring devices in the packaging process to the supervising device 1 as packaging process information.

[0031] 4 is a block diagram showing an example of the internal configuration of the supervising device 1. The supervising device 1 operates as a platform that provides the functions of each section of the design section 2. The supervising device 1 includes a wafer process information collecting section 50, a packaging process information collecting section 60, a design process learning section 70, and a separating section 73.

[0032] The wafer process information collecting unit 50 accumulates wafer process information acquired for each wafer manufactured in the wafer process, and outputs the wafer process information to the design process learning unit 70. The wafer process information collecting unit 50 includes a data acquiring unit 51, a feedback unit 52, and a wafer process database (hereinafter referred to as DB) 53.

[0033] The data acquisition unit 51 acquires a large amount of data for each wafer in the wafer process as wafer process information. The data acquired by the data acquisition unit 51 is stored in the wafer process DB 53.

[0034] The feedback unit 52 outputs the data (wafer process information) read from the wafer process DB 53 to the design process learning unit 70 .

[0035] The packaging process information collection unit 60 accumulates packaging process information acquired each time a chip cut out from a wafer manufactured in the packaging process is packaged, and outputs the packaging process information to the design process learning unit 70. This packaging process information collection unit 60 includes a data acquisition unit 61, a feedback unit 62, and a packaging process DB 63.

[0036] The data acquisition unit 61 acquires a large amount of data measured for each packaged product in the packaging process as packaging process information. The data acquired by the data acquisition unit 61 is stored in a packaging process DB 63. The feedback unit 62 outputs the data (packaging process information) read from the packaging process DB 63 to the design process learning unit 70.

[0037] The design process learning unit 70 obtains design support information that supports the design of the wafer process based on the wafer process information. Furthermore, the design process learning unit 70 obtains design support information that supports the design of the packaging process based on the packaging process information. The design process learning unit 70 creates a design AI model based on this design support information and supplies it to the design unit 2. The design process learning unit 70 includes a design DB 71 and a design learning unit 72.

[0038] The design DB 71 accumulates wafer process information provided by the wafer process information collection unit 50 and packaging process information provided by the packaging process information collection unit 60. The design DB 71 also stores design AI models used in the design process. The design AI models have functions to support various designs in the design process. Machine learning in the design AI models uses either unsupervised learning, supervised learning, or reinforcement learning depending on the DMCO application. The design learning unit 72 performs machine learning etc. based on the wafer process information and packaging process information to update the design AI models. The updated design AI models are stored in the design DB 71.

[0039] The dividing unit 73 can set the dividing range between the process of the designer who is the customer and the process of the manufacturer who manufactures wafers based on that design.

[0040] The design department 2 designs wafer specifications and package specifications using a design AI model provided by the design process learning department 70. The wafer specifications designed by the design department 2 are transmitted to the wafer process department 3. The package specifications designed by the design department 2 are transmitted to the package department 4.

[0041] The design unit 2 performs design using a design AI model in a so-called on-premise environment prepared within a company that has the design support system 10 according to this embodiment. However, the design unit 2 of this embodiment transfers data to a cloud server 90 prepared in a cloud environment, and performs part of the design using the cloud server 90. Details of the processing performed by this design unit 2 using the cloud server 90 will be described in Figure 5 and subsequent figures.

[0042] 5 shows an example of the configuration of the design unit 2. The design unit 2 includes a specification input unit 101. The specification input unit 101 performs specification input processing to acquire and input specifications (such as a specification sheet) of the semiconductor to be designed from a user company or the like. The specification data input to the specification input unit 101 is supplied to the code generation LLM processing unit 110. The specifications input to the specification input unit 101 are written in natural language.

[0043] The code generation LLM processing unit 110 is a code generation language model processing unit that generates code, which is a design specification in a design language required for designing wafers and packages, through natural language processing using a large language model (LLM). The code generation LLM processing unit 110 uses the design AI model provided by the design process learning unit 70 as the large language model.

[0044] The code generated by the code generation LLM processing unit 110 is written in, for example, C++, a language used in semiconductor design. The code is written at, for example, the RTL (Register Transfer Level) level. At the RTL level, details of hardware resources, details of data transfer registers, etc. are written.

[0045] When generating code, the code generation LLM processing unit 110 acquires additional information about the semiconductor design from a Retrieval-Augmented Generation (RAG) processing unit 140, which performs an augmentation process called RAG. The additional information acquired from the RAG processing unit 140 is used together with the design AI model when the code generation LLM processing unit 110 performs natural language processing using a large-scale language model.

[0046] The code generation LLM processing unit 110 is also configured to be able to transfer data to and from the external cloud server 90 via a transmission / reception unit 111. The transmission / reception unit 111 executes transmission / reception processing between the code generation LLM processing unit 110 and the cloud server 90 via a predetermined network.

[0047] The cloud server 90 is a general-purpose server that is provided on a network such as the Internet and performs natural language processing using a large-scale language model. The cloud server 90 is used by various users and has an extremely large-scale language model that is an AI model that has been accumulated through repeated learning based on use by the various users.

[0048] Therefore, the large-scale language model held by the cloud server 90 is likely to be larger in scale than the code generation LLM processing unit 110 of the design unit 2 prepared in an on-premise environment. Note that the cloud server 90 may be one having a design AI model specialized for semiconductor design, or a general-purpose cloud server that is not specialized for semiconductor design may be used.

[0049] The code generation LLM processing unit 110 uses the cloud server 90 to generate code that meets appropriate design specifications through the interaction of the large-scale language models possessed by both parties. That is, the transmission / reception unit 111 sends the code generated by the code generation LLM processing unit 110 and training data from the AI ​​model to the cloud server 90 as data d1, and receives the code that has been further processed by the cloud server 90 as data d2.

[0050] The code included in the data d2 received by the transmitting / receiving unit 111 is supplied to the code generating LLM processing unit 110 and output as a code generated by the code generating LLM processing unit 110. The process in which the code generating LLM processing unit 110 generates a code using the cloud server 90 will be described later with reference to the flowchart in FIG.

[0051] The code generated by the code generation LLM processing unit 110 is verified by the C++ verification unit 120 and the RTL verification unit 130 to determine whether it is correct. At this time, the C++ verification unit 120 and the RTL verification unit 130 perform equivalence verification to determine whether they have been mutually verified correctly. As the C++ verification unit 120 and the RTL verification unit 130, commercially available tools (software) for semiconductor design can be used.

[0052] After the verification by the C++ verification unit 120 and the RTL verification unit 130 is completed, the code generated by the code generation LLM processing unit 110 and the cloud server 90 is output to the wafer process unit 3 and the packaging unit 4 shown in Figure 4.

[0053] 6 is a flowchart showing the flow of the code generation process performed by the code generation LLM processing unit 110. First, the specification input unit 101 of the design unit 2 acquires the specifications of the semiconductor to be designed (step S11). The acquired specifications are written in natural language, for example, in a specification table provided by a semiconductor user company.

[0054] The specification data acquired by the specification input unit 101 is supplied to the code generation LLM processing unit 110. The code generation LLM processing unit 110 generates code as wafer and package design data using a large-scale language model as a design AI model (step S12). In the LLM processing at this time, the specification data acquired by the specification input unit 101 becomes a prompt.

[0055] When generating code in step S12, the code generation LLM processing unit 110 acquires the additional status for performing the extension process from the RAG processing unit 140, and executes the code generation process after taking into consideration, for example, information specific to the design of the current software or package (step S18). Furthermore, the code generation process in step S12 is performed both in an on-premise environment by the code generation LLM processing unit 110 provided in the design unit 2 and in a cloud environment by the cloud server 90, as will be described in the following FIG. 7 .

[0056] Next, the design unit 2 acquires the programming language of the code obtained by the generation process in step S12 (step S13). Once the programming language is acquired in step S13, the C++ verification unit 120 and the RTL verification unit 130 of the design unit 2 verify the acquired programming language (step S14). Once the verification in step S14 is completed, the design unit 2 determines whether the verification result is OK (step S15).

[0057] If it is determined in step S15 that the programming language is not appropriate (No in step S15), the user of the design support system 10 executes specification correction (step S16). After the specification correction in step S16 is executed, the design unit 2 returns to the processing of step S11 and receives the corrected specification in the specification input unit 101.

[0058] If it is determined in step S15 that the programming language is appropriate (Yes in step S15), the design unit 2 performs processing such as high-level synthesis for the programming language acquired in step S13 (step S17), and ends the processing for acquiring the programming language. The high-level synthesis in step S17 is performed using, for example, an existing high-level synthesis tool.

[0059] 7 is a flowchart showing the flow of processing performed by the code generation LLM processing unit 110 when generating code, using the cloud server 90. First, the design unit 2 executes the code generation processing by the code generation LLM processing unit 110 on-premise (step S101).

[0060] During the code generation process in step S101, the code generation LLM processing unit 110 performs code generation through natural language processing using a design AI model obtained from the design DB 71 (FIG. 4). Then, the code generation LLM processing unit 110 acquires learning data from the used design AI model (step S102).

[0061] Next, the design unit 2 receives input of information (confidential data) that cannot be disclosed, as instructed by the user of the design support system 10 (step S103). This confidential data that cannot be disclosed may be held in advance by the design unit 2 or the like. The confidential data that cannot be disclosed is input, for example, as a list of keywords. Specifically, as a semiconductor manufacturer, keywords related to design matters that the manufacturer wants to keep secret as know-how become confidential data that cannot be disclosed.

[0062] When the confidential data is input in step S103, the transmitting / receiving unit 111 of the design unit 2 excludes the confidential data specified in step S103 from the learning data acquired in step S102 (step S104).Then, the transmitting / receiving unit 111 transmits the learning data from which the confidential data has been excluded and the code generated in step S101 to the cloud server 90.

[0063] The cloud server 90 executes a process of further converting the transmitted code into an appropriate code through natural language processing using the transmitted learning data and learning data already stored in the cloud server 90 (step S105). Note that the learning data stored in the cloud server 90 is learning data resulting from past code generation processes executed by multiple users.

[0064] Then, the transmitting / receiving unit 111 acquires the program language using the code obtained in the code generation process in step S105 from the cloud server 90 (step S106). The program language acquired in step S106 corresponds to the program language acquired in step S13 in FIG. 6.

[0065] As described above, according to this embodiment, design code generation in an on-premise environment prepared by a semiconductor design company and design code generation in a cloud environment using an external server are executed in cooperation with each other, thereby enabling appropriate semiconductor design in a short time. That is, according to this embodiment, design code generation processing is performed using natural language processing in both the on-premise environment and the cloud environment, so that appropriate semiconductor design code can be generated in a short time by taking advantage of the capabilities of each processing function.

[0066] In this embodiment, data that should be kept confidential is removed from the training data used in the on-premise environment before the training data is sent to the cloud environment. Therefore, according to this embodiment, the confidentiality of data that a semiconductor design company does not want to be made public is ensured, and natural language processing is executed in the cloud environment, thereby achieving both ensuring the confidentiality of the training data and reducing the design time.

[0067] <Second Embodiment> Next, a design support system and a design support method according to a second embodiment of the present invention will be described with reference to Figures 8 to 11. In Figures 8 to 11, which are described in the second embodiment, the same parts as those in Figures 1 to 7 described in the first embodiment are assigned the same reference numerals, and duplicated explanations will be omitted.

[0068] In this embodiment, the configuration and processing of the design unit 2 are different from those of the first embodiment. The overall configuration and processing of the design support system 10, excluding the design unit 2, are the same as those described in FIG. 3 and other figures as the first embodiment.

[0069] [Configuration of Design Unit] Fig. 8 shows the configuration of the design unit 2 of the design support system 10 according to this embodiment. The design unit 2 of this embodiment differs from the design unit 2 shown in Fig. 5 in that it includes a linguistic LLM processing unit 150. The linguistic LLM processing unit 150 receives the semiconductor specifications (such as specifications) input to the specification input unit 101 in natural language.

[0070] The language LLM processing unit 150 is a language generation language model processing unit that uses natural language processing with a large-scale language model (LLM) to generate natural language with specifications that match code generation from input specifications such as specifications. The language LLM processing unit 150 uses a design AI model provided by the design process learning unit 70 as the large-scale language model. When generating the specifications, the language LLM processing unit 150 also acquires additional information related to semiconductor design from the RAG processing unit 140 and generates specifications that reflect the additional information. A specific example of the language LLM processing unit 150 generating natural language with specifications that match code generation from data such as a specification table will be described later.

[0071] The specifications generated by the language LLM processing unit 150 are supplied to the code generation LLM processing unit 110. The code generation LLM processing unit 110 generates code, which is a design specification in a design language required for wafer and package design, by natural language processing using a large-scale language model (LLM), from the specifications that match the code generation supplied from the language LLM processing unit 150. This code generation LLM processing unit 110 is the same as the code generation LLM processing unit 110 of the first embodiment in that it uses a design AI model provided by the design process learning unit 70 as the large-scale language model.

[0072] Furthermore, in this embodiment, the code generation LLM processing unit 110 is the same as the code generation LLM processing unit 110 in the first embodiment in that when generating code, the code generation LLM processing unit 110 obtains and uses additional information regarding semiconductor design from the RAG processing unit 140.

[0073] In this embodiment, the code generation LLM processing unit 110 generates code using a cloud server 90. The code generation LLM processing unit 110 is configured to be able to transfer data to and from the external cloud server 90 via a transmission / reception unit 111. The process in which the code generation LLM processing unit 110 uses the cloud server 90 is the same as the process described in the flowchart of FIG. 7 of the first embodiment. Furthermore, in this embodiment, the design unit 2 includes a C++ verification unit 120 and an RTL verification unit 130, which verify whether the generated code is appropriate, just like the first embodiment. The design unit 2 also includes an additional prompt creation unit 112. When the code or specifications generated by the code generation LLM processing unit 110 or the language LLM processing unit 150 are inappropriate, the additional prompt creation unit 112 creates an additional prompt and supplies it to the code generation LLM processing unit 110 or the language LLM processing unit 150.

[0074] 9 is a flowchart showing an example (example 1) of the flow of processing performed by the language LLM processing unit 150 and the code generation LLM processing unit 110. First, the specification input unit 101 of the design unit 2 acquires the specifications of the semiconductor to be designed (step S21). The acquired semiconductor specifications are, for example, a specification table provided by a semiconductor user company, and are written in natural language.

[0075] The specification data acquired by the specification input unit 101 is supplied to the language LLM processing unit 150. The language LLM processing unit 150 uses a large-scale language model as a design AI model to generate specifications suitable for generating code for wafer and package design (step S22). In this LLM processing, the specification data acquired by the specification input unit 101 serves as a prompt. When generating specifications suitable for code generation in step S22, the language LLM processing unit 150 acquires additional status for performing extension processing from the RAG processing unit 140 and executes code generation processing (step S30).

[0076] The design unit 2 then acquires the specifications obtained by the generation process in step S22 and supplies the acquired specifications as a prompt to the code generation LLM processing unit 110 (step S23). The code generation LLM processing unit 110 then generates code as design data for the wafer and package using a large-scale language model as a design AI model (step S24).

[0077] Even when generating code in step S24, the code generation LLM processing unit 110 acquires the additional status for performing extension processing from the RAG processing unit 140 and executes code generation processing (step S30). Note that the code generation processing in step S24 is performed both in the on-premise environment by the code generation LLM processing unit 110 provided in the design unit 2 and in the cloud environment by the cloud server 90, as described in FIG. 7 of the first embodiment.

[0078] Next, the design unit 2 acquires the programming language of the code obtained in the generation process in step S24 (step S25). After acquiring the programming language in step S25, the C++ verification unit 120 and the RTL verification unit 130 verify the acquired programming language (step S26). After completing the verification in step S26, the design unit 2 determines whether the verification result is OK (step S27).

[0079] If it is determined in step S27 that the programming language is not appropriate (No in step S27), the user of the design support system 10 performs a process of creating an additional prompt to be instructed to the language LLM processing unit 150 (step S28a). Also, the user of the design support system 10 performs a process of creating an additional prompt to be instructed to the code generation LLM processing unit 110 (step S28b). The created additional prompt is input to the language LLM processing unit 150 or the code generation LLM processing unit 110 and is used to generate specifications in step S22 or to generate code in step S24.

[0080] The process of creating these additional prompts is performed by the user based on the verification results. Alternatively, the design unit 2 may automatically create prompts to supplement the specifications of inappropriate parts based on the verification results. Also, in FIG. 9 , both the creation of an additional prompt for the language LLM processing unit 150 in step S28a and the creation of an additional prompt for the code generation LLM processing unit 110 in step S28b are performed. Alternatively, the design unit 2 of this embodiment may only create an additional prompt for the code generation LLM processing unit 110 in step S28b.

[0081] Then, if it is determined in step S27 that the programming language is appropriate (Yes in step S27), the design unit 2 performs processing such as high-level synthesis for the programming language obtained in step S25 (step S29), and terminates the processing of obtaining the programming language.

[0082] [Processing in the Language LLM Processing Unit and the Code Generation LLM Processing Unit (Example 2)] Fig. 10 is a flowchart showing an example (Example 2) of the flow of processing performed by the language LLM processing unit 150 and the code generation LLM processing unit 110. Example 2 shown in Fig. 10 differs from Example 1 shown in Fig. 9 in that, during code generation in the code generation LLM processing unit 110, an intermediate language is generated and then a final program language is obtained from the intermediate language.

[0083] First, the specification input unit 101 of the design unit 2 acquires specifications for the semiconductor to be designed (step S31). The acquired specifications are, for example, a specification table provided by a semiconductor user company and are written in natural language. The specification data acquired by the specification input unit 101 is supplied as a prompt to the language LLM processing unit 150. The language LLM processing unit 150 uses a large-scale language model as a design AI model to generate specifications suitable for generating code for wafer and package design (step S32). When generating specifications suitable for code generation in step S32, the language LLM processing unit 150 acquires additional status for performing extension processing from the RAG processing unit 140 and executes generation processing (step S44).

[0084] The design unit 2 then acquires the specifications obtained by the generation process in step S22 and supplies the acquired specifications as a prompt to the code generation LLM processing unit 110 (step S33). The code generation LLM processing unit 110 generates code for wafer and package design using a large-scale language model as a design AI model (step S34). The code generated here is code in a programming language that serves as an intermediate language for wafer and package design. Furthermore, when generating code in step S34, the code generation LLM processing unit 110 also acquires an addition status for performing extension processing from the RAG processing unit 140 and executes code generation processing in step S44.

[0085] 7 of the first embodiment, the code generation process in step S44 is performed both in the on-premise environment by the code generation LLM processing unit 110 included in the design unit 2 and in the cloud environment by the cloud server 90. However, the design unit 2 performs the code generation in both the on-premise environment by the code generation LLM processing unit 110 included in the design unit 2 and in the cloud environment by the cloud server 90 only when reprocessing step S34, which will be described later. The design unit 2 may omit the generation in the cloud environment by the cloud server 90 when processing step S34 for the first time.

[0086] The design unit 2 acquires the intermediate language programming language obtained by the generation process in step S24 (step S35). After acquiring the intermediate language programming language in step S35, the C++ verification unit 120 and the RTL verification unit 130 of the design unit 2 verify the acquired programming language (step S36). After completing the verification in step S36, the design unit 2 determines whether the verification result is OK (step S37).

[0087] If it is determined in step S37 that the programming language is not appropriate (No in step S37), the user of the design support system 10 creates an additional prompt to be instructed to the language LLM processing unit 150 (step S38a).The user of the design support system 10 also creates an additional prompt to be instructed to the code generation LLM processing unit 110 (step S38b).

[0088] Each of the generated additional prompts is input to the language LLM processing unit 150 or the code generation LLM processing unit 110, where specification generation in step S32 or code generation in step S34 is performed. The generation of these additional prompts may be performed by a user after viewing the verification results, or automatically by the design unit 2. Furthermore, only one of the generation of the additional prompt for the language LLM processing unit 150 in step S38a and the generation of the additional prompt for the code generation LLM processing unit 110 in step S38b may be performed.

[0089] If it is determined in step S37 that the programming language is appropriate (Yes in step S37), the design unit 2 inputs the intermediate programming language acquired in step S35 to the code generation LLM processing unit 110. This causes the code generation LLM processing unit 110 to generate code as a programming language for wafer and package manufacturing (re-executing step S34). Furthermore, the design unit 2 acquires the generated programming language (step S39).

[0090] When the programming language for manufacturing is acquired by re-executing step S34, the C++ verification unit 120 and the RTL verification unit 130 of the design unit 2 verify the acquired programming language (step S40). When the verification in step S40 is completed, the design unit 2 determines whether the verification result is OK (step S41).

[0091] If the verification in step S41 determines that the programming language is not appropriate (No in step S41), the user of the design support system 10 performs a process of creating an additional prompt to instruct the code generation LLM processing unit 110 (step S42). Then, the code generation LLM processing unit 110 adds the prompt obtained in step S42 and performs a process of generating code again as a programming language for manufacturing wafers and packages.

[0092] Furthermore, if the verification in step S41 determines that the programming language is appropriate (Yes in step S41), the design unit 2 executes processing such as high-level synthesis (step S43) and terminates the processing of obtaining the programming language.

[0093] [Processing Configuration of Code Generated by Code Generating LLM Processing Unit] Fig. 11 shows a processing configuration for obtaining design data based on code generated by the code generating LLM processing unit 110. The configuration shown in Fig. 11 corresponds to the configuration for performing, for example, the processing in step S20 of the flowchart in Fig. 9 and the processing in step S43 of the flowchart in Fig. 10.

[0094] 8, the code generated by the code generation LLM processing unit 110 is supplied to an EDA (Electronic Design Automation) tool 5. The EDA tool 5 is a tool that supports circuit design for semiconductors, etc. Note that the use of an EDA tool by the design support system of this embodiment is just one example, and other circuit support design tools may also be used.

[0095] The EDA tool 5 includes a high-level synthesis unit 51, an RTL netlist processing unit 52, and a placement and routing unit 53. Design data obtained by the EDA tool 5 is output from a design data output unit 54. The high-level synthesis unit 51 receives as input code in C++ or other language generated by the code generation LLM processing unit 110, and generates RTL level data, which is semiconductor circuit data. The circuit data generated by the high-level synthesis unit 51 is supplied to the RTL netlist processing unit 52.

[0096] The RTL netlist processing unit 52 generates a netlist describing the wiring of each element from semiconductor circuit data (RTL level data). The netlist generated by the RTL netlist processing unit 52 is supplied to a placement and routing unit 53. The placement and routing unit 53 executes a process of placing the wiring and elements indicated in the netlist generated by the RTL netlist processing unit 52 on the device. The semiconductor placement and routing data obtained by the placement and routing unit 53 is supplied to a design data output unit 54.

[0097] The design data output unit 54 outputs placement and routing data, which is semiconductor design data obtained by the placement and routing unit 53. As described above, according to this embodiment, the EDA tool 5 can generate semiconductor design data based on the code generated by the code generation LLM processing unit 110. Note that the EDA tool 5 shown in Fig. 11 may also perform similar processing on the code generated by the code generation LLM processing unit 110 shown in Fig. 5 to obtain semiconductor design data.

[0098] As explained above, in this embodiment, as in the first embodiment, by linking and executing design code generation in an on-premise environment prepared by the semiconductor design company and design code generation in a cloud environment using an external server, it becomes possible to design an appropriate semiconductor in a short amount of time.

[0099] In this embodiment, specifications suitable for code generation are generated by the language LLM processing unit 150 from specifications such as a specification sheet provided by a semiconductor user company, and the generated specifications are then supplied to the code generation LLM processing unit 110, which generates a programming language for semiconductor manufacturing. Therefore, according to this embodiment, code generation by the code generation LLM processing unit 110 is performed with appropriate prompts, enabling appropriate code generation in a shorter time. Furthermore, according to this embodiment, semiconductor circuit design data can be obtained based on the generated code, as shown in FIG. 11 , contributing to appropriate semiconductor design in a shorter time.

[0100] Furthermore, according to this embodiment, as shown in the flowchart of Figure 10, the code generation LLM processing unit 110 first generates an intermediate language, and then the final program language is obtained from that intermediate language, making it possible to verify whether there are any errors at the intermediate language stage. Therefore, according to this embodiment, there is a high possibility that the corrections required will be smaller than correcting the final program language, and the time required for designing wafers and packages can be shortened.

[0101] [Specific Example of Processing in the Language LLM Processing Unit] Next, a specific example will be described in which the language LLM processing unit 150 generates a natural language with specifications that match the code generation from data such as a specification table. The language shown here is an example of a language that is unrelated to code generation for a programming language for semiconductor manufacturing. However, the principle of generating specifications that match the code generation is the same for code generation for a programming language for semiconductor manufacturing.

[0102] For example, the specification to be input to the linguistic LLM processing unit 150 is the following natural language sentence: Input specification: Please create a specification for the problem of using a Naive Bayes learner to predict whether approximately 100 different animals are classified as "mammals," "birds," "fish," "reptiles," "amphibians," "insects," or "invertebrates" given 16 attributes of the animals.

[0103] In this case, the specifications that match the code generated by the language LLM processing unit 150 are as follows: Output specifications: 1. Problem definition: This learner classifies over 100 types of animals into seven categories ("Mammals," "Crows," "Fish," "Reptiles," "Amphibians," "Insects," and "Invertebrates"). 2. Model: This learner uses a Naive Bayes learner and fold-wise cross-validation to evaluate accuracy. 3. Data: The dataset contains 16 attributes for each animal (e.g., body temperature, breathing pattern, skin type, etc.). The data is labeled, and each animal must already be classified into one of the aforementioned categories. 4. Feature extraction: The 16 attributes become features for the model. This learner performs attribute engineering (e.g., combining or transforming some attributes) as needed. 5. Training: This learner divides the dataset into training data and test data, and uses the training data to train a Naive Bayes learner. During this learning process, the learner determines the probability of each animal classification occurring based on the given attributes. 6. Testing: After learning is complete, the learner verifies the model's predictive accuracy using unknown data (test data). 7. Evaluation: To evaluate the model's performance, the learner uses statistical indicators such as confusion matrix, accuracy, precision, recall, and F-measure. This allows the linguistic LLM processing unit 150 to evaluate how accurately each classification is predicted. 8. Optimization: If the model's accuracy is insufficient, feature engineering and hyperparameter adjustment are performed to improve the model. 9. Prediction: When the user inputs new animal attributes, the learner uses the trained model to predict which classification those animals belong to and outputs the results.

[0104] As shown in this specific example, the language LLM processing unit 150 generates a detailed analysis of the input specifications by dividing them into categories such as problem definition, model, data, feature extraction, learning, testing, optimization, and prediction. If the design AI model provided to the language LLM processing unit 150 is appropriate, the language LLM processing unit 150 can generate specifications with optimal categories for obtaining a programming language for wafer and package manufacturing. In particular, if the specifications are divided into categories as described above, the code generation LLM processing unit 110 can easily generate code in a hierarchical structure, enabling optimal code generation.

[0105] [Example of Code and Operation Generated by Code LLM Processing Unit] Fig. 12 shows an example of code generated by the code generation LLM processing unit 110. As shown in Fig. 12, the code generation LLM processing unit 110 generates a predetermined programming language such as C++, and the generated programming language can be supplied as is to the wafer process unit 3 or packaging unit 4 shown in Fig. 3 to instruct manufacturing.

[0106] 13 shows an example of output of how the code generation LLM processing unit 110 operates based on the design AI model. That is, the example in FIG. 13 shows operations such as implementing a naive Bayes learner, reading data and dividing it into training and test sets, training the model, evaluating accuracy on the test set, and performing predictions on new input data. This output of the operating status is referenced, for example, during the process of creating an additional prompt, allowing the user of the design support system 10 to input an appropriate additional prompt.

[0107] 14 shows a specific example of an additional prompt generated in steps S28a and S28b of FIG. 9 and steps S38a and S38b of FIG. 10. For example, as shown in FIG. 14, the linguistic LLM processing unit 150 may input, as an additional prompt, sentences such as, "Could you please explain the detailed code for the steps of training the model with the training data?" or "More detailed code for implementing training of the Naive Bayes model with the training data is as follows..." In this manner, this embodiment allows instructions to inquire about inappropriate or omitted portions of the code generated by the code-generating LLM processing unit 110.

[0108] While the above-described embodiments have been described with respect to the process of generating a programming language made up of codes for designing both the wafer process and the packaging process, the design support system of the present invention may be configured to perform a process of generating a programming language made up of codes for designing either the wafer process or the packaging process.

[0109] In addition, in each of the above-described embodiments, the design unit 2 in the design support system 10 shown in Fig. 3 is equipped with a code generation LLM processing unit 110, a language LLM processing unit 150, etc. Alternatively, the design support system 10 may be configured by installing a program as a design support method in an existing computer that designs the wafer process and the packaging process, the program executing the processes shown in the flowcharts of Figs. 6 and 7 in the first embodiment, or the processing procedures shown in the flowcharts of Figs. 8, 9, and 10 in the second embodiment. In this case, the program can be installed in the computer via various recording media.

[0110] DESCRIPTION OF SYMBOLS 1...Supervising device, 2...Designing section, 3...Wafer process section, 4...Packaging section, 10...Design support system, 50...Wafer process information collecting section, 51...Data acquiring section, 52...Feedback section, 53...Wafer process database, 60...Packaging process information collecting section, 61...Data acquiring section, 62...Feedback section, 63...Packaging process database, 70...Design process learning section, 72...Design learning section, 73...Isolation section, 90...Cloud server, 101...Specification input section, 110...Code generation LLM processing section, 111...Transmitting / receiving section, 112...Additional prompt creating section, 120...Verification section, 130...RTL verification section, 140...RAG processing section, 150...Language LLM processing section

Claims

1. A design support system for designing either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from the wafers, comprising: a specification input unit for acquiring specifications for the wafer and / or the package; a code-generation language model processing unit for generating code required for designing the wafer and / or the package through natural language processing using a language model based on the specifications input to the specification input unit; a transceiver unit for transmitting confidential data-excluded training data, which is training data used in the natural language processing in the code-generation language model processing unit, with data that needs to be kept confidential removed, and the input and output of the code-generation language model processing unit to an external server that performs natural language processing, and receiving the results of the natural language processing at the server; and a verification unit for verifying the code obtained by the transceiver unit as a result of the natural language processing at the server, wherein the design support system outputs the verified code as design data for the wafer and / or the package if the verification unit determines that the verified code is appropriate.

2. The design support system according to claim 1, further comprising a language model processing unit for language generation that converts the specifications input to the specification input unit into specifications suitable for code generation through natural language processing using a language model, and supplies the specifications obtained by the language model processing unit for language generation to the language model processing unit for code generation.

3. The design support system according to claim 2, further comprising a search expansion generation unit, which refers to external information searched by said search expansion generation unit when performing natural language processing in said code generation language model processing unit and natural language processing in said language generation language model processing unit.

4. The design support system according to claim 2, further comprising an additional prompt creation unit, wherein if the code is found to be inappropriate by the verification unit, the additional prompt creation unit creates an additional prompt related to the inappropriate code, and supplies the created additional prompt to the code generation language model processing unit and / or the language generation language model processing unit, thereby generating code and / or specifications through natural language processing using a language model.

5. A design support system as described in claim 2, wherein the code generation language model processing unit generates code in an intermediate language, and when the verification unit verifies that the generated intermediate language code is appropriate, the code generation language model processing unit generates code necessary for designing the wafer and / or the package.

6. A design support method for designing either or both of a wafer process for manufacturing wafers and a packaging process for manufacturing packages from the wafers by computational processing using a computer, the computational processing executed by the computer including: a specification input process for acquiring specifications for the wafer and / or the package; a code generation language model process for generating code required for designing the wafer and / or the package by natural language processing using a language model based on the specifications input by the specification input process; a transmission and reception process for transmitting confidential data-excluded training data, which is training data used in the natural language processing by the code generation language model process that has excluded data that needs to be kept confidential, and the input and output used in the code generation language model processing to an external server that performs natural language processing, and receiving the natural language processing results from the server; and a verification process for verifying the code obtained by the transmission and reception process as the result of the natural language processing by the server, wherein the verified code is output as design data for the wafer and / or the package if it is determined to be appropriate by the verification process.

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