Counter circuit, a / d converter, and imaging device

Abstract

The present invention enables acceleration of count operation while suppressing an increase in circuit scale.　This counter circuit comprises: a main counting unit that performs counting on the basis of a first input; a sub-counting unit that is provided corresponding to the main counting unit and that performs counting on the basis of the time difference between the first input and a second input; and a control unit that controls the count timing of the sub-counting unit on the basis of the first input and the second input. The main counting unit may count clock pulses until an inversion timing of the first input is detected. The sub-counting unit may count clock pulses until an inversion timing of the second input is detected after the inversion timing of the first input is detected.

Description

Counter circuit, AD converter and imaging device

[0001] The present technology relates to a counter circuit, an AD converter, and an imaging device. More specifically, the present technology relates to a counter circuit, an AD converter, and an imaging device that support multiple inputs.

[0002] There is a technology that realizes high-speed data readout by using multiple AD converters for each output line to which pixels are connected for each column of an image sensor. For example, there is disclosed a technology that includes a selection unit that selects the number of AD conversion units that output pixel signals for each pixel, and a control unit that controls the selection unit to select the number of AD conversion units according to a request (see, for example, Patent Document 1).

[0003] JP 2013-55589 A

[0004] However, in the above-mentioned conventional technology, if a plurality of AD conversion units are provided for each column in order to increase the frame rate, there is a risk that this will lead to an increase in the circuit area.

[0005] This technology was developed in light of these circumstances, and aims to enable faster counting operations while suppressing increases in circuit size.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a counter circuit including: a main count unit that counts based on a first input; a sub-count unit that is provided corresponding to the main count unit and counts based on a time difference between the first input and a second input; and a control unit that controls the count timing of the sub-count unit based on the first input and the second input. This provides the effect of realizing counting of each of the two inputs while reducing the circuit size of the sub-count unit compared to the circuit size of the main count unit.

[0007] In addition, in the first aspect, the main count unit may count clock pulses until an inversion timing of the first input is detected, and the sub count unit may count the clock pulses from the inversion timing of the first input to the inversion timing of the second input, thereby achieving a count according to the time difference between the first input and the second input following the count according to the first input.

[0008] In the first aspect, the first input may be an output of a first comparator, and the second input may be an output of a second comparator, thereby achieving a count according to the first input and a count according to the time difference between the first input and the second input based on the comparison results of the first comparator and the second comparator.

[0009] In the first aspect, the first comparator output and the second comparator output may be a comparison result between a signal voltage and a reference voltage, thereby providing an effect that the first comparator output and the second comparator output are generated based on the signal level.

[0010] In the first aspect, the signal voltage may be a pixel signal read out from the same pixel, thereby providing an effect of multiplexing AD conversion of the pixel signal based on a count corresponding to the first input and a count corresponding to the time difference between the first input and the second input.

[0011] In addition, in the first aspect, the main count unit may include a main counter that generates the clock pulses and a main latch that counts clock pulses of the main counter until an inversion timing of the first input is detected and latches a count value of the clock pulses, and the sub count unit may include a sub counter that starts generating the clock pulses after an inversion timing of the first input is detected and a sub latch that counts clock pulses of the sub counter until an inversion timing of the second input is detected and latches a count value of the clock pulses. This brings about the effect that counting according to the first input is performed based on the inversion timing of the first input, and counting according to the time difference between the first input and the second input is performed based on the inversion timing of each of the first input and the second input.

[0012] In the first aspect, the main counter and the sub-counter may each be a Gray code counter, and the main latch and the sub-latch may each be a Gray code latch, thereby improving the counting accuracy according to the first input and the counting accuracy according to the time difference between the first input and the second input.

[0013] In addition, in the first aspect, the clock generator may include a main converter that converts the Gray code latched in the main latch into a binary code, a sub-converter that converts the Gray code latched in the sub-latch into a binary code, and an adder that adds the binary code converted by the main converter and the binary code converted by the sub-converter. This provides the effect of reducing the circuit size of the adder while improving the counting accuracy according to the first input and the counting accuracy according to the time difference between the first input and the second input.

[0014] A second aspect of the present invention is an AD converter including: a first comparator that compares a first input with a second input; a second comparator that compares the first input with the second input; and a counter circuit that performs counting based on the comparison results of the first comparator and the first comparator, wherein the counter circuit includes: a main count unit that performs counting based on the output of the first comparator; a sub-count unit that performs counting based on the output of the first comparator and the output of the second comparator; and a control unit that controls the count timing of the sub-count unit based on the output of the first comparator and the output of the second comparator. This provides the effect of realizing AD conversion of each of the two inputs while suppressing an increase in the circuit size of the AD converter.

[0015] In a second aspect, the main count unit may count clock pulses until the output of the first comparator is inverted, and the sub count unit may count the clock pulses from when the output of the first comparator is inverted until the output of the second comparator is inverted. This brings about an effect that AD conversion according to a time difference between the first input and the second input is realized following AD conversion according to a first input.

[0016] In a second aspect, the main count unit may include a main counter that generates the clock pulses and a main latch that counts clock pulses of the main counter until the output of the first comparator is inverted and latches the count value of the clock pulses, and the sub count unit may include a sub counter that starts generating the clock pulses after the output of the first comparator is inverted and a sub latch that counts clock pulses of the sub counter until the output of the second comparator is inverted and latches the count value of the clock pulses. This provides the effect of realizing AD conversion according to a first input and AD conversion according to a time difference between the first input and the second input based on comparison results of the first comparator and the second comparator.

[0017] According to a third aspect, there is provided an imaging device including: a pixel array unit in which pixels are arranged in a matrix in row and column directions; and a column ADC unit that performs analog-to-digital (ADC) conversion on pixel signals output from the pixels for each column, the column ADC unit including a first comparator that compares the pixel signals with a reference signal for each column; a second comparator that compares the pixel signals with the reference signal for each column; and a counter circuit that performs counting based on comparison results of the first comparator and the first comparator, the counter circuit including a main count unit that performs counting based on an output of the first comparator, a sub-count unit that counts based on the outputs of the first comparator and the second comparator, and a control unit that controls count timing of the sub-count unit based on the outputs of the first comparator and the second comparator. This provides an effect of realizing low noise in pixel signals while suppressing an increase in the circuit size of the imaging device.

[0018] In addition, in a third aspect, the main count unit may count clock pulses until the output of the first comparator is inverted, and the sub count unit may count the clock pulses from when the output of the first comparator is inverted until the output of the second comparator is inverted. This brings about an effect that, following AD conversion of a pixel signal according to the output of the first comparator, AD conversion of a pixel signal according to a time difference between the output of the first comparator and the output of the second comparator is realized.

[0019] In a third aspect, the main count unit may include a main counter that generates the clock pulses and a main latch that counts clock pulses of the main counter until the output of the first comparator is inverted and latches a count value of the clock pulses, and the sub count unit may include a sub counter that starts generating the clock pulses after the output of the first comparator is inverted and a sub latch that counts clock pulses of the sub counter until the output of the second comparator is inverted and latches a count value of the clock pulses. This brings about an effect that, based on the comparison results of the first comparator and the second comparator, AD conversion of the pixel signal corresponding to the output of the first comparator and AD conversion of the pixel signal corresponding to the time difference between the output of the first comparator and the output of the second comparator are realized.

[0020] In the third aspect, the main counter and the sub-counter may each be a Gray code counter, and the main latch and the sub-latch may each be a Gray code latch. This brings about an effect of improving the AD conversion accuracy of the pixel signal corresponding to the output of the first comparator and the AD conversion accuracy of the pixel signal corresponding to the time difference between the output of the first comparator and the output of the second comparator.

[0021] In addition, in a third aspect, the pixel shift register may include a main converter that converts the Gray code latched in the main latch into a binary code, a sub-converter that converts the Gray code latched in the sub-latch into a binary code, and an adder that adds the binary code converted by the main converter and the binary code converted by the sub-converter. This provides the effect of reducing the circuit size of the adder while improving the AD conversion accuracy of the pixel signal corresponding to the output of the first comparator and the AD conversion accuracy of the pixel signal corresponding to the time difference between the output of the first comparator and the output of the second comparator.

[0022] In addition, in a third aspect, the image pickup device may further include a bit shifter that shifts the binary code converted by the main converter by one bit, a temporary latch that temporarily latches an output of the bit shifter and returns the binary code to the adder, and an IF (Interface) latch that latches a result of correlated double sampling (CDS) of a P-phase level and a D-phase level of the pixel signal. This brings about an effect that CDS processing of pixel signals that have been multiplexed by AD conversion is realized while suppressing an increase in the circuit size of the image pickup device.

[0023] In the third aspect, the pixel signals may be pixel signals read out from the same pixel, thereby suppressing an increase in the circuit scale of the imaging device and achieving the effect of multiplexing AD conversion of pixel signals read out from the same pixel.

[0024] In a third aspect, the pixel may include a phase-difference pixel, and the first comparator and the second comparator may be exclusively assigned to a right-side phase-difference pixel and a left-side phase-difference pixel, respectively. This provides an effect of simultaneously generating phase-difference outputs and average outputs of the right-side phase-difference pixel and the left-side phase-difference pixel while suppressing an increase in circuit size of the imaging device.

[0025] In a third aspect, the column ADC unit may simultaneously generate an average output and a differential output from the right phase-difference pixel and the left phase-difference pixel, thereby suppressing an increase in the circuit scale of the imaging device and increasing the speed of reading out the phase-difference data and the imaging data.

[0026] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a block diagram showing an example of a schematic configuration of a counter circuit according to the first embodiment. FIG. 5 is a diagram showing waveforms of each unit when a pixel signal is read out according to the first embodiment. FIG. 6 is a diagram showing waveforms of each unit when the counter circuit according to the first embodiment is operating. FIG. 7 is a block diagram showing a specific example of the counter circuit according to the first embodiment. FIG. 8 is a block diagram showing a data flow in the counter circuit according to the first embodiment. FIG. 9 is a timing chart showing the operation of the counter circuit according to the first embodiment. FIG. 10 is a diagram showing waveforms of a reference signal during AD conversion according to the second embodiment. FIG. 11 is a plan view showing an example of the layout of a phase difference pixel according to a third embodiment. FIG. 12 is a block diagram showing an example of the schematic configuration of a counter circuit according to the third embodiment. FIG. 13 is a diagram showing waveforms of each unit when the counter circuit according to the third embodiment is operating. FIG. 14 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to a fourth embodiment. FIG. 15 is a block diagram showing an example of the schematic configuration of a vehicle control system. FIG. 16 is an explanatory diagram showing an example of the installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a counter circuit is provided with a main count unit that counts based on a first input and a sub-count unit that counts based on the time difference between the first input and a second input) 2. Second embodiment (an example in which a counter circuit provided with a main count unit that counts based on a first input and a sub-count unit that counts based on the time difference between the first input and a second input is applied to multiplexed 4AD drive) 3. Third embodiment (an example in which a counter circuit provided with a main count unit that counts based on a first input and a sub-count unit that counts based on the time difference between the first input and a second input is applied to readout from phase difference pixels) 4. Fourth embodiment (an example in which pixel array units are stacked) 5. Application to a moving body

[0028] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0029] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Single-slope AD conversion can be used to digitize the electrical signal. In this case, the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS (Dynamic Differential Sampling) readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a lateral overflow integration capacitor (LOFIC) image sensor.

[0032] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0038] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0039] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0040] The pixel array unit 111 includes a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX for each row when reading out a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read out from the pixels PX to the column signal processing unit 114 for each column.

[0041] Each pixel PX may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixel PX may also include an image plane phase difference pixel. Each pixel PX may support rolling shutter readout or global shutter readout. The pixels PX may also form a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0042] The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out signals from each pixel PX, the vertical scanning circuit 112 can drive each pixel PX row by row via a horizontal drive line HSL.

[0043] The column readout circuit 113 can form a source follower with each pixel PX when reading out a signal from the pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0044] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PX. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output an imaging signal Gout. The imaging signal Gout may include not only imaging data but also phase difference data. The column signal processing unit 114 includes a column ADC unit 114A.

[0045] The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion. At this time, the column ADC unit 114A can multiplex the AD conversion of the pixel signals. In multiplexing the AD conversion, the column ADC unit 114A may drive the counter circuit used for the single-slope AD conversion in a multiplexed 2AD manner or in a multiplexed 4AD manner.

[0046] The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0047] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0048] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0049] 1, a pixel PX includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS transistors.

[0050] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to a power supply voltage VDD via a reset transistor 123. The power supply voltage VDD is connected to a vertical signal line VSL via a series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0051] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in FIG.

[0052] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0053] 4 is a block diagram showing a schematic configuration example of a counter circuit according to the first embodiment. Note that, although the figure shows one column of vertical signal lines VSL, the present invention can be similarly applied to a case where there are more vertical signal lines.

[0054] In the figure, pixels PX are connected to a vertical signal line VSL. At this time, the amplification transistor 124 of each pixel PX is connected to the vertical signal line VSL via a selection transistor 125.

[0055] The column readout circuit 113 includes a current source LM. A current source LM is provided for each column. Each current source LM is connected to a vertical signal line VSL. During signal readout, each current source LM can form a source follower with each pixel PX via the vertical signal line VSL. Each current source LM may be a MOS transistor.

[0056] The column ADC unit 114A includes comparators CP1 and CP2 and a counter circuit CN for each column. Each comparator CP1 and CP2 compares a pixel signal transmitted via a vertical signal line VSL with a reference signal REF. The reference signal REF can be generated based on DA conversion of digital data.

[0057] An auto-zero signal AZ is input to each comparator CP1 and CP2. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, a DC-blocking capacitor CA1 is connected to the non-inverting input terminal of the comparator CP1, and a DC-blocking capacitor CB1 is connected to the inverting input terminal. Furthermore, a DC-blocking capacitor CA2 is connected to the non-inverting input terminal of the comparator CP2, and a DC-blocking capacitor CB2 is connected to the inverting input terminal.

[0058] In the auto-zero operation, the charges stored in the DC blocking capacitors CA1 and CB1 are controlled so that the non-inverting input and the inverting input of the comparator CP1 are balanced, and in the auto-zero operation, the charges stored in the DC blocking capacitors CA2 and CB2 are controlled so that the non-inverting input and the inverting input of the comparator CP2 are balanced.

[0059] The counter circuit CN performs a counting operation for each column based on the period until the level of the pixel signal read out from the pixel PX matches the level of the ramp wave of the reference signal REF, and generates a digital value DA of the pixel signal read out from the pixel PX for each column.

[0060] At this time, the column ADC unit 114A can multiplex the comparison operation and count operation accompanying the AD conversion of the pixel signal read out from each pixel PX. Multiplexing the comparison operation allows the comparison operations of the comparators CP1 and CP2 to be parallelized. Multiplexing the count operation allows the counter circuit CN to perform counting based on the outputs CO1 and CO2 of the comparators CP1 and CP2 that have an earlier inversion timing, and counting based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2.

[0061] The counter circuit CN includes a main count unit MB, a sub-count unit SB, a control unit CT, a bit shifter BS, a temporary latch TL, and an IF (Interface) latch FL.

[0062] The main count unit MB counts based on the outputs CO1 and CO2 of the comparators CP1 and CP2, whichever has the earlier inversion timing. At this time, the main count unit MB can count clock pulses until the outputs CO1 and CO2 of the comparators CP1 and CP2, which has the earlier inversion timing, are inverted. The main count unit MB includes a main latch ML and a main counter MC.

[0063] The main counter MC generates clock pulses. At this time, the main counter MC can operate as a pulse generator. The main latch ML counts the clock pulses of the main counter MC until the outputs CO1 and CO2 of the comparators CP1 and CP2, whichever inverts first, are inverted, and latches the count value MO1 of the clock pulses.

[0064] The sub-counting unit SB counts based on the outputs CO1 and CO2 of the comparators CP1 and CP2. At this time, the sub-counting unit SB can count clock pulses from the time when the outputs CO1 and CO2 of the comparators CP1 and CP2, which have earlier inversion timing, are inverted until the time when the outputs CO1 and CO2 of the comparators CP1 and CP2, which have later inversion timing, are inverted. The sub-counting unit SB includes a sub-latch SL and a sub-counter SC.

[0065] The sub-counter SC starts generating clock pulses after the outputs CO1 and CO2 of the comparators CP1 and CP2, which have earlier inversion timing, are inverted. The sub-latch SL counts the clock pulses of the sub-counter SC until the outputs CO1 and CO2 of the comparators CP1 and CP2, which have later inversion timing, are inverted, and latches the count value MO2 of the clock pulses.

[0066] The main counter MC and the sub-counter SC may each be a Gray code counter, and the main latch ML and the sub-latch SL may each be a Gray code latch.

[0067] The control unit CT controls the count timing of the main count unit MB and the sub-count unit SB based on the outputs CO1 and CO2 of the comparators CP1 and CP2. At this time, the control unit CT monitors the inversion timing of each comparator CP1 and CP2. When the output CO1 or CO2 of the comparator CP1 or CP2 with the earlier inversion timing is inverted, the control unit CT causes the main latch ML to latch the count value MO1 of the clock pulses of the main counter MC at that time. Furthermore, when the output CO1 or CO2 of the comparator CP1 or CP2 with the earlier inversion timing is inverted, the control unit CT causes the sub-counter SC to start generating clock pulses. Furthermore, when the output CO1 or CO2 of the comparator CP1 or CP2 with the later inversion timing is inverted, the control unit CT causes the sub-latch SL to latch the count value MO2 of the clock pulses of the sub-counter SC at that time.

[0068] The bit shifter BS shifts the count value latched in the main latch ML. At this time, the bit shifter BS can double the count value latched in the main latch ML. The temporary latch TL temporarily latches the count value latched in the sub-latch SL and the output of the bit shifter BS. The temporary latch TL can be used for CDS between the P-phase level and D-phase level of the pixel signal. The IF latch FL latches the CDS result between the P-phase level and D-phase level of the pixel signal.

[0069] At this time, in each comparator CP1, CP2, during an AD conversion period provided in each horizontal scanning period, the pixel signal read out from each pixel PX is compared with the ramp wave included in the reference signal REF for each column. Then, based on the comparison results in each comparator CP1, CP2 during that AD conversion period, the pixel signal read out from each pixel PX is subjected to multiple AD conversion and CDS processing, and the resulting digital value DA is held in the counter circuit CN.

[0070] 5 is a diagram showing waveforms at various parts when pixel signals are read out according to the first embodiment, and shows an example of waveforms within a 1H period (one horizontal synchronization period).

[0071] In the figure, the reset signal RST rises (t1), turning on the reset transistor 123 and resetting the floating diffusion FD. Also, the selection signal SEL rises, turning on the selection transistor 125. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the power supply voltage VDD is applied to the gate of the amplification transistor 124.

[0072] Next, the reset signal RST falls (t2), turning off the reset transistor 123. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0073] Next, in each comparator CP1, CP2, the potential of the vertical signal line VSL corresponding to the P-phase level is compared in parallel with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of the vertical signal line VSL is output in parallel as the comparison result. At this time, the P-phase level read out from the pixel PX is AD-converted for each column based on the counting operation until the level of the reference signal REF matches the potential of the vertical signal line VSL. Here, the counter circuit CN performs counting based on the outputs CO1, CO2 of the comparators CP1, CP2 which have an earlier inversion timing, and counting based on the time difference between the outputs CO1, CO2 of the comparators CP1, CP2, thereby multiplexing the AD conversion of the P-phase level.

[0074] Next, when the transfer signal TGL rises (t3), the transfer transistor 122 is turned on and the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the cathode potential of the photodiode 121 is applied to the gate of the amplification transistor 124.

[0075] Next, when the transfer signal TGL falls (t4), the transfer transistor 122 is turned off. At this time, the potential of the vertical signal line VSL is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124.

[0076] Next, in each comparator CP1, CP2, the potential of the vertical signal line VSL corresponding to the D-phase level is compared in parallel with the reference signal REF, and the timing when the level of the reference signal REF matches the potential of the vertical signal line VSL is output in parallel as the comparison result. At this time, the D-phase level read out from the pixel PX is AD-converted for each column based on the counting operation until the level of the reference signal REF matches the potential of the vertical signal line VSL. Here, the counter circuit CN performs counting based on the outputs CO1, CO2 of the comparators CP1, CP2 which have an earlier inversion timing, and counting based on the time difference between the outputs CO1, CO2 of the comparators CP1, CP2, thereby multiplexing the AD conversion of the D-phase level.

[0077] 6 is a diagram showing waveforms of various parts during operation of the counter circuit according to the first embodiment. Note that while the diagram shows an example in which the inversion timing of comparator CP1 is earlier than the inversion timing of comparator CP2, the same applies to the case in which the inversion timing of comparator CP2 is earlier than the inversion timing of comparator CP1.

[0078] In the figure, a clock pulse CK1 is generated by a main counter MC, and the clock pulse CK1 is counted by a main latch ML. When the output CO1 of a comparator CP1 is inverted (t11), the count value MO1 of the clock pulse CK1 at that time is latched by the main latch ML.

[0079] When the output CO1 of the comparator CP1 is inverted (t11), the sub-counter SC starts generating clock pulses CK2, which are counted by the sub-latch SL. When the output CO2 of the comparator CP2 is inverted (t12), the count value MO2 of the clock pulses CK2 at that time is latched by the sub-latch SL.

[0080] For example, let us say that the number of counts counted based on the output CO1 of comparator CP1 is 100, the number of counts counted based on the output CO2 of comparator CP2 is 102, and the inversion timing of the output CO1 of comparator CP1 is earlier than the inversion timing of the output CO2 of comparator CP2. In this case, (number of counts counted based on the output CO1 of comparator CP1) x 2 + (difference between the number of counts counted based on the output CO1 of comparator CP1 and the number of counts counted based on the output CO2 of comparator CP2) = 100 x 2 + (102 - 100) = 202. Therefore, (number of counts counted based on the output CO1 of comparator CP1) + (number of counts counted based on the output CO2 of comparator CP2) = 100 + 102 = 202.

[0081] Regarding the 1-bit shift, the output of the main counter MC may be shifted by 1 bit and latched in the temporary latch TL. In this case, the bit shifter BS may be omitted.

[0082] 7 is a block diagram showing a specific example of the counter circuit according to the first embodiment, which illustrates a specific example of the counter circuit CN shown in FIG.

[0083] In the figure, the counter circuit CN includes a main Gray code counter MGC, a sub Gray code counter SGC, a main Gray code latch MGL, a sub Gray code latch SGL, a control unit CT, a bit shifter BS, a temporary latch TL, and an IF latch FL. The counter circuit CN further includes a main converter MCV, a sub converter SCV, and a full adder FA.

[0084] The main Gray code counter MGC generates a clock pulse CK1. The bit width of the main Gray code counter MGC can be set to, for example, 11 bits.

[0085] The main Gray code latch MGL counts the clock pulses CK1 of the main Gray code counter MGC until the outputs CO1 and CO2 of the comparators CP1 and CP2, whichever has the earlier inversion timing, are inverted, and latches the count value MO1 of the clock pulses CK1. The bit width of the main Gray code latch MGL can be set to, for example, 11 bits.

[0086] The sub-Gray code counter SGC starts generating a clock pulse CK2 after the outputs CO1 and CO2 of the comparators CP1 and CP2, whichever has the earlier inversion timing, are inverted. The bit width of the sub-Gray code counter SGC can be set to, for example, 2 bits.

[0087] The sub-Gray code latch SGL counts the clock pulses CK2 of the sub-Gray code counter SGC until the outputs CO1 and CO2 of the comparators CP1 and CP2, which have the later inversion timing, are inverted, and latches the count value MO2 of the clock pulses CK2. The bit width of the sub-Gray code latch SGL can be set to, for example, 2 bits.

[0088] When the outputs CO1, CO2 of the comparators CP1, CP2, which have earlier inversion timing, are inverted, the control unit CT causes the main Gray code latch MGL to latch the count value MO1 of the clock pulse CK1 of the main Gray code counter MGC at that time. Also, when the outputs CO1, CO2 of the comparators CP1, CP2, which have earlier inversion timing, are inverted, the control unit CT causes the sub-counter SC to start generating a clock pulse CK2. Furthermore, when the outputs CO1, CO2 of the comparators CP1, CP2, which have later inversion timing, are inverted, the control unit CT causes the sub-Gray code latch SGL to latch the count value MO2 of the clock pulse CK2 of the sub-Gray code counter SGC at that time.

[0089] The main converter MCV converts the Gray code latched in the main Gray code latch MGL into a binary code. The bit width of the main converter MCV can be set to, for example, 2 bits.

[0090] The sub-converter SCV converts the Gray code latched in the sub-Gray code latch SGL into a binary code. The bit width of the sub-converter SCV can be set to, for example, 2 bits.

[0091] The full adder FA adds the binary code converted by the main converter MCV and the binary code converted by the sub converter SCV. The full adder FA also performs subtraction between the P-phase level and the D-phase level of the pixel signal based on the binary code returned from the temporary latch TL. At this time, the full adder FA can repeat the addition or subtraction of binary codes for the number of data given in Gray code. The bit width of the full adder FA can be set to, for example, 2 bits.

[0092] Here, by performing counting based on the Gray code, the counting accuracy can be improved. Also, by converting the Gray code into a binary code and performing addition or subtraction, it is sufficient to provide a full adder FA for 2 bits, and the circuit scale of the full adder FA can be reduced.

[0093] The bit shifter BS shifts the count value MO1 latched in the main converter MCV by one bit. At this time, the bit shifter BS doubles the count value MO1 latched in the main converter MCV and outputs the doubled count value to the temporary latch TL.

[0094] The temporary latch TL temporarily latches the output of the bit shifter BS and returns the latched binary code to the full adder FA. The bit width of the temporary latch TL can be set to, for example, 11 bits.

[0095] The IF latch FL latches the CDS result of the P-phase level and D-phase level of the pixel signal based on the output of the bit shifter BS. The bit width of the IF latch FL can be set to, for example, 12 bits.

[0096] 8 is a block diagram showing the flow of data in the counter circuit according to the first embodiment. In the figure, the case where the inversion timing of the comparator CP1 is earlier than the inversion timing of the comparator CP2 is taken as an example, but the same applies to the case where the inversion timing of the comparator CP2 is earlier than the inversion timing of the comparator CP1.

[0097] In the figure, a clock pulse CK1 generated by the main Gray code counter MGC is output to the main Gray code latch MGL (K1).Then, the main Gray code latch MGL counts the clock pulses CK1 of the main Gray code counter MGC until the output CO1 of the comparator CP1 is inverted, and latches the count value MO1 of the clock pulses CK1.

[0098] When the output CO1 of the comparator CP1 is inverted, the sub-Gray code counter SGC starts generating a clock pulse CK2, which is output to the sub-Gray code latch SGL (K2).Then, the sub-Gray code latch SGL counts the clock pulse CK2 of the sub-Gray code counter SGC until the output CO2 of the comparator CP2 is inverted, and latches the count value MO2 of the clock pulse CK2.

[0099] When the count value MO1 corresponding to the P phase is latched by the main Gray code counter MGC, the main converter MCV converts the Gray code into a binary code and outputs it to the full adder FA, while the binary code latched in the temporary latch TL is returned to the full adder FA (RT).Then, in the full adder FA, the binary code converted by the main converter MCV and the binary code returned from the temporary latch TL are added together, and the result is latched in the temporary latch TL via the bit shifter BS (P1).

[0100] Furthermore, when the count value MO2 corresponding to the P phase is latched in the sub-Gray code latch SGL, the sub-converter SCV converts the Gray code to a binary code and outputs it to the full adder FA, while the binary code latched in the temporary latch TL is returned to the full adder FA (RT). Then, in the full adder FA, the binary code converted by the sub-converter SCV and the binary code returned from the temporary latch TL are added together, and the result is latched in the temporary latch TL via the bit shifter BS (P2). At this time, the P phase AD conversion result is latched in the temporary latch TL.

[0101] On the other hand, when the count value MO1 corresponding to the D phase is latched by the main Gray code counter MGC, the main converter MCV converts the Gray code into a binary code and outputs it to the full adder FA, while the binary code latched in the temporary latch TL is returned to the full adder FA (RT).Then, in the full adder FA, the binary code converted by the main converter MCV is subtracted from the binary code returned from the temporary latch TL, and the result is latched in the temporary latch TL via the bit shifter BS (D1).

[0102] When the count value MO2 corresponding to the D phase is latched by the sub-Gray code latch SGL, the sub-converter SCV converts the Gray code into a binary code and outputs it to the full adder FA, while the binary code latched in the temporary latch TL is returned to the full adder FA (RT).Then, in the full adder FA, the binary code converted by the sub-converter SCV and the binary code returned from the temporary latch TL are added together, and the result is latched in the temporary latch TL via the bit shifter BS (D2).

[0103] The full adder FA can repeat the addition or subtraction two bits at a time. At this time, the binary code returned from the temporary latch TL can use the lower two bits. When the addition or subtraction in the full adder FA is completed, the CDS data is latched in the IF latch FL via the bit shifter BS (D3).

[0104] 9 is a timing chart showing the operation of the counter circuit according to the first embodiment, which shows an example of a timing chart within a 1H period.

[0105] 1, the reference signal REF includes a ramp wave PRA that is compared with the P-phase level of the pixel signal, and a ramp wave DRA that is compared with the D-phase level of the pixel signal. The operation period of the counter circuit CN includes a P-phase count period AD1, a D-phase count period AD2, a P-phase reset period R1, a D-phase reset period R2, a P-phase preprocessing period E1, a D-phase preprocessing period E2, a P-phase conversion period MC1, a P-phase addition period ML1, a D-phase subtraction period MC2, a D-phase addition period ML2, a P-phase initialization period I1, and a D-phase initialization period I2 within a 1H period.

[0106] In addition, the processing during the current D-phase reset period R2, D-phase pre-processing period E2, D-phase subtraction period MC2, D-phase addition period ML2, and D-phase initialization period I2 is performed on the count value counted during the previous D-phase count period AD2.

[0107] During the P-phase reset period R1, the control unit CT, the main converter MCV, the sub-converter SCV, and the full adder FA are reset for the P-phase AD conversion.

[0108] During the P-phase preprocessing period E1, preprocessing is performed on the main converter MCV and the sub-converter SCV for P-phase AD conversion. At this time, the main converter MCV and the sub-converter SCV calculate a binary least significant bit (LSB).

[0109] During the P-phase conversion period MC1, for P-phase AD conversion, the Gray code latched in the main Gray code latch MGL is converted to a binary code by the main converter MCV, bit-shifted by the bit shifter BS, and then latched in the temporary latch TL.

[0110] During the P-phase addition period ML1, for P-phase AD conversion, the Gray code latched in the sub-Gray code latch SGL is converted into a binary code by the sub-converter SCV. The binary code converted by the sub-converter SCV and the binary code latched in the temporary latch TL are added by the full adder FA and then latched in the temporary latch TL. The binary code latched in the temporary latch TL can use the lower two bits.

[0111] During the P-phase initialization period I1, the main Gray code counter MGC, the sub Gray code counter SGC, the main Gray code latch MGL, and the sub Gray code latch SGL are reset for P-phase AD conversion. At this time, the count values ​​of the main Gray code counter MGC and the sub Gray code counter SGC and the latch data of the main Gray code latch MGL and the sub Gray code latch SGL are initialized.

[0112] During the P-phase count period AD1, for P-phase AD conversion, the main Gray code counter MGC generates a clock pulse CK1, and the count value MO1 of the clock pulse CK1 is latched by the main Gray code latch MGL. Also, the sub Gray code counter SGC generates a clock pulse CK2, and the count value MO2 of the clock pulse CK2 is latched by the sub Gray code latch SGL.

[0113] During the D-phase reset period R2, the control unit CT, main converter MCV, sub-converter SCV, and full adder FA are reset for the D-phase AD conversion.

[0114] During the D-phase preprocessing period E2, preprocessing is performed on the main converter MCV and the sub-converter SCV for the D-phase AD conversion. At this time, the binary LSB is calculated in the main converter MCV and the sub-converter SCV.

[0115] During the D-phase subtraction period MC2, for D-phase AD conversion, the Gray code latched in the main Gray code latch MGL is converted to a binary code by the main converter MCV, bit-shifted by the bit shifter BS, and input to the full adder FA. Then, the binary code latched in the temporary latch TL is subtracted from the binary code bit-shifted by the bit shifter BS by the full adder FA, and then latched in the temporary latch TL.

[0116] During the D-phase addition period ML2, for D-phase AD conversion, the Gray code latched in the sub-Gray code latch SGL is converted to a binary code by the sub-converter SCV. The binary code converted by the sub-converter SCV and the binary code latched in the temporary latch TL are added by the full adder FA and then latched in the IF latch FL. The binary code latched in the temporary latch TL can use the lower two bits.

[0117] During the D-phase initialization period I2, the main Gray code counter MGC, the sub Gray code counter SGC, the main Gray code latch MGL, and the sub Gray code latch SGL are reset for D-phase AD conversion. At this time, the count values ​​of the main Gray code counter MGC and the sub Gray code counter SGC and the latch data of the main Gray code latch MGL and the sub Gray code latch SGL are initialized.

[0118] During the D-phase count period AD2, for D-phase AD conversion, the main Gray code counter MGC generates a clock pulse CK1, and the count value MO1 of the clock pulse CK1 is latched by the main Gray code latch MGL. Also, the sub Gray code counter SGC generates a clock pulse CK2, and the count value MO2 of the clock pulse CK2 is latched by the sub Gray code latch SGL.

[0119] As described above, in the first embodiment, the counter circuit CN performs counting based on the outputs CO1 and CO2 of the comparators CP1 and CP2, whichever has the earlier inversion timing, and counting based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2. This allows the circuit size of the sub-counter unit SB to be reduced compared to the circuit size of the main count unit MB, while multiplexing the AD conversion of pixel signals read out from each pixel PX. This prevents an increase in the circuit size of the column ADC unit 114A and enables low-noise pixel signals read out from each pixel PX without causing white spots or an increase in frame rate.

[0120] 2. Second Embodiment In the first embodiment described above, a count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 with an earlier inversion timing and a count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to multiplexed 2AD drive. In this second embodiment, a count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 with an earlier inversion timing and a count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to multiplexed 4AD drive.

[0121] FIG. 10 is a diagram showing the waveform of a reference signal during AD conversion according to the second embodiment.

[0122] 9, in multiplexed 4AD driving, P-phase AD conversion periods PAD1 and PAD2 and D-phase AD conversion periods DAD1 and DAD2 are provided within a 1H period. At this time, the reference signal REF includes ramp waves PRA1 and PRA2 that are sequentially compared with the P-phase level of the pixel signal, and ramp waves DRA1 and DRA2 that are sequentially compared with the D-phase level of the pixel signal. In this multiplexed 4AD driving, each period in FIG. 9 can be repeated only twice.

[0123] In this way, in the second embodiment described above, the count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 with the earlier inversion timing and the count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to multiplexed 4AD drive. This makes it possible to suppress an increase in the circuit size of the column ADC unit 114A, suppress an increase in white spots and frame rate, and further reduce noise in the pixel signals read out from each pixel PX, even in multiplexed 4AD drive.

[0124] The counter circuit CN may be applied to multiple n AD driving (n is a multiple of 2) as well as the multiple 2 AD driving and multiple 4 AD driving described above.

[0125] 3. Third Embodiment In the first embodiment described above, the count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 having the earlier inversion timing and the count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to multiplexed 2AD drive. In this third embodiment, the count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 having the earlier inversion timing and the count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to readout from phase difference pixels.

[0126] FIG. 11 is a plan view illustrating an example of the layout of a phase difference pixel according to the third embodiment.

[0127] In the figure, pixels PX are arranged in the row and column directions in the pixel array section 111. In the figure, a Bayer array is used as an example of the arrangement of the pixels PX. In this case, of the 2×2 pixels PX, green pixels Pg are arranged diagonally, and one blue pixel Pb and one red pixel Pr are arranged.

[0128] Furthermore, in the pixel array unit 111, a pair of a right phase difference pixel PXR and a left phase difference pixel PXL are discretely arranged in a Bayer array as phase difference pixels. The phase difference pixels may be image plane phase difference pixels. The right phase difference pixel PXR and the left phase difference pixel PXL are arranged close to each other in the pixel array unit 111. One side of each of the right phase difference pixel PXR and the left phase difference pixel PXL is covered with light-shielding films Sy1 and Sy2, respectively. The light-shielding films Sy1 and Sy2 are arranged at positions shifted in opposite directions from each other.

[0129] The phase difference pixel may be of a 2PD type. In the 2PD type, a photodiode corresponding to one on-chip lens is divided into two to form a first divided pixel and a second divided pixel, and distance measurement is performed from a first received light image obtained from the first divided pixel and a second received light image obtained from the second divided pixel, and a pixel signal for one pixel can be generated by integrating the output of the first divided pixel and the output of the second divided pixel. As a result, the 2PD type can obtain phase difference information used for AF while obtaining image quality equivalent to that of an image sensor with the same number of pixels but without image-plane phase difference pixels.

[0130] 12 is a block diagram showing a schematic configuration example of a counter circuit according to the third embodiment. Although the diagram shows vertical signal lines VSL1 and VSL2 for two columns, the present invention can be similarly applied to a case where there are more vertical signal lines.

[0131] In the figure, this solid-state imaging device includes a column ADC unit 114A' instead of the column ADC unit 114A of the first embodiment described above. Furthermore, in this solid-state imaging device, right-side phase difference pixels PXR and left-side phase difference pixels PXL are arranged in some of the pixels PX of the pixel array unit 111 of the first embodiment described above. Other configurations of the solid-state imaging device of the third embodiment are similar to those of the solid-state imaging device of the first embodiment described above.

[0132] The right-side phase difference pixel PXR and the left-side phase difference pixel PXL are connected to the vertical signal lines VSL1 and VSL2, respectively. At this time, the amplification transistors 124 of the right-side phase difference pixel PXR and the left-side phase difference pixel PXL are connected to the vertical signal lines VSL1 and VSL2 via the selection transistors 125, respectively.

[0133] The column readout circuit 113 includes current sources LM1 and LM2. The current sources LM1 and LM2 are provided for each column. Each current source LM1 and LM2 is connected to a vertical signal line VSL1 or VSL2, respectively. During signal readout, each current source LM1 or LM2 can form a source follower with each pixel PX1 or PX2 via the vertical signal line VSL1 or VSL2, respectively.

[0134] The column ADC unit 114A' includes comparators CP1 and CP2 and a counter CN'. The comparators CP1 and CP2 are provided for each column. The right-side phase difference pixel PXR and the left-side phase difference pixel PXL are exclusively assigned to the comparators CP1 and CP2. At this time, the comparator CP1 compares the pixel signal read from the right-side phase difference pixel PXR with a reference signal REF. The comparator CM2 compares the pixel signal read from the left-side phase difference pixel PXL with the reference signal REF.

[0135] The counter circuit CN′ performs a counting operation based on a period until the levels of the pixel signals read out from the right-side phase difference pixel PXR and the left-side phase difference pixel PXL respectively match the level of the ramp wave of the reference signal REF, and simultaneously generates an average output DA1 and a difference output DA2 from the right-side phase difference pixel PXR and the left-side phase difference pixel PXL.

[0136] At this time, the counter circuit CN' can perform counting based on the outputs CO1 and CO2 of the comparators CP1 and CP2 which have an earlier inversion timing, and counting based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2.

[0137] The counter circuit CN' includes temporary latches TL1 and TL2 and IF latches FL1 and FL2 instead of the temporary latch TL and IF latch FL of the first embodiment. The other configurations of the counter circuit CN' are the same as those of the counter circuit CN of the first embodiment.

[0138] The temporary latch TL1 temporarily latches the count value latched in the sub-latch SL and the output of the bit shifter BS. The temporary latch TL2 temporarily latches the count value latched in the sub-latch SL. The IF latch FL1 latches an average output DA1 from the right phase difference pixel PXR and the left phase difference pixel PXL. The average output DA1 from the right phase difference pixel PXR and the left phase difference pixel PXL can be used as imaging data. The IF latch FL2 latches a differential output DA2 from the right phase difference pixel PXR and the left phase difference pixel PXL. The differential output DA2 from the right phase difference pixel PXR and the left phase difference pixel PXL can be used as phase difference data. The phase difference data can be used for autofocusing the imaging device.

[0139] FIG. 13 is a diagram showing waveforms at various parts during operation of the counter circuit according to the third embodiment.

[0140] In the diagram, in readout of the phase difference pixels, a P-phase AD conversion period PAD and a D-phase AD conversion period DAD are provided within a 1H period. At this time, the reference signal REF includes a ramp wave PRA that is compared with the P-phase level of the pixel signal and a ramp wave DRA that is compared with the D-phase level of the pixel signal. During the D-phase AD conversion period DAD, an average output DA1 and a differential output DA2 can be generated simultaneously from the right-side phase difference pixel PXR and the left-side phase difference pixel PXL.

[0141] In this way, in the third embodiment described above, a count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 with an earlier inversion timing and a count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to readout from the phase difference pixels. This makes it possible to simultaneously extract the average output DA1 and the difference output DA2 from the right phase difference pixel PXR and the left phase difference pixel PXL, thereby speeding up readout of phase difference data and imaging data.

[0142] In the above-described embodiment, an example was shown in which a counter circuit was applied to an AD converter of a solid-state imaging device. The counter circuit of the above-described embodiment may also be applied to electronic circuits other than AD converters and electronic devices other than solid-state imaging devices. For example, the counter circuit may be applied to electronic circuits such as microprocessors, memories, and communication interfaces, or to electronic devices such as smartphones, personal computers, and display devices. In this case, the counter circuit may include a main counting unit that performs counting based on a first input, a sub-counting unit that is provided corresponding to the main counting unit and performs counting based on a time difference between the first input and a second input, and a control unit that controls the count timing of the sub-counting unit based on the first input and the second input.

[0143] 4. Fourth Embodiment In the first embodiment described above, a count based on the outputs CO1 and CO2 of the comparators CP1 and CP2 with earlier inversion timing and a count based on the time difference between the outputs CO1 and CO2 of the comparators CP1 and CP2 are applied to multiplexed 2AD drive. In this fourth embodiment, semiconductor chips each having a pixel array section in which pixels are arranged in a matrix are stacked.

[0144] FIG. 14 is a perspective view showing an example of a stack of pixel array units according to the fourth embodiment.

[0145] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0146] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0147] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillation circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The column ADC 926 can be formed with a counter circuit according to any one of the first to third embodiments described above.

[0148] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0149] As described above, in the fourth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0150] 5. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0151] FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0152] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 15, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0153] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0154] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0155] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0156] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0157] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0159] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0160] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0161] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 15, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0162] FIG. 16 is a diagram showing an example of the installation position of the imaging unit 12031.

[0163] In FIG. 16, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0164] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0165] 16 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0166] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0167] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0168] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0169] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0170] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, each counter circuit of the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve the image quality of the image generated by the imaging unit 12031 while suppressing an increase in the circuit size of the imaging unit 12031.

[0171] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0172] The present technology may also be configured as follows: (1) A counter circuit including: a main count unit that counts based on a first input; a sub-count unit that is provided corresponding to the main count unit and counts based on a time difference between the first input and a second input; and a control unit that controls count timing of the sub-count unit based on the first input and the second input. (2) The counter circuit according to (1), wherein the main count unit counts clock pulses until an inversion timing of the first input is detected, and the sub-count unit counts the clock pulses from the inversion timing of the first input to the inversion timing of the second input. (3) The counter circuit according to (2), wherein the first input is a first comparator output and the second input is a second comparator output. (4) The counter circuit according to (3), wherein the first comparator output and the second comparator output are comparison results between a signal voltage and a reference voltage. (5) The counter circuit according to (4), wherein the signal voltage is a pixel signal read from the same pixel. (6) The counter circuit according to any one of (2) to (5), wherein the main count unit comprises: a main counter that generates the clock pulses; and a main latch that counts clock pulses of the main counter until an inversion timing of the first input is detected and latches the count value of the clock pulses, and the sub count unit comprises: a sub counter that starts generating the clock pulses after an inversion timing of the first input is detected, and a sub latch that counts clock pulses of the sub counter until an inversion timing of the second input is detected and latches the count value of the clock pulses. (7) The counter circuit according to (6), wherein the main counter and the sub counter are each a Gray code counter, and the main latch and the sub latch are each a Gray code latch.(8) The counter circuit according to (7), comprising: a main converter that converts the Gray code latched in the main latch into a binary code, a sub-converter that converts the Gray code latched in the sub-latch into a binary code, and an adder that adds the binary code converted by the main converter and the binary code converted by the sub-converter. (9) An AD converter comprising: a first comparator that compares a first input with a second input, a second comparator that compares the first input with the second input, and a counter circuit that counts based on the comparison results of the first comparator and the first comparator, wherein the counter circuit comprises: a main count unit that counts based on the output of the first comparator, a sub-count unit that counts based on the output of the first comparator and the output of the second comparator, and a control unit that controls the count timing of the sub-count unit based on the output of the first comparator and the output of the second comparator. (10) The AD converter according to (9), wherein the main count unit counts clock pulses until the output of the first comparator is inverted, and the sub-count unit counts the clock pulses from when the output of the first comparator is inverted until when the output of the second comparator is inverted. (11) The AD converter according to (10), wherein the main count unit comprises: a main counter that generates the clock pulses; and a main latch that counts clock pulses of the main counter until the output of the first comparator is inverted and latches the count value of the clock pulses, and the sub-counter comprises: a sub-counter that starts generating the clock pulses after the output of the first comparator is inverted, and a sub-latch that counts clock pulses of the sub-counter until the output of the second comparator is inverted and latches the count value of the clock pulses.(12) An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in row and column directions; and a column ADC section that performs A / D (Analog to Digital) conversion of pixel signals output from the pixels for each column, wherein the column ADC section comprises: a first comparator that compares the pixel signal with a reference signal for each column; a second comparator that compares the pixel signal with the reference signal for each column; and a counter circuit that performs counting based on the comparison results of the first comparator and the second comparator, wherein the counter circuit comprises: a main count section that performs counting based on the output of the first comparator; a sub-count section that counts based on the output of the first comparator and the output of the second comparator; and a control section that controls the count timing of the sub-count section based on the output of the first comparator and the output of the second comparator. (13) The imaging device according to (12), wherein the main count unit counts clock pulses until the output of the first comparator is inverted, and the sub-count unit counts the clock pulses from when the output of the first comparator is inverted until when the output of the second comparator is inverted. (14) The imaging device according to (13), wherein the main count unit comprises: a main counter that generates the clock pulses; and a main latch that counts clock pulses of the main counter until the output of the first comparator is inverted and latches the count value of the clock pulses, and the sub-counter comprises: a sub-counter that starts generating the clock pulses after the output of the first comparator is inverted, and a sub-latch that counts clock pulses of the sub-counter until the output of the second comparator is inverted and latches the count value of the clock pulses. (15) The imaging device according to (14), wherein the main counter and the sub-counter are each Gray code counters, and the main latch and the sub-latch are each Gray code latches.(16) The imaging device according to (15), comprising: a main converter that converts the Gray code latched in the main latch into a binary code; a sub-converter that converts the Gray code latched in the sub-latch into a binary code; and an adder that adds the binary code converted by the main converter and the binary code converted by the sub-converter. (17) The imaging device according to (16), comprising: a bit shifter that shifts the binary code converted by the main converter by one bit; a temporary latch that temporarily latches the output of the bit shifter and returns the binary code to the adder; and an IF (Interface) latch that latches a CDS (Correlated Double Sampling) result of the P-phase level and D-phase level of the pixel signal. (18) The imaging device according to any of (12) to (17), wherein the pixel signal is a pixel signal read out from the same pixel. (19) The imaging device according to any one of (12) to (17), wherein the pixel includes a phase difference pixel, and the first comparator and the second comparator are exclusively assigned to a right phase difference pixel and a left phase difference pixel. (20) The imaging device according to (19), wherein the column ADC unit simultaneously generates an average output and a difference output from the right phase difference pixel and the left phase difference pixel.

[0173] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 114A Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HSL Horizontal drive line VSL Vertical signal line PD Photodiode FD Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplifying transistor 125 Selection transistor LM Current source CP1, CP2 Comparator CN Counter circuit MB Main count unit SB Sub-count unit CT Control unit ML Main latch MC Main counter SL Sub-latch SC Sub-counter BS Bit shifter TL Temporary latch FL IF latch

Claims

1. A counter circuit comprising: a main count unit that counts based on a first input; a sub-count unit that is provided corresponding to the main count unit and counts based on the time difference between the first input and a second input; and a control unit that controls the count timing of the sub-count unit based on the first input and the second input.

2. The counter circuit according to claim 1, wherein the main counting unit counts clock pulses until an inversion timing of the first input is detected, and the sub-counting unit counts clock pulses from the inversion timing of the first input is detected until an inversion timing of the second input is detected.

3. The counter circuit of claim 2, wherein the first input is the output of a first comparator and the second input is the output of a second comparator.

4. The counter circuit according to claim 3, wherein the first comparator output and the second comparator output are the results of comparing a signal voltage with a reference voltage.

5. The counter circuit according to claim 4, wherein the signal voltage is a pixel signal read out from the same pixel.

6. The counter circuit according to claim 2, wherein the main counting unit comprises: a main counter that generates the clock pulse; and a main latch that counts clock pulses of the main counter until an inversion timing of the first input is detected and latches the count value of the clock pulses; and the sub-counting unit comprises: a sub-counter that starts generating the clock pulses after an inversion timing of the first input is detected; and a sub-latch that counts clock pulses of the sub-counter until an inversion timing of the second input is detected and latches the count value of the clock pulses.

7. The counter circuit according to claim 6, wherein the main counter and the sub-counter are each a Gray code counter, and the main latch and the sub-latch are each a Gray code latch.

8. The counter circuit of claim 7, comprising: a main converter that converts the Gray code latched in the main latch into a binary code; a sub-converter that converts the Gray code latched in the sub-latch into a binary code; and an adder that adds the binary code converted by the main converter and the binary code converted by the sub-converter.

9. An AD converter comprising: a first comparator that compares a first input with a second input; a second comparator that compares the first input with the second input; and a counter circuit that counts based on the comparison results of the first comparator and the first comparator, wherein the counter circuit comprises: a main count unit that counts based on the output of the first comparator; a sub-count unit that counts based on the output of the first comparator and the output of the second comparator; and a control unit that controls the count timing of the sub-count unit based on the output of the first comparator and the output of the second comparator.

10. The AD converter according to claim 9, wherein the main counting unit counts clock pulses until the output of the first comparator is inverted, and the sub-counting unit counts clock pulses from when the output of the first comparator is inverted until the output of the second comparator is inverted.

11. An AD converter as described in claim 10, wherein the main counting unit comprises: a main counter that generates the clock pulse; and a main latch that counts clock pulses of the main counter until the output of the first comparator is inverted and latches the count value of the clock pulses; and the sub-counting unit comprises: a sub-counter that starts generating the clock pulses after the output of the first comparator is inverted; and a sub-latch that counts clock pulses of the sub-counter until the output of the second comparator is inverted and latches the count value of the clock pulses.

12. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row and column directions; and a column ADC section that performs AD (Analog to Digital) conversion on a column-by-column basis for pixel signals output from the pixels, wherein the column ADC section comprises: a first comparator that compares the pixel signal with a reference signal on a column-by-column basis; a second comparator that compares the pixel signal with the reference signal on a column-by-column basis; and a counter circuit that performs counting based on the comparison results of the first comparator and the second comparator, wherein the counter circuit comprises: a main count section that counts based on the output of the first comparator; a sub-count section that counts based on the output of the first comparator and the output of the second comparator; and a control section that controls the count timing of the sub-count section based on the output of the first comparator and the output of the second comparator.

13. The imaging device according to claim 12, wherein the main counting unit counts clock pulses until the output of the first comparator is inverted, and the sub-counting unit counts clock pulses from when the output of the first comparator is inverted until the output of the second comparator is inverted.

14. The imaging device described in claim 13, wherein the main counting unit comprises: a main counter that generates the clock pulse; and a main latch that counts the clock pulses of the main counter until the output of the first comparator is inverted and latches the count value of the clock pulses; and the sub-counting unit comprises: a sub-counter that starts generating the clock pulses after the output of the first comparator is inverted; and a sub-latch that counts the clock pulses of the sub-counter until the output of the second comparator is inverted and latches the count value of the clock pulses.

15. The imaging device according to claim 14, wherein the main counter and the sub-counter are each a Gray code counter, and the main latch and the sub-latch are each a Gray code latch.

16. An imaging device as described in claim 15, comprising: a main converter that converts the Gray code latched in the main latch into a binary code; a sub-converter that converts the Gray code latched in the sub-latch into a binary code; and an adder that adds the binary code converted by the main converter and the binary code converted by the sub-converter.

17. The imaging device according to claim 16, further comprising: a bit shifter that shifts the binary code converted by the main converter by one bit; a temporary latch that temporarily latches the output of the bit shifter and returns the binary code to the adder; and an IF (Interface) latch that latches the CDS (Correlated Double Sampling) result of the P-phase level and D-phase level of the pixel signal.

18. The imaging device according to claim 12, wherein the pixel signals are pixel signals read out from the same pixel.

19. The imaging device according to claim 12, wherein the pixels include phase difference pixels, and the first comparator and the second comparator are exclusively assigned to right phase difference pixels and left phase difference pixels.

20. The imaging device according to claim 19, wherein the column ADC unit simultaneously generates an average output and a differential output from the right phase difference pixel and the left phase difference pixel.

Images