Solid-state imaging device

Abstract

[Problem] To provide a solid-state imaging device in which an adverse effect on an image by a capacitor can be suppressed. A solid-state imaging device according to the present disclosure comprises a substrate including a photoelectric conversion unit and a charge storage unit, a charge transfer unit provided on the substrate, an insulating film provided on the substrate and the charge transfer unit, and a multilayer wiring structure provided in the insulating film, the multilayer wiring structure including a first capacitor provided in a first pixel of a plurality of pixels, and a shield layer provided between the first pixel and a second pixel of the plurality of pixels.

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] In order to improve the characteristics of a solid-state imaging device, a capacitor may be disposed within each pixel of the solid-state imaging device. An example of such a capacitor is a metal-insulator-metal (MIM) capacitor formed within a multilayer wiring structure of the solid-state imaging device. For example, when the solid-state imaging device is applied to a digital camera, disposing a capacitor within each pixel can expand the dynamic range of the solid-state imaging device.

[0003] JP 2023-016789 A JP 2023-122576 A

[0004] When multiple pixels of a solid-state imaging device are collectively driven by a horizontal drive line (VDD line), a high-intensity pixel receiving a signal may adversely affect a low-intensity pixel not receiving a signal via the drive line. This phenomenon occurs due to coupling between the capacitors in the high-intensity pixel and the low-intensity pixel. This results in horizontally extending bands appearing in the image output from the solid-state imaging device. It is desirable to prevent such bands from appearing in the image.

[0005] Therefore, the present disclosure provides a solid-state imaging device that can suppress the capacitor from adversely affecting an image.

[0006] A solid-state imaging device according to a first aspect of the present disclosure includes a substrate including a photoelectric conversion unit and a charge accumulation unit, a charge transfer unit provided on the substrate, an insulating film provided on the substrate and the charge transfer unit, and a multilayer wiring structure provided in the insulating film, the multilayer wiring structure including a first capacitor provided in a first pixel of a plurality of pixels, and a shield layer provided between the first pixel and a second pixel of the plurality of pixels. As a result, for example, by disposing the shield layer between the capacitor in the first pixel (first capacitor) and the capacitor in the second pixel, it is possible to prevent the capacitor in the first pixel (first capacitor) and the capacitor in the second pixel from adversely affecting an image.

[0007] In this first aspect, the first capacitor may include a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, which makes it possible to form the first capacitor by, for example, a semiconductor process technology.

[0008] In this first aspect, the shielding layer may be formed of one or more wiring layers and / or one or more via plug layers included in the multilayer wiring structure, thereby making it possible to form the shielding layer using, for example, the wiring layers and / or via plug layers that constitute the multilayer wiring structure.

[0009] In this first aspect, the shielding layer may include wiring extending between two or more pixels including the first pixel and two or more pixels including the second pixel, thereby making it possible to form the shielding layer using wiring extending linearly between a large number of pixels, for example.

[0010] In this first aspect, the shielding layer may further include a plurality of via plugs provided on the upper surface or the lower surface of the wiring, thereby making it possible to form the shielding layer by, for example, a large number of via plugs arranged on the upper surface or the lower surface of the wiring.

[0011] In addition, in this first aspect, the multilayer wiring structure may include, as the shield layer, a first shield layer provided between the first pixel and the second pixel and extending in a first direction, and the multilayer wiring structure may further include a second shield layer provided between the first pixel and a third pixel of the plurality of pixels and extending in a second direction different from the first direction. This makes it possible to provide shield layers on two or more side surfaces of the first pixel (e.g., a side surface of the first pixel facing the second pixel and a side surface of the first pixel facing the third pixel).

[0012] In addition, in this first aspect, the shield layer may include a lower wiring having an upper surface facing the lower surface of the first lower electrode, which makes it possible to dispose the shield layer below the first capacitor, for example.

[0013] In addition, in this first aspect, the shield layer may include an upper wiring having a lower surface facing the upper surface of the first upper electrode, which makes it possible to dispose the shield layer above the first capacitor, for example.

[0014] In this first aspect, the multilayer wiring structure may further include a second capacitor provided in the first pixel and electrically connected to the first capacitor, the first capacitor being supplied with a drive voltage and a signal charge, and the second capacitor being supplied with a ground voltage. This makes it possible to prevent the first capacitor from adversely affecting an image by using the second capacitor as a bypass capacitor, for example.

[0015] In this first aspect, the multilayer wiring structure may further include a switch provided in the first pixel and arranged in parallel with the first capacitor, thereby making it possible to, for example, reset the first capacitor with the switch, thereby preventing the first capacitor from adversely affecting an image.

[0016] A solid-state imaging device according to a second aspect of the present disclosure includes a substrate including a photoelectric conversion unit and a charge accumulation unit, a charge transfer unit provided on the substrate, an insulating film provided on the substrate and the charge transfer unit, and a multilayer wiring structure provided in the insulating film, the multilayer wiring structure including a first capacitor provided in a first pixel of a plurality of pixels and supplied with a drive voltage and a signal charge, and a second capacitor provided in the first pixel, electrically connected to the first capacitor, and supplied with a ground voltage. This makes it possible to prevent the first capacitor from adversely affecting an image by using the second capacitor as a bypass capacitor, for example.

[0017] In this second aspect, the first capacitor may include a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and the second capacitor may include a second lower electrode, a second dielectric layer provided on the second lower electrode, and a second upper electrode provided on the second dielectric layer, which makes it possible to form the first and second capacitors by, for example, semiconductor process technology.

[0018] In this second aspect, the first upper electrode of the first capacitor may be supplied with the drive voltage, and the first lower electrode of the first capacitor may be supplied with the signal charge, thereby making it possible to arrange a drive line at a position higher than the first capacitor, for example.

[0019] In this second aspect, the second upper electrode or the second lower electrode of the second capacitor may be supplied with the ground voltage, which allows the second capacitor to be used as a pass capacitor, for example.

[0020] In this second aspect, the second lower electrode of the second capacitor may be electrically connected to the first lower electrode of the first capacitor, or the second upper electrode of the second capacitor may be electrically connected to the first upper electrode of the first capacitor, thereby enabling the second capacitor to be used as a bypass capacitor for the first capacitor, for example.

[0021] In this second aspect, the multilayer wiring structure may further include a switch provided in the first pixel and arranged in parallel with the first capacitor, thereby making it possible to, for example, reset the first capacitor with the switch, thereby preventing the first capacitor from adversely affecting an image.

[0022] A solid-state imaging device according to a third aspect of the present disclosure includes a substrate including a photoelectric conversion unit and a charge accumulation unit, a charge transfer unit provided on the substrate, an insulating film provided on the substrate and the charge transfer unit, and a multilayer wiring structure provided in the insulating film, the multilayer wiring structure including a first capacitor provided in a first pixel among a plurality of pixels, and a switch provided in the first pixel and arranged in parallel with the first capacitor. This makes it possible, for example, to prevent the first capacitor from adversely affecting an image by resetting the first capacitor with the switch. This makes it possible, for example, to prevent the first capacitor from adversely affecting an image by resetting the first capacitor with the switch.

[0023] In the third aspect, the first capacitor may include a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, which makes it possible to form the first capacitor by, for example, semiconductor processing technology.

[0024] In the third aspect, the switch may be capable of electrically connecting the first lower electrode and the first upper electrode, thereby making it possible to short-circuit the first lower electrode and the first upper electrode by the switch, for example.

[0025] In the third aspect, the switch may be capable of switching between three values, thereby making it possible to supply a plurality of different voltages to the first capacitor, for example.

[0026] 14 is a block diagram showing the configuration of a solid-state imaging device of the first embodiment. FIG. 15 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment. FIG. 16 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. FIG. 17 is a plan view and a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. FIG. 18 is a plan view showing the structure of the solid-state imaging device of the first embodiment. FIG. 19 is a cross-sectional view showing the structure of a solid-state imaging device of a first modified example of the first embodiment. FIG. 19 is a plan view showing the structure of a solid-state imaging device of a second modified example of the first embodiment. FIG. 19 is a plan view and a cross-sectional view showing the structure of a solid-state imaging device of a third modified example of the first embodiment. FIG. 19 is a plan view and a cross-sectional view showing the structure of a solid-state imaging device of the second embodiment. FIG. 19 is a circuit diagram showing the configuration of a solid-state imaging device of the second embodiment and its modified examples. FIG. 19 is a block diagram showing an example of the configuration of an electronic device. FIG. 19 is a block diagram showing an example of the configuration of a mobile object control system. FIG. 19 is a plan view showing a specific example of the setting position of the imaging unit in FIG. 13. FIG. 19 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. FIG. 19 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0028] First Embodiment FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to a first embodiment.

[0029] The solid-state imaging device of this embodiment includes a pixel array 2 including a plurality of pixels 1, a control circuit 3, a vertical drive circuit 4, a plurality of column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, a plurality of vertical signal lines (VSL) 8, and a horizontal signal line (HSL) 9. The solid-state imaging device of this embodiment is, for example, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (CIS).

[0030] Each pixel 1 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. The pixel transistor may be, for example, a transfer transistor, a reset transistor, an amplification transistor, or a selection transistor. Each pixel transistor may be shared by several pixels 1. Each pixel 1 may further include a floating diffusion unit, a pixel memory, etc.

[0031] The pixel array 2 includes a plurality of pixels 1 arranged in a two-dimensional array. The pixel array 2 also includes an effective pixel region that receives light, performs photoelectric conversion, and outputs signal charges generated by the photoelectric conversion, and a black reference pixel region that outputs optical black, which serves as a reference for the black level. The black reference pixel region is generally arranged on the periphery of the effective pixel region.

[0032] The control circuit 3 generates various signals that serve as references for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, a master clock, etc. The signals generated by the control circuit 3 are, for example, clock signals and control signals, and are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0033] The vertical drive circuit 4 includes, for example, a shift register, and vertically scans each pixel 1 in the pixel array 2 row by row. The vertical drive circuit 4 further supplies a pixel signal based on the signal charge generated by each pixel 1 to a column signal processing circuit 5 through a vertical signal line 8.

[0034] The column signal processing circuit 5 is arranged, for example, for each column of pixels 1 in the pixel array 2, and performs signal processing for each column of signals output from one row of pixels 1 based on signals from the black reference pixel region. Examples of this signal processing include noise removal and signal amplification.

[0035] The horizontal drive circuit 6 includes, for example, a shift register, and supplies pixel signals from each column signal processing circuit 5 to a horizontal signal line 9 .

[0036] The output circuit 7 processes the signals supplied from each column signal processing circuit 5 through the horizontal signal line 9, and outputs the processed signals.

[0037] FIG. 2 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0038] Fig. 2 illustrates two pixels 1a and 1b included in the plurality of pixels 1. These pixels 1a and 1b are adjacent to each other in the horizontal direction of the pixel array 2. Fig. 2 illustrates an example in which pixel 1a is a high-illuminance pixel and pixel 1b is a low-illuminance pixel.

[0039] 2, each pixel 1 of this embodiment includes a photodiode PD, a first floating diffusion FD1, a second floating diffusion FD2, a third floating diffusion FD3, a capacitor MIM, a transfer transistor TG, a conversion efficiency switching transistor FDG, a capacitor control transistor FCG, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The photodiode PD, the first floating diffusion FD1, and the transfer transistor TG are examples of the photoelectric conversion unit, the charge accumulation unit, and the charge transfer unit, respectively, of the present disclosure.

[0040] 2 further shows a drive line FCVDD and a drive line VDDHPX. The drive line FCVDD supplies a predetermined drive voltage (hereinafter referred to as "drive voltage FCVDD"). The drive line VDDHPX supplies a predetermined drive voltage (hereinafter referred to as "drive voltage VDDHPX") different from the drive voltage FCVDD. FIG. 2 further shows a resistance R on the drive line FCVDD, which is a resistance R between the capacitor MIM in pixel 1a and the capacitor MIM in pixel 1b.

[0041] 2 further shows a vertical signal line VSL of pixel 1a and a vertical signal line VSL of pixel 1b, which correspond to vertical signal line 8 shown in FIG.

[0042] The photodiode PD performs photoelectric conversion of light incident on the pixel 1. The anode of the photodiode PD is electrically connected to a ground line that supplies a ground voltage, and the cathode of the photodiode PD is electrically connected to the transfer transistor TG.

[0043] The transfer transistor TG transfers charges generated by photoelectric conversion of the photodiode PD to the first floating diffusion FD1. One of the source and drain of the transfer transistor TG is electrically connected to the photodiode PD, and the other of the source and drain of the transfer transistor TG is electrically connected to the first floating diffusion FD1.

[0044] The first floating diffusion FD1 accumulates the charge transferred from the photodiode PD. The first floating diffusion FD1 is electrically connected to the transfer transistor TG, the conversion efficiency switching transistor FDG, and the amplification transistor AMP. The first floating diffusion FD1 can also accumulate the charge transferred from the second floating diffusion FD2.

[0045] The conversion efficiency switching transistor FDG functions as a switch for switching the conversion efficiency of photoelectric conversion by the photodiode PD. One of the source and drain of the conversion efficiency switching transistor FDG is electrically connected to the first floating diffusion portion FD1, and the other of the source and drain of the conversion efficiency switching transistor FDG is electrically connected to the second floating diffusion portion FD2. The conversion efficiency switching transistor FDG can transfer charges between the first floating diffusion portion FD1 and the second floating diffusion portion FD2.

[0046] The second floating diffusion FD2 accumulates the charges transferred from the first floating diffusion FD1. The second floating diffusion FD2 is electrically connected to the conversion efficiency switching transistor FDG and the capacitor control transistor FCG. The second floating diffusion FD2 can further accumulate the charges transferred from the third floating diffusion FD3.

[0047] The capacitor control transistor FCG functions as a switch that controls the capacitor MIM. One of the source and drain of the capacitor control transistor FCG is electrically connected to the second floating diffusion FD2, and the other of the source and drain of the capacitor control transistor FCG is electrically connected to the third floating diffusion FD3. The third floating diffusion FD3 can further store the charge discharged from the capacitor MIM.

[0048] The capacitor MIM has one electrode electrically connected to the third floating diffusion FD3 and the other electrode electrically connected to the drive line FCVDD, and can store the charge discharged from the third floating diffusion FD3 in the former electrode, or can discharge the charge accumulated in the former electrode to the third floating diffusion FD3.

[0049] The reset transistor RST drains electric charges from the first, second, and third floating diffusions FD1, FD2, and FD3, and resets the potentials of the first, second, and third floating diffusions FD1, FD2, and FD3 to the potential of the drive line VDDHPX (drive voltage VDDHPX). One of the source and drain of the reset transistor RST is electrically connected to the third floating diffusion FD3, and the other of the source and drain of the reset transistor RST is electrically connected to the drive line VDDHPX.

[0050] The amplifier transistor AMP receives the charge accumulated in the first floating diffusion region FD1 at its gate and outputs the charge to the select transistor SEL via a source follower. The gate of the amplifier transistor AMP is electrically connected to the first floating diffusion region FD1. One of the source and drain of the amplifier transistor AMP is electrically connected to the drive line VDDHPX, and the other of the source and drain of the amplifier transistor AMP is electrically connected to the select transistor SEL. The amplifier transistor AMP converts the charge accumulated in the first floating diffusion region FD1 into a voltage signal and outputs it to the select transistor SEL.

[0051] The select transistor SEL can electrically connect the amplifier transistor AMP and the vertical signal line VSL. When the select transistor SEL is turned on, the amplifier transistor AMP and the vertical signal line VSL are electrically connected. When the select transistor SEL is turned off, the amplifier transistor AMP and the vertical signal line VSL are electrically isolated. One of the source and drain of the select transistor SEL is electrically connected to the amplifier transistor AMP, and the other of the source and drain of the select transistor SEL is electrically connected to the vertical signal line VSL.

[0052] Here, the high-illuminance pixel 1a and the low-illuminance pixel 1b will be described.

[0053] The high-illuminance pixel 1a is a pixel 1 to which light of high illuminance is incident. The high-illuminance pixel 1a is also called a bright pixel. On the other hand, the low-illuminance pixel 1b is a pixel 1 to which light of low illuminance is incident or a pixel 1 to which no light is incident. The low-illuminance pixel 1a is also called a dark pixel.

[0054] In this embodiment, a capacitor MIM is disposed in each pixel 1 of the solid-state imaging device in order to improve the characteristics of the solid-state imaging device. The capacitor MIM in each pixel 1 is, for example, an MIM capacitor formed in a multilayer wiring structure of the solid-state imaging device. The solid-state imaging device of this embodiment is mounted in, for example, a digital camera. According to this embodiment, by disposing the capacitor MIM in each pixel 1, it is possible to expand the dynamic range of the solid-state imaging device.

[0055] When multiple pixels 1 of a solid-state imaging device are collectively operated using the FCVDD line, a high-intensity pixel 1a receiving a signal may adversely affect a low-intensity pixel 1b not receiving a signal via the FCVDD line. This phenomenon occurs due to coupling between the capacitor MIM in the high-intensity pixel 1a and the capacitor MIM in the low-intensity pixel 1b. This results in horizontally extending bands appearing in the image output from the solid-state imaging device. It is desirable to prevent such bands from appearing in the image.

[0056] In the above coupling, the capacitor MIM in the high-intensity pixel 1a raises the potential of the FCVDD line, which affects the capacitor MIM in the low-intensity pixel 1b, causing the low-intensity pixel 1b to become a bright pixel instead of a dark pixel.

[0057] In this embodiment, in order to suppress such coupling, a shield layer is formed between adjacent pixels 1. Details of this shield layer will be described later.

[0058] FIG. 3 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment.

[0059] Fig. 3 shows three pixels 1 in a pixel array 2 of this embodiment. As shown in Fig. 3, the solid-state imaging device of this embodiment includes a substrate 11, an interlayer insulating film 12, a multilayer wiring structure 13, a filter layer 14, and a lens layer 15. Fig. 3 further illustrates three wiring layers 13a, 13b, and 13c in the multilayer wiring structure 13.

[0060] 3 shows X-axis, Y-axis, and Z-axis, which are perpendicular to each other. The X-axis and Y-axis correspond to the horizontal direction, and the Z-axis corresponds to the vertical direction. The +Z-axis corresponds to the upward direction, and the −Z-axis corresponds to the downward direction. Note that the −Z-axis may or may not strictly coincide with the direction of gravity.

[0061] The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Fig. 3 shows an upper surface S1 and a lower surface S2 of the substrate 11. In Fig. 3, the upper surface S1 of the substrate 11 is the front surface of the substrate 11, and the lower surface S2 of the substrate 11 is the back surface of the substrate 11. Since the solid-state imaging device of this embodiment is a back-illuminated type, the back surface of the substrate 11 is the light incident surface (light receiving surface) of the substrate 11. As shown in Fig. 3, each pixel 1 of this embodiment includes a photodiode PD, a first floating diffusion region FD1, etc. within the substrate 11, and a transfer transistor TG, etc. on the upper surface S1 of the substrate 11.

[0062] The interlayer insulating film 12 is provided on the upper surface S1 of the substrate 11. In Fig. 3, the interlayer insulating film 12 is formed on the substrate 11 so as to cover the transfer transistor TG of each pixel 1. The interlayer insulating film 12 is made of, for example, SiO ２ It is a laminated insulating film including a silicon oxide layer and the like.

[0063] The multilayer wiring structure 13 is provided in the interlayer insulating film 12. The multilayer wiring structure 13 includes one or more contact plug layers, one or more wiring layers, one or more via plug layers, etc., formed on the upper surface S1 side of the substrate 11. FIG. 3 shows wiring layers 13a, 13b, and 13c as examples of the one or more wiring layers. The multilayer wiring structure 13 is formed, for example, of one or more types of metal layers. At least a portion of the multilayer wiring structure 13 may be formed of a semiconductor layer such as a polysilicon layer.

[0064] The filter layer 14 is provided on the lower surface S2 of the substrate 11. The filter layer 14 in each pixel 1 functions as a color filter that transmits light of a predetermined wavelength. For example, the filter layers 14 in the pixels 1 for red (R), green (G), blue (B), and infrared light (IR) function as color filters for red, green, blue, and infrared light, respectively.

[0065] The lens layer 15 is provided below the filter layer 14. The lens layer 15 in each pixel 1 functions as a lens that collects incident light. In each pixel 1, light that is incident on the lens layer 15 is collected by the lens layer 15, passes through the filter layer 14, and enters the photodiode PD. The photodiode PD converts this light into electric charges by photoelectric conversion, thereby generating signal charges.

[0066] FIG. 4 is a plan view and a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment.

[0067] Fig. 4A shows a plan view of one pixel 1 in a pixel array 2 of this embodiment. Fig. 4B shows a vertical cross section of this pixel 1 taken along line XX' shown in Fig. 4A. The pixel array 2 of this embodiment includes a plurality of pixels 1 having a structure similar to that of the pixel 1 shown in Figs. 4A and 4B. The structure of these pixels 1 will be described below using the pixel 1 shown in Figs. 4A and 4B as an example.

[0068] The pixel 1 shown in Figures 4A and 4B includes the above-mentioned capacitor MIM, a portion of the shield layer SHa, and a portion of the shield layer SHb. The shield layer SHa is provided between the pixel 1 shown in Figures 4A and 4B and the pixel 1 adjacent to it on the left side. The shield layer SHb is provided between the pixel 1 shown in Figures 4A and 4B and the pixel 1 adjacent to it on the right side. These three pixels 1 correspond to, for example, the three pixels 1 shown in Figure 3. The capacitor MIM is an example of a first capacitor of the present disclosure. The pixel 1 shown in Figures 4A and 4B is an example of a first pixel of the present disclosure, and the pixel 1 adjacent to it on the left or right side is an example of a second pixel of the present disclosure.

[0069] 4A and 4B show the interlayer insulating film 12 and a part of the multilayer wiring structure 13. The capacitor MIM, the shield layer SHa, and the shield layer SHb are formed as part of the multilayer wiring structure 13. Further details of the multilayer wiring structure 13 will be described later.

[0070] The MIM capacitor includes a lower electrode 21, a dielectric layer 22, and an upper electrode 23. The lower electrode 21 is formed above the substrate 11 (see FIG. 3). The lower electrode 21 is, for example, a conductive film such as a metal layer. The dielectric layer 22 is formed on the lower electrode 21. The dielectric layer 22 is, for example, a SiO ２ The lower electrode 21 is an insulating film such as a layer. The upper electrode 23 is formed on the dielectric layer 22. The lower electrode 23 is, for example, a conductive film such as a metal layer. As shown in FIG. 4A , the lower electrode 21, the dielectric layer 22, and the upper electrode 23 of this embodiment each have a quadrilateral (e.g., square or rectangular) shape in plan view. The lower electrode 21, the dielectric layer 22, and the upper electrode 23 are examples of the first lower electrode, the first dielectric layer, and the first upper electrode of the present disclosure, respectively.

[0071] The lower electrode 21 is formed on a trench wiring layer 24. Specifically, as shown in Fig. 4A, the trench wiring layer 24 includes trench wirings 24a, 24b, and 24c extending in the Y direction, and the lower electrode 21 is formed on the trench wirings 24a, 24b, and 24c. In Fig. 4A, the contours of the trench wirings 24a, 24b, and 24c are indicated by dashed lines. The trench wiring layer 24 is, for example, a conductive film such as a metal layer.

[0072] The multilayer wiring structure 13 of this embodiment includes a wiring layer 31, a via plug layer 32, and a wiring layer 33. The wiring layer 31 is formed above the substrate 11 (see FIG. 3). The via plug layer 32 is formed on the wiring layer 31. The wiring layer 33 is formed on the via plug layer 32. Each of the wiring layer 31, the via plug layer 32, and the wiring layer 33 is, for example, a conductive film such as a metal layer. The wiring layers 31 and 33 correspond to, for example, two of the wiring layers 13a to 13c shown in FIG. 3.

[0073] 4A and 4B, the wiring layer 31 includes wiring 31a, wiring 31b, wiring 31c, and wiring 31d. The via plug layer 32 includes a plurality of via plugs 32a, a plurality of via plugs 32b, and a via plug 32c. The wiring layer 33 includes wiring 33a, wiring 33b, and wiring 33c. In FIG. 4A, the outline of the via plug 32c is indicated by a dashed line. Meanwhile, in FIG. 4A, the via plugs 32a and 32b arranged on the lower side of the wirings 33a and 33b are illustrated on the upper side of the wirings 33a and 33b in order to clearly illustrate the shapes and arrangement of the via plugs 32a and 32b (the same applies to later figures).

[0074] The shield layer SHa is formed by a wiring 31a, a plurality of via plugs 32a, a wiring 33a, and the like. The wiring 31a extends in the Y direction. The plurality of via plugs 32a are arranged on the wiring 31a so as to be adjacent to each other in the Y direction. The wiring 33a is arranged on these via plugs 32a and extends in the Y direction. The shield layer SHa may further include via plugs and wiring below the wiring 31a and via plugs and wiring above the wiring 33a. According to this embodiment, the shield layer SHa can suppress coupling between the capacitor MIM in the pixel 1 shown in FIGS. 4A and 4B and the capacitor MIM in the pixel 1 adjacent to it on the left side. This makes it possible to suppress adverse effects of these capacitors MIM on images.

[0075] The shield layer SHb is formed by a wiring 31b, a plurality of via plugs 32b, a wiring 33b, and the like. The wiring 31b extends in the Y direction. The plurality of via plugs 32b are arranged on the wiring 31b so as to be adjacent to each other in the Y direction. The wiring 33b is arranged on these via plugs 32b and extends in the Y direction. The shield layer SHb may further include via plugs and wiring below the wiring 31b and via plugs and wiring above the wiring 33b. According to this embodiment, the shield layer SHb can suppress coupling between the capacitor MIM in the pixel 1 shown in FIGS. 4A and 4B and the capacitor MIM in the pixel 1 adjacent to it on the right. This makes it possible to suppress adverse effects of these capacitors MIM on images.

[0076] The wiring 31c is disposed below the trench wiring 24a. The wiring 31d is disposed below the trench wiring 24b. In this embodiment, at least one of the wirings 31c and 31d electrically connects the lower electrode 21 of the capacitor MIM to the third floating diffusion FD3 (see FIG. 2).

[0077] The via plug 32c is disposed on the upper electrode 23. In Fig. 4A, the outline of the via plug 32c is indicated by a dashed line. The wiring 33c is disposed on the via plug 32c. In this embodiment, the via plug 32c and the wiring 33c electrically connect the upper electrode 23 of the capacitor MIM to the drive line FCVDD (see Fig. 2).

[0078] 4B , the trench wiring layer 24, the lower electrode 21, the dielectric layer 22, and the upper electrode 23 are formed between the height of the upper surface and the height of the lower surface of the via plug layer 32. In this embodiment, the via plug layer 32 is formed after the trench wiring layer 24, the lower electrode 21, the dielectric layer 22, and the upper electrode 23 are formed. Because the via plug 32c is formed on the upper electrode 23, the length of the via plug 32c in the Z direction is shorter than the lengths of the via plugs 33a and 33b in the Z direction.

[0079] In this embodiment, each of the shield layers SHa and SHb is electrically connected to a power supply line (VDD line) or a ground line (GND line) within the solid-state imaging device. This allows the potential of the shield layers SHa and SHb to be fixed. This also applies to shield layers (described later) other than the shield layers SHa and SHb.

[0080] FIG. 5 is a plan view showing the structure of the solid-state imaging device of the first embodiment.

[0081] 5 shows eight pixels 1 in the pixel array 2 of this embodiment. In the following description, the four pixels 1 on the left side will be referred to as "left pixels 1," and the four pixels 1 on the right side will be referred to as "right pixels 1."

[0082] 5, the outline of the drive line FCVDD for the left pixel 1 and the outline of the drive line FCVDD for the right pixel 1 are indicated by dashed lines. The drive line FCVDD for the left pixel 1 extends in the Y direction within the left pixel 1 and is disposed above the capacitor MIM (see FIGS. 4A and 4B) within each left pixel 1. The capacitor MIM within each left pixel 1 is electrically connected to this drive line FCVDD. The drive line FCVDD for the right pixel 1 extends in the Y direction within the right pixel 1 and is disposed above the capacitor MIM (see FIGS. 4A and 4B) within each right pixel 1. The capacitor MIM within each right pixel 1 is electrically connected to this drive line FCVDD.

[0083] 5 further shows the above-mentioned shield layer SHa, the above-mentioned shield layer SHb, and a further shield layer SHa′, which is also formed as part of the multilayer wiring structure 13.

[0084] The shield layer SHa is disposed between the left pixel 1 and a plurality of pixels 1 adjacent to the left side of the left pixel 1. The wiring 33a and wiring 31a (not shown) in the shield layer SHa extend in the Y direction between these pixels 1. The plurality of via plugs 32a shown in FIG. 5 are disposed between the lower surface of the wiring 33a and the upper surface of the wiring 31a so as to be adjacent to each other in the Y direction. According to this embodiment, the shield layer SHa can suppress coupling between the capacitors MIM in these pixels 1.

[0085] The shield layer SHb is disposed between the left pixel 1 and the right pixel 1. The wiring 33b and wiring 31b (not shown) in the shield layer SHb extend in the Y direction between these pixels 1. The multiple via plugs 32b shown in FIG. 5 are disposed between the lower surface of the wiring 33b and the upper surface of the wiring 31b so as to be adjacent to each other in the Y direction. According to this embodiment, the shield layer SHb can suppress coupling between the capacitors MIM in these pixels 1.

[0086] The shield layer SHa' is disposed between the right pixel 1 and a plurality of pixels 1 adjacent to the right side of the right pixel 1. The wiring 33a' and wiring 31a' (not shown) in the shield layer SHa' extend in the Y direction between these pixels 1. The plurality of via plugs 32a' shown in FIG. 5 are disposed between the lower surface of the wiring 33a' and the upper surface of the wiring 31a' so as to be adjacent to each other in the Y direction. According to this embodiment, the shield layer SHa' can suppress coupling between the capacitors MIM in these pixels 1.

[0087] FIG. 6 is a cross-sectional view showing the structure of a solid-state imaging device according to a first modified example of the first embodiment.

[0088] 6 shows a longitudinal cross section of the capacitor MIM, similar to FIG. 4B. The capacitor MIM shown in FIG. 4B has flat upper and lower surfaces, whereas the capacitor MIM shown in FIG. 6 has uneven upper and lower surfaces. The structure shown in FIG. 4B makes it possible to easily form the capacitor MIM. On the other hand, the structure shown in FIG. 6 makes it possible to increase the capacitance of the capacitor MIM.

[0089] The capacitor MIM of this embodiment may have a structure different from the structures shown in Fig. 4B and Fig. 6. For example, the capacitor MIM of this embodiment may have a cylindrical structure.

[0090] FIG. 7 is a plan view showing the structure of a solid-state imaging device according to a second modification of the first embodiment.

[0091] FIG. 7 shows multiple shield layers SHb' in addition to the components shown in FIG. 5 . These shield layers SHb' are also formed as part of the multilayer wiring structure 13. Each shield layer SHb' is disposed between two pixels 1 adjacent to each other in the Y direction. The shield layers SHa, SHb, and SHa' extend in the Y direction between the adjacent pixels 1, while each shield layer SHb' extends in the X direction between the adjacent pixels 1. The shield layers SHa, SHb, and SHa' are examples of the first shield layer of the present disclosure that extends in the first direction between the first pixel and the second pixel. Each shield layer SHb' is an example of the second shield layer of the present disclosure that extends in the second direction between the first pixel and the third pixel.

[0092] As described above, each shield layer SHb' is disposed between two pixels 1 adjacent to each other in the Y direction. The wiring 33b' and wiring 31b' (not shown) in each shield layer SHb' extend in the X direction between these pixels 1. The multiple via plugs 32b' in each shield layer SHb' are disposed between the lower surface of the wiring 33b' and the upper surface of the wiring 31b' so as to be adjacent to each other in the X direction. According to this embodiment, the shield layer SHb' can suppress coupling between the capacitors MIM in these pixels 1.

[0093] FIG. 8 is a plan view and a cross-sectional view showing the structure of a solid-state imaging device according to a third modified example of the first embodiment.

[0094] 8A and 8B show a lower wiring layer 41 including lower wiring 41a and an upper wiring layer 42 including upper wiring 42a in addition to the components shown in Figures 4A and 4B. In Figure 8A, the outlines of the lower wiring 41a and the upper wiring 42a are shown by dashed lines.

[0095] The lower wiring layer 41 is formed between the wiring layer 31 and the via plug layer 32 as part of the multilayer wiring structure 13. The lower wiring layer 41 is, for example, a conductive film such as a metal layer. The height of the upper surface of the lower wiring layer 41 is lower than the height of the lower surface of the lower electrode 21.

[0096] The upper wiring layer 42 is formed between the via plug layer 32 and the wiring layer 33 as part of the multilayer wiring structure 13. The upper wiring layer 42 is, for example, a conductive film such as a metal layer. The height of the lower surface of the upper wiring layer 42 is lower than the height of the upper surface of the upper electrode 23.

[0097] The lower wiring 41a is included in the shield layer SHb and is provided between the wiring 31b and the plurality of via plugs 32b. The lower wiring 41a further has an upper surface facing the lower surface of the lower electrode 21 of the capacitor MIM. This makes it possible to suppress the above-mentioned coupling from occurring from the lower side of the capacitor MIM.

[0098] The upper wiring 42a is included in the shield layer SHa and is provided between the via plugs 32a and the wiring 33a. The upper wiring 42a further has a lower surface facing the upper surface of the upper electrode 23 of the capacitor MIM. This makes it possible to suppress the above-mentioned coupling from occurring from the upper side of the capacitor MIM.

[0099] The pixel 1 shown in FIGS. 8A and 8B may include both the lower wiring 41a and the upper wiring 42a, or may include only one of the lower wiring 41a and the upper wiring 42a.

[0100] As described above, the solid-state imaging device of this embodiment includes the shield layers SHa and SHb that protect the capacitor MIM. Therefore, according to this embodiment, the shield layers SHa and SHb can prevent the capacitor MIM from adversely affecting an image.

[0101] Second Embodiment FIG. 9 is a plan view and a cross-sectional view showing the structure of a solid-state imaging device according to a second embodiment.

[0102] 9A, like FIG. 4A, shows a single pixel 1 in the pixel array 2 in a plan view. Similarly to FIG. 4B, FIG. 9B shows a vertical cross section of this pixel 1 taken along line XX' shown in FIG. 9A. The solid-state imaging device of this embodiment includes multiple pixels 1 having the same structure as the pixel 1 shown in FIGS. 9A and 9B. The structure of these pixels 1 will be described below using the pixel 1 shown in FIGS. 9A and 9B as an example.

[0103] 9A and 9B includes capacitors MIM1 and MIM2 instead of capacitor MIM. Capacitors MIM1 and MIM2 are formed as part of multilayer wiring structure 13 and are electrically connected to each other. Capacitor MIM1 is an example of a first capacitor of the present disclosure. Capacitor MIM2 is an example of a second capacitor of the present disclosure. Note that pixel 1 shown in FIGS. 9A and 9B does not include shield layers SHa and SHb, but may include shield layers SHa and SHb.

[0104] The capacitors MIM1 and MIM2 of this embodiment have the same structure as the capacitor MIM of the first embodiment. The capacitor MIM1 includes a lower electrode 21a formed above the substrate 11 (FIG. 3), a dielectric layer 22a formed on the lower electrode 21a, and an upper electrode 23a formed on the dielectric layer 22a. The capacitor MIM2 includes a lower electrode 21b formed above the substrate 11 (FIG. 3), a dielectric layer 22b formed on the lower electrode 21b, and an upper electrode 23b formed on the dielectric layer 22b. The lower electrodes 21a and 21b are, for example, conductive films such as metal layers. The dielectric layers 22a and 22b are, for example, SiO ２ The lower electrodes 23a and 23b are, for example, insulating films such as metal layers. The lower electrode 21a, the dielectric layer 22a, and the upper electrode 23a are examples of a first lower electrode, a first dielectric layer, and a first upper electrode, respectively, of the present disclosure. The lower electrode 21b, the dielectric layer 22b, and the upper electrode 23b are examples of a second lower electrode, a second dielectric layer, and a second upper electrode, respectively, of the present disclosure.

[0105] 9A , the lower electrodes 21 a, 21 b, the dielectric layers 22 a, 22 b, and the upper electrodes 23 a, 23 b of this embodiment each have a quadrilateral (e.g., square or rectangular) shape in plan view. The capacitors MIM1, MIM2 of this embodiment can be formed, for example, by forming the lower electrode 21, the dielectric layer 22, and the upper electrode 23 of the capacitor MIM of the first embodiment, and dividing the lower electrode 21, the dielectric layer 22, and the upper electrode 23 into the lower electrode 21 a, the dielectric layer 22 a, and the upper electrode 23 a of the capacitor MIM1, and the lower electrode 21 b, the dielectric layer 22 b, and the upper electrode 23 b of the capacitor MIM2. The lower electrode 21, the dielectric layer 22, and the upper electrode 23 can be divided by dry etching such as RIE (reactive ion etching).

[0106] The lower electrodes 21a and 21b are formed on the trench wiring layer 24. Specifically, the lower electrode 21a is formed on the trench wirings 24a and 24c, and the lower electrode 21b is formed on the trench wiring 24b. Note that in Figures 9A and 9B, the arrangement of the trench wirings 24a and 24b is reversed from the arrangement shown in Figures 4A and 4B for the sake of convenience in explanation, in order to make the trench wiring 24a correspond to the lower electrode 21a and the trench wiring 24b correspond to the lower electrode 21b.

[0107] The multilayer wiring structure 13 of this embodiment includes a connection wiring layer 51 shown in FIG. 9B in addition to the above-described wiring layer 31, via plug layer 32, and wiring layer 33. The connection wiring layer 51 is, for example, a conductive film such as a metal layer. The connection wiring layer 51 includes a connection wiring 51a. The multilayer wiring structure 13 of this embodiment further includes a via plug 32d in the via plug layer 32 and a wiring 33d in the wiring layer 33.

[0108] As in the first embodiment, the wiring 31c is disposed below the trench wiring 24a, and the wiring 31d is disposed below the trench wiring 24b. In this embodiment, the connection wiring 51a is disposed below the wirings 31c and 31d. As shown in FIG. 9B , the lower electrode 21a of the capacitor MIM1 and the lower electrode 21b of the capacitor MIM2 are electrically connected to each other by the connection wiring 51a. In this embodiment, the connection wiring 51a electrically connects the lower electrodes 21a and 21b of the capacitors MIM1 and MIM2 to the third floating diffusion FD3 ( FIG. 2 ). Therefore, the lower electrodes 21a and 21b in this embodiment are supplied with signal charges from the third floating diffusion FD3.

[0109] The via plug 32c is disposed on the upper electrode 23a. In FIG. 9A, the outline of the via plug 32c is indicated by a dashed line. The wiring 33c is disposed on the via plug 32c. In this embodiment, the via plug 32c and the wiring 33c electrically connect the upper electrode 23a of the capacitor MIM1 to the driving line FCVDD (FIG. 2). Therefore, the upper electrode 23a in this embodiment is supplied with the driving voltage FCVDD from the driving line FCVDD.

[0110] The via plug 32d is disposed on the upper electrode 23a. In FIG. 9A, the outline of the via plug 32d is indicated by a dashed line. The wiring 33d is disposed on the via plug 32d. In this embodiment, the via plug 32d and the wiring 33d electrically connect the upper electrode 23b of the capacitor MIM2 to the ground line. Therefore, the upper electrode 23b in this embodiment is supplied with a ground voltage from the ground line.

[0111] In this embodiment, since the capacitor MIM2 is electrically connected to the ground line, the capacitor MIM2 can be used as a bypass capacitor for the capacitor MIM1. Specifically, by bypassing noise from the pixel 1 shown in FIGS. 9A and 9B to the ground line, a stable power supply can be achieved. According to this embodiment, the capacitor MIM2 of each pixel 1 can suppress the adverse effect of the capacitor MIM1 of each pixel 1 on the image.

[0112] In each pixel 1 of this embodiment, in plan view, it is desirable that the area of ​​the lower electrode 21 a be larger than the area of ​​the lower electrode 21 b, and the area of ​​the upper electrode 23 a be larger than the area of ​​the upper electrode 23 b, which makes it possible to reduce the size of the capacitor MIM2 used as a pass capacitor, and accordingly increase the size of the capacitor MIM1.

[0113] FIG. 10 is a circuit diagram showing the configuration of a solid-state imaging device according to the second embodiment and its modified example.

[0114] FIG. 10A illustrates the circuit configuration of the solid-state imaging device of this embodiment. Similar to FIG. 2, FIG. 10A illustrates two pixels 1a and 1b in the pixel array 2. In each of the pixels 1a and 1b, a capacitor MIM1 is disposed between the drive line FCVDD and the signal line SIG, and a capacitor MIM2 is disposed between the ground line GND and the signal line SIG. The signal line SIG is, for example, a wiring extending from the third floating diffusion region FD3 (FIG. 2). The capacitor MIM1 receives the drive voltage FCVDD from the drive line FCVDD and the signal charge from the signal line SIG. The capacitor MIM2 receives the ground voltage GND from the ground line GND and the signal charge from the signal line SIG. Each of the pixels 1a and 1b illustrated in FIG. 10A corresponds to the pixel 1 illustrated in FIGS. 9A and 9B.

[0115] The configuration shown in FIG. 10A may be replaced with the configuration shown in FIG. 10B. FIG. 10B shows the circuit configuration of a solid-state imaging device according to a modified example of this embodiment. In each of pixels 1a and 1b, a capacitor MIM1 is disposed between the drive line FCVDD and the signal line SIG, and a capacitor MIM2 is disposed between the drive line FCVDD and the ground line GND. The capacitor MIM1 is supplied with the drive voltage FCVDD from the drive line FCVDD and with the signal charge from the signal line SIG. The capacitor MIM2 is supplied with the drive voltage FCVDD from the drive line FCVDD and with the ground voltage GND from the ground line GND.

[0116] 9A and 9B , the upper electrode 23 b of the capacitor MIM2 is electrically connected to the upper electrode 23 a of the capacitor MIM1 and is electrically connected to the drive line FCVDD in the same manner as the upper electrode 23 a of the capacitor MIM1. On the other hand, the lower electrode 21 b of the capacitor MIM2 is electrically connected to the ground line GND rather than the signal line SIG (third floating diffusion FD3).

[0117] As described above, the solid-state imaging device of this embodiment includes the capacitor MIM2 in addition to the capacitor MIM1. Therefore, according to this embodiment, it is possible to suppress the adverse effect of the capacitor MIM1 on the image by using the capacitor MIM2.

[0118] Third Embodiment FIG. 11 is a circuit diagram showing the configuration of a solid-state imaging device according to a third embodiment and its modified example.

[0119] Fig. 11A shows the circuit configuration of the solid-state imaging device of this embodiment. Similar to Fig. 2, Fig. 11A illustrates two pixels 1a and 1b in the pixel array 2 described above. In each of the pixels 1a and 1b, a switch SW is arranged in parallel with a capacitor MIM. The switch SW is, for example, a MOS transistor. Hereinafter, each of the pixels 1a and 1b will be referred to as "each pixel 1."

[0120] 11A, a capacitor MIM is arranged between a drive line FCVDD and a signal line SIG. The capacitor MIM is supplied with a drive voltage FCVDD from the drive line FCVDD and with a signal charge from the signal line SIG (third floating diffusion FD3).

[0121] Each pixel 1 shown in Fig. 11A has a structure similar to that of the pixel 1 shown in Fig. 4A and Fig. 4B . In each pixel 1 shown in Fig. 11A , the upper electrode 23 of the capacitor MIM is electrically connected to the drive line FCVDD, and the lower electrode 21 of the capacitor MIM is electrically connected to the signal line SIG (third floating diffusion FD3).

[0122] One terminal of the switch SW is electrically connected to the upper electrode 23 of the capacitor MIM, and the other terminal of the switch SW is electrically connected to the lower electrode 21 of the capacitor MIM. Therefore, according to this embodiment, by closing the switch SW, it is possible to electrically connect the upper electrode 23 and the lower electrode 21 of the capacitor MIM. This makes it possible to short-circuit the upper electrode 23 and the lower electrode 21 of the capacitor MIM with the switch SW, thereby resetting the capacitor MIM.

[0123] According to this embodiment, it is possible to prevent the capacitor MIM of each pixel 1 from adversely affecting an image by using the switch SW of each pixel 1. For example, by resetting the capacitor MIM of each pixel 1 in the rows before and after readout, it is possible to suppress the above-mentioned coupling.

[0124] The configuration shown in FIG. 11A may be replaced with the configuration shown in FIG. 11B. FIG. 11B shows the circuit configuration of a solid-state imaging device according to a modification of this embodiment. The switch SW according to this modification is capable of three-state switching. In a first state, the switch SW electrically connects the lower electrode 21 to the upper electrode 23. In a second state, the switch SW simply electrically insulates the lower electrode 21 from the upper electrode 23. In a third state, the switch SW electrically insulates the lower electrode 21 from the upper electrode 23 and electrically connects the lower electrode 21 to the power supply line VDD (or ground line GND). In the third state, the lower electrode 21 can be reset using the power supply line VDD (or ground line GND).

[0125] As described above, the solid-state imaging device of this embodiment includes the switch SW arranged in parallel with the capacitor MIM. Therefore, according to this embodiment, the switch SW can prevent the capacitor MIM from adversely affecting an image.

[0126] The switch SW of this embodiment may be applied to the solid-state imaging device of the first embodiment, thereby making it possible to prevent the capacitor MIM from adversely affecting an image by the shield layers SHa and SHb and the switch SW.

[0127] The switch SW of this embodiment may be applied to the solid-state imaging device of the second embodiment, thereby making it possible to suppress the adverse effect of the capacitor MIM1 on the image by the capacitor MIM2 and the switch SW.

[0128] 12 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0129] The camera 100 includes an optical unit 101 including a lens group and the like, an imaging device 102 which is a solid-state imaging device according to any one of the first to third embodiments, a DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, a frame memory 104, a display unit 105, a recording unit 106, an operation unit 107, and a power supply unit 108. The DSP circuit 103, the frame memory 104, the display unit 105, the recording unit 106, the operation unit 107, and the power supply unit 108 are connected to one another via a bus line 109.

[0130] The optical unit 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light formed on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0131] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one frame of a moving image or still image captured by the imaging device 102.

[0132] The display unit 105 includes a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 on a recording medium such as a hard disk or semiconductor memory.

[0133] The operation unit 107, under the operation of the user, issues operation commands for various functions of the camera 100. The power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources.

[0134] By using the solid-state imaging device according to any one of the first to third embodiments as the imaging device 102, it is possible to expect to obtain a good image.

[0135] The solid-state imaging device can be applied to various other products, for example, the solid-state imaging device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0136] 13 is a block diagram showing an example of the configuration of a mobile object control system. The mobile object control system shown in FIG.

[0137] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 13, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 13 further shows components of the integrated control unit 250, such as a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0138] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates braking force for the vehicle, etc.

[0139] Body system control unit 220 controls the operation of various devices equipped in the vehicle body in accordance with various programs. For example, body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, backup lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 220. Body system control unit 220 receives input of such radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0140] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture images outside the vehicle and receives the captured images from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0141] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 231 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 231 may be visible light or invisible light such as infrared light. The imaging unit 231 includes a solid-state imaging device according to any one of the first to third embodiments.

[0142] The in-vehicle information detection unit 240 detects information about the inside of a vehicle equipped with the vehicle control system 200. A driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240, for example. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver or determine whether the driver is dozing off based on the detection information input from the driver state detection unit 241. This camera may include the solid-state imaging device of any of the first to third embodiments, and may be, for example, the camera 100 shown in FIG. 12 .

[0143] The microcomputer 251 can calculate control target values ​​for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside information detection unit 230 or the inside information detection unit 240, and output control commands to the drivetrain control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), such as vehicle collision avoidance, impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, collision warning, and lane departure warning.

[0144] In addition, the microcomputer 251 can perform cooperative control for purposes such as autonomous driving, in which the vehicle travels autonomously without the driver's operation, by controlling the driving force generating device, steering mechanism, or braking device based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0145] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information about the outside of the vehicle acquired by the outside information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0146] The audio / video output unit 252 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 13, an audio speaker 261, a display unit 262, and an instrument panel 263 are shown as such output devices. The display unit 262 may include, for example, an on-board display or a head-up display.

[0147] FIG. 14 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0148] 14 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 300.

[0149] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the top of the windshield inside the vehicle mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0150] FIG. 14 shows an example of the imaging ranges of imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of imaging unit 304 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 301 to 304, an overhead image of vehicle 300 viewed from above can be obtained. Hereinafter, imaging ranges 311, 312, 313, and 314 will be referred to as "imaging ranges 311 to 314."

[0151] At least one of the image capturing units 301 to 304 may have a function of acquiring distance information. For example, at least one of the image capturing units 301 to 304 may be a stereo camera including multiple image capturing devices, or may be an image capturing device having pixels for detecting a phase difference.

[0152] For example, the microcomputer 251 (FIG. 13) calculates the distance to each three-dimensional object within the imaging ranges 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 300 and traveling in approximately the same direction as the vehicle 300 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 251 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle and perform automatic braking control (including adaptive cruise control), automatic acceleration control (including adaptive cruise control), and the like. In this way, according to this example, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without driver operation.

[0153] For example, based on the distance information obtained from the imaging units 301 to 304, the microcomputer 251 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. The microcomputer 251 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drivetrain control unit 210.

[0154] At least one of the image capturing units 301-304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 301-304. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 301-304 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the images captured by the image capturing units 301-304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like representing the pedestrian in a desired position.

[0155] FIG. 15 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0156] 15 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0157] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the example shown in the figure, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0158] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens toward an observation target inside the body cavity of the patient 532. The endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0159] An optical system and an image sensor are provided inside the camera head 502, and light reflected from an object to be observed (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 601 as RAW data.

[0160] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502 and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0161] Under the control of the CCU 601 , the display device 602 displays an image based on the image signal that has been subjected to image processing by the CCU 601 .

[0162] The light source device 603 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when photographing an operation site or the like.

[0163] The input device 604 is an input interface for the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 500.

[0164] The treatment tool control device 605 controls the driving of the energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 sends gas into the body cavity of the patient 532 via the insufflation tube 511 to ensure a clear field of view for the endoscope 500 and a working space for the surgeon. The recorder 607 is a device capable of recording various types of information related to the surgery. The printer 608 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0165] The light source device 603, which supplies illumination light to the endoscope 500 when photographing the surgical site, can be configured from a white light source formed, for example, by an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 603 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 502 in synchronization with the irradiation timing. This method allows color images to be obtained without providing a color filter to the image sensor.

[0166] Furthermore, the light source device 603 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0167] The light source device 603 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 603 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0168] FIG. 16 is a block diagram showing an example of the functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0169] The camera head 502 has a lens unit 701, an imaging unit 702, a drive unit 703, a communication unit 704, and a camera head control unit 705. The CCU 601 has a communication unit 711, an image processing unit 712, and a control unit 713. The camera head 502 and the CCU 601 are connected to each other via a transmission cable 700 so as to be able to communicate with each other.

[0170] The lens unit 701 is an optical system provided at the connection portion with the lens barrel 501. Observation light taken in from the tip of the lens barrel 501 is guided to the camera head 502 and enters the lens unit 701. The lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0171] The imaging unit 702 is composed of an imaging element. The imaging element constituting the imaging unit 702 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 702 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 702 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 531 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 702 is composed of a multi-chip type, multiple lens units 701 may be provided corresponding to each imaging element. The imaging unit 702 may be, for example, a solid-state imaging device according to any of the first to third embodiments.

[0172] Furthermore, the imaging unit 702 does not necessarily have to be provided in the camera head 502. For example, the imaging unit 702 may be provided inside the lens barrel 501, immediately after the objective lens.

[0173] The driving unit 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control unit 705. This allows the magnification and focus of the image captured by the imaging unit 702 to be adjusted appropriately.

[0174] The communication unit 704 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0175] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601 and supplies the control signal to the camera head control unit 705. The control signal includes information relating to the image capturing conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing an image, and / or information specifying the magnification and focus of the captured image.

[0176] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 713 of the CCU 601 based on the acquired image signal. In the latter case, the endoscope 500 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0177] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0178] The communication unit 711 is configured by a communication device for transmitting and receiving various types of information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0179] Furthermore, the communication unit 711 transmits to the camera head 502 a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0180] The image processing unit 712 performs various types of image processing on the image signal, which is RAW data, sent from the camera head 502 .

[0181] The control unit 713 performs various controls related to the imaging of the surgical site, etc. by the endoscope 500 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0182] Furthermore, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal subjected to image processing by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 713 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated during use of the energy treatment tool 512, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 602, the control unit 713 may use the recognition results to superimpose various surgical support information on the image of the surgical site. Superimposing the surgical support information and presenting it to the surgeon 531 reduces the burden on the surgeon 531 and enables the surgeon 531 to proceed with the surgery reliably.

[0183] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electric signal cable for communication of electric signals, an optical fiber for optical communication, or a composite cable of these.

[0184] In the illustrated example, communication is performed by wire using the transmission cable 700, but communication between the camera head 502 and the CCU 601 may also be performed wirelessly.

[0185] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications within the scope of the gist of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0186] The present disclosure may also be configured as follows.

[0187] (1) A solid-state imaging device comprising: a substrate including a photoelectric conversion section and a charge accumulation section; a charge transfer section provided on the substrate; an insulating film provided on the substrate and the charge transfer section; and a multilayer wiring structure provided in the insulating film, wherein the multilayer wiring structure includes: a first capacitor provided in a first pixel of a plurality of pixels; and a shielding layer provided between the first pixel and a second pixel of the plurality of pixels.

[0188] (2) The solid-state imaging device according to (1), wherein the first capacitor includes a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer.

[0189] (3) The solid-state imaging device according to (1), wherein the shield layer is formed of one or more wiring layers and / or one or more via plug layers included in the multilayer wiring structure.

[0190] (4) The solid-state imaging device according to (1), wherein the shield layer includes wiring extending between two or more pixels including the first pixel and two or more pixels including the second pixel.

[0191] (5) The solid-state imaging device according to (4), wherein the shield layer further includes a plurality of via plugs provided on an upper surface or a lower surface of the wiring.

[0192] (6) The solid-state imaging device described in (1), wherein the multilayer wiring structure includes, as the shielding layer, a first shielding layer provided between the first pixel and the second pixel and extending in a first direction, and the multilayer wiring structure further includes a second shielding layer provided between the first pixel and a third pixel of the plurality of pixels and extending in a second direction different from the first direction.

[0193] (7) The solid-state imaging device according to (1), wherein the shield layer includes a lower wiring having an upper surface facing the lower surface of the first lower electrode.

[0194] (8) The solid-state imaging device according to (1), wherein the shield layer includes an upper wiring having a lower surface facing the upper surface of the first upper electrode.

[0195] (9) The solid-state imaging device according to (1), wherein the multilayer wiring structure further includes a second capacitor provided in the first pixel and electrically connected to the first capacitor, the first capacitor being supplied with a drive voltage and a signal charge, and the second capacitor being supplied with a ground voltage.

[0196] (10) The solid-state imaging device according to (1), wherein the multilayer wiring structure further includes a switch provided in the first pixel and arranged in parallel with the first capacitor.

[0197] (11) A solid-state imaging device comprising: a substrate including a photoelectric conversion section and a charge accumulation section; a charge transfer section provided on the substrate; an insulating film provided on the substrate and the charge transfer section; and a multilayer wiring structure provided in the insulating film, the multilayer wiring structure including: a first capacitor provided in a first pixel of a plurality of pixels, to which a drive voltage and a signal charge are supplied; and a second capacitor provided in the first pixel, electrically connected to the first capacitor, and to which a ground voltage is supplied.

[0198] (12) The solid-state imaging device described in (11), wherein the first capacitor includes a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and the second capacitor includes a second lower electrode, a second dielectric layer provided on the second lower electrode, and a second upper electrode provided on the second dielectric layer.

[0199] (13) The solid-state imaging device according to (12), wherein the first upper electrode of the first capacitor is supplied with the driving voltage, and the first lower electrode of the first capacitor is supplied with the signal charge.

[0200] (14) The solid-state imaging device according to (12), wherein the second upper electrode or the second lower electrode of the second capacitor is supplied with the ground voltage.

[0201] (15) The solid-state imaging device according to (12), wherein the second lower electrode of the second capacitor is electrically connected to the first lower electrode of the first capacitor, or the second upper electrode of the second capacitor is electrically connected to the first upper electrode of the first capacitor.

[0202] (16) The solid-state imaging device according to (11), wherein the multilayer wiring structure further includes a switch provided in the first pixel and arranged in parallel with the first capacitor.

[0203] (17) A solid-state imaging device comprising: a substrate including a photoelectric conversion section and a charge accumulation section; a charge transfer section provided on the substrate; an insulating film provided on the substrate and the charge transfer section; and a multilayer wiring structure provided in the insulating film, wherein the multilayer wiring structure includes: a first capacitor provided in a first pixel of a plurality of pixels; and a switch provided in the first pixel and arranged in parallel with the first capacitor.

[0204] (18) The solid-state imaging device according to (17), wherein the first capacitor includes a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer.

[0205] (19) The solid-state imaging device according to (18), wherein the switch is capable of electrically connecting the first lower electrode and the first upper electrode.

[0206] (20) The solid-state imaging device according to (17), wherein the switch is capable of switching between three values.

[0207] 1: Pixel, 1a: High-intensity pixel, 1b: Low-intensity pixel, 2: Pixel array, 3: Control circuit, 4: Vertical drive circuit, 5: Column signal processing circuit, 6: Horizontal drive circuit, 7: Output circuit, 8: Vertical signal line, 9: Horizontal signal line, 11: Substrate, 12: Interlayer insulating film, 13: Multilayer wiring structure, 13a: Wiring layer, 13b: Wiring layer, 13c: Wiring layer, 14: Filter layer, 15: Lens layer, 21: Lower electrode, 21a: Lower electrode, 21b: Lower electrode, 22: Dielectric layer, 22a: Dielectric layer, 22b: Dielectric layer, 23: Upper electrode, 23a: Upper electrode, 23b: Upper electrode, 24: Trench wiring layer, 24a: Trench wiring, 24b: Trench wiring, 24c: Trench wiring 31: wiring layer, 31a: wiring, 31b: wiring, 31c: wiring, 31d: wiring, 32: via plug layer, 32a: via plug, 32a': via plug, 32b: via plug, 32b': via plug, 32c: via plug, 32d: via plug, 33: wiring layer, 33a: wiring, 33a': wiring, 33b: wiring, 33b': wiring, 33c: wiring, 33d: wiring, 41: lower wiring layer, 41a: lower wiring, 42: upper wiring layer, 42a: upper wiring, 51: connection wiring layer, 51a: connection wiring

Claims

1. A solid-state imaging device comprising: a substrate including a photoelectric conversion section and a charge storage section; a charge transfer section provided on the substrate; an insulating film provided on the substrate and the charge transfer section; and a multilayer wiring structure provided in the insulating film, wherein the multilayer wiring structure includes: a first capacitor provided in a first pixel of a plurality of pixels; and a shielding layer provided between the first pixel and a second pixel of the plurality of pixels.

2. A solid-state imaging device as described in claim 1, wherein the first capacitor includes a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer.

3. The solid-state imaging device according to claim 1, wherein the shield layer is formed of one or more wiring layers and / or one or more via plug layers included in the multilayer wiring structure.

4. The solid-state imaging device according to claim 1, wherein the shielding layer includes wiring extending between two or more pixels including the first pixel and two or more pixels including the second pixel.

5. The solid-state imaging device according to claim 4, wherein said shielding layer further includes a plurality of via plugs provided on the upper or lower surface of said wiring.

6. The solid-state imaging device of claim 1, wherein the multilayer wiring structure includes, as the shielding layer, a first shielding layer provided between the first pixel and the second pixel and extending in a first direction, and the multilayer wiring structure further includes a second shielding layer provided between the first pixel and a third pixel of the plurality of pixels and extending in a second direction different from the first direction.

7. The solid-state imaging device according to claim 1, wherein the shield layer includes a lower wiring having an upper surface facing the lower surface of the first lower electrode.

8. The solid-state imaging device according to claim 1, wherein the shield layer includes an upper wiring having a lower surface facing the upper surface of the first upper electrode.

9. The solid-state imaging device according to claim 1, wherein the multilayer wiring structure further includes a second capacitor provided within the first pixel and electrically connected to the first capacitor, the first capacitor being supplied with a drive voltage and signal charges, and the second capacitor being supplied with a ground voltage.

10. The solid-state imaging device according to claim 1, wherein said multilayer wiring structure further includes a switch provided in said first pixel and arranged in parallel with said first capacitor.

11. A solid-state imaging device comprising: a substrate including a photoelectric conversion section and a charge accumulation section; a charge transfer section provided on the substrate; an insulating film provided on the substrate and the charge transfer section; and a multilayer wiring structure provided in the insulating film, the multilayer wiring structure including: a first capacitor provided in a first pixel of a plurality of pixels and supplied with a drive voltage and signal charge; and a second capacitor provided in the first pixel, electrically connected to the first capacitor, and supplied with a ground voltage.

12. A solid-state imaging device as described in claim 11, wherein the first capacitor includes a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and the second capacitor includes a second lower electrode, a second dielectric layer provided on the second lower electrode, and a second upper electrode provided on the second dielectric layer.

13. The solid-state imaging device according to claim 12, wherein the first upper electrode of the first capacitor is supplied with the drive voltage, and the first lower electrode of the first capacitor is supplied with the signal charge.

14. The solid-state imaging device according to claim 12, wherein the second upper electrode or the second lower electrode of the second capacitor is supplied with the ground voltage.

15. The solid-state imaging device of claim 12, wherein the second lower electrode of the second capacitor is electrically connected to the first lower electrode of the first capacitor, or the second upper electrode of the second capacitor is electrically connected to the first upper electrode of the first capacitor.

16. The solid-state imaging device according to claim 11, wherein the multilayer wiring structure further includes a switch provided in the first pixel and arranged in parallel with the first capacitor.

17. A solid-state imaging device comprising: a substrate including a photoelectric conversion section and a charge storage section; a charge transfer section provided on the substrate; an insulating film provided on the substrate and the charge transfer section; and a multilayer wiring structure provided in the insulating film, wherein the multilayer wiring structure includes: a first capacitor provided in a first pixel of a plurality of pixels; and a switch provided in the first pixel and arranged in parallel with the first capacitor.

18. A solid-state imaging device as described in claim 17, wherein the first capacitor includes a first lower electrode, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer.

19. The solid-state imaging device according to claim 18, wherein the switch is capable of electrically connecting the first lower electrode and the first upper electrode.

20. The solid-state imaging device according to claim 17, wherein the switch is capable of switching between three values.

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