Electronic device

Abstract

This electronic device comprises: a base substrate; power source lines; a pixel unit including pixels, each including a light-emitting element; contact electrodes, each surrounding the light-emitting element and being disposed in a non-light-emitting area; an interlayer insulating layer disposed between the power source lines and the contact electrodes; and a gap insulating layer which is disposed on the interlayer insulating layer, and which includes grooves that overlap the non-light-emitting area, each exposing at least some of the contact electrodes, wherein a second electrode included in the pixels is connected to the contact electrodes in an area overlapping the grooves, and the contact electrodes are connected to the power source lines through a contact hole passing through the interlayer insulating layer.

Description

electronic devices

[0001] The present invention relates to electronic devices, and more particularly, to electronic devices with improved display quality.

[0002] Electronic devices that typically provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include electronic devices for displaying images. These devices generate images and display them to users via a display screen.

[0003] An electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0004] Large-scale electronic devices such as tablets and smart televisions may experience differences in the driving voltages delivered to each pixel, and a design that compensates for this may be required.

[0005] The present invention aims to provide an electronic device capable of providing a uniform driving voltage to pixels in an electronic device.

[0006] An electronic device according to an embodiment of the present invention comprises: a base substrate including a display area and a non-display area, the display area including light-emitting areas and a non-light-emitting area disposed between the light-emitting areas; power lines disposed on the base substrate and overlapping the display area; pixel units including pixels, each pixel including a light-emitting element including a first electrode, a second electrode disposed on the first electrode, and a common layer disposed between the first electrode and the second electrode; contact electrodes each surrounding the light-emitting element and disposed in the non-light-emitting area; an interlayer insulating layer disposed between the power lines and the contact electrodes; and a interlayer insulating layer disposed on the interlayer insulating layer, the interlayer insulating layer overlapping the non-light-emitting area and including grooves each exposing at least a portion of the contact electrode, wherein the second electrode is connected to the contact electrode in an area overlapping the groove, and the contact electrode is connected to the power line through a contact hole penetrating the interlayer insulating layer.

[0007] The light-emitting element may further include a first sealing layer and a second sealing layer that cover the light-emitting element and contact each other in the light-emitting areas and the non-light-emitting area, and the first sealing layer and the second sealing layer may be characterized by including an inorganic material.

[0008] The device may further include a pixel defining film comprising an inorganic material, wherein openings exposing at least a portion of each of the first electrodes are defined, a via insulating layer disposed between the interlayer insulating layer and the pixel defining film and comprising an organic material, and a protective layer disposed on the second electrodes, wherein the via insulating layer, the pixel defining film, the common layer, the second electrode, and the protective layer are characterized in that they are disconnected within the groove.

[0009] The encapsulation region, which overlaps the non-emitting region and is disposed between the adjacent light-emitting elements among the pixel-defining film, may be exposed by the common layer, the second electrode, the protective layer, and the first encapsulation layer, and the pixel-defining film in the encapsulation region may be in contact with the second encapsulation layer.

[0010] The lower portion of the above-mentioned bag region may be characterized in that the interlayer insulating layer is not disposed and the interlayer insulating layer is disposed.

[0011] The side of the contact electrode adjacent to the light-emitting region may be exposed from the insulating layer between the contact electrodes by a groove, and the second electrode may be characterized in that it contacts the exposed side.

[0012] The above side surface may have a predetermined curvature, and the contact electrodes may be characterized by including molybdenum.

[0013] It may be characterized in that it comprises a first pattern layer and a second pattern layer sequentially laminated on the interlayer insulating layer and overlapping the contact electrodes, and the first pattern layer and the second pattern layer include different inorganic materials.

[0014] A portion of the first pattern layer may be characterized as being exposed from the second pattern layer.

[0015] The common layer may be characterized in that it contacts a portion and a side surface of the first pattern layer and a side surface of the second pattern layer within the groove.

[0016] A portion of the insulating layer adjacent to the groove and disposed in the non-luminous region may protrude in a direction toward the luminous region more than the contact electrode, and a trench groove may be defined such that the portion protrudes upward to define a predetermined internal space.

[0017] The method may further include a dam pattern overlapping the non-luminous region and surrounding at least a portion of the luminous region, wherein the dam pattern includes a first pattern disposed on the pixel defining film and a second pattern disposed on the first pattern.

[0018] The first pattern and the second pattern may include different inorganic materials, and the thickness of the first pattern may be greater than the thickness of the second pattern, and the width of the first pattern may be smaller than the width of the second pattern.

[0019] The common layer, the second electrode, and the protective layer arranged in the non-luminous region may be disconnected by the dam pattern, and the dam pattern may be covered by the first sealing layer and the second sealing layer.

[0020] A portion of the upper surface of the contact electrode may be exposed from the insulating layer between the grooves, and the second electrode may be characterized in that it contacts the exposed upper surface.

[0021] The above contact electrode may include first to third conductive layers sequentially laminated on the interlayer insulating layer, wherein the first conductive layer and the third conductive layer include titanium, and the second conductive layer includes aluminum.

[0022] Among the side surfaces of the insulating layer defining the groove, the side overlapping the non-luminous region may be characterized by having a predetermined curvature.

[0023] The device may further include a pixel defining film comprising an inorganic material and disposed on the interlayer insulating layer, wherein openings exposing at least a portion of each of the first electrodes are defined, and an auxiliary electrode disposed on the interlayer insulating layer in the non-emitting region and covered by the pixel defining film, wherein the auxiliary electrode is connected to the contact electrode through a contact hole defined in the pixel defining film.

[0024] It may be characterized in that a portion of the upper surface of the contact electrode is exposed from the insulating layer between the grooves, and a portion of the common layer is disposed on the upper surface exposed within the grooves.

[0025] The second electrode may be disposed on the part of the common layer within the groove, and a side of the auxiliary electrode adjacent to the light-emitting region may be in contact with the second electrode.

[0026] The auxiliary electrode may be characterized by including the same material as the first electrode.

[0027] The pixels may include a first pixel, a second pixel, and a third pixel that provide light of different colors, and the light-emitting regions may include a first light-emitting region that overlaps the first pixel and provides red light, a second light-emitting region that overlaps the second pixel and is spaced apart from the first light-emitting region along a first direction and extends along a second direction intersecting the first direction and provides blue light, and a third light-emitting region that overlaps the third pixel and is spaced apart from the first light-emitting region along the second direction and provides green light, and an area of ​​the first light-emitting region may be smaller than an area of ​​the second light-emitting region and larger than an area of ​​the third light-emitting region.

[0028] The pixels include a first pixel, a first pixel, a second pixel, and a third pixel that provide light of different colors, and the light-emitting regions include a first light-emitting region that overlaps the first pixel and provides green light, a first light-emitting region that overlaps the first pixel and is spaced apart from the first light-emitting region along a first direction and provides the green light, a second light-emitting region that overlaps the second pixel and is spaced apart from the first light-emitting region along a diagonal direction of each of the first light-emitting region and the first light-emitting region and provides red light, and a third light-emitting region that overlaps the third pixel and is spaced apart from the second light-emitting region along a second direction intersecting the first direction and provides blue light, and each of the first to third light-emitting regions may be characterized in that it has a rhombus shape.

[0029] One of the pixels may include sub-pixels that provide light of different colors, and one contact electrode may be characterized in that it surrounds the sub-pixels included in the pixel.

[0030] According to an embodiment of the present invention, by individually contacting each pixel within a display area with a power supply wire that provides a driving voltage and a light-emitting element, a constant driving voltage can be provided regardless of the size / area of ​​the display area. Accordingly, an electronic device with improved reliability can be provided. In addition, an electronic device with reduced unnecessary area in the non-display area can be provided.

[0031] FIG. 1A is a perspective view of an electronic device according to one embodiment of the present invention.

[0032] FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention.

[0033] Figure 2 is a cross-sectional view of an electronic device according to one embodiment of the present invention.

[0034] Figure 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0035] FIG. 4a is a block diagram of a display module according to one embodiment of the present invention.

[0036] Figure 4b is an equivalent circuit of one of the pixels illustrated in Figure 4a.

[0037] FIG. 5a is a plan view of a pixel unit according to one embodiment of the present invention.

[0038] Figure 5b is a plan view of a pixel according to one embodiment of the present invention.

[0039] FIG. 5c is a plan view of a pixel unit according to one embodiment of the present invention.

[0040] Figure 6 is a cross-sectional view taken along line I-I' of Figure 5a.

[0041] Figure 7a is an enlarged cross-sectional view of area AA' of Figure 6.

[0042] FIG. 7b is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0043] FIG. 7c is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0044] FIG. 7d is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0045] Fig. 8 is a cross-sectional view taken along line II-II' of Fig. 5a.

[0046] Fig. 9 is a cross-sectional view taken along line III-III' of Fig. 5a.

[0047] FIGS. 10A to 10K are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention.

[0048] FIGS. 11A to 11G are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention.

[0049] FIG. 12A is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0050] FIG. 12b is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0051] FIGS. 13A to 13G are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention.

[0052] Figure 14 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0053] FIGS. 15A to 15I are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention.

[0054] Fig. 16 is a cross-sectional view of a light emitting element according to one embodiment of the present invention.

[0055] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0056] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0057] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0058] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0059] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0061] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0062] FIG. 1A is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 1B is a block diagram of an electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of an electronic device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 4A is a block diagram of a display module according to an embodiment of the present invention. FIG. 4B is an equivalent circuit of one of the pixels illustrated in FIG. 4A.

[0063] Referring to FIG. 1A, an electronic device (DD) according to an embodiment of the present invention may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). The corners of the electronic device (DD) connecting the long sides and the short sides may have a curved shape. The corners of the electronic device (DD) having a curved shape may be defined as rounded corners. The shape of the electronic device (DD) may be defined as a rounded corner rectangle. However, this is only one example of the shape of the electronic device (DD) and is not limited to a rounded corner rectangle.

[0064] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0065] The front surface of the electronic device (DD) may be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) may be provided to a user through the display surface (DS).

[0066] A display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the edge or periphery of the display area (DA). The display area (DA) may display an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) may define a border of the electronic device (DD) that surrounds the display area (DA) and is printed in a predetermined color.

[0067] The display area (DA) may have a rounded-corner rectangular shape, depending on the shape of the electronic device (DD). For example, the display area (DA) may include rectangular sides extending in a first direction (DR1) and a second direction (DR2) and rounded corners connecting the sides. Of the four sides, the sides extending in the first direction (DR1) may be defined as long sides, and of the four sides, the sides extending in the second direction (DR2) may be defined as short sides.

[0068] An electronic device (DD) can detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) can detect a first input by a touch pen (PEN) and a second input by a touch (TC). The touch pen (PEN) can be defined as an input device.

[0069] A touch pen (PEN) may be an active pen that outputs signals. The second input by touch (TC) may include various forms of external input, such as a part of the user's body, light, heat, or pressure.

[0070] The electronic device (DD) and the touch pen (PEN) can communicate bidirectionally. The electronic device (DD) can provide an uplink signal to the touch pen (PEN). For example, the uplink signal may include, but is not limited to, information such as panel information and protocol version.

[0071] The touch pen (PEN) can provide a downlink signal to the electronic device (DD). The downlink signal may include a synchronization signal or status information of the touch pen (PEN). For example, the downlink signal may include, but is not limited to, coordinate information of the touch pen (PEN), battery information of the touch pen (PEN), tilt information of the touch pen (PEN), and / or various information stored in the touch pen (PEN).

[0072] The electronic device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Furthermore, the electronic device (DD) can also be used in small and medium-sized electronic devices such as personal computers, laptops, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented as exemplary embodiments only, and the electronic device (DD) can be used in other electronic devices without departing from the scope of the present invention.

[0073] FIG. 1B illustrates a block diagram of an electronic device (DD) according to one embodiment. Referring to FIG. 1B, the electronic device (DD) outputs various information through a display module (DM) within an operating system. When the processor (110) executes an application stored in the memory (120), the display module (DM) provides application information to the user through a display panel (DP).

[0074] The processor (110) obtains external input through the input module (130) or the sensor module (161) and executes an application corresponding to the external input. For example, when a user selects a camera icon displayed on the display panel (DP), the processor (110) obtains the user input through the input sensor (161-2) and activates the camera module (171). The processor (110) transmits image data corresponding to the captured image obtained through the camera module (171) to the display module (DM). The display module (DM) can display an image corresponding to the captured image through the display panel (DP).

[0075] As another example, when personal information authentication is performed in the display module (DM), the fingerprint sensor (161-1) acquires the input fingerprint information as input data. The processor (110) compares the input data acquired through the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and executes an application based on the comparison result. The display module (DM) can display the information executed according to the application's logic through the display panel (DP).

[0076] As another example, when a music streaming icon displayed on a display module (DM) is selected, the processor (110) acquires user input through an input sensor (161-2) and activates a music streaming application stored in a memory (120). When a music execution command is input from the music streaming application, the processor (110) activates an audio output module (163) to provide the user with audio information corresponding to the music execution command.

[0077] Above, the operation of the electronic device (DD) has been briefly described. Below, the configuration of the electronic device (DD) is described in detail. Some of the configurations of the electronic device (DD) described below may be integrated and provided as a single configuration, or one configuration may be provided as two or more separate configurations.

[0078] Referring to FIG. 1B, the electronic device (DD) may communicate with an external electronic device (102) via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (DD) may include a processor (110), a memory (120), an input module (130), a display module (DM), a power module (150), a built-in module (160), and an external module (170). According to one embodiment, the electronic device (DD) may omit at least one of the above-described components, or may have one or more other components added. According to one embodiment, some of the above-described components (e.g., the sensor module (161), the antenna module (162), or the audio output module (163)) may be integrated into another component (e.g., the display module (DM)).

[0079] The processor (110) may execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (DD) connected to the processor (110) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (110) may store commands or data received from other components (e.g., an input module (130), a sensor module (161), or a communication module (173)) in a volatile memory (121), process the commands or data stored in the volatile memory (121), and store the resulting data in a non-volatile memory (122).

[0080] The processor (110) may include a main processor (111) and a secondary processor (112). The main processor (111) may include one or more of a central processing unit (CPU: central processing unit) (111-1) or an application processor (AP: application processor). The main processor (111) may further include one or more of a graphic processing unit (GPU: graphic processing unit) (111-2), a communication processor (CP: communication processor), and an image signal processor (ISP: image signal processor). The main processor (111) may further include a neural network processing unit (NPU: neural processing unit) (111-3). The neural network processing unit is a processor specialized in processing artificial intelligence models, and the artificial intelligence models can be generated through machine learning. The artificial intelligence models may include a plurality of artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), deep Q-networks, or a combination of two or more of the above, but is not limited to the examples described above. In addition to or as an alternative to the hardware structure, the artificial intelligence model may include a software structure. At least two of the processing units and processors described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0081] The auxiliary processor (112) may include a controller (112-1). The controller (112-1) may include an interface conversion circuit and a timing control circuit. The controller (112-1) receives a video signal from the main processor (111), converts the data format of the video signal to conform to the interface specifications with the display module (DM), and outputs the video data. The controller (112-1) may output various control signals necessary for driving the display module (DM).

[0082] The auxiliary processor (112) may further include a data conversion circuit (112-2), a gamma correction circuit (112-3), a rendering circuit (112-4), etc. The data conversion circuit (112-2) may receive image data from the controller (112-1) and compensate for the image data so that the image is displayed at a desired luminance according to the characteristics of the electronic device (DD) or the user's settings, or may convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit (112-3) may convert the image data or the gamma reference voltage so that the image displayed on the electronic device (DD) has a desired gamma characteristic. The rendering circuit (112-4) may receive image data from the controller (112-1) and render the image data in consideration of the pixel layout of the display panel (DP) applied to the electronic device (DD). At least one of the data conversion circuit (112-2), the gamma correction circuit (112-3), and the rendering circuit (112-4) may be integrated into another component (e.g., the main processor (111) or the controller (112-1)). At least one of the data conversion circuit (112-2), the gamma correction circuit (112-3), and the rendering circuit (112-4) may also be integrated into a data driving unit (DDV) described later.

[0083] The memory (120) can store various data used by at least one component of the electronic device (DD) (e.g., a processor (110) or a sensor module (161)) and input data or output data for commands related thereto. The memory (120) can include at least one of a volatile memory (121) and a non-volatile memory (122).

[0084] The input module (130) can receive commands or data to be used for components of the electronic device (DD) (e.g., a processor (110), a sensor module (161), or an audio output module (163)) from an external source of the electronic device (DD) (e.g., a user or an external electronic device (102)).

[0085] The input module (130) may include a first input module (131) for inputting a command or data from a user and a second input module (132) for inputting a command or data from an external electronic device (102). The first input module (131) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (132) may support a designated protocol that may be connected to the external electronic device (102) by wire or wirelessly. According to one embodiment, the second input module (132) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (132) may include a connector that may be physically connected to the external electronic device (102), for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0086] A display module (DM) provides visual information to a user. The display module (DM) may include a display panel (DP), a scan driver (SDC), and a data driver (DDV). The display module (DM) may further include a window, a chassis, and a bracket to protect the display panel (DP).

[0087] The display panel (DP) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel (DP) is not particularly limited. The display panel (DP) may be of a rigid type or of a flexible type that can be rolled or folded. The display module (DM) may further include a supporter, a bracket, or a heat dissipation member that supports the display panel (DP).

[0088] The scan driver (SDC) can be mounted on the display panel (DP) as a driver chip. In addition, the scan driver (SDC) can be integrated into the display panel (DP). For example, the scan driver (SDC) can include an Amorphous Silicon TFT Gate driver circuit (ASG), a Low Temperature Polycrystalline Silicon (LTPS) TFT Gate driver circuit, or an Oxide Semiconductor TFT Gate driver circuit (OSG) built into the display panel (DP). The scan driver (SDC) receives a control signal from the controller (112-1) and outputs scan signals to the display panel (DP) in response to the control signal.

[0089] The display panel (DP) may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel (DP) in response to a control signal received from the controller (112-1). The light-emitting driver may be formed separately from the scan driver (SDC) or may be integrated into the scan driver (SDC).

[0090] The data drive unit (DDV) receives a control signal from the controller (112-1), converts image data into analog voltages (e.g., data voltages) in response to the control signal, and then outputs the data voltages to the display panel (DP).

[0091] The data driver (DDV) may be integrated into another component (e.g., the controller (112-1)). The functions of the interface conversion circuit and timing control circuit of the controller (112-1) described above may also be integrated into the data driver (DDV).

[0092] The display module (DM) may further include a light emitting driver and a voltage generation circuit. The voltage generation circuit may output various voltages required to drive the display panel (DP).

[0093] The power module (150) supplies power to components of the electronic device (DD). The power module (150) may include a battery that charges a power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (150) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and those described below. The power module (150) may include a wireless power transmitting / receiving member electrically connected to the battery. The wireless power transmitting / receiving member may include a plurality of coil-shaped antenna radiators.

[0094] The electronic device (DD) may further include a built-in module (160) and an external module (170). The built-in module (160) may include a sensor module (161), an antenna module (162), and an audio output module (163). The external module (170) may include a camera module (171), a light module (172), and a communication module (173).

[0095] The sensor module (161) can detect input by the user's body or input by a pen among the first input modules (131), and generate an electric signal or data value corresponding to the input. The sensor module (161) can include at least one of a fingerprint sensor (161-1), an input sensor (161-2), and a digitizer (161-3).

[0096] The fingerprint sensor (161-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (161-1) can include either an optical or capacitive fingerprint sensor.

[0097] The input sensor (161-2) can generate data values ​​corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (161-2) generates a data value based on the amount of change in electrostatic capacity due to the input. The input sensor (161-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0098] The input sensor (161-2) can also measure bio-signals such as blood pressure, moisture, or body fat. For example, when a user touches a part of his or her body to the sensor layer or sensing panel and remains motionless for a certain period of time, the input sensor (161-2) can detect the bio-signal based on the change in the electric field caused by the part of his or her body and output the information desired by the user to the display module (DM).

[0099] The digitizer (161-3) can generate data values ​​corresponding to coordinate information input by the pen. The digitizer (161-3) generates the electromagnetic change amount due to the input as a data value. The digitizer (161-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0100] At least one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) may be implemented as a sensor layer formed on the display panel (DP) through a continuous process. The fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) may be arranged on the upper side of the display panel (DP), and any one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3), for example, the digitizer (161-3), may be arranged on the lower side of the display panel (DP).

[0101] At least two of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) may be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel may be arranged between the display panel (DP) and a window arranged on an upper side of the display panel (DP). According to one embodiment, the sensing panel may be arranged on the window, and the position of the sensing panel is not particularly limited.

[0102] At least one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) can be built into the display panel (DP). That is, at least one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) can be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (DP).

[0103] In addition, the sensor module (161) can generate an electrical signal or data value corresponding to an internal or external state of the electronic device (DD). The sensor module (161) may further include, for example, a gesture sensor, a gyro sensor, a pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0104] The antenna module (162) may include one or more antennas for transmitting or receiving signals or power to or from the outside. According to one embodiment, the communication module (173) may transmit signals to or receive signals from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (162) may be integrated into one component of the display module (DM) (e.g., a display panel (DP)) or an input sensor (161-2).

[0105] The audio output module (163) is a device for outputting audio signals to the outside of the electronic device (DD), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for phone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The audio output pattern of the audio output module (163) may also be integrated into the display module (DM).

[0106] The camera module (171) can capture still images and videos. According to one embodiment, the camera module (171) may include one or more lenses, image sensors, or image signal processors. The camera module (171) may further include an infrared camera capable of measuring the presence or absence of a user, the user's location, the user's line of sight, etc.

[0107] The light module (172) can provide light. The light module (172) can include a light-emitting diode or a xenon lamp. The light module (172) can operate in conjunction with the camera module (171) or can operate independently.

[0108] The communication module (173) can support the establishment of a wired or wireless communication channel between the electronic device (DD) and the external electronic device (102), and the performance of communication through the established communication channel. The communication module (173) can include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module such as a local area network (LAN) communication module or a power line communication module. The communication module (173) can communicate with the external electronic device (102) through a short-range communication network such as Bluetooth, WiFi direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN). The various types of communication modules (173) described above can be implemented as one chip or can be implemented as separate chips.

[0109] The input module (130), sensor module (161), camera module (171), etc. can be used to control the operation of the display module (DM) in conjunction with the processor (110).

[0110] The processor (110) outputs a command or data to the display module (DM), the audio output module (163), the camera module (171), or the light module (172) based on the input data received from the input module (130). For example, the processor (110) may generate image data corresponding to input data applied through a mouse or an active pen, etc., and output the image data to the display module (DM), or generate command data corresponding to the input data, and output the command data to the camera module (171) or the light module (172). When no input data is received from the input module (130) for a certain period of time, the processor (110) may reduce the power consumed by the electronic device (DD) by switching the operation mode of the electronic device (DD) to a low-power mode or a sleep mode.

[0111] The processor (110) outputs a command or data to the display module (DM), the audio output module (163), the camera module (171), or the light module (172) based on the sensing data received from the sensor module (161). For example, the processor (110) may compare the authentication data authorized by the fingerprint sensor (161-1) with the authentication data stored in the memory (120), and then execute an application based on the comparison result. The processor (110) may execute a command or output corresponding image data to the display module (DM) based on the sensing data detected by the input sensor (161-2) or the digitizer (161-3). When the sensor module (161) includes a temperature sensor, the processor (110) may receive temperature data on the temperature measured from the sensor module (161) and further perform brightness correction, etc. on the image data based on the temperature data.

[0112] The processor (110) can receive measurement data regarding the presence or absence of a user, the user's location, the user's line of sight, etc. from the camera module (171). The processor (110) can further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor (110) that determines the presence or absence of a user through input from the camera module (171) can output the brightness-corrected image data to the display module (DM) through the data conversion circuit (112-2) or the gamma correction circuit (112-3).

[0113] Some of the above components may be interconnected with each other through a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (110) may communicate with the display module (DM) through a mutually agreed upon interface, and may use, for example, any one of the above-described communication methods, and is not limited to the above-described communication methods.

[0114] The electronic device (DD) according to various embodiments disclosed in this document may be a device of various forms. The electronic device (DD) may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device (DD) according to the embodiments of this document is not limited to the aforementioned devices.

[0115] Fig. 2 is a drawing illustrating a cross-section of the electronic device illustrated in Fig. 1a. Fig. 2 illustrates a cross-section of the electronic device (DD) as viewed from a second direction (DR2). Some of the components of the electronic device (DD) described in Fig. 1b are omitted in Fig. 2.

[0116] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensor (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2). The input sensor (ISP) illustrated in FIG. 2 may have the same configuration as the input sensor (161-2) described in FIG. 1B.

[0117] The display panel (DP) according to one embodiment of the present invention may be an emissive display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0118] An input sensor (ISP) may be disposed on a display panel (DP). The input sensor (ISP) may include a plurality of sensing units (not shown) for sensing an external input in a capacitive manner. The input sensor (ISP) may be manufactured directly on the display panel (DP) during the manufacturing of the electronic device (DD). Therefore, the input sensor (ISP) according to one embodiment may be directly disposed on the display panel (DP). However, the present invention is not limited thereto, and the input sensor (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) by an adhesive layer.

[0119] An anti-reflection layer (RPL) may be disposed on the input sensor (ISP). The anti-reflection layer (RPL) may be manufactured directly on the input sensor (ISP) during the manufacturing of the electronic device (DD). However, this is not limited to the above, and the anti-reflection layer (RPL) may be manufactured as a separate panel and attached to the input sensor (ISP) using an adhesive layer.

[0120] An anti-reflection layer (RPL) can be defined as an external light anti-reflection film. The RPL can reduce the reflectance of external light incident from above the electronic device (DD) toward the display panel (DP). The RPL can prevent the external light from being perceived by the user.

[0121] When external light directed toward the display panel (DP) is reflected by the display panel (DP) and re-exposed to an external user, the user may perceive the external light as a mirror. To prevent this phenomenon, for example, the anti-reflection layer (RPL) may include a plurality of color filters that display the same color as the pixels of the display panel (DP).

[0122] Color filters can filter external light to the same color as the pixels. In this case, the external light may not be visible to the user. However, the present invention is not limited thereto, and the anti-reflection layer (RPL) may include a phase retarder and / or a polarizer to reduce the reflectance of external light.

[0123] The window (WIN) can be placed on an anti-reflection layer (RPL). The window (WIN) can protect the display panel (DP), the input sensor (ISP), and the anti-reflection layer (RPL) from external scratches and impacts.

[0124] A panel protection film (PPF) may be placed under the display panel (DP). The panel protection film (PPF) may protect the lower portion of the display panel (DP). The panel protection film (PPF) may include a flexible plastic material such as polyethylene terephthalate (PET).

[0125] A first adhesive layer (AL1) is disposed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded to each other by the first adhesive layer (AL1). A second adhesive layer (AL2) is disposed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded to each other by the second adhesive layer (AL2).

[0126] Fig. 3 is a drawing illustrating a cross-section of the display panel illustrated in Fig. 2. As an example, Fig. 3 illustrates a cross-section of the display panel (DP) as viewed from the second direction (DR2).

[0127] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0128] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A display element layer (DP-OLED) may be disposed on the display area (DA).

[0129] A plurality of pixels may be arranged on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor arranged on the circuit element layer (DP-CL) and a light-emitting element arranged on the display element layer (DP-OLED) and connected to the transistor.

[0130] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) may protect pixels from moisture, oxygen, and external foreign substances. The thin film encapsulation layer (TFE) may include inorganic layers and organic layers. The organic layer may be disposed between the inorganic layers to be sealed from the inorganic layers, thereby providing a flat surface. According to one embodiment, the organic layer may be disposed on the inorganic layers or may be omitted, and is not limited to any one embodiment.

[0131] FIG. 4a is a block diagram of the electronic device illustrated in FIG. 1a.

[0132] Referring to FIG. 4a, the electronic device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDC), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG).

[0133] The display panel (DP) may include a plurality of scanning lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), a plurality of light emitting lines (EML1 to EMLm), a plurality of data lines (DL1 to DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0134] The pixels (PX) can be electrically connected to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), emission lines (EML1 to EMLm), and data lines (DL1 to DLn), respectively. Each of the pixels (PX) can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission line.

[0135] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) may include a plurality of initialization scan lines (GIL1 to GILm), a plurality of compensation scan lines (GCL1 to GCLm), a plurality of write scan lines (GWL1 to GWLm), and a plurality of bias scan lines (GBL1 to GBLm).

[0136] Each of the pixels (PX) can be connected to a corresponding one of the initialization scan lines (GIL1 to GILm), a corresponding one of the compensation scan lines (GCL1 to GCLm), a corresponding one of the write scan lines (GWL1 to GWLm), and a corresponding one of the bias scan lines (GBL1 to GBLm).

[0137] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) are connected to a scan driver (SDC), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The light emitting lines (EML1 to EMLm) are connected to a light emitting driver (EDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The data lines (DL1 to DLn) are connected to a data driver (DDV), extend in a second direction (DR2), and can be arranged in a first direction (DR1).

[0138] The scan driver (SDC), the emission driver (EDV), and the data driver (DDV) can be substantially arranged on the display panel (DP), and this configuration will be illustrated in FIG. 8 below.

[0139] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can also receive an enable signal (MFD_EN). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to conform to the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0140] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0141] The scan driver (SDC) can receive a scan control signal (SCS) from a timing controller (TC). The scan driver (SDC) can output scan signals to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm).

[0142] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from a timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to the pixels (PX) through data lines (DL1 to DLn).

[0143] The emission driver (EDV) can receive an emission control signal (ECS) from a timing controller (TC). The emission driver (EDV) can output emission signals to the emission lines (EML1 to EMLm) in response to the emission control signal (ECS). The emission signals can be applied to the pixels (PX) through the emission lines (EML1 to EMLm).

[0144] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission signals.

[0145] FIG. 4b is a diagram showing an equivalent circuit of one of the pixels illustrated in FIG. 4a.

[0146] For example, FIG. 4b illustrates a pixel (PXij) connected to the jth data line (DLj), the ith scan lines (GWLi, GCLi, GILi, GBLi), and the ith emission line (EMLi). i and j are natural numbers.

[0147] Referring to FIG. 4b, a pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) may drive the light-emitting element (OLED).

[0148] The pixel circuit (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) may control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) may generate light having a predetermined brightness depending on the amount of current supplied.

[0149] The ith write scan line (GWLi) can receive the ith write scan signal (GWi), the ith compensation scan line (GCLi) can receive the ith compensation scan signal (GCi), the ith initialization scan line (GILi) can receive the ith initialization scan signal (GIi), the ith bias scan line (GBLi) can receive the ith bias scan signal (GBi), and the ith emission line (EMLi) can receive the ith emission signal (EMi).

[0150] A pixel (PXij) can be connected to a j-th data line (DLj), an i-th write scan line (GWLi), an i-th compensation scan line (GCLi), an i-th initialization scan line (GILi), an i-th bias scan line (GBLi), an i-th emission line (EMLi), a first initialization line (VIL1), a second initialization line (VIL2), a bias line (VBL), and first and second power lines (PL1, PL2).

[0151] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0152] Each of the transistors (T1 to T8) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 4b, for convenience, one of the source electrode and the drain electrode is defined as the first electrode, and the other is defined as the second electrode. In addition, the gate electrode is defined as the control electrode.

[0153] The transistors (T1 to T8) may include first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0154] The first transistor (T1) may be defined as a driving transistor, the second transistor (T2) may be defined as a switching transistor, the third transistor (T3) may be defined as a compensation transistor, the fourth transistor (T4) and the seventh transistor (T7) may be defined as initialization transistors, the fifth transistor (T5) and the sixth transistor (T6) may be defined as light-emitting control transistors, and the eighth transistor (T8) may be defined as a bias transistor.

[0155] The light-emitting element (OLED) may be defined as an organic light-emitting element. The light-emitting element (OLED) may include a first electrode (AE) and a second electrode (CE). The first electrode (AE) may receive a first driving voltage (ELVDD) through the sixth, first, and fifth transistors (T6, T1, T5). The first driving voltage (ELVDD) may be applied to the pixel circuit (PC) through the first power line (PL1).

[0156] The second electrode (CE) can receive a second driving voltage (ELVSS) having a lower level than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel circuit (PC) through a second power line (PL2).

[0157] A first transistor (T1) is disposed between a fifth transistor (T5) and a sixth transistor (T6), and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to a first power line (PL1) through the fifth transistor (T5), and to a first electrode (AE) of a light-emitting element (OLED) through the sixth transistor (T6).

[0158] The first transistor (T1) may include a first electrode connected to the first power line (PL1) via a fifth transistor (T5), a second electrode connected to the first electrode (AE) via a sixth transistor (T6), and a control electrode connected to the first node (N1).

[0159] A first electrode of a first transistor (T1) may be connected to a fifth transistor (T5), and a second electrode of the first transistor (T1) may be connected to a sixth transistor (T6). The first transistor (T1) may control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0160] A second transistor (T2) may be disposed between the first transistor (T1) and the j-th data line (DLj) and may be connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0161] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation of providing the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0162] A third transistor (T3) may be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the ith compensation scan line (GCLi).

[0163] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in a diode form (for example, the first transistor (T1) can be connected in a diode form).

[0164] A fourth transistor (T4) may be connected to a first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to a first initialization line (VIL1), and a control electrode connected to an ith initialization scan line (GILi). The fourth transistor (T4) may be turned on by an ith initialization scan signal (GIi) applied through the ith initialization scan line (GILi) and may provide a first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0165] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the ith light emitting line (EMLi).

[0166] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first electrode (AE) of the light-emitting element (OLED), and a control electrode connected to the ith light-emitting line (EMLi).

[0167] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the ith light-emitting signal (EMi) applied through the ith light-emitting line (EMLi). The first driving voltage (ELVDD) is provided to the light-emitting element (OLED) by the turned-on fifth transistor (T5) and sixth transistor (T6), so that a driving current can flow to the light-emitting element (OLED). Therefore, the light-emitting element (OLED) can emit light.

[0168] The seventh transistor (T7) may include a first electrode connected to the first electrode (AE) of the light-emitting element (OLED), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the ith bias scan line (GBLi). The seventh transistor (T7) may be turned on by the ith bias scan signal (GBi) applied through the ith bias scan line (GBLi), and may provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the first electrode (AE) of the light-emitting element (OLED).

[0169] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0170] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when implementing black luminance, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and thus the black expression capability can be improved.

[0171] The capacitor (CST) may include a first electrode connected to a first power line (PL1) and a second electrode connected to a first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing to the first transistor (T1) may be determined according to the voltage stored in the capacitor (CST).

[0172] The eighth transistor (T8) may include a first electrode connected to a bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to an i-th bias scan line (GBLi).

[0173] The eighth transistor (T8) is turned on by the ith bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1). However, the transistors included in the pixel (PXij) are not limited thereto.

[0174] Fig. 5a is a plan view of a pixel unit according to an embodiment of the present invention. Fig. 5b is a plan view of a pixel according to an embodiment of the present invention. Fig. 5c is a plan view of a pixel unit according to an embodiment of the present invention. Fig. 6 is a cross-sectional view taken along line II' of Fig. 5a.

[0175] Referring to FIG. 5a, in the present embodiment, one pixel unit (PXU) may include the pixels described in FIGS. 4a and 4b. The pixel units (PXU) may be provided in plurality and arranged along the first and second directions (DR1, DR2) within the display area (DA) described in FIG. 1a.

[0176] A pixel unit (PXU) according to one embodiment may include first to third pixels (PX-R, PX-B, PX-G). The first pixel (PX-R) may provide red light. Light generated in the first pixel (PX-R) may be provided to a display area (DA, see FIG. 1A) through a first light-emitting area (PXA-R). In the present embodiment, the first light-emitting area (PXA-R) may have a rounded corner square shape.

[0177] The second pixel (PX-B) can provide blue light. The light generated in the second pixel (PX-B) can be provided to the display area (DA, see FIG. 1A) through the second light-emitting area (PXA-B). The second light-emitting area (PXA-B) can be spaced apart from the first light-emitting area (PXA-R) along the first direction (DR1). When viewed in the second direction (DR2), the second light-emitting area (PXA-B) can overlap the first and third light-emitting areas (PXA-R, PXA-G). The second light-emitting area (PXA-B) can have a rounded corner square shape extending along the second direction (DR2).

[0178] The third pixel (PX-G) can provide green light. The light generated from the third pixel (PX-G) can be provided to the display area (DA, see FIG. 1A) through the third emission area (PXA-G). The third emission area (PXA-G) can be spaced apart from the first emission area (PXA-R) along the second direction (DR2) and spaced apart from the second emission area (PXA-B) along the first direction. The third emission area (PXA-G) can have a rounded corner square shape.

[0179] The area between the first to third light-emitting areas (PXA-R, PXA-B, PXA-G) can be defined as a non-light-emitting area (NPXA).

[0180] According to the present invention, first to third contact electrodes (PE-R, PE-B, PE-G) may be included, each surrounding first to third light-emitting regions (PXA-R, PXA-B, PXA-G). Each of the first to third contact electrodes (PE-R, PE-B, PE-G) may overlap a non-light-emitting region (NPXA).

[0181] The first contact electrode (PE-R) may surround the first light-emitting region (PXA-R), the second contact electrode (PE-B) may surround the second light-emitting region (PXA-B), and the third contact electrode (PE-G) may surround the third light-emitting region (PXA-G).

[0182] According to the present embodiment, the first to third contact electrodes (PE-R, PE-B, PE-G) are illustrated as having a closed-line shape surrounding the entire corresponding light-emitting area, but at least one portion may have an open shape, and are not limited to any one embodiment.

[0183] The first contact electrode (PE-R) may be connected to the second electrode (CE-R) included in the first pixel (PX-R) in the non-emitting region (NPXA). The second contact electrode (PE-B) may be connected to the second electrode (CE-B) included in the second pixel (PX-B) in the non-emitting region (NPXA). The third contact electrode (PE-G) may be connected to the second electrode (CE-G) included in the third pixel (PX-G) in the non-emitting region (NPXA). According to the present embodiment, the second electrodes (CE-R, CE-B, CE-G) included in each pixel may be disconnected in the non-emitting region (NPXA). In Fig. 5a, the second electrodes (CE-R, CE-B, CE-G) are illustrated by dotted lines.

[0184] According to the present embodiment, a second power line (PL2, FIG. 4b) that applies a second driving voltage (ELVSS, FIG. 4b) to pixels may extend from a non-display area (NDA, see FIG. 1a) to a display area (DA, see FIG. 1a) and overlap each of the first to third contact electrodes (PE-R, PE-B, PE-G).

[0185] In Fig. 5a, the second power line (PL2, Fig. 4b) arranged within the display area (DA, see Fig. 1a) is illustrated as first to third power lines (ES-R, ES-B, ES-G). According to one embodiment, the first to third power lines (ES-R, ES-B, ES-G) are spaced apart along the first direction (DR1), and each of the first to third power lines (ES-R, ES-B, ES-G) can extend along the second direction (DR2).

[0186] A first power line (ES-R) may overlap a portion of a first contact electrode (PE-R) and be connected through a contact hole (CNT). A second power line (ES-B) may overlap a portion of a second contact electrode (PE-B) and be connected through a contact hole (CNT). A third power line (ES-G) may overlap a portion of a third contact electrode (PE-G) and be connected through a contact hole (CNT). The contact holes (CNT) may be defined in an interlayer insulating layer disposed between the power lines and the contact electrodes.

[0187] According to the present invention, an area between adjacent pixels within a non-emissive area (NPXA) may be defined as an encapsulation area (ENA). The encapsulation area (ENA) may be defined as an area where insulating layers including inorganic materials contact each other. According to the present embodiment, the encapsulation area (ENA) may surround each of the pixels (PX-R, PX-B, PX-G). Accordingly, the pixels (PX-R, PX-B, PX-G) may be individually encapsulated. Accordingly, moisture / oxygen flowing into the pixels (PX-R, PX-B, PX-G) may have their paths blocked by the encapsulation area (ENA). A detailed description thereof will be provided later.

[0188] Unlike the present invention, in a panel in which a second electrode (or cathode) formed in a single pattern, such as a common electrode, is connected to a second power line (PL2, Fig. 4b) and a non-emitting area (NPXA), a problem may occur in which a constant voltage cannot be provided to pixels due to a voltage drop phenomenon.

[0189] According to the present invention, the second electrodes (CE-R, CE-B, CE-G) included in each of the pixels (PX-R, PX-B, PX-G) can be individually disconnected and connected to corresponding first to third contact electrodes (PE-R, PE-B, PE-G). In addition, the first to third contact electrodes (PE-R, PE-B, PE-G) can be individually connected to first to third power lines (ES-R, ES-B, ES-G) through contact holes (CNT).

[0190] Accordingly, a voltage drop phenomenon can be prevented and a constant voltage can be provided to the pixels. Therefore, an electronic device (DD) with improved display quality can be provided. In addition, as in the comparative example, a separate space for connecting the second electrode (or cathode) to the second power line (PL2, FIG. 4b) in the non-display area (NDA, see FIG. 1a) can be omitted, so an electronic device (DD) with a reduced non-display area (NDA, see FIG. 1a) can be provided.

[0191] Referring to FIG. 5b, one pixel (PX-a) may include a plurality of sub-pixels (SPX-1, SPX-2, SPX-3). The pixels (PX-a) may be provided in plurality and arranged spaced apart from each other along the first and second directions (DR1, DR2) in the display area (DA) described in FIG. 1a.

[0192] In this embodiment, three sub-pixels (SPX-1, SPX-2, SPX-3) are included in one pixel (PX-a), but the number, shape, and arrangement of the sub-pixels are not limited thereto.

[0193] Each of the sub-pixels (SPX-1, SPX-2, SPX-3) may include a pixel circuit (PC) described in FIG. 4B and a light-emitting element (OLED) connected to the pixel circuit (PC). The sub-pixels (SPX-1, SPX-2, SPX-3) may generate light of different colors or may form light of the same color, and are not limited to any one embodiment. The light-emitting areas (PXA-1, PXA-2, PXA-3) that provide light generated in the sub-pixels (SPX-1, SPX-2, SPX-3) may have different areas. However, the shape and arrangement of the light-emitting areas (PXA-1, PXA-2, PXA-3) are not limited to any one embodiment.

[0194] According to the present embodiment, the contact electrode (PE-C) may be arranged in the non-display area (NDA) and surround the sub-pixels (SPX-1, SPX-2, SPX-3). The sub-pixels (SPX-1, SPX-2, SPX-3) may include a second electrode (CE-C) that is commonly arranged. The second electrode (CE-C) may be connected to the contact electrode (PE-C) within the non-display area (NDA).

[0195] According to one embodiment, a second power line (PL2, FIG. 4b) that applies a second driving voltage (ELVSS, FIG. 4b) to a pixel may extend from a non-display area (NDA, see FIG. 1a) to a display area (DA, see FIG. 1a) and overlap a contact electrode (PE-C). The power line (ES-C) may be a portion of the second power line (PL2, FIG. 4b) that extends to the display area (DA, see FIG. 1a).

[0196] The power line (ES-C) may overlap a portion of the contact electrode (PE-C) and be connected through a contact hole (CNT). The contact hole (CNT) may be defined in an interlayer insulating layer disposed between the power line (ES-C) and the contact electrode (PE-C). According to the present embodiment, one contact electrode (PE-C) may be connected to one second electrode (CE-C) disposed as a common electrode for the sub-pixels (SPX-1, SPX-2, SPX-3) to provide the same voltage to the sub-pixels (SPX-1, SPX-2, SPX-3).

[0197] Referring to FIG. 5c, in the present embodiment, one pixel unit (PXU-A) may include the pixels described in FIGS. 4a and 4b. The pixel units (PXU-As) may be provided in plurality and arranged along the first and second directions (DR1, DR2) within the display area (DA) described in FIG. 1a.

[0198] A pixel unit (PXU-A) according to one embodiment may include first to third pixels (PX-G1, PX-G2, PX-R, PX-B). The first pixel (PX-G1) may provide green light. Light generated in the first pixel (PX-G1) may be provided to a display area (DA, see FIG. 1A) through the first emission area (PXA-G1). In the present embodiment, the first emission area (PXA-G1) may have a rhombus shape.

[0199] The first-second pixel (PX-G2) can provide the same green light as the first-first pixel (PX-G1). The light generated in the first-second pixel (PX-G2) can be provided to the display area (DA, see FIG. 1A) through the first-second emission area (PXA-G2). The first-second emission area (PXA-G2) can be spaced apart from the first-first emission area (PXA-G1) along the first direction (DR1). In the present embodiment, the first-second emission area (PXA-G2) can have a rhombus shape.

[0200] The second pixel (PX-R) can provide red light. The light generated in the second pixel (PX-R) can be provided to the display area (DA, see FIG. 1A) through the second light-emitting area (PXA-R). The second light-emitting area (PXA-R) can be spaced apart from the third light-emitting area (PXA-G) along the second direction (DR2). The second light-emitting area (PXA-R) can be spaced apart from the first-first light-emitting area (PXA-G1) along the first diagonal direction (CDR1) and can be spaced apart from the first-second light-emitting area (PXA-G2) along the second diagonal direction (CDR2). In the present embodiment, the second light-emitting area (PXA-R) can have a diamond shape.

[0201] The third pixel (PX-B) can provide blue light. The light generated from the third pixel (PX-B) can be provided to the display area (DA, see FIG. 1A) through the third light-emitting area (PXA-G). The third light-emitting area (PXA-G) can be spaced apart from the first-second light-emitting area (PXA-G2) along the first diagonal direction (CDR1) and can be spaced apart from the first-first light-emitting area (PXA-G1) along the second diagonal direction (CDR2). In the present embodiment, the third light-emitting area (PXA-G) can have a rhombus shape.

[0202] According to one embodiment, the area of ​​the second light-emitting region (PXA-R) may be larger than the areas of the first-first and first-second light-emitting regions (PXA-G1, PXA-G1) and smaller than the area of ​​the third light-emitting region (PXA-G).

[0203] The area between the first to third light-emitting areas (PXA-G1, PXA-G2, PXA-R, PXA-B) can be defined as a non-light-emitting area (NPXA).

[0204] According to the present invention, the first to third contact electrodes (PE-G1, PE-G2, PE-R, PE-B) may be included, each surrounding the first to third light-emitting regions (PXA-G1, PXA-G2, PXA-R, PXA-B). Each of the first to third contact electrodes (PE-G1, PE-G2, PE-R, PE-B) may overlap a non-light-emitting region (NPXA).

[0205] The first-first contact electrode (PE-G1) may surround the first-first light-emitting region (PXA-G1), the first-second contact electrode (PE-G2) may surround the first-second light-emitting region (PXA-G2), the second contact electrode (PE-R) may surround the second light-emitting region (PXA-R), and the third contact electrode (PE-G) may surround the third light-emitting region (PXA-G).

[0206] According to the present embodiment, the first to third contact electrodes (PE-G1, PE-G2, PE-R, PE-B) are illustrated as having a closed-line shape surrounding the entire corresponding light-emitting region, but at least one portion may have an open shape, and are not limited to any one embodiment.

[0207] The first-first contact electrode (PE-G1) may be connected to the second electrode (CE-G1) included in the first-first pixel (PX-G1) in the non-emitting region (NPXA). The first-second contact electrode (PE-G2) may be connected to the second electrode (CE-G2) included in the second pixel (PX-G2) in the non-emitting region (NPXA). The second contact electrode (PE-R) may be connected to the second electrode (CE-R) included in the second pixel (PX-R) in the non-emitting region (NPXA). The third contact electrode (PE-G) may be connected to the second electrode (CE-B) included in the third pixel (PX-B) in the non-emitting region (NPXA). According to the present embodiment, the second electrodes (CE-G1, CE-G2, CE-R, CE-B) included in each pixel may be disconnected in the non-emitting region (NPXA). In Fig. 5c, the second electrodes (CE-G1, CE-G2, CE-R, CE-B) are depicted by dotted lines.

[0208] According to the present embodiment, a second power line (PL2, FIG. 4b) that applies a second driving voltage (ELVSS, FIG. 4b) to pixels may extend from a non-display area (NDA, see FIG. 1a) to a display area (DA, see FIG. 1a) and overlap each of the first to third contact electrodes (PE-G1, PE-G2, PE-R, PE-B).

[0209] In Fig. 5c, the second power line (PL2, Fig. 4b) arranged within the display area (DA, see Fig. 1a) is illustrated as the first to third power lines (ES-G1, ES-G2, ES-R, ES-B). According to one embodiment, the first to third power lines (ES-G1, ES-G2, ES-R, ES-B) are spaced apart along the first direction (DR1), and each of the first to third power lines (ES-G1, ES-G2, ES-R, ES-B) may extend along the second direction (DR2).

[0210] The first-first power line (ES-G1) may overlap a portion of the first-first contact electrode (PE-G1) and be connected through a contact hole (CNT). The first-second power line (ES-G2) may overlap a portion of the first-second contact electrode (PE-G2) and be connected through a contact hole (CNT). The second power line (ES-R) may overlap a portion of the second contact electrode (PE-R) and be connected through a contact hole (CNT). The third power line (ES-B) may overlap a portion of the third contact electrode (PE-G) and be connected through a contact hole (CNT). The contact holes (CNT) may be defined in an interlayer insulating layer disposed between the power lines and the contact electrodes.

[0211] According to the present invention, an area between adjacent pixels within a non-emissive area (NPXA) may be defined as an encapsulation area (ENA). The encapsulation area (ENA) may be defined as an area where insulating layers including inorganic materials contact each other. According to the present embodiment, the encapsulation area (ENA) may surround each of the pixels (PX-G1, PX-G2, PX-R, PX-B). Accordingly, the pixels (PX-G1, PX-G2, PX-R, PX-B) may be individually encapsulated. Accordingly, moisture / oxygen flowing into the pixels (PX-G1, PX-G2, PX-R, PX-B) may have their paths blocked by the encapsulation area (ENA). A detailed description thereof will be provided later.

[0212] According to the present invention, the second electrodes (CE-G1, CE-G2, CE-R, CE-B) included in each of the pixels (PX-G1, PX-G2, PX-R, PX-B) can be individually disconnected and connected to the corresponding first to third contact electrodes (PE-G1, PE-G2, PE-R, PE-B). In addition, the first to third contact electrodes (PE-G1, PE-G2, PE-R, PE-B) can be individually connected to the first to third power lines (ES-G1, ES-G2, ES-R, ES-B) through contact holes (CNT).

[0213] Fig. 6 is a cross-sectional view taken along line I-I' of Fig. 5a. Fig. 6 illustrates a cross-sectional view of a portion of a light-emitting element (OLED-R), a first transistor (T1), a fourth transistor (T4), and a sixth transistor (T6) included in the first pixel (PX-R) described in Fig. 4b, as an example. The description of the cross-sectional view can be commonly applied to the pixels (PX-R, PX-B, PX-G) described in Fig. 5a.

[0214] Referring to FIG. 6, a light-emitting element (OLED-R) according to one embodiment may include a first electrode (AE-R), a second electrode (CE-R), and a first common layer (CL-R). The first common layer (CL-R) may include a hole control layer, an electron control layer, and a light-emitting layer.

[0215] A second electrode (CE-R) may be disposed on a first electrode (AE-R), and a first common layer (CL-R) may be disposed between the first electrode (AE-R) and the second electrode (CE-R). The light-emitting element (OLED-R) according to one embodiment may further include a protective layer (CPL) disposed on the second electrode (CE-R). The protective layer (CPL) includes an organic material and may prevent damage to components disposed under the protective layer (CPL) during a subsequent process. According to one embodiment, the protective layer (CPL) may be omitted. According to the present embodiment, components included in the light-emitting element (OLED-R) may be disconnected in a non-emitting region (NPXA).

[0216] The first, fourth, and sixth transistors (T1, T4, T6) and the light-emitting element (OLED-R) may be arranged on the substrate (SUB). The display area (DA) may include a light-emitting area (PXA-R) corresponding to a pixel (PXij, see FIG. 4b) and a non-light-emitting area (NPXA) adjacent to the light-emitting area (PXA-R). The light-emitting element (OLED-R) may be arranged in the non-light-emitting area (NPXA).

[0217] The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE) may be arranged on the substrate (SUB).

[0218] A circuit element layer (DP-CL) may be disposed on a substrate (SUB). The circuit element layer (DP-CL) may include insulating layers and conductive patterns.

[0219] A barrier layer (BRL) may be disposed on a substrate (SUB). The barrier layer (BRL) may increase the bonding strength between the semiconductor pattern included in the transistors and the substrate (SUB). The barrier layer (BRL) may include an inorganic material.

[0220] A metal layer (BML) may be disposed on the barrier layer (BRL). The metal layer (BML) may overlap the first transistor (T1). According to one embodiment, the metal layer (BML) may be applied with a constant voltage. When the constant voltage is applied to the metal layer (BML), the threshold voltage (Vth) value of the first transistor (T1) disposed on the metal layer (BML) may be maintained without change.

[0221] The metal layer (BML) can block light incident on the first transistor (T1) from beneath the metal layer (BML). The metal layer (BML) can include a reflective metal. In one embodiment, the metal layer (BML) can be omitted.

[0222] A buffer layer (BFL) may be disposed on a barrier layer (BRL) and cover a metal layer (BML). The buffer layer (BFL) may include an inorganic material.

[0223] The semiconductor layers (S1, A1, D1) of the first transistor (T1) and the semiconductor layers (S6, A6, D6) of the sixth transistor (T6) may be arranged on the buffer layer (BFL). The semiconductor layers (S1, A1, D1, S6, A6, D6) may include polysilicon. However, the present invention is not limited thereto, and the semiconductor layers (S1, A1, D1, S6, A6, D6) may include amorphous silicon.

[0224] The semiconductor layers (S1, A1, D1, S6, A6, D6) may be doped with an N-type dopant or a P-type dopant. The semiconductor layers (S1, A1, D1, S6, A6, D6) may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region, and may substantially function as a source electrode and a drain electrode of the first and sixth transistors (T1, T6). The low-doping region may substantially correspond to an active (or channel) of the first and sixth transistors (T1, T6).

[0225] The first source region (S1), the first channel region (A1), and the first drain region (D1) of the first transistor (T1) may be formed from semiconductor layers (S1, A1, D1). The sixth source region (S6), the sixth channel region (A6), and the sixth drain region (D6) of the sixth transistor (T6) may be formed from semiconductor layers (S6, A6, D6). The first channel region (A1) may be disposed between the first source region (S1) and the first drain region (D1). The sixth channel region (A6) may be disposed between the sixth source region (S6) and the sixth drain region (D6).

[0226] A first insulating layer (INS1) may be disposed on a buffer layer (BFL) to cover the semiconductor layers (S1, A1, D1, S6, A6, D6). A first gate electrode (G1, or control electrode) of a first transistor (T1) and a sixth gate electrode (G6, or control electrode) of sixth transistors (T6) may be disposed on the first insulating layer (INS1). When viewed in plan view, the first gate electrode (G1) may overlap the first channel region (A1), and the sixth gate electrode (G6) may overlap the sixth channel region (A6).

[0227] Although not shown, the structure of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors (T2, T5, T7) may be substantially the same as that of the first and sixth transistors (T1, T6).

[0228] A second insulating layer (INS2) may be disposed on the first insulating layer (INS1) to cover the first and sixth gate electrodes (G1, G6). A dummy electrode (DME) may be disposed on the second insulating layer (INS2). The dummy electrode (DME) is disposed on the first gate electrode (G1) and may overlap the first gate electrode (G1) when viewed in a plan view. The dummy electrode (DME) may form the aforementioned capacitor together with the first gate electrode (G1).

[0229] A third insulating layer (INS3) may be disposed on the second insulating layer (INS2) to cover the dummy electrode (DME). A semiconductor layer (S4, A4, D4) of the fourth transistor (T4) may be disposed on the third insulating layer (INS3). The semiconductor layers (S4, A4, D4) may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0230] The semiconductor layer (S4, A4, D4) may include a plurality of regions that are distinguished depending on whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as a reduced region) may have higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as a non-reduced region). The reduced region may substantially function as a source electrode or a drain electrode of the fourth transistor (T4). The non-reduced region may substantially correspond to the active (or channel) of the fourth transistor (T4).

[0231] The fourth source region (S4), the fourth channel region (A4), and the fourth drain region (D4) of the fourth transistor (T4) may be formed from semiconductor layers (S4, A4, D4). The fourth channel region (A4) may be positioned between the fourth source region (S4) and the fourth drain region (D4).

[0232] A fourth insulating layer (INS4) may be disposed on the third insulating layer (INS3) to cover the semiconductor layers (S4, A4, D4). A fourth gate electrode (G4) of a fourth transistor (T4) may be disposed on the fourth insulating layer (INS4). When viewed in plan view, the fourth gate electrode (G4) may overlap the fourth channel region (A4).

[0233] A fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4) to cover the fourth gate electrode (G4). Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of the third transistor (T3) may be substantially the same as that of the fourth transistor (T4).

[0234] The barrier layer (BRL), the buffer layer (BFL), and the first to fifth insulating layers (INS1 to INS5) may include an inorganic material. For example, the barrier layer (BRL), the buffer layer (BFL), and the first to fifth insulating layers (INS1 to INS5) may include either silicon oxide or silicon nitride, or one insulating layer may include multiple inorganic layers, without being limited to any embodiment. The multiple inorganic layers may have a structure in which layers including silicon nitride and silicon oxide are alternately laminated.

[0235] A connection electrode (CNE) may be disposed between the sixth transistor (T6) and the light-emitting element (OLED-R). The connection electrode (CNE) may electrically connect the sixth transistor (T6) and the light-emitting element (OLED-R). The connection electrode (CNE) may include a first connection electrode (CNE1), a second connection electrode (CNE2) disposed on the first connection electrode (CNE1), and a third connection electrode (CNE3) disposed on the second connection electrode (CNE2).

[0236] The first connection electrode (CNE1) may be disposed on the fifth insulating layer (INS5) and connected to the sixth drain region (D6) through the first contact hole (CH1) defined in the first to fifth insulating layers (INS1 to INS5). A sixth insulating layer (INS6) may be disposed on the fifth insulating layer (INS5) to cover the first connection electrode (CNE1).

[0237] The second connection electrode (CNE2) may be disposed on the sixth insulating layer (INS6). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a second contact hole (CH2) defined in the sixth insulating layer (INS6).

[0238] According to the present embodiment, the first power wiring (ES-R) may be disposed on the sixth insulating layer (INS6) and covered by the seventh insulating layer (INS7). The first power wiring (ES-R) may be disposed in the non-emitting area (NPXA) as described in FIG. 5A. The first power wiring (ES-R) and the second connection electrode (CNE2) may be patterned by the same process and may include the same material.

[0239] A seventh insulating layer (INS7) may be disposed on the sixth insulating layer (INS6) to cover the second connecting electrode (CNE2) and the first power wiring (ES-R). The sixth and seventh insulating layers (INS6, INS7) may include an inorganic material or an organic material.

[0240] The third connection electrode (CNE3) may be disposed on the seventh insulating layer (INS7). The third connection electrode (CNE3) may be connected to the second connection electrode (CNE2) through a third contact hole (CH3) defined in the seventh insulating layer (INS7). The seventh insulating layer (INS7) may be defined as an “interlayer insulating layer” in this specification. Accordingly, the contact holes (CNT) described in FIG. 5A may be defined in the seventh insulating layer (INS7).

[0241] According to the present embodiment, the first contact electrode (PE-R) may be disposed on the seventh insulating layer (INS7) and covered by the eighth insulating layer (INS8). The first contact electrode (PE-R) may be disposed in the non-emitting area (NPXA) as described in FIG. 5A. The first contact electrode (PE-R) and the third connection electrode (CNE3) may be patterned by the same process and may include the same material.

[0242] An eighth insulating layer (INS8) may be disposed on the seventh insulating layer (INS7) to cover the third connecting electrode (CNE3) and the first contact electrode (PE-R). The eighth insulating layer (INS8) may include an inorganic material. A groove (GR) exposing a portion of the first contact electrode (PE-R) may be defined in the eighth insulating layer (INS8).

[0243] A side of the first contact electrode (PE-R) adjacent to the light-emitting region (PXA-R) within the area overlapping the groove (GR) may be exposed from the eighth insulating layer (INS8) by the groove (GR). The eighth insulating layer (INS8) may be defined as an “intermediate insulating layer” in this specification.

[0244] A ninth insulating layer (INS9) may be disposed on the eighth insulating layer (INS8). The ninth insulating layer (INS9) may include an organic material. The ninth insulating layer (INS9) may provide a flat surface to components to be disposed on the ninth insulating layer (INS9). According to the present embodiment, the ninth insulating layer (INS9) may be short-circuited in a region overlapping the groove (GR). The ninth insulating layer (INS9) may be defined as a “via insulating layer” in the present specification. According to one embodiment, the ninth insulating layer (INS9) may be omitted.

[0245] A pixel defining layer (PDL) may be disposed on a ninth insulating layer (INS9). An opening (PDL-OP) that leads out at least a portion of a first electrode (AE-R) may be defined in the pixel defining layer (PDL). In the present embodiment, the pixel defining layer (PDL) may include an inorganic material. In addition, the pixel defining layer (PDL) may have a predetermined color and is not limited to any one embodiment. According to the present embodiment, the pixel defining layer (PDL) may be disconnected in an area overlapping the groove (GR).

[0246] A first common layer (CL-R), a second electrode (CE-R), and a protective layer (CPL) included in a light-emitting element (OLED-R) may be disposed on a pixel defining layer (PDL). The first common layer (CL-R), the second electrode (CE-R), and the protective layer (CPL) may be disconnected in an area overlapping the groove (GR).

[0247] As illustrated in FIG. 7a, the side surface of the second electrode (CE-R) extending from the first light-emitting region (PXA-R) to the non-light-emitting region (NPXA) can be in contact with the side surface (PS) of the contact electrode (PE-S) exposed from the eighth insulating layer (INS8) through the groove (GR) within the region overlapping with the groove (GR).

[0248] According to the present invention, the second electrode (CE-R) disconnected by the groove (GR) is in direct contact with the side surface (PS) of the first contact electrode (PE-R) within an area overlapping the groove (GR), and as described in FIG. 5a, the first contact electrode (PE-R) can be connected to the first power wire (ES-R) by a contact hole (CNT) defined in the seventh insulating layer (INS7), which is an interlayer insulating layer.

[0249] According to the present invention, since the light-emitting elements included in each pixel are individually connected to a power line, they can receive a uniform power voltage regardless of the size / area of ​​the display area (DA, see Fig. 1a). Accordingly, a voltage drop phenomenon can be prevented, and a display panel (DP) with improved reliability can be provided.

[0250] According to one embodiment, a second dummy electrode (CE-D) may be disposed on a non-luminous region (NPXA). The second dummy electrode (CE-D) may be formed by the same process as the second electrode (CE-R), and may be defined as a portion disposed on the non-luminous region (NPXA) among portions that are disconnected from the second electrode (CE-R) by a groove (GR). The second dummy electrode (CE-D) may be in a floating state.

[0251] Again, referring to FIG. 6, a thin film encapsulation layer (TFE) may be disposed on the display element layer (DP-OLED). The thin film encapsulation layer (TFE) may be disposed over the entire area of ​​the display area (DA). The thin film encapsulation layer (TFE) may include a first encapsulation layer (TE1) and a second encapsulation layer (TE2). The second encapsulation layer (TE2) may be in direct contact with the first encapsulation layer (TE1) on the first emission area (PXA-R) and the non-emission area (NPXA).

[0252] According to one embodiment, the thin film encapsulation layer (TFE) may further include an organic layer disposed on the second encapsulation layer (TE2) and an additional inorganic layer covering the organic layer, but is not limited to any one embodiment.

[0253] Fig. 7a is an enlarged cross-sectional view of area AA' of Fig. 6. Fig. 7b is a cross-sectional view of a display panel according to an embodiment of the present invention. Fig. 7c is a cross-sectional view of a display panel according to an embodiment of the present invention. Fig. 7d is a cross-sectional view of a display panel according to an embodiment of the present invention. Fig. 8 is a cross-sectional view taken along line II-II' of Fig. 5a. Fig. 9 is a cross-sectional view taken along line III-III' of Fig. 5a.

[0254] As illustrated in FIG. 7a, the first encapsulating layer (TE1) may be in contact with the protective layer (CPL) and the second encapsulating layer (TE2) may be in contact with the first encapsulating layer (TE1) within an area overlapping the groove (GR). The first encapsulating layer (TE1) may cover each side of the pixel defining layer (PDL), the first common layer (CL-R), the second electrode (CE-R), and the protective layer (CPL) that are disconnected by the groove (GR) and the side of the eighth insulating layer (INS8) that defines the groove (GR).

[0255] Fig. 7b is an embodiment of a display panel (DP-1) illustrating an area corresponding to Fig. 7a. Differences from the display panel (DP) described in Fig. 7a will be mainly described, and duplicate descriptions will be omitted.

[0256] Referring to FIG. 7B, the display panel (DP-1) according to one embodiment may further include a dam pattern (OVH) overlapping the non-emission area (NPXA). The dam pattern (OVH) overlaps the first contact electrode (PE-R) and may have a shape corresponding to the shape of the first contact electrode (PE-R) in a plane described in FIG. 5A. Accordingly, the dam pattern (OVH) may have a shape that surrounds at least a portion of the first emission area (PXA-R, see FIG. 5A).

[0257] The dam pattern (OVH) may include a first pattern (OV1) disposed on a pixel defining layer (PDL) and a second pattern (OV2) disposed on the first pattern (OV1). In a third direction (DR3), a thickness of the first pattern (OV1) may be greater than a thickness of the second pattern (OV2), and in the first direction (DR1), a width of the first pattern (OV1) may be less than a width of the second pattern (OV2). The first pattern (OV1) and the second pattern (OV2) may include different inorganic materials. For example, the first pattern (OV1) may include silicon nitride and the second pattern (OV2) may include silicon oxide. The shape of the dam pattern (OVH) may be formed due to a difference in etching rates.

[0258] The first common layer (CL-R), the second dummy electrode (CE-D), and the protective layer (CPL) can be disconnected in the non-emitting region (NPXA) by the dam pattern (OVH). Accordingly, since the first common layer (CL-R), the second dummy electrode (CE-D), and the protective layer (CPL) are not arranged within the groove (GR), the second electrode (CE-R) can easily come into contact with the side surface (PS) of the first contact electrode (PE-R).

[0259] According to one embodiment, a dummy pattern (OD) may be arranged on the dam pattern (OVH). The dummy pattern (OD) may be formed by arranging portions of each of a first common layer (CL-R), a second dummy electrode (CE-D), and a protective layer (CPL). The first encapsulation layer (TE1) and the second encapsulation layer (TE2) may cover the dam pattern (OVH) in the non-emitting area (NPXA).

[0260] Fig. 7c is an embodiment of a display panel (DP-2) showing an area corresponding to Fig. 7b. Differences from the display panel (DP-1) described in Fig. 7b will be mainly described, and duplicate descriptions will be omitted.

[0261] Referring to FIG. 7c, a display panel (DP-2) according to one embodiment may include a first pattern layer (SI1) and a second pattern layer (SI2). The first pattern layer (SI1) and the second pattern layer (SI2) may overlap with the non-emission area (NPXA) and be disposed between the first contact electrode (PE-R) and the seventh insulating layer (INS7). The first pattern layer (SI1) and the second pattern layer (SI2) may overlap with the first contact electrode (PE-R). Therefore, the first pattern layer (SI1) and the second pattern layer (SI2) may have a shape that surrounds at least a portion of the first emission area (PXA-R, see FIG. 5a).

[0262] The first pattern layer (SI1) may be disposed on the seventh insulating layer (INS7). The second pattern layer (SI2) may be disposed on the first pattern layer (SI1). The first pattern layer (SI1) and the second pattern layer (SI2) may include different inorganic materials. For example, the first pattern layer (SI1) may include silicon oxide, and the second pattern layer (SI2) may include silicon nitride.

[0263] However, this is not limited thereto, and if the first pattern layer (SI1) includes silicon nitride and the second pattern layer (SI2) includes silicon oxide, the width of the second pattern layer (SI2) in the first direction (DR1) may be larger than the width of the first pattern layer (SI1).

[0264] According to the present embodiment, the width of the second pattern layer (SI2) in the first direction (DR1) may be smaller than the width of the first pattern layer (SI1). Accordingly, a portion (SU) of the upper surface of the first pattern layer (SI1) may be exposed from the second pattern layer (SI2).

[0265] According to the present embodiment, a first contact electrode (PE-R) may be disposed on a second pattern layer (SI2). The first contact electrode (PE-R) may be disposed as high as the thickness of the first pattern layer (SI1) and the second pattern layer (SI2). Accordingly, the first common layer (CL-R) may contact only the first pattern layer (SI1) and the second pattern layer (SI2) and may be spaced apart from the first contact electrode (PE-R). For example, the first common layer (CL-R) may contact a portion (SU) of the side surface and the upper surface of the first pattern layer (SI1) and the side surface of the second pattern layer (SI2). The second electrode (CE-R) may be disposed on the first common layer (CL-R) and may directly contact the side surface (PS) of the first contact electrode (PE-R).

[0266] According to the present embodiment, by including the first pattern layer (SI1) and the second pattern layer (SI2), the contact area between the first contact electrode (PE-R) and the second electrode (CE-R) can be increased.

[0267] According to the present embodiment, the side surface (PS) of the first contact electrode (PE-R) may have a predetermined curvature. More specifically, the side surface (PS) of the first contact electrode (PE-R) may have a concave shape in the direction from the first light-emitting area (PXA-R) toward the non-light-emitting area (NPXA).

[0268] Fig. 7d is an embodiment of a display panel (DP-3) illustrating an area corresponding to Fig. 7c. Differences from the display panel (DP-2) described in Fig. 7c will be mainly described, and redundant descriptions will be omitted.

[0269] Referring to FIG. 7d, a portion of the eighth insulating layer (INS8, inter-insulating layer) according to one embodiment, adjacent to the groove (GR) and positioned in the non-emitting area (NPXA), may protrude in a direction toward the first emitting area (PXA-R) rather than the first contact electrode (PE-R).

[0270] The protruding part may be defined as a trench groove (TR) that protrudes in a third direction (DR3, upward direction) to define a predetermined internal space.

[0271] According to the present embodiment, since the eighth insulating layer (INS8, interlayer insulating layer) in the non-emissive region (NPXA) includes a trench groove (TR), the configurations arranged on the eighth insulating layer (INS8, interlayer insulating layer) in the non-emissive region (NPXA) can facilitate short-circuiting. Accordingly, the process of forming the dam pattern (OVH) described in FIGS. 7b and 7c can be omitted.

[0272] Fig. 8 is a cross-sectional view between adjacent light-emitting regions illustrated in Fig. 5a. Description of configurations overlapping with those described in Figs. 7 and 7a will be omitted.

[0273] As described in FIGS. 5a, 6 and 7a, the components included in the light-emitting elements of the present invention are connected by grooves (GR), so individual sealing is required for each light-emitting element to prevent oxygen / moisture penetration.

[0274] According to the present invention, the region between adjacent light-emitting elements in the non-luminescent region (NPXA) can be defined as an encapsulation region (ENA). The encapsulation region (ENA) can block a path through which moisture / oxygen can penetrate into the interior of the light-emitting elements by bringing the inorganic layers into contact.

[0275] In the encapsulation area (ENA), the sixth and seventh insulating layers (INS6, INS7) disposed on the fifth insulating layer (INS5) can be removed. An eighth insulating layer (INS8) including an inorganic material, a pixel defining layer (PDL), and a second encapsulation layer (TE2) can be laminated on the fifth insulating layer (INS5) exposed by the removal of the sixth and seventh insulating layers (INS6, INS7) and can be in contact with each other.

[0276] The encapsulating region (ENA) can surround each of the light-emitting regions (PXA-R, PXA-B, PXA-G) described in Fig. 5a. Accordingly, a display panel (DP) with improved reliability can be provided by blocking the path through which moisture / oxygen can penetrate into the interior of the light-emitting elements.

[0277] Fig. 9 illustrates the connection relationship between the first contact electrode (PE-R) and the first power line (ES-R) described in Fig. 5a. The first power line (ES-R) may be disposed on the sixth insulating layer (INS6) and covered by the seventh insulating layer (INS7, interlayer insulating layer). The first contact electrode (PE-R) may be disposed on the seventh insulating layer (INS7, interlayer insulating layer).

[0278] The first contact electrode (PE-R) can be connected to the first power line (ES-R) through a contact hole (CNT) defined in the seventh insulating layer (INS7, interlayer insulating layer). According to the display panel (DP-2) described in Fig. 7c, a first pattern layer (SI1) and a second pattern layer (SI2) including a hole overlapping the contact hole (CNT) can be arranged on the seventh insulating layer (INS7, interlayer insulating layer).

[0279] FIGS. 10A to 10K are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention. FIGS. 10A to 10K are drawings regarding a method for forming the display panel (DP-2) described in FIG. 7C. The manufacturing steps for the fifth insulating layer (INS5) and the components disposed below the fifth insulating layer (INS5) among the components described in FIG. 6 are omitted.

[0280] Referring to FIG. 10A, a method for manufacturing a display panel according to one embodiment may include a step of forming a sixth insulating layer (INS6) on a fifth insulating layer (INS5), and a step of forming a seventh insulating layer (INS7) on the sixth insulating layer (INS6). The fifth insulating layer (INS5) may include an inorganic material, and the sixth insulating layer (INS6) and the seventh insulating layer (INS7) may include organic materials.

[0281] Thereafter, a step of removing the sixth insulating layer (INS6) and the seventh insulating layer (INS7) so that a portion of the fifth insulating layer (INS5) is exposed may be included.

[0282] Thereafter, the method may include a step of forming a first pattern layer (SI1) on the seventh insulating layer (INS7) and a step of forming a second pattern layer (SI2) on the first pattern layer (SI1). The first pattern layer (SI1) may include silicon oxide, and the second pattern layer (SI2) may include silicon nitride.

[0283] Thereafter, a step of forming a first contact electrode (PE-R) on the second pattern layer (SI2) may be included. In the present embodiment, the first contact electrode (PE-R) may include molybdenum. The first contact electrode (PE-R) is formed by the same process as the third connection electrode (CNE3) described in FIG. 6 and may include the same material.

[0284] Hereinafter, referring to FIG. 10b, a method for manufacturing a display panel according to one embodiment may include a step of patterning a first pattern layer (SI1), a second pattern layer (SI2), and a first contact electrode (PE-R). The first pattern layer (SI1), the second pattern layer (SI2), and the first contact electrode (PE-R) may be formed using a dry etching process. The first pattern layer (SI1) and the second pattern layer (SI2) may be patterned to overlap the first contact electrode (PE-R) using the first contact electrode (PE-R) as a mask.

[0285] Hereinafter, referring to FIG. 10c, a method for manufacturing a display panel according to one embodiment may include a step of forming an eighth insulating layer (INS8) on a seventh insulating layer (INS7) so that a first contact electrode (PE-R) is covered. The eighth insulating layer (INS8) may include an inorganic material.

[0286] Thereafter, a step of patterning the eighth insulating layer (INS8) may be included. The eighth insulating layer (INS8) may be etched to form a groove (GR) that exposes a portion of a side surface of the first contact electrode (PE-R). The patterning step may be performed using a dry etching process.

[0287] The side of the eighth insulating layer (INS8) defining the groove (GR) can expose the side of the first contact electrode (PE-R), the side of the first pattern layer (SI1), and the side of the second pattern layer (SI2).

[0288] Hereinafter, referring to FIG. 10d, a method for manufacturing a display panel according to an embodiment may include a step of patterning a first contact electrode (PE-R). A side surface of the first contact electrode (PE-R) exposed from the eighth insulating layer (INS8) by the groove (GR) may be etched to form a side surface (PS) having a predetermined curvature. The patterning step may be performed using a wet etching process. According to an embodiment, the wet etching process may be performed by forming a PR pattern (photoresist) on the first contact electrode (PE-R) and then using this as a mask.

[0289] According to the present embodiment, the lower portion of the eighth insulating layer (INS8) can be exposed from the patterned first contact electrode (PE-R).

[0290] Hereinafter, referring to FIG. 10e, a method for manufacturing a display panel according to one embodiment may include a step of patterning a second pattern layer (SI2). The patterning step may be performed by a dry etching process. Due to a difference in etching rates between the first pattern layer (SI1) and the second pattern layer (SI2), a relatively large portion of the second pattern layer (SI2) may be removed. Accordingly, the second pattern layer (SI2) may expose a portion (SU) of the upper surface of the first pattern layer (SI1).

[0291] Hereafter, referring to FIG. 10f, a method for manufacturing a display panel according to one embodiment may include a step of forming a ninth insulating layer (INS9) on an eighth insulating layer (INS8). The ninth insulating layer (INS9) may include an organic material. The ninth insulating layer (INS9) may be formed by removing a portion overlapping the groove (GR) using a photo process so that the ninth insulating layer (INS9) does not overlap with the groove (GR).

[0292] Hereinafter, referring to FIG. 10g, a method for manufacturing a display panel according to one embodiment may include a step of forming a pixel defining layer (PDL) on a ninth insulating layer (INS9). The pixel defining layer (PDL) may include an inorganic material. The pixel defining layer (PDL) may be formed by removing a portion overlapping the groove (GR) through an etching process so that the pixel defining layer (PDL) does not overlap with the groove (GR).

[0293] Hereinafter, referring to FIG. 10h, a method for manufacturing a display panel according to one embodiment may include a step of forming a dam pattern on a pixel defining layer (PDL). The step of forming the dam pattern may include a step of forming a first pattern (OV1) and a second pattern (OV2). The first pattern (OV1) and the second pattern (OV2) may include an inorganic material. The first pattern (OV1) may include silicon nitride, and the second pattern (OV2) may include silicon oxide.

[0294] Hereinafter, referring to FIG. 10i, a method for manufacturing a display panel according to one embodiment may include a step of patterning a first pattern (OV1) and a second pattern (OV2). The patterning step may be performed by a dry etching process. The patterned first pattern (OV1) and second pattern (OV2) may overlap a first contact electrode (PE-R) and be formed on a pixel defining layer (PDL). The shapes of the first pattern (OV1) and the second pattern (OV2) may be formed due to a difference in etching rates.

[0295] The step of forming the first electrode (AE-R) described in Fig. 6 is performed before the step of forming the pixel defining layer (PDL), and the step of forming the first electrode (AE-R) is omitted.

[0296] Hereinafter, referring to FIG. 10j, a method for manufacturing a display panel according to an embodiment may include a step of forming a first common layer (CL-R) on a pixel defining layer (PDL), a step of forming a second electrode (CE-R) on the first common layer (CL-R), and a step of forming a protective layer (CPL) on the second electrode (CE-R). The first common layer (CL-R), the second electrode (CE-R), and the protective layer (CPL) may be primarily disconnected by the dam pattern (OVH) and secondarily disconnected by the groove (GR). Therefore, the second dummy electrode (CE-D) formed on the dam pattern (OVH) may be defined as being in a floating state.

[0297] The short-circuited first common layer (CL-R) can be in contact with the side surface of the first pattern layer (SI1) and a portion of the upper surface (SU) and the side surface of the second pattern layer (SI2) within the groove (GR).

[0298] The shorted second electrode (CE-R) can be in contact with the side surface (PS) of the first contact electrode (PE-R) within the groove (GR).

[0299] A dummy pattern (OD) may be formed on the dam pattern (OVH). The dummy pattern (OD) may be formed on the dam pattern (OVH) by disconnecting portions of each of the first common layer (CL-R), the second dummy electrode (CE-D), and the protective layer (CPL) by the dam pattern (OVH).

[0300] Thereafter, a step of forming a first encapsulating layer (TE1) on the protective layer (CPL) may be included. The first encapsulating layer (TE1) may include an inorganic material. The first encapsulating layer (TE1) may cover the portions that are disconnected by the dam pattern (OVH) and the groove (GR).

[0301] Hereinafter, referring to FIG. 10k, a method for manufacturing a display panel according to one embodiment may include a step of patterning a first common layer (CL-R), a second dummy electrode (CE-D), a protective layer (CPL), and a first encapsulating layer (TE1). As described in FIG. 5a, the first common layer (CL-R), the second dummy electrode (CE-D), the protective layer (CPL), and the first encapsulating layer (TE1) disposed on a pixel defining layer (PDL) in an area between adjacent light-emitting elements may be removed to form an encapsulating area (ENA).

[0302] Thereafter, a step of forming a second encapsulating layer (TE2) on the first encapsulating layer (TE1) may be included. The second encapsulating layer (TE2) may include an inorganic material. The second encapsulating layer (TE2) may be in contact with the first common layer (CL-R), the second dummy electrode (CE-D), the protective layer (CPL), and the pixel defining layer (PDL) exposed by removing the first encapsulating layer (TE1) to form an encapsulating area (ENA). The encapsulating area (ENA) may individually surround the light-emitting elements described in FIGS. 5A and 6. Accordingly, a path through which moisture / oxygen flows into the light-emitting elements may be blocked.

[0303] FIGS. 11A to 11G are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 11A to 11G are drawings regarding a method for forming the display panel (DP-3) described in FIG. 7D. The same / similar reference numerals are given to configurations identical / similar to those described in FIGS. 10A to 10K, and duplicate descriptions are omitted. The manufacturing steps for the configurations arranged under the sixth insulating layer (INS6) among the configurations described in FIG. 6 are omitted.

[0304] Referring to FIG. 11A, a method for manufacturing a display panel according to one embodiment may include a step of forming a sixth insulating layer (INS6) on a fifth insulating layer (INS5), and a step of forming a seventh insulating layer (INS7) on the sixth insulating layer (INS6). The fifth insulating layer (INS5) may include an inorganic material, and the sixth insulating layer (INS6) and the seventh insulating layer (INS7) may include an organic material.

[0305] Thereafter, a step of removing the sixth insulating layer (INS6) and the seventh insulating layer (INS7) so that a portion of the fifth insulating layer (INS5) is exposed may be included.

[0306] Thereafter, the method may include a step of forming a first pattern layer (SI1) on the seventh insulating layer (INS7) and a step of forming a second pattern layer (SI2) on the first pattern layer (SI1). The first pattern layer (SI1) may include silicon oxide, and the second pattern layer (SI2) may include silicon nitride.

[0307] Thereafter, a step of forming a first contact electrode (PE-R) on the second pattern layer (SI2) may be included. In the present embodiment, the first contact electrode (PE-R) may include molybdenum. The first contact electrode (PE-R) is formed by the same process as the third connection electrode (CNE3) described in FIG. 6 and may include the same material.

[0308] Thereafter, a step of forming a trench pattern layer (TI) on the seventh insulating layer (INS7) to cover the first contact electrode (PE-R) may be included. The trench pattern layer (TI) may include silicon nitride.

[0309] Thereafter, referring to FIG. 11b, a step of patterning a trench pattern layer (TI) may be included. The patterning step may be performed by a dry etching process. The patterned trench pattern layer (TI) may be formed directly on the first contact electrode (PE-R).

[0310] Hereinafter, referring to FIG. 11c, a method for manufacturing a display panel according to one embodiment may include a step of forming an eighth insulating layer (INS8) on a seventh insulating layer (INS7) so as to cover a first contact electrode (PE-R). The eighth insulating layer (INS8) may include an inorganic material. The eighth insulating layer (INS8) may cover a trench pattern layer (TI) and a first contact electrode (PE-R) exposed from the trench pattern layer (TI).

[0311] Thereafter, a step of patterning the eighth insulating layer (INS8) may be included. The eighth insulating layer (INS8) may be etched to form a groove (GR) that exposes a portion of the first contact electrode (PE-R). The patterning step may be performed using a dry etching process.

[0312] The side of the eighth insulating layer (INS8) defining the groove (GR) can expose the side of the first contact electrode (PE-R), the side of the first pattern layer (SI1), and the side of the second pattern layer (SI2).

[0313] Hereinafter, referring to FIG. 11d, a method for manufacturing a display panel according to an embodiment may include a step of patterning a first contact electrode (PE-R). A side surface of the first contact electrode (PE-R) exposed from the eighth insulating layer (INS8) by the groove (GR) may be etched to form a side surface (PS) having a predetermined curvature. The patterning step may be performed using a wet etching process. According to an embodiment, the wet etching process may be performed by forming a PR pattern (photoresist) on the first contact electrode (PE-R) and then using this as a mask.

[0314] According to the present embodiment, the lower portion of the trench pattern layer (TI) can be exposed from the eighth insulating layer (INS8) through the patterned first contact electrode (PE-R).

[0315] Hereinafter, referring to FIG. 11e, a method for manufacturing a display panel according to one embodiment may include a step of patterning a second pattern layer (SI2). The patterning step may be performed by a dry etching process. Due to the difference in etching rates between the first pattern layer (SI1) and the second pattern layer (SI2), a relatively large portion of the second pattern layer (SI2) may be removed. Accordingly, the second pattern layer (SI2) may expose a portion (SU) of the upper surface of the first pattern layer (SI1).

[0316] Since the second pattern layer (SI2) and the trench pattern layer (TI) include silicon nitride, the trench pattern layer (TI) can be removed from the eighth insulating layer (INS8) simultaneously with the process of patterning the second pattern layer (SI2).

[0317] At this time, the eighth insulating layer (INS8) may form a trench groove (TR) with a predetermined internal space defined corresponding to the formation of the trench pattern layer (TI). The trench groove (TR) may surround a corresponding light-emitting region corresponding to the formation of the first contact electrode (PE-R) in FIG. 5a.

[0318] Thereafter, a step of forming a ninth insulating layer (INS9) on the eighth insulating layer (INS8) may be included. The ninth insulating layer (INS9) may include an organic material. The ninth insulating layer (INS9) may be formed by removing a portion overlapping the groove (GR) using a photo process so that the ninth insulating layer (INS9) does not overlap with the groove (GR).

[0319] Thereafter, a step of forming a pixel defining layer (PDL) on the ninth insulating layer (INS9) may be included. The pixel defining layer (PDL) may include an inorganic material. The pixel defining layer (PDL) may be formed by removing a portion overlapping the groove (GR) through an etching process so that the portion does not overlap with the groove (GR).

[0320] The step of forming the first electrode (AE-R) described in Fig. 6 is performed before the step of forming the pixel defining layer (PDL), and the step of forming the first electrode (AE-R) is omitted.

[0321] Hereinafter, referring to FIG. 11f, a method for manufacturing a display panel according to one embodiment may include a step of forming a first common layer (CL-R) on a pixel defining film (PDL).

[0322] The first common layer (CL-R) may be short-circuited within the groove (GR). The short-circuited first common layer (CL-R) may contact the side surface of the first pattern layer (SI1), a portion of the upper surface (SU), and the side surface of the second pattern layer (SI2) within the groove (GR). The first common layer (CL-R) may be more easily short-circuited by the trench groove (TR).

[0323] Thereafter, referring to FIG. 11g, a step of forming a second electrode (CE-R) on the first common layer (CL-R) may be included. The second electrode (CE-R) may be primarily disconnected by the trench groove (TR) and secondarily disconnected by the groove (GR). Accordingly, the second dummy electrode (CE-D) formed on the first contact electrode (PE-R) may be defined as being in a floating state.

[0324] The shorted second electrode (CE-R) can be in contact with the side surface (PS) of the first contact electrode (PE-R) within the groove (GR).

[0325] According to the present embodiment, by forming a trench groove (TR) in the eighth insulating layer (INS8), the step of forming a dam pattern (OVH) described in FIGS. 10h and 10i can be omitted.

[0326] Thereafter, the steps performed on the second electrode (CE-R) may be the same as those described in FIGS. 10j to 10k.

[0327] Fig. 12a is a cross-sectional view of a display panel according to an embodiment of the present invention. Fig. 12b is a cross-sectional view of a display panel according to an embodiment of the present invention. Components identical to or similar to those described in Figs. 6 to 7d are designated by the same or similar reference numerals, and duplicate descriptions are omitted. Differences from Fig. 7c will be primarily described.

[0328] Fig. 12a is an embodiment of a display panel (DP-A) illustrating an area corresponding to Fig. 7c. Differences from the display panel (DP-2) described in Fig. 7c will be mainly described, and duplicate descriptions will be omitted.

[0329] Referring to FIG. 12A, a first contact electrode (PE-R) included in a display panel (DP-A) according to one embodiment may include first to third conductive layers (C1, C2, C3) sequentially stacked on a seventh insulating layer (INS7). The thicknesses of the first and third conductive layers (C1, C3) may be smaller than the thickness of the second conductive layer (C2).

[0330] The first and third conductive layers (C1, C3) may include titanium, and the second conductive layer (C2) may include aluminum.

[0331] An eighth insulating layer (INS8) covering the first contact electrode (PE-R) may be disposed on the seventh insulating layer (INS7). The eighth insulating layer (INS8) may include an inorganic material. According to the present embodiment, a groove (GR) exposing a portion (CU) of an upper surface of the first contact electrode (PE-R) may be defined in the eighth insulating layer (INS8). The portion (CU) of the upper surface of the first contact electrode (PE-R) may correspond to a portion of an upper surface of the third conductive layer (C3). One side surface (IS) of the eighth insulating layer (INS8) defining the groove (GR) may have a predetermined curvature.

[0332] The first common layer (CL-R) may be short-circuited within the groove (GR), and a portion of the first common layer (CL-R) may be disposed on a portion (CU) of the upper surface of the first contact electrode (PE-R).

[0333] The second electrode (CE-R) is short-circuited within the groove (GR), and a portion of the second electrode (CE-R) can be in contact with a portion (CU) of the upper surface of the first contact electrode (PE-R) and a side surface (IS) of the eighth insulating layer (INS8).

[0334] According to the present embodiment, as the second electrode (CE-R) comes into contact with the upper surface of the first contact electrode (PE-R), the contact area between the first contact electrode (PE-R) and the second electrode (CE-R) can be increased.

[0335] Referring to FIG. 12B, a first contact electrode (PE-R) included in a display panel (DP-B) according to one embodiment may include first to third conductive layers (C1, C2, C3) sequentially stacked on a seventh insulating layer (INS7). The first and third conductive layers (C1, C3) may include titanium, and the second conductive layer (C2) may include aluminum.

[0336] An eighth insulating layer (INS8) covering the first contact electrode (PE-R) may be disposed on the seventh insulating layer (INS7). The eighth insulating layer (INS8) may include an inorganic material. According to the present embodiment, a groove (GR) exposing a side surface of the first contact electrode (PE-R) may be defined in the eighth insulating layer (INS8). A portion (CS) of the side surface of the first contact electrode (PE-R) may correspond to a portion of the side surface of the second conductive layer (C2). The portion (CS) of the side surface of the first contact electrode (PE-R) may have a predetermined curvature. The undercut shape of the first to third conductive layers (C1, C2, C3) may be a shape formed due to a difference in etching rates.

[0337] The first common layer (CL-R) may be short-circuited within the groove (GR), and a portion of the first common layer (CL-R) may be disposed on the seventh insulating layer (INS7).

[0338] The second electrode (CE-R) is short-circuited within the groove (GR), and a portion of the second electrode (CE-R) can be in contact with a portion (CS) of a side surface of the first contact electrode (PE-R).

[0339] FIGS. 13A to 13G are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 13A to 13G are drawings regarding a method for forming the display panel (DP-A) described in FIG. 12. The same / similar reference numerals are given to configurations identical / similar to those described in FIGS. 10A to 10K, and duplicate descriptions are omitted.

[0340] Referring to FIG. 13A, a method for manufacturing a display panel according to one embodiment may include a step of forming a sixth insulating layer (INS6) on a fifth insulating layer (INS5), and a step of forming a seventh insulating layer (INS7) on the sixth insulating layer (INS6). The fifth insulating layer (INS5) may include an inorganic material, and the sixth insulating layer (INS6) and the seventh insulating layer (INS7) may include organic materials.

[0341] Thereafter, a step of removing the sixth insulating layer (INS6) and the seventh insulating layer (INS7) so that a portion of the fifth insulating layer (INS5) is exposed may be included.

[0342] Thereafter, a step of forming a first contact electrode (PE-R) on the seventh insulating layer (INS7) may be included. The step of forming the first contact electrode (PE-R) may include a step of forming a first conductive layer (C1) including titanium on the seventh insulating layer (INS7), a step of forming a second conductive layer (C2) including aluminum on the first conductive layer (C1), and a step of forming a third conductive layer (C3) including titanium on the second conductive layer (C2).

[0343] Thereafter, the first to third conductive layers (C1, C2, C3) can be patterned to form a first contact electrode (PE-R).

[0344] Hereinafter, referring to FIG. 13b, a method for manufacturing a display panel according to one embodiment may include a step of forming an eighth insulating layer (INS8) on a seventh insulating layer (INS7) so that a first contact electrode (PE-R) is covered. The eighth insulating layer (INS8) may include an inorganic material.

[0345] Thereafter, a step of patterning the eighth insulating layer (INS8) may be included. The eighth insulating layer (INS8) may be etched to form a groove (GR) that exposes a portion (CU) of the upper surface of the first contact electrode (PE-R). The patterning step may be performed using a dry etching process. The side surface (IS) of the eighth insulating layer (INS8) defining the groove (GR) may have a predetermined curvature.

[0346] Hereinafter, referring to FIGS. 13c and 13d, a method for manufacturing a display panel according to one embodiment may include a step of forming a ninth insulating layer (INS9) on an eighth insulating layer (INS8). The ninth insulating layer (INS9) may include an organic material. The ninth insulating layer (INS9) may be formed by removing a portion overlapping the groove (GR) using a photo process so that the ninth insulating layer (INS9) does not overlap with the groove (GR).

[0347] Thereafter, a step of forming a pixel defining layer (PDL) on the ninth insulating layer (INS9) may be included. The pixel defining layer (PDL) may include an inorganic material. The pixel defining layer (PDL) may be formed by removing a portion overlapping the groove (GR) through an etching process so that the pixel defining layer (PDL) does not overlap with the groove (GR). By removing the pixel defining layer (PDL), a portion (CU) of the upper surface of the first contact electrode (PE-R) may be exposed.

[0348] Thereafter, a step of forming a pixel defining layer (PDL) on the ninth insulating layer (INS9) may be included. The pixel defining layer (PDL) may include an inorganic material. The pixel defining layer (PDL) may be formed by removing a portion overlapping the groove (GR) through an etching process so that the pixel defining layer (PDL) does not overlap with the groove (GR). The pixel defining layer (PDL) may expose a portion (CU) of the upper surface of the first contact electrode (PE-R).

[0349] Thereafter, a step of forming a dam pattern on the pixel defining layer (PDL) may be included. The step of forming the dam pattern may include a step of forming a first pattern (OV1) and a second pattern (OV2). The first pattern (OV1) and the second pattern (OV2) may include an inorganic material. The first pattern (OV1) may include silicon nitride, and the second pattern (OV2) may include silicon oxide.

[0350] Hereinafter, referring to FIG. 13E, a method for manufacturing a display panel according to one embodiment may include a step of patterning a first pattern (OV1) and a second pattern (OV2). The patterning step may be performed by a dry etching process. The patterned first pattern (OV1) and second pattern (OV2) may overlap with the first contact electrode (PE-R) and be formed on a pixel defining layer (PDL). The shapes of the first pattern (OV1) and the second pattern (OV2) may be formed due to a difference in etching rates.

[0351] The step of forming the first electrode (AE-R) described in Fig. 6 is performed before the step of forming the pixel defining layer (PDL), and the step of forming the first electrode (AE-R) is omitted.

[0352] Thereafter, the method may include forming a first common layer (CL-R) on a pixel defining layer (PDL), forming a second electrode (CE-R) on the first common layer (CL-R), and forming a protective layer (CPL) on the second electrode (CE-R). The first common layer (CL-R), the second electrode (CE-R), and the protective layer (CPL) may be primarily disconnected by the dam pattern (OVH) and secondarily disconnected by the groove (GR). Therefore, the second dummy electrode (CE-D) formed on the dam pattern (OVH) may be defined as being in a floating state.

[0353] A single-layer first common layer (CL-R) can be disposed on a portion (CU) of the upper surface of the first contact electrode (PE-R) within the groove (GR).

[0354] The shorted second electrode (CE-R) can be in contact with a portion (CU) of the upper surface of the first contact electrode (PE-R) within the groove (GR) and a side surface (IS) of the eighth insulating layer (INS8) defining the groove (GR).

[0355] A dummy pattern (OD) may be formed on the dam pattern (OVH). The dummy pattern (OD) may be formed on the dam pattern (OVH) by disconnecting portions of each of the first common layer (CL-R), the second dummy electrode (CE-D), and the protective layer (CPL) by the dam pattern (OVH).

[0356] Thereafter, the steps performed on the protective layer (CPL) may be the same as those described in FIGS. 10j to 10k.

[0357] Fig. 14 is a cross-sectional view of a display panel according to one embodiment of the present invention. Components identical to or similar to those described in Figs. 6 to 7d are designated by the same or similar reference numerals, and duplicate descriptions are omitted. The following description will focus on differences from Fig. 7a.

[0358] Fig. 14 is an embodiment of a display panel (DP-C) illustrating an area corresponding to Fig. 7a. Differences from the display panel (DP) described in Fig. 7a will be mainly described, and duplicate descriptions will be omitted.

[0359] Referring to FIG. 14, a display panel (DP-C) according to one embodiment may have a first power line (ES-R) disposed on a sixth insulating layer (INS6) and a first contact electrode (PE-R) disposed on a seventh insulating layer (INS7). The connection between the first power line (ES-R) and the first contact electrode (PE-R) may be made through a contact hole (CNT) defined in the seventh insulating layer (INS7), as described in FIG. 9.

[0360] An eighth insulating layer (INS8) may be disposed on the seventh insulating layer (INS7). A groove (GR) exposing a portion (PU) of the upper surface of the first contact electrode (PE-R) and an auxiliary contact hole (CT) exposing another portion of the upper surface may be defined in the eighth insulating layer (INS8).

[0361] A first electrode (AE-R) may be placed in a portion of the eighth insulating layer (INS8) that overlaps with the first light-emitting region (PXA-R), and an auxiliary electrode (BE) may be placed in a portion of the eighth insulating layer (INS8) that overlaps with the non-light-emitting region (NPXA).

[0362] The auxiliary electrode (BE) is connected to the first contact electrode (PE-R) through the auxiliary contact hole (CT), and the first contact electrode (PE-R) can be connected to the first power line (ES-R) through the contact hole (CNT) defined in the seventh insulating layer (INS7) as described in FIG. 9.

[0363] An etching prevention layer (TPL) may be disposed on the edge of the first electrode (AE-R) and the auxiliary electrode (BE). The etching prevention layer (TPL) may prevent damage such as heat from being applied to the first electrode (AE-R) during a subsequent dry etching process. The etching prevention layer (TPL) may include an inorganic material.

[0364] A pixel defining layer (PDL) may be disposed on the eighth insulating layer (INS8) to cover the auxiliary electrode (BE) and the first electrode (AE-R). An opening (PDL-OP) exposing at least a portion of the first electrode (AE-R) may be defined in the pixel defining layer (PDL). The pixel defining layer (PDL) may be short-circuited within the groove (GR).

[0365] A first common layer (CL-R) may be disposed on the first electrode (AE-R). The first common layer (CL-R) may be short-circuited within the groove (GR), and a portion of the first common layer (CL-R) may be disposed on a portion (PU) of the upper surface of the first contact electrode (PE-R).

[0366] A portion of the first common layer (CL-R) disposed within the groove (GR) may be in contact with a side surface of the eighth insulating layer (ISN8). Since the first common layer (CL-R) is disposed within the groove (GR) with a predetermined thickness, the second electrode (CE-R) may be disposed spaced apart from the seventh insulating layer (INS7) by the thickness of the first common layer (CL-R).

[0367] A second electrode (CE-R) may be disposed on the first common layer (CL-R). The second electrode (CE-R) may be short-circuited within the groove (GR), and a portion of the second electrode (CE-R) may be disposed on the first common layer (CL-R) within the groove (GR).

[0368] The second electrode (CE-R) disposed within the groove (GR) is disposed spaced apart from the seventh insulating layer (INS7) by the thickness of the first common layer (CL-R), and according to the present embodiment, the second electrode (CE-R) disconnected by the thickness of the first common layer (CL-R) can contact the side surface (BS) of the auxiliary electrode (BE).

[0369] A protective layer (CPL) is disposed on the second electrode (CE-R), and the protective layer (CPL) can be short-circuited within the groove (GR).

[0370] The dam pattern (OVH) is disposed on a pixel defining layer (PDL) overlapping a first contact electrode (PE-R), and may include a first pattern (OV1) and a second pattern (OV2) disposed on the first pattern (OV1).

[0371] A dummy pattern (OD) may be arranged on the dam pattern (OVH). The dummy pattern (OD) may be formed by arranging portions of each of the first common layer (CL-R), the second dummy electrode (CE-D), and the protective layer (CPL). The first encapsulation layer (TE1) and the second encapsulation layer (TE2) may cover the dam pattern (OVH) in the non-emitting area (NPXA).

[0372] FIGS. 15A to 15I are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 15A to 15I are drawings for a method for explaining the display panel (DP-C) described in FIG. 14. The same / similar reference numerals are given to configurations identical / similar to those described in FIGS. 10A to 10K, and duplicate descriptions are omitted.

[0373] Referring to FIG. 15A, a method for manufacturing a display panel according to one embodiment may include a step of forming a sixth insulating layer (INS6) on a fifth insulating layer (INS5), and a step of forming a seventh insulating layer (INS7) on the sixth insulating layer (INS6). The fifth insulating layer (INS5) may include an inorganic material, and the sixth insulating layer (INS6) and the seventh insulating layer (INS7) may include organic materials.

[0374] Thereafter, a step of removing the sixth insulating layer (INS6) and the seventh insulating layer (INS7) so that a portion of the fifth insulating layer (INS5) is exposed may be included.

[0375] Thereafter, a step of forming a first contact electrode (PE-R) on the seventh insulating layer (INS7) may be included. In the present embodiment, the first contact electrode (PE-R) may include molybdenum. The first contact electrode (PE-R) is formed by the same process as the third connection electrode (CNE3) described in FIG. 6 and may include the same material.

[0376] Hereinafter, referring to FIG. 15b, a method for manufacturing a display panel according to one embodiment may include a step of forming an eighth insulating layer (INS8) on a seventh insulating layer (INS7) so that a first contact electrode (PE-R) is covered. The eighth insulating layer (INS8) may include an inorganic material.

[0377] Thereafter, a step of patterning the eighth insulating layer (INS8) may be included. The eighth insulating layer (INS8) may be etched to form a groove (GR) exposing a portion (PU) of the upper surface of the first contact electrode (PE-R) and an auxiliary contact hole (CT) exposing another portion of the upper surface of the first contact electrode (PE-R).

[0378] Hereinafter, referring to FIG. 15c, a method for manufacturing a display panel according to one embodiment may include a step of forming a first electrode (AE-R) and an auxiliary electrode (BE) on an eighth insulating layer (INS8) and a step of forming an etching prevention layer (TPL) on the first electrode (AE-R) and the auxiliary electrode (BE). The first electrode (AE-R) and the auxiliary electrode (BE) may be formed by the same process and may include the same material. The auxiliary electrode (BE) may be formed in an auxiliary contact hole (CT) and connected to the first contact electrode (PE-R).

[0379] The etching prevention layer (TPL) may include either indium tin oxide or indium zinc oxide. The etching prevention layer (TPL) can prevent damage such as heat from being applied to the first electrode (AE-R) and the auxiliary electrode (BE) during the dry etching process in the subsequent process.

[0380] Hereinafter, referring to FIGS. 15d and 15e, a method for manufacturing a display panel according to one embodiment may include a step of forming a pixel defining layer (PDL) on an eighth insulating layer (INS8). The pixel defining layer (PDL) may include an inorganic material. The pixel defining layer (PDL) may cover an etching prevention layer (TPL).

[0381] Thereafter, a step of forming a dam pattern (OVH) on the pixel defining layer (PDL) may be included. The step of forming the dam pattern (OVH) may include a step of forming a first pattern (OV1) and a second pattern (OV2). The first pattern (OV1) and the second pattern (OV2) may include an inorganic material. The first pattern (OV1) may include silicon nitride, and the second pattern (OV2) may include silicon oxide.

[0382] Thereafter, referring to FIG. 15f, a step of patterning a pixel defining layer (PDL) may be included. The pixel defining layer (PDL) may be patterned so as not to overlap with the groove (GR). At this time, an opening (PDL-OP) overlapping with the first electrode (AE-R) and the etching prevention layer (TPL) may be formed. The patterning step may be performed by a dry etching process.

[0383] According to the present embodiment, since an etching prevention layer (TPL) is formed on the first electrode (AE-R) and the auxiliary electrode (BE) in the step of patterning the pixel defining layer (PDL) by a dry etching process, the first electrode (AE-R) and the auxiliary electrode (BE) can be prevented from being damaged by heat or the like. Accordingly, a method for manufacturing a display panel with improved reliability can be provided.

[0384] Thereafter, a step of removing an etching prevention layer (TPL) disposed on the first electrode (AE-R) may be included. The removing step may be performed using a wet etching process. At this time, the remaining etching prevention layer (TPL) may overlap the edge of the first electrode (AE-R) and be covered by a pixel defining layer (PDL).

[0385] Thereafter, a step of forming a dam pattern on the pixel defining layer (PDL) may be included. The step of forming the dam pattern may include a step of forming a first pattern (OV1) and a second pattern (OV2). The first pattern (OV1) and the second pattern (OV2) may include an inorganic material. The first pattern (OV1) may include silicon nitride, and the second pattern (OV2) may include silicon oxide.

[0386] Thereafter, a step of patterning the first pattern (OV1) and the second pattern (OV2) may be included. The patterning step may be performed by a dry etching process. The patterned first pattern (OV1) and the second pattern (OV2) may overlap the first contact electrode (PE-R) and be formed on the pixel defining layer (PDL). The shapes of the first pattern (OV1) and the second pattern (OV2) may be formed due to a difference in etching rates.

[0387] Hereinafter, referring to FIG. 15g, a method for manufacturing a display panel according to an embodiment may include a step of forming a first common layer (CL-R) on a pixel defining layer (PDL), a step of forming a second electrode (CE-R) on the first common layer (CL-R), and a step of forming a protective layer (CPL) on the second electrode (CE-R). The first common layer (CL-R), the second electrode (CE-R), and the protective layer (CPL) may be primarily disconnected by the dam pattern (OVH) and secondarily disconnected by the groove (GR). Therefore, the second dummy electrode (CE-D) formed on the dam pattern (OVH) may be defined as being in a floating state.

[0388] According to the present embodiment, the short-circuited second electrode (CE-R) is placed on the first common layer (CL-R) within the groove (GR) and can be in contact with the side surface (BS) of the auxiliary electrode (BE).

[0389] A dummy pattern (OD) may be formed on the dam pattern (OVH). The dummy pattern (OD) may be formed on the dam pattern (OVH) by disconnecting portions of each of the first common layer (CL-R), the second dummy electrode (CE-D), and the protective layer (CPL) by the dam pattern (OVH).

[0390] Thereafter, as disclosed in FIG. 15h, a step of forming a first encapsulating layer (TE1) on the protective layer (CPL) may be included. The first encapsulating layer (TE1) may include an inorganic material. The first encapsulating layer (TE1) may cover the portions disconnected by the dam pattern (OVH) and the groove (GR).

[0391] Hereinafter, referring to FIG. 15i, a method for manufacturing a display panel according to one embodiment may include a step of patterning a first common layer (CL-R), a second dummy electrode (CE-D), a protective layer (CPL), and a first encapsulating layer (TE1). As described in FIG. 5a, the first common layer (CL-R), the second dummy electrode (CE-D), the protective layer (CPL), and the first encapsulating layer (TE1) disposed on a pixel defining layer (PDL) in an area between adjacent light-emitting elements may be removed to form an encapsulating area (ENA, see FIG. 8).

[0392] Thereafter, a step of forming a second encapsulating layer (TE2) on the first encapsulating layer (TE1) may be included. The second encapsulating layer (TE2) may include an inorganic material. The second encapsulating layer (TE2) may be in contact with the first common layer (CL-R), the second dummy electrode (CE-D), the protective layer (CPL), and the pixel defining layer (PDL) exposed by removing the first encapsulating layer (TE1) to form an encapsulating area (ENA). The encapsulating area (ENA) may individually surround the light-emitting elements described in FIGS. 5A and 6. Accordingly, a path through which moisture / oxygen flows into the light-emitting elements may be blocked.

[0393] Fig. 16 is a cross-sectional view of a light-emitting element according to one embodiment of the present invention. Fig. 16 can be applied to the light-emitting element (OLED-R) described in Fig. 6. In addition, it can also be applied to the light-emitting element included in each of the pixels (PX-R, PX-B, PX-G) described in Fig. 5a.

[0394] Referring to FIG. 16, a light-emitting device (OLED) of one embodiment may include a first electrode (AE), a second electrode (CE) facing the first electrode (AE), and a common layer (CL) disposed between the first electrode (AE) and the second electrode (CE). The common layer (CL) may include first and second light-emitting stacks (ST1, ST2). Meanwhile, FIG. 16 exemplarily illustrates that the light-emitting device (OLED) includes two light-emitting stacks, but the number of light-emitting stacks included in the light-emitting device (OLED) may be greater than this.

[0395] The light emitting device (OLED) may include a first charge generation layer (CGL1) disposed between first and second light emitting stacks (ST1, ST2).

[0396] When voltage is applied, the first charge generation layer (CGL1) can generate charges (electrons and holes) by forming a complex through an oxidation-reduction reaction. Thereafter, the first charge generation layer (CGL1) can provide the generated charges to the adjacent stacks (ST1, ST2), respectively. The first charge generation layer (CGL1) can double the efficiency of the current generated in the adjacent stacks (ST1, ST2) and can play a role in controlling the balance of charges between the adjacent stacks (ST1, ST2).

[0397] Each of the first charge generation layers (CGL1) may include an n-type layer and a p-type layer. The first charge generation layer (CGL1) may have a structure in which the n-type layer and the p-type layer are bonded to each other. However, the present invention is not limited thereto, and the first charge generation layer (CGL1) may include only one of the n-type layer and the p-type layer. The n-type layer may be a charge generation layer that provides electrons to an adjacent stack. The n-type layer may be a layer in which an n-dopant is doped into a base material. The p-type layer may be a charge generation layer that provides holes to an adjacent stack.

[0398] In one embodiment, the thickness of each of the first charge generation layers (CGL1) may be 1 angstrom or more and 150 angstroms or less. The concentration of the n-dopant doped in the first charge generation layer (CGL1) may be 0.1% or more and 3% or less, and specifically, 1% or less. When the concentration is less than 0.1%, the effect of the first charge generation layer (CGL1) for controlling the balance of charges may hardly occur. When the concentration is greater than 3%, the light efficiency of the light-emitting element (OLED) may be reduced.

[0399] Each of the first charge generation layers (CGL1) may include a charge generation compound composed of an aryl amine organic compound, a metal, an oxide, carbide, fluoride of a metal, or a mixture thereof. For example, the aryl amine organic compound may include α-NPD, 2-TNATA, TDATA, MTDATA, sprio-TAD, or sprio-NPB. The metal may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). The oxides, carbides, and fluorides of the metal may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF, LiF, or CsF. However, the material of the first charge generation layer (CGL1) is not limited to the above examples.

[0400] Each of the first and second light-emitting stacks (ST1, ST2) may include a light-emitting layer. The first light-emitting stack (ST1) may include a first light-emitting layer (BEML1), and the second light-emitting stack (ST2) may include a second light-emitting layer (BEML2). The light-emitting layers (BEML1, BEML2) included in the first and second light-emitting stacks (ST1, ST2) may emit light of the same color or light of different colors.

[0401] The light-emitting element (OLED) can emit light from the first electrode (AE) toward the second electrode (CE). In one embodiment of the light-emitting element (OLED), each of the stacks (ST1, ST2) can include a hole transport region (HTR1, HTR2) and an electron transport region (ETR1, ETR2). The hole transport region (HTR1, HTR2) can transfer holes provided from the first electrode (AE) or the first charge generation layer (CGL1) to the light-emitting layer. The electron transport region (ETR1, ETR2) can transfer electrons provided from the second electrode (CE) or the first charge generation layer (CGL1) to the light-emitting layer.

[0402] In one embodiment, the light-emitting device (OLED) has an illustrative structure in which the hole transport regions (HTR1, HTR2) are disposed below the light-emitting layers (BEML1, BEML2) included in the stacks (ST1, ST2) and the electron transport regions (ETR1, ETR2) are disposed above the light-emitting layers (BEML1, BEML2) included in the stacks (ST1, ST2) based on the light-emitting direction. That is, the light-emitting device (OLED) in one embodiment may have a forward device structure. However, the present invention is not limited thereto and may have an inverted device structure in which the electron transport regions (ETR1, ETR2) are disposed below the light-emitting layers (BEML1, BEML2) included in the stacks (ST1, ST2) and the hole transport regions (HTR1, HTR2) are disposed above the light-emitting layers (BEML1, BEML2) included in the stacks (ST1, ST2) based on the light-emitting direction.

[0403] Each of the hole transport regions (HTR1, HTR2) may include a hole injection layer (HIL1, HIL2) and a hole transport layer (HTL1, HTL2) disposed on the hole injection layer (HIL1, HIL2). The hole transport layer (HTL1, HTL2) may contact a lower surface of the light emitting layer. However, the present invention is not limited thereto, and the hole transport regions (HTR1, HTR2) may further include a hole-side additional layer disposed on the hole transport layer (HTL1, HTL2). The hole-side additional layer may include at least one of a hole buffer layer, a light emitting auxiliary layer, and an electron blocking layer. The hole buffer layer may be a layer that compensates for a resonance distance according to a wavelength of light emitted from the light emitting layer to increase light emission efficiency. The electron blocking layer may be a layer that serves to prevent electron injection from the electron transport region to the hole transport region.

[0404] The electron transport region (ETR1, ETR2) may include an electron transport layer. The electron transport region (ETR1, ETR2) may further include an electron injection layer disposed on the electron transport layer. For example, the second electron transport region (ETR2) included in the second light-emitting stack (ST2) may further include a second electron injection layer (EIL2) disposed on the second electron transport layer (ETR2). The electron transport region (ETR1, ETR2) may further include an electron-side additional layer disposed between the electron transport layer and the light-emitting layers (BEML1, BEML2). The electron-side additional layer may include at least one of an electron buffer layer and a hole blocking layer.

[0405] In a light-emitting device (OLED) according to one embodiment, the first electrode (AE) may be a reflective electrode. For example, the first electrode (AE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (for example, a mixture of Ag and Mg) having high reflectivity. Alternatively, the first electrode (AE) may have a multi-layer structure including a reflective film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the first electrode (AE) may have a two-layer structure of ITO / Ag and a three-layer structure of ITO / Ag / ITO, but is not limited thereto. In addition, the embodiment is not limited thereto, and the first electrode (AE) may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, or an oxide of the above-described metal materials. The thickness of the first electrode (AE) may be about 70 nm to about 1000 nm. For example, the thickness of the first electrode (AE) may be about 100 nm to about 300 nm.

[0406] In a light-emitting device (OLED) according to one embodiment, each of the hole transport regions (HTR1, HTR2) may have a multilayer structure having a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials.

[0407] Each of the hole transport regions (HTR1, HTR2) can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0408] Each of the hole transport regions (HTR1, HTR2) contains phthalocyanine compounds such as copper phthalocyanine, DNTPD (N1,N1'-([1,1'-biphenyl]-4,4'-diyl)bis(N1-phenyl-N4,N4-di-m-tolylbenzene-1,4-diamine)), m-MTDATA (4,4',4"-[tris(3-methylphenyl)phenylamino] triphenylamine), TDATA (4,4'4"-Tris(N,N-diphenylamino)triphenylamine), 2-TNATA (4,4',4"-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), PEDOT / PSS (Poly(3,4-ethylenedioxythiophene) / Poly(4-styrenesulfonate)), It may include PANI / DBSA (Polyaniline / Dodecylbenzenesulfonic acid), PANI / CSA (Polyaniline / Camphor sulfonicacid), PANI / PSS (Polyaniline / Poly(4-styrenesulfonate)), NPB (N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), polyether ketone containing triphenylamine (TPAPEK), 4-Isopropyl-4'-methyldiphenyliodonium [Tetrakis(pentafluorophenyl)borate], HATCN (dipyrazino[2,3-f: 2',3'-h] quinoxaline-2,3,6,7,10,11-hexacarbonitrile), etc.

[0409] Each of the hole transport regions (HTR1, HTR2) is composed of carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), TCTA (4,4',4"-tris(N-carbazolyl)triphenylamine), NPB (N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), TAPC (4,4'-Cyclohexylidene bis[N,N-bis(4-methylphenyl)benzenamine]), HMTPD (4,4'-Bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl), It may also contain mCP (1,3-Bis(N-carbazolyl)benzene).

[0410] Additionally, each of the hole transport regions (HTR1, HTR2) may include CzSi (9-(4-tert-Butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole), CCP (9-phenyl-9H-3,9'-bicarbazole), or mDCP (1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene).

[0411] The hole transport region (HTR1, HTR2) may include the compounds of the above-described hole transport region in at least one of the hole injection layer (HIL1, HIL2), the hole transport layer (HTL1, HTL2), and the hole-side additional layer.

[0412] The thickness of each of the hole transport regions (HTR1, HTR2) may be from about 10 nm to about 1000 nm, for example, from about 10 nm to about 500 nm. The thickness of each of the hole injection layers (HIL1, HIL2) may be from about 5 nm to about 100 nm, for example. The thickness of each of the hole transport layers (HTL1, HTL2) may be from about 5 nm to about 100 nm. When the hole transport regions (HTR1, HTR2) include a hole-side additional layer, the thickness of the hole-side additional layer may be from about 1 nm to about 100 nm. When the thicknesses of the hole transport regions (HTR1, HTR2) and each layer included therein satisfy the ranges described above, satisfactory hole transport characteristics can be obtained without a substantial increase in driving voltage.

[0413] In addition to the aforementioned materials, each of the hole transport regions (HTR1, HTR2) may further include a charge generating material to improve conductivity. The charge generating material may be uniformly or non-uniformly dispersed within the hole transport regions (HTR1, HTR2). The charge generating material may be, for example, a p-type dopant. The p-type dopant may include, but is not limited to, at least one of a halogenated metal compound, a quinone derivative, a metal oxide, and a cyano group-containing compound. For example, the p-type dopant may include, but is not limited to, halogenated metal compounds such as CuI and RbI, quinone derivatives such as TCNQ (Tetracyanoquinodimethane) and F4-TCNQ (2,3,5,6-tetrafluoro-7,7'8,8-tetracyanoquinodimethane), and metal oxides such as tungsten oxide and molybdenum oxide.

[0414] The first light-emitting layer (BEML1) and the second light-emitting layer (BEML2) may be a blue light-emitting layer or a green light-emitting layer. The blue light-emitting layer or the green light-emitting layer may include a host material and a dopant material. Each of the blue light-emitting layer and the green light-emitting layer may include a material including a carbazole derivative moiety or an amine derivative moiety as a hole-transporting host material. Each of the blue light-emitting layer and the green light-emitting layer may include a material including a nitrogen-containing aromatic ring structure such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, or a triazine derivative moiety as an electron-transporting host material.

[0415] Each of the blue light-emitting layer and the green light-emitting layer may include, as a host material, an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a chrysene derivative, a dihydrobenzanthracene derivative, or a triphenylene derivative. In addition, each of the blue light-emitting layer and the green light-emitting layer may further include, as a host material, a general material known in the art. For example, each of the blue emitting layer and the green emitting layer may include at least one of DPEPO (Bis[2-(diphenylphosphino)phenyl] ether oxide), CBP (4,4'-Bis(carbazol-9-yl)biphenyl), mCP (1,3-Bis(carbazol-9-yl)benzene), PPF (2,8-Bis(diphenylphosphoryl)dibenzo[b,d]furan), TCTA (4,4',4''-Tris(carbazol-9-yl)-triphenylamine), and TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazole-2-yl)benzene) as a host material.However, it is not limited thereto, and for example, Alq3(tris(8-hydroxyquinolino)aluminum), PVK(poly(N-vinylcarbazole), ADN(9,10-di(naphthalene-2-yl)anthracene), TBADN(2-tert-butyl-9,10-di(naphth-2-yl)anthracene), DSA(distyrylarylene), CDBP(4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl), MADN(2-Methyl-9,10-bis(naphthalen-2-yl)anthracene), CP1(Hexaphenyl cyclotriphosphazene), UGH2 (1,4-Bis(triphenylsilyl)benzene), DPSiO3(Hexaphenylcyclotrisiloxane), DPSiO4(Octaphenylcyclotetra siloxane), etc. can be used as the host material.

[0416] In one embodiment, the blue emitting layer is a known fluorescent dopant material, such as a styryl derivative (e.g., 1, 4-bis[2-(3-N-ethylcarbazoryl)vinyl]benzene (BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene (DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylbenzenamine (N-BDAVBi)), 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl (DPAVBi), perylene and its derivatives (e.g., 2, 5, 8, 11-Tetra-t-butylperylene (TBP)), pyrene and its derivatives (e.g., It may include 1, 1-dipyrene, 1, 4-dipyrenylbenzene, 1, 4-Bis(N, N-Diphenylamino)pyrene, etc.

[0417] The green light-emitting layer may include a known phosphorescent dopant material. For example, the phosphorescent dopant may be a metal complex including iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm). Specifically, FIrpic (iridium(III) bis(4,6-difluorophenylpyridinato-N,C2')picolinate), Fir6 (Bis(2,4-difluorophenylpyridinato)-tetrakis(1-pyrazolyl)borate iridium(Ⅲ)), or PtOEP (platinum octaethyl porphyrin) may be used as the phosphorescent dopant.

[0418] Each of the electron transport regions (ETR1, ETR2) may have a multilayer structure including a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials. For example, at least some of the electron transport regions (ETR1, ETR2) may include an electron transport layer (ETL4) and an electron injection layer (EIL4).

[0419] Each of the electron transport regions (ETR1, ETR2) can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0420] The electron transport domain (ETR1, ETR2) may contain an anthracene compound. However, it is not limited thereto, and each of the electron transport domains (ETR1, ETR2) may be, for example, Alq3 (Tris(8-hydroxyquinolinato)aluminum), 1,3,5-tri[(3-pyridyl)-phen-3-yl]benzene, T2T (2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine), 2-(4-(N-phenylbenzoimidazol-1-yl)phenyl)-9,10-dinaphthylanthracene, TPBi (1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene), BCP (2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-Diphenyl-1,10-phenanthroline), It may include TAZ(3-(4-Biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(Naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD(2-(4-Biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq(Bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-Biphenyl-4-olato)aluminum), Bebq2(berylliumbis(benzoquinolin-10-olate)), ADN(9,10-di(naphthalene-2-yl)anthracene), BmPyPhB(1,3-Bis[3,5-di(pyridin-3-yl)phenyl]benzene) and mixtures thereof.

[0421] In addition, each of the electron transport regions (ETR1, ETR2) may include a halogenated metal such as LiF, NaCl, CsF, RbCl, RbI, CuI, KI, a lanthanide metal such as Yb, and a co-deposition material of the halogenated metal and the lanthanide metal. For example, the electron transport regions (ETR1, ETR2) may include KI:Yb, RbI:Yb, etc. as the co-deposition material. The electron transport regions (ETR1, ETR2) may include two or more materials selected from Mg, Ag, Yb, and Al. For example, the electron transport regions (ETR1, ETR2) may include Mg and Yb.

[0422] Meanwhile, the electron transport regions (ETR1, ETR2) may use metal oxides such as Li2O, BaO, or Liq (8-hydroxyl-Lithium quinolate), but the embodiment is not limited thereto. Each of the electron transport regions (ETR1, ETR2) may also be formed of a material in which an electron transport material and an insulating organometal salt are mixed. The organometal salt may be a material having an energy band gap of approximately 4 eV or more. Specifically, for example, the organometal salt may include metal acetate, metal benzoate, metal acetoacetate, metal acetylacetonate, or metal stearate.

[0423] Each of the electron transport regions (ETR1, ETR2) may further include at least one of BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline) and Bphen (4,7-diphenyl-1,10-phenanthroline) in addition to the aforementioned materials, but the embodiments are not limited thereto.

[0424] The electron transport region (ETR1, ETR2) may include the compounds of the electron transport region described above in the electron injection layer or the electron transport layer. When the electron transport region (ETR1, ETR2) includes an electron-side additional layer, the electron-side additional layer may include the above-described material. In one embodiment, the electron injection layer (EIL4) may be composed of two or more materials selected from Mg, Ag, Yb, and Al. The electron injection layer (EIL4) may be composed of a mixture of Mg and Yb, for example.

[0425] The thickness of each of the electron transport regions (ETR1, ETR2) may be, for example, about 10 nm to about 150 nm. The thickness of the electron transport layer may be, for example, about 0.1 nm to about 100 nm, for example, about 0.3 nm to about 50 nm. When the thickness of the electron transport layer satisfies the range described above, satisfactory electron transport characteristics can be obtained without a substantial increase in driving voltage.

[0426] The second electrode (CE) is provided on a plurality of stacks (ST1, ST2). The second electrode (CE) may be a common electrode. The second electrode (CE) may be a cathode or an anode, but the embodiment is not limited thereto. For example, when the first electrode (AE) is an anode, the second electrode (CE) may be a cathode, and when the first electrode (AE) is a cathode, the second electrode (CE) may be an anode.

[0427] The second electrode (CE) may be a semi-transmissive electrode or a transmissive electrode. When the second electrode (CE) is a transmissive electrode, the second electrode (CE) may be made of a transparent metal oxide, for example, ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc.

[0428] When the second electrode (CE) is a semi-transmissive electrode or a reflective electrode, the second electrode (CE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture containing these (for example, AgMg, AgYb, or MgAg). Alternatively, the second electrode (CE) may have a multi-layer structure including a reflective film or a semi-transmissive film formed of the above material and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the second electrode (CE) may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, or an oxide of the above-described metal materials.

[0429] Meanwhile, a protective layer (CPL) may be further disposed on the second electrode (CE) of the light-emitting element (OLED) of one embodiment. The protective layer (CPL) may include multiple layers or a single layer.

[0430] In one embodiment, the protective layer (CPL) may be an organic layer or an inorganic layer. For example, when the protective layer (CPL) comprises an inorganic material, the inorganic material may comprise an alkali metal compound such as LiF, an alkaline earth metal compound such as MgF2, SiON, SiNX, SiOy, or the like.

[0431] For example, when the protective layer (CPL) includes an organic material, the organic material may include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, TPD15 (N4,N4,N4',N4'-tetra (biphenyl-4-yl) biphenyl-4,4'-diamine), TCTA (4,4',4"- Tris (carbazol sol-9-yl) triphenylamine), etc., or may include an acrylate such as an epoxy resin or a methacrylate.

[0432] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes to the present invention can be made without departing from the spirit and technical scope of the present invention as set forth in the claims to be described below.

[0433] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

[0434] According to the present invention, a pixel unit including pixels, a power line connected to the pixels, contact electrodes, an interlayer insulating layer disposed between the power lines and the contact electrodes, grooves exposing at least a portion of the contact electrodes, a second electrode included in the pixels is connected to the contact electrode in an area overlapping the groove, and the contact electrode is connected to the power line through a contact hole penetrating the interlayer insulating layer, thereby providing an electronic device capable of providing a constant driving voltage regardless of the size / area of ​​a display area and reducing an unnecessary area, and thus has high industrial applicability.

Claims

1. A base substrate including a display area and a non-display area including light-emitting areas and a non-light-emitting area arranged between the light-emitting areas; Power lines overlapping the above display area and arranged on the base substrate; A pixel unit comprising pixels, each pixel including a light-emitting element including a first electrode, a second electrode disposed on the first electrode, and a common layer disposed between the first electrode and the second electrode; Contact electrodes each surrounding the light-emitting element and arranged in the non-light-emitting region; an interlayer insulating layer disposed between the power lines and the contact electrodes; and a groove overlapping the non-luminous region and each groove exposing at least a portion of the contact electrode, and a sandwich insulating layer disposed on the interlayer insulating layer; The second electrode is connected to the contact electrode in an area overlapping the groove, The above contact electrode is an electronic device connected to the power line through a contact hole penetrating the interlayer insulating layer.

2. In paragraph 1, Further comprising a first sealing layer and a second sealing layer covering the light-emitting element and contacting each other in the light-emitting areas and the non-light-emitting area, An electronic device wherein the first sealing layer and the second sealing layer comprise an inorganic material.

3. In paragraph 2, Further comprising a pixel defining film comprising an inorganic material, wherein openings exposing at least a portion of each of the first electrodes are defined, a via insulating layer disposed between the interlayer insulating layer and the pixel defining film and comprising an organic material, and a protective layer disposed on the second electrodes, An electronic device in which the via insulating layer, the pixel defining film, the common layer, the second electrode, and the protective layer are short-circuited within the groove.

4. In paragraph 3, The encapsulation region, which overlaps the non-emission region and is positioned between the adjacent light-emitting elements among the pixel definition film, is exposed by the common layer, the second electrode, the protective layer, and the first encapsulation layer. An electronic device in which the pixel defining film in the above encapsulation area is in contact with the second encapsulation layer.

5. In paragraph 4, An electronic device in which the interlayer insulating layer is not disposed and the interlayer insulating layer is disposed at the lower part of the above-mentioned bag region.

6. In paragraph 3, Among the above contact electrodes, the side adjacent to the light-emitting region is exposed from the insulating layer between the grooves, The second electrode is an electronic device in contact with the exposed side surface.

7. In paragraph 6, The above side has a certain curvature, The above contact electrodes are electronic devices containing molybdenum.

8. In the first paragraph, An electronic device comprising a first pattern layer and a second pattern layer sequentially laminated on the interlayer insulating layer and overlapping the contact electrodes, wherein the first pattern layer and the second pattern layer comprise different inorganic materials.

9. In paragraph 8, An electronic device wherein a portion of the first pattern layer is exposed from the second pattern layer.

10. In paragraph 9, An electronic device in which the common layer is in contact with a side surface of the first pattern layer and a side surface of the second pattern layer within the groove.

11. In paragraph 6, A portion of the insulating layer adjacent to the groove and disposed in the non-luminous region protrudes in a direction toward the luminous region more than the contact electrode, An electronic device in which a trench groove is defined, wherein the above-mentioned portion protrudes upward and defines a predetermined internal space.

12. In paragraph 3, Further comprising a dam pattern overlapping the non-luminous region and surrounding at least a portion of the luminous region, An electronic device wherein the dam pattern includes a first pattern disposed on the pixel defining film and a second pattern disposed on the first pattern.

13. In paragraph 12, The first pattern and the second pattern contain different inorganic materials, The thickness of the first pattern is greater than the thickness of the second pattern, An electronic device wherein the width of the first pattern is smaller than the width of the second pattern.

14. In paragraph 13, The common layer, the second electrode, and the protective layer arranged in the non-luminous region are disconnected by the dam pattern, An electronic device in which the above dam pattern is covered by the first sealing layer and the second sealing layer.

15. In paragraph 3, A portion of the upper surface of the contact electrode is exposed from the insulating layer between the grooves, The above second electrode is an electronic device in contact with the exposed upper surface.

16. In paragraph 15, The above contact electrode includes first to third conductive layers sequentially laminated on the interlayer insulating layer, An electronic device wherein the first conductive layer and the third conductive layer comprise titanium, and the second conductive layer comprises aluminum.

17. In paragraph 16, An electronic device wherein the side of the insulating layer defining the groove and overlapping the non-luminous region has a predetermined curvature.

18. In paragraph 2, Further comprising: a pixel defining film comprising an inorganic material and disposed on the interlayer insulating layer, wherein openings exposing at least a portion of each of the first electrodes are defined; and an auxiliary electrode disposed on the interlayer insulating layer in the non-emitting region and covered by the pixel defining film. An electronic device in which the auxiliary electrode is connected to the contact electrode through a contact hole defined in the pixel definition film.

19. In paragraph 18, A portion of the upper surface of the contact electrode is exposed from the insulating layer between the grooves, An electronic device disposed on the upper surface, wherein a portion of the common layer is exposed within the groove.

20. In paragraph 18, An electronic device wherein the second electrode is disposed on the part of the common layer within the groove, and a side of the auxiliary electrode adjacent to the light-emitting region is in contact with the second electrode.

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