Display apparatus and electronic device including same

Abstract

This display apparatus comprises: a substrate including a display area including first areas and second areas, and a non-display area; a gate driving circuit disposed in the non-display area; a first write gate line extending in a first direction and electrically connected to the gate driving circuit; a second write gate line extending in the first direction to pass through the first areas and the second areas, and overlapping the first write gate line; first contact parts disposed between the first write gate line and the second write gate line and electrically connecting the first write gate line and the second write gate line; and pixels disposed in each of the first areas and the second areas of the display area and each including sub-pixels electrically connected to the second write gate line, wherein the first contact parts of the second write gate line are disposed in the second areas.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device and a structure of an electronic device including the same.

[0002] In recent years, electronic devices containing display devices have become increasingly diverse in their applications. Furthermore, the thinner and lighter these devices are, the broader their range of applications is expanding.

[0003] As electronic devices including display devices are utilized in various ways, there may be various methods for designing the form of the display device, and the functions that can be grafted or linked to the display device are also increasing.

[0004] Embodiments of the present invention can provide a display device with improved display quality and an electronic device including the same. However, these tasks are exemplary and do not limit the scope of the present invention.

[0005] According to one embodiment of the present invention, a display device includes a substrate including a display area including a plurality of first areas and a plurality of second areas and a non-display area surrounding at least a portion of the display area, a gate driving circuit disposed in the non-display area, a first write gate line extending in a first direction and electrically connected to the gate driving circuit, a second write gate line extending in the first direction so as to pass through the first areas and the second areas on a plane and overlapping the first write gate line, first contact portions disposed between the first write gate line and the second write gate line and electrically connecting the first write gate line and the second write gate line, and pixels including subpixels disposed in each of the first areas and the second areas of the display area and each electrically connected to the second write gate line, wherein the first contact portions may be disposed in the second areas and may not be disposed in the first areas.

[0006] In one embodiment, the first contact portions of the second write gate line may be arranged spaced apart from each of the first regions.

[0007] In one embodiment, the first contact portions may not overlap with each of the first regions.

[0008] In one embodiment, the second regions are spaced apart from the non-display region in the first direction, and at least one of the first regions can be disposed between the non-display region and the plurality of second regions.

[0009] In one embodiment, the first regions and the second regions may be arranged alternately along the first direction.

[0010] In one embodiment, each of the pixels includes a first subpixel, a second subpixel, and a third subpixel, and a first subpixel circuit region in which a first subpixel circuit of the first subpixel is arranged, a second subpixel circuit region in which a second subpixel circuit of the second subpixel is arranged, and a third subpixel circuit region in which a third subpixel circuit of the third subpixel is arranged are arranged adjacent to each other in the first direction, and the first contact portions may be arranged in each of the second regions to correspond to each of the first subpixel circuit region, the second subpixel circuit region, and the third subpixel circuit region.

[0011] In one embodiment, the width of one of the first regions in the first direction may be greater than the width of one of the second regions in the first direction.

[0012] In one embodiment, the total number of pixels arranged in each of the first regions may be greater than the total number of pixels arranged in each of the second regions.

[0013] In one embodiment, the display device further includes an insulating layer disposed between the first write gate line and the second write gate line, the insulating layer defining contact holes penetrating the insulating layer, and the first contact portions can be respectively disposed within the contact holes. In one embodiment, the first write gate line includes a first lower write gate line and a first upper write gate line, and the first upper write gate line is disposed on the first lower write gate line and can overlap the first lower write gate line on a plane.

[0014] In one embodiment, the display device further includes second contact portions disposed between the first lower write gate line and the first upper write gate line and electrically connecting the first lower write gate line and the first upper write gate line, and the second contact portions may be disposed in each of the first regions and the second regions.

[0015] In one embodiment, the second write gate line may be disposed above the first write gate line.

[0016] In one embodiment, the second write gate line may be positioned below the first write gate line.

[0017] In one embodiment, each of the subpixels includes a data write transistor to which a data voltage is applied, and the second write gate line can be electrically connected to a gate electrode of the data write transistor.

[0018] In one embodiment, the display device further includes a data line extending along a second direction intersecting the first direction, wherein the data line can be electrically connected to the data write transistor.

[0019] According to one embodiment of the present invention, a display device includes a substrate including a display area and a non-display area surrounding at least a portion of the display area, a gate driving circuit disposed in the non-display area, a first write gate line extending in a first direction and electrically connected to the gate driving circuit, a second write gate line extending in the first direction and overlapping the first write gate line in a plane, first contact portions disposed between the first write gate line and the second write gate line and electrically connecting the first write gate line and the second write gate line, and pixels disposed in the display area and including sub-pixels each electrically connected to the second write gate line, wherein a total number of the first contact portions may be smaller than a total number of the sub-pixels electrically connected to the second write gate line.

[0020] In one embodiment, the display area includes a plurality of first areas and a plurality of second areas, at least one of the pixels is arranged in each of the first areas and the second areas, each of the first writing gate line and the second writing gate line extends through the first areas and the second areas, and the first contact portions are arranged in the second areas and may not be arranged in the first areas. In one embodiment, the second areas are spaced apart from the non-display area in the first direction, and at least one of the first areas may be arranged between the non-display area and the plurality of second areas in the first direction.

[0021] In one embodiment, the first regions and the second regions may be arranged alternately along the first direction.

[0022] In one embodiment, each of the plurality of pixels includes a first subpixel, a second subpixel, and a third subpixel, and a first subpixel circuit region in which a first subpixel circuit of the first subpixel is arranged, a second subpixel circuit region in which a second subpixel circuit of the second subpixel is arranged, and a third subpixel circuit region in which a third subpixel circuit of the third subpixel is arranged are arranged adjacent to each other in the first direction, and the first contact portions may be arranged in each of the second regions to correspond to each of the first subpixel circuit region, the second subpixel circuit region, and the third subpixel circuit region.

[0023] An electronic device according to one embodiment of the present invention includes a display device including a processor and a controller that receives a control signal from the processor and outputs a scan control signal based on the control signal, the display device including a substrate including a display area including first areas and second areas and a non-display area surrounding at least a portion of the display area, a gate driving circuit disposed in the non-display area, a first writing gate line extending in a first direction and electrically connected to the gate driving circuit, a second writing gate line extending in the first direction so as to pass through the first areas and the second areas and overlapping the first writing gate line on a plane, first contact portions disposed between the first writing gate line and the second writing gate line and electrically connecting the first writing gate line and the second writing gate line, and pixels including subpixels disposed in each of the first areas and the second areas of the display area and each electrically connected to the second writing gate line, the first contact portions being disposed in the second areas, and the first May not be deployed in areas.

[0024] According to embodiments of the present invention, a display device with improved display quality and an electronic device including the same can be provided. Of course, the scope of the present invention is not limited by these effects.

[0025] FIG. 1A is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention.

[0026] FIG. 1b is an exploded perspective view of an electronic device according to one embodiment of the present invention.

[0027] FIG. 2 is a block diagram schematically illustrating an electronic device according to one embodiment of the present invention.

[0028] FIG. 3 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0029] FIG. 4 is an equivalent circuit diagram schematically showing a subpixel circuit of one subpixel of a display device according to one embodiment of the present invention and a light-emitting diode electrically connected to the subpixel circuit.

[0030] FIG. 5 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0031] FIG. 6 is an enlarged plan view illustrating an enlarged portion of a portion of a display device according to one embodiment of the present invention.

[0032] FIG. 7 is a cross-sectional view schematically showing a cross-section of a display device according to one embodiment cut along the line II' of FIG. 6.

[0033] FIG. 8 is a cross-sectional view schematically showing a cross-section of a display device according to one embodiment cut along the line II' of FIG. 6.

[0034] FIG. 9 is a cross-sectional view schematically showing a cross-section of a display device according to one embodiment cut along the line II' of FIG. 6.

[0035] Fig. 10 is a cross-sectional view showing a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0036] FIG. 11 is a plan view showing the first to third subpixel circuit regions of the first to third subpixels included in one pixel arranged in the first region of a display device according to one embodiment of the present invention.

[0037] FIG. 12 is a plan view showing the first to third subpixel circuit regions of the first to third subpixels included in one pixel arranged in the second region of a display device according to one embodiment of the present invention.

[0038] Fig. 13 is a cross-sectional view schematically showing a cross-section of one embodiment cut along the II-II' cutting line of Fig. 11.

[0039] Fig. 14 is a cross-sectional view schematically showing a cross-section of one embodiment cut along the III-III' cutting line of Fig. 12.

[0040] FIGS. 15 to 19 are plan views according to the stacking order of the components of each layer constituting the first to third subpixels in the second area of ​​the display device illustrated in FIG. 12.

[0041] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0043] In the examples below, the terms first, second, 1-1, 1-2, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0044] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0045] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0046] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0047] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0048] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0049] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. In addition, “at least one of A and B” or “at least one of A or B” refers to the case where it is A, or B, or both A and B.

[0050] In the following examples, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0051] The x-axis, y-axis, and z-axis are not limited to the three axes in the Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0052] FIG. 1A is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention. FIG. 1B is an exploded perspective view of an electronic device according to one embodiment of the present invention.

[0053] An electronic device (1) according to one embodiment is a device that displays a moving image or a still image, and may be a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), and the like, as well as various products such as a television, a laptop, a monitor, a billboard, and an Internet of Things (IOT) or a part thereof. In addition, the electronic device (1) according to one embodiment may be a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD), or a part thereof. An electronic device (1) according to one embodiment may be a dashboard of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, a display placed on the rear seat entertainment of a vehicle or the back of a front seat, a head-up display (HUD) installed at the front of a vehicle or projected on a front window glass, or a holographic augmented reality head-up display (CGH AR HUD).

[0054] For example, the electronic device (1) may be one of a flat panel display, a curved display, a computer monitor, a medical monitor, a television, a billboard, an indoor or outdoor lighting and / or signal light, a head-up display, a fully or partially transparent display, a flexible display, a rollable display, a foldable display, a stretchable display, a laser printer, a telephone, a mobile phone, a tablet, a phablet, a personal digital assistant (PDA), a wearable device, a laptop computer, a digital camera, a camcorder, a viewfinder, a microdisplay, a 3D display, a virtual reality or augmented reality display, an automotive display, a video wall including multiple displays tiled together, a theater or stadium screen, a light therapy device, and a signage.

[0055] Referring to FIGS. 1A and 1B, the electronic device (1) can display an image in a third direction (e.g., the z direction) perpendicular to a first direction (e.g., the x direction) and a second direction (e.g., the y direction). The image can include a still image as well as a dynamic image.

[0056] An electronic device (1) can detect user input applied from outside. The user input may include various forms of external input, such as a part of the user's body, light, heat, or pressure. The user input may be provided in various forms. Depending on the structure of the electronic device (1), the electronic device (1) may also detect user input applied to the side or back of the electronic device (1).

[0057] An electronic device (1) may include a cover window (CW), a housing (HU), and a display device (10). In one embodiment, the cover window (CW) and the housing (HU) may be combined to form the exterior of the electronic device (1).

[0058] The cover window (CW) may include a light-transmitting area (LTA) and a bezel area (BZA). The light-transmitting area (LTA) may be an optically transparent area. For example, the light-transmitting area (LTA) may be an area with a visible light transmittance of about 90% or greater.

[0059] The bezel area (BZA) can define the shape of the light-transmitting area (LTA). The bezel area (BZA) can be adjacent to the light-transmitting area (LTA) and surround the light-transmitting area (LTA). The bezel area (BZA) can be an area having relatively low light transmittance compared to the light-transmitting area (LTA). The bezel area (BZA) can include an opaque material that blocks light. The bezel area (BZA) can have a predetermined color. The bezel area (BZA) can be defined by a bezel layer provided separately from a transparent substrate defining the light-transmitting area (LTA), or by an ink layer formed by inserting or coloring the transparent substrate.

[0060] A housing (HU) can be coupled with a cover window (CW). The housing (HU) can accommodate a display device (10). The housing (HU) can include a rear surface and a side surface. A cover window (CW) can be arranged on a front surface of the housing (HU). That is, the cover window (CW) can be arranged above the housing (HU). The housing (HU) can be coupled with the cover window (CW) to provide a predetermined accommodation space. The display device (10) can be accommodated in a predetermined accommodation space provided between the housing (HU) and the cover window (CW).

[0061] The housing (HU) may comprise a material with relatively high rigidity. For example, the housing (HU) may comprise a plurality of frames and / or plates made of glass, plastic, or metal, or a combination thereof. The housing (HU) can reliably protect the components of the electronic device (1) housed within the internal space from external impact.

[0062] The display device (10) can display an image. The display device (10) can include a display area (DA) and a non-display area (NDA). Since the display device (10) includes a substrate (100, see FIG. 7), it can be said that the substrate (100) has a display area (DA) and a non-display area (NDA).

[0063] The display area (DA) may be an active area activated according to an electrical signal. In one embodiment, the display area (DA) may be an area where an image is displayed and, at the same time, an area where a user's input is detected. The display area (DA) may be an area where a plurality of pixels (P) are arranged. The plurality of pixels (P) may be repeatedly arranged along a first direction (e.g., an x ​​direction) and a second direction (e.g., a y direction). In one embodiment, the pixel (P) may include a first subpixel (SP1), a second subpixel (SP2), and a third subpixel (SP3).

[0064] The display area (DA) may overlap at least partially with the light-transmitting area (LTA) of the cover window (CW). For example, part or all of the display area (DA) may overlap with the light-transmitting area (LTA). Accordingly, a user may view an image or provide an external input through the light-transmitting area (LTA). However, the present invention is not limited thereto. In another example, the area where an image is displayed and the area where a user's input is detected within the display area (DA) may be separated from each other.

[0065] The non-display area (NDA) may overlap at least partially with the bezel area (BZA) of the cover window (CW). The non-display area (NDA) may be an area covered by the bezel area (BZA). The non-display area (NDA) may be adjacent to the display area (DA). The non-display area (NDA) may be an area where an image (IM) is not displayed. A driving circuit or driving wiring for driving the display area (DA) may be arranged in the non-display area (NDA).

[0066] Fig. 2 is a block diagram schematically illustrating an electronic device according to one embodiment of the present invention. Fig. 3 is a plan view schematically illustrating a display device according to one embodiment of the present invention. The “plan view” is a view viewed from the thickness direction (e.g., z direction) of the display device (10).

[0067] Referring to FIG. 2, an electronic device (1) may include a display device (10) and a processor (20). The display device (10) may include a pixel unit (11), a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0068] The pixel unit (11) may include a plurality of pixels (P, FIG. 1b) arranged in the display area (DA). Each subpixel (e.g., a first subpixel (SP1, FIG. 1b), a second subpixel (SP2, FIG. 1b), and a third subpixel (SP3, FIG. 1b)) included in the pixel (P, FIG. 1b) includes a subpixel circuit, and a display element (e.g., a light-emitting diode) may be electrically connected to the subpixel circuit. The subpixels may express an image in the display area (DA, FIG. 3) using light emitted from a display element corresponding to each subpixel. In one embodiment, each of the subpixels may emit red, green, or blue light. In another embodiment, each of the subpixels may emit red, green, blue, or white light. Figure 2 shows a subpixel (SP) located in the i-th (i is a natural number) row and j-th (j is a natural number) column among multiple subpixels. ij ) is shown as an example.

[0069] The subpixel circuit of each subpixel can be electrically connected to the gate line and the data line, and can include a plurality of transistors and at least one capacitor. FIG. 2 and FIG. 3 show a subpixel (SP) located in the i-th (i is a natural number) row and j-th (j is a natural number) column. ij ) is the gate line (GL) located in the i-th row i) and is connected to the data line (DLj) located in the jth column.

[0070] In the non-display area (NDA, Fig. 3), various conductive lines for transmitting electrical signals to be applied to the display area (DA, Fig. 3), peripheral circuits electrically connected to sub-pixel circuits, and pads to which printed circuit boards or driver IC chips are attached may be located. For example, the non-display area (NDA) may be provided with a gate driving circuit (13), a data driving circuit (15), a power supply circuit (17), and a controller (19).

[0071] The gate driving circuit (13) is electrically connected to a plurality of gate lines and can receive a scan control signal (GCS) from the controller (19). The gate driving circuit (13) can generate a gate signal in response to the scan control signal (GCS) and sequentially supply the gate signal to the gate lines. The gate signal may be a gate control signal that controls turning on and off a transistor of a subpixel electrically connected to the gate line. The gate signal may be a square wave signal including an on voltage that can turn on the transistor and an off voltage that can turn off the transistor. In one embodiment, the on voltage may be a high level voltage (first level voltage) or a low level voltage (second level voltage).

[0072] The gate driving circuit (13) is a gate line (GL) arranged in the i-th row (i is a natural number) i ) can provide a gate signal to the subpixels located in the ith (i is a natural number) row. For example, the gate driving circuit (13) can provide a gate signal to the subpixels located in the ith (i is a natural number) row through the gate line (GL i ) through the subpixel (SP) located at the i-th row (i is a natural number) and the j-th column (j is a natural number) ij ) can provide a gate signal to the gate line (GL). In other words, the gate line (GL i ) can transmit gate signals to sub-pixels in the same row.

[0073] In Fig. 2 and Fig. 3, any one of the subpixels (SP ij ) is one gate line (GL i ) is shown as being connected to a single subpixel (SP) but this is an example. ij ) is connected to two or more gate lines, and the gate driving circuit (13) can supply two or more gate signals with different timings of applying the on voltage to the corresponding gate lines. For example, one subpixel (SP ij ) are electrically connected to the first to fifth gate lines, and the gate driving circuit (13) can apply a first gate signal (GW), a second gate signal (GR), a third gate signal (EM), a fourth gate signal (GI), and a fifth gate signal (EMB) to the first gate lines, the second gate lines, the third gate lines, the fourth gate lines, and the fifth gate line, respectively.

[0074] The data driving circuit (15) is connected to a plurality of data lines and can supply a data signal (DATA) to the data lines in response to a data control signal (DCS) from the controller (19). The data signal (DATA) supplied to the data line can be provided to a subpixel circuit of a subpixel. The data driving circuit (15) can convert input image data having a grayscale input from the controller (19) into a data signal (DATA) in the form of a voltage or current.

[0075] The data drive circuit (15) is a data line (DL) arranged in the jth column (j is a natural number). j ) can provide a data signal (DATA) to the subpixels located in the jth (j is a natural number) column. For example, the data driving circuit (15) can provide a data signal (DATA) to the subpixels located in the jth (j is a natural number) column through the data line (DL) located in the jth (j is a natural number) column. j ) through the subpixel (SP) located at the i-th row (i is a natural number) and the j-th column (j is a natural number) ij ) can provide a data signal (DATA).

[0076] The power supply circuit (17) can generate voltages necessary for driving the subpixels in response to a power control signal (PCS) from the controller (19). The power supply circuit (17) can generate a driving voltage (ELVDD) and a common voltage (ELVSS) and supply them to the subpixels. The driving voltage (ELVDD) can be a high-level voltage provided to a first electrode (pixel electrode or anode) of a display element included in each subpixel. The common voltage (ELVSS) can be a low-level voltage provided to a second electrode (counter electrode or cathode) of a display element included in each subpixel. The power supply circuit (17) can generate a reference voltage (Vref) and an initialization voltage (Vaint) and supply them to the subpixels.

[0077] The voltage level of the driving voltage (ELVDD) can be higher than the voltage level of the common voltage (ELVSS). The voltage level of the reference voltage (Vref) can be lower than the voltage level of the driving voltage (ELVDD). The voltage level of the initialization voltage (Vaint) can be equal to or higher than the voltage level of the common voltage (ELVSS).

[0078] The controller (19) can receive a control signal (CS) and input data (IDAT) from an external processor (20) (e.g., an application processor (AP), a graphic processing unit (GPU), a central processing unit (CPU), an image signal processor, a sensor hub processor, or a communication processor, etc.). In one embodiment, the control signal (CS) may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. In another example, the controller (19) can output a scan control signal (GCS), a data control signal (DCS), and a power control signal (PCS) based on the control signal (CS) and the input data (IDAT) transmitted from the processor (20). The scan control signal (GCS), the data control signal (DCS), and the power control signal (PCS) generated by the controller (19) can be transmitted to the gate driving circuit (13), the data driving circuit (15), and the power supply circuit (17), respectively. The scan control signal (GCS) output to the gate drive circuit (13) may include a plurality of clock signals and a gate start signal. The data control signal (DCS) output to the data drive circuit (15) may include a source start signal and clock signals.

[0079] Referring to FIG. 3, the display device (10) may include a display area (DA) and a non-display area (NDA) outside the display area (DA). The non-display area (NDA) may surround at least a portion of the display area (DA).

[0080] When the display area (DA) is viewed in a planar shape, the display area (DA) may have a rectangular shape. In another embodiment, the display area (DA) may have a polygonal shape such as a triangle, a pentagon, a hexagon, a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have a rounded corner at an edge. In one embodiment, the display device (10) may have a display area (DA) of a shape in which a length in a first direction (e.g., an x-direction) is longer than a length in a second direction (e.g., an y-direction), as illustrated in FIG. 3. In another embodiment, the display device (10) may have a display area (DA) of a shape in which a length in a second direction (e.g., an y-direction) is longer than a length in the first direction (e.g., an x-direction).

[0081] The non-display area (NDA) may include a first non-display area (NDA1), a second non-display area (NDA2), a third non-display area (NDA3), and a fourth non-display area (NDA4).

[0082] The gate driving circuit (13) may be disposed in each of the first non-display area (NDA1) and the second non-display area (NDA2) disposed on both sides of the display area (DA). For example, each of the first non-display area (NDA1) and the second non-display area (NDA2) may be disposed adjacent to the display area (DA) along a first direction (e.g., the x direction). The gate driving circuit (13) may include drivers for providing an electrical signal to each gate electrode of the transistors electrically connected to the light-emitting diodes. Some of the sub-pixels disposed in the display area (DA) may be electrically connected to the gate driving circuit (13) disposed in the first non-display area (NDA1), and the rest may be connected to the gate driving circuit (13) disposed in the second non-display area (NDA2). Although FIG. 3 illustrates that a gate driving circuit (13) is disposed in each of the first non-display area (NDA1) and the second non-display area (NDA2), the present invention is not limited thereto. In another embodiment, the gate driving circuit (13) may be disposed in either the first non-display area (NDA1) or the second non-display area (NDA2).

[0083] The data driving circuit (15) may be disposed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). For example, each of the third non-display area (NDA3) and the fourth non-display area (NDA4) may be disposed adjacent to the display area (DA) in the second direction (e.g., the y direction). In one embodiment, FIG. 3 illustrates that the data driving circuit (15) is disposed in the fourth non-display area (NDA4). In another embodiment, the data driving circuit (15) may be disposed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0084] Although Fig. 3 illustrates that the data driving circuit (15) is arranged in the fourth non-display area (NDA4) of the display device (10), the present invention is not limited thereto. In another embodiment, the display device (10) may further include a flexible circuit board (not shown) electrically connected through a terminal portion (not shown) arranged in the fourth non-display area (NDA4), and the data driving circuit (15) may be arranged on the aforementioned flexible circuit board.

[0085] FIG. 4 is an equivalent circuit diagram schematically showing a subpixel circuit of one subpixel of a display device according to one embodiment of the present invention and a light-emitting diode electrically connected to the subpixel circuit.

[0086] Referring to FIG. 4, a subpixel circuit (SPC) may be electrically connected to a first gate line (GWL) for transmitting a first gate signal (GW), a second gate line (GRL) for transmitting a second gate signal (GR), a third gate line (EML) for transmitting a third gate signal (EM), a fourth gate line (GIL) for transmitting a fourth gate signal (GI), a fifth gate line (EMBL) for transmitting a fifth gate signal (EMB), and a data line (DL) for transmitting a data signal (DATA). The first gate signal (GW) may be a write gate signal, and the first gate line (GWL) may be referred to as a write gate line. Since the light emission of a light emitting diode (LED) is controlled by the third gate signal (EM) and the fifth gate signal (EMB), the third gate signal (EM) and the fifth gate signal (EMB) may be light emission control signals, and the third gate line (EML) and the fifth gate line (EMBL) may be referred to as light emission control lines. The subpixel circuit (SPC) can be electrically connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (Vref), and an initialization voltage line (VAL) that transmits an initialization voltage (Vaint).

[0087] In one embodiment, each of the plurality of transistors included in the subpixel circuit (SPC) may be an NMOS (n-channel MOSFET) including an oxide semiconductor layer. However, this is exemplary, and the transistors of the present invention are not limited thereto. In another embodiment, some of the plurality of transistors (T1, T2, T3, T4, T5, T6, T7, and T8) may be PMOS (p-channel MOSFETs), and the remaining some may be NMOS (n-channel MOSFETs). For example, the fifth transistor (T5) and / or the sixth transistor (T6) among the plurality of transistors may be PMOS, and the remaining transistors may be NMOS. For example, the PMOS (e.g., the fifth transistor (T5) and / or the sixth transistor (T6)) may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon), an organic semiconductor, etc.

[0088] The subpixel circuit (SPC) may include first to sixth transistors (T1, T2, T3, T4, T5, and T6), a first capacitor (C1), a second capacitor (C2), and an auxiliary capacitor (Ca). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal (DATA), and the second to sixth transistors (T2, T3, T4, T5, and T6) may be switching transistors that transmit signals. The first transistor (T1) may be referred to as a driving transistor, the second transistor (T2) as a data writing transistor, the third transistor (T3) as a compensation transistor, the fourth transistor (T4) as an initialization transistor, the fifth transistor (T5) as an operation control transistor, and the sixth transistor (T6) as an emission control transistor.

[0089] The first terminal (or first electrode) and the second terminal (or second electrode) of each of the first to sixth transistors (T1, T2, T3, T4, T5, and T6) may be a source (or source electrode) or a drain (or drain electrode) depending on the voltage of the first terminal and the second terminal. For example, depending on the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. Hereinafter, the node to which the first-first gate electrode of the first transistor (T1) is connected may be defined as a first node (N1), and the node to which the second terminal of the first transistor (T1) is connected may be defined as a second node (N2).

[0090] A first transistor (T1) may be connected to a driving voltage line (PL) and a light emitting diode (LED). The first transistor (T1) may be connected between a fifth transistor (T5) and a sixth transistor (T6). The first transistor (T1) may include a first gate electrode, a first terminal, and a second terminal connected to a second node (N2). The first transistor (T1) may include a 1-1 gate electrode connected to the first node (N1). The first transistor (T1) may further include a 1-2 gate electrode connected to its second terminal. The 1-1 gate electrode and the 1-2 gate electrode may be disposed to face each other in different layers. For example, the 1-1 gate electrode and the 1-2 gate electrode of the first transistor (T1) may face each other, and the semiconductor layer may be disposed between the 1-1 gate electrode and the 1-2 gate electrode of the first transistor (T1). In this specification, the first gate electrode of the first transistor (T1) may refer to the first-first gate electrode involved in turning on and off the first transistor (T1).

[0091] The first-first gate electrode of the first transistor (T1) may be connected to the second terminal of the second transistor (T2), the first terminal of the third transistor (T3), and the first capacitor (C1). The first-second gate electrode of the first transistor (T1) may be connected to the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first terminal of the first transistor (T1) may be connected to the driving voltage line (PL) via the fifth transistor (T5), and the second terminal may be connected to the pixel electrode of the light emitting diode (LED) via the sixth transistor (T6). The first terminal of the first transistor (T1) may be connected to the second terminal of the fifth transistor (T5). The second terminal of the first transistor (T1) may be connected to the first terminal of the sixth transistor (T6), the first capacitor (C1), and the second capacitor (C2). The first transistor (T1) can receive a data signal (DATA) according to the switching operation of the second transistor (T2) and control the amount of driving current flowing to the light-emitting diode (LED).

[0092] The second transistor (T2) may be connected to the data line (DL) and the first gate electrode of the first transistor (T1). The second transistor (T2) may include a second gate electrode connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second terminal of the second transistor (T2) may be connected to the first gate electrode of the first transistor (T1), a first terminal of a third transistor (T3), and a first capacitor (C1). The second transistor (T2) may be turned on by the first gate signal (GW) transmitted to the first gate line (GWL), electrically connect the data line (DL) and the first node (N1), and transmit the data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0093] A third transistor (T3) may be connected to a first gate electrode of the first transistor (T1) and a reference voltage line (VRL). The third transistor (T3) may include a third gate electrode connected to a second gate line (GRL), a first terminal connected to a first node (N1), and a second terminal connected to the reference voltage line (VRL). The first terminal of the third transistor (T3) may be connected to the first gate electrode of the first transistor (T1), the second terminal of the second transistor (T2), and the first capacitor (C1). The third transistor (T3) may be turned on by a second gate signal (GR) transmitted to the second gate line (GRL) and may transmit the reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1).

[0094] The fourth transistor (T4) may be connected to the sixth transistor (T6) and the initialization voltage line (VAL). The fourth transistor (T4) may be connected between a light emitting diode (LED) and the initialization voltage line (VAL). The fourth transistor (T4) may include a fourth gate electrode connected to a fourth gate line (GIL), a first terminal connected to a third node (N3), and a second terminal connected to the initialization voltage line (VAL). The first terminal of the fourth transistor (T4) may be connected to a second terminal of the sixth transistor (T6) and a pixel electrode of the light emitting diode (LED). The fourth transistor (T4) may be turned on by the fourth gate signal (GI) transmitted to the fourth gate line (GIL) and may transmit the initialization voltage (Vaint) transmitted to the initialization voltage line (VAL) to the third node (N3) and initialize the pixel electrode (e.g., anode) of the light emitting diode (LED).

[0095] The fifth transistor (T5) may be connected to the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a fifth gate electrode connected to the third gate line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a third gate signal (EM) transmitted to the third gate line (EML).

[0096] The sixth transistor (T6) may be connected to the first transistor (T1) and a light emitting diode (LED). The sixth transistor (T6) may be connected between the second node (N2) and the third node (N3). The sixth transistor (T6) may include a sixth gate electrode connected to the fifth gate line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The first terminal of the sixth transistor (T6) may be connected to the second terminal of the first transistor (T1), the first capacitor (C1), and the second capacitor (C2). The second terminal of the sixth transistor (T6) may be connected to the first terminal of the fourth transistor (T4) and the pixel electrode of the light emitting diode (LED). The sixth transistor (T6) may be turned on or off according to the fifth gate signal (EMB) transmitted to the fifth gate line (EMBL).

[0097] A first capacitor (C1) may be connected between a first gate electrode of a first transistor (T1) and a second terminal of the first transistor (T1). A first electrode of the first capacitor (C1) may be connected to a first node (N1), and a second electrode may be connected to a second node (N2). A first electrode of the first capacitor (C1) may be connected to a first gate electrode of the first transistor (T1), a second terminal of the second transistor (T2), and a first terminal of a third transistor (T3). A second electrode of the first capacitor (C1) may be connected to a second terminal of the first transistor (T1), the first-second gate electrodes, the second electrode of the second capacitor (C2), and a first terminal of a sixth transistor (T6). The first capacitor (C1) may be a storage capacitor and may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0098] When the third transistor (T3) and the fifth transistor (T5) are turned on, the first transistor (T1) can be turned on. When the voltage of the second terminal of the first transistor (T1) drops to the difference (Vref-Vth1) between the reference voltage (Vref) and the threshold voltage (Vth1) of the first transistor (T1), the first transistor (T1) is turned off, and a voltage corresponding to the threshold voltage (Vth1) of the first transistor (T1) is stored in the first capacitor (C1), so that the threshold voltage (Vth1) of the first transistor (T1) can be compensated.

[0099] The second capacitor (C2) may be connected between the driving voltage line (PL) and the second node (N2). The first electrode of the second capacitor (C2) may be connected to the driving voltage line (PL). The second electrode of the second capacitor (C2) may be connected to the second terminal and the first-second gate electrode of the first transistor (T1), the second electrode of the first capacitor (C1), and the first terminal of the sixth transistor (T6).

[0100] The capacitance of each of the first capacitor (C1) and the second capacitor (C2) may vary depending on the color of light emitted from the light emitting diode (LED).

[0101] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSSL), and the pixel electrode of the light emitting diode (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to the voltage difference between the pixel electrode of the light emitting diode (LED) and the sustain voltage line (VSSL), thereby preventing the problem of the black luminance increasing when the sixth transistor (T6) is turned off.

[0102] A light emitting diode (LED) can be connected to the first transistor (T1) via a sixth transistor (T6). The light emitting diode (LED) includes a pixel electrode (anode) connected to a third node (N3) and a counter electrode (cathode) facing the pixel electrode, and the counter electrode can receive a common voltage (ELVSS). In one embodiment, the counter electrode (cathode) can be electrically connected to a sustain voltage line (VSSL) that extends to a display area and provides the common voltage (ELVSS). A driving current output by the first transistor (T1) flows through the light emitting diode (LED) by the turned-on fifth transistor (T5) and the turned-on sixth transistor (T6), and the light emitting diode (LED) can emit light with a brightness corresponding to the magnitude of the driving current.

[0103] Although FIG. 4 illustrates that the subpixel circuit (SPC) includes six transistors, the present invention is not limited thereto. In another embodiment, the subpixel circuit (SPC) may include seven transistors. In another embodiment, the number of transistors in the subpixel circuit (SPC) may be five or less, or eight or more.

[0104] Fig. 5 is a plan view schematically illustrating a display device according to one embodiment of the present invention. Fig. 6 is an enlarged plan view illustrating a portion of a display device according to one embodiment of the present invention. Fig. 7 is a cross-sectional view schematically illustrating a cross-section of one embodiment taken along the line II' of Fig. 6.

[0105] FIG. 6 is an enlarged view of a portion of the display device (10) of FIG. 5, and exemplarily illustrates one of the first-first region (R1a), the first-second region (R1b), and the second region (R2), which are regions positioned at both ends of the first regions (R1) in the display region (DA).

[0106] Referring to FIGS. 5 and 6, the display device (10) may include a display area (DA) and a non-display area (NDA) disposed outside the display area (DA).

[0107] The display area (DA) may include first areas (R1) and second areas (R2). As illustrated in FIG. 6, at least one pixel (P) including subpixels (e.g., a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3) may be arranged in each of the first areas (R1) and the second areas (R2). Since the display device (10) includes a substrate (100, see FIG. 7), it may be said that the substrate (100, see FIG. 7) has a display area (DA) including first areas (R1) and second areas (R2).

[0108] Each of the second regions (R2) is spaced apart from the non-display area (NDA) in a first direction (e.g., x direction), and at least one of the first regions (R1) may be disposed between the second regions (R2) and the non-display area (NDA). For example, some of the first regions (R1) may be disposed in contact with the non-display area (NDA). For example, each of the first-first region (R1a) and the first-second region (R1b), which are disposed at opposite ends of the first regions (R1) along the first direction (e.g., x direction), may be disposed in contact with the non-display area (NDA). For example, each of the first-first region (R1a) and the first-second region (R1b) may be disposed closer to the non-display area (NDA) than the second regions (R2). In one embodiment, the first regions (R1) and the second regions (R2) may be arranged alternately along a first direction (e.g., the x-direction). In one embodiment, as illustrated in FIG. 5, the second regions (R2) may be arranged to be spaced apart from each other at equal intervals along the first direction (e.g., the x-direction). For example, the second regions (R2) may be positioned at positions 1 / 7, 2 / 7, 3 / 7, 4 / 7, 5 / 7, and 6 / 7 of the display area (DA), respectively. However, the present embodiment is not limited thereto. In one embodiment, the second regions (R2) may be arranged to be spaced apart from each other at uneven intervals along the first direction (e.g., the x-direction). In one embodiment, as illustrated in FIG. 5, six second regions (R2) and seven first regions (R1) are illustrated. However, the present embodiment is not limited thereto, and the number of first regions (R1) and second regions (R2) may be varied.

[0109] In one embodiment, the number of pixels (P) arranged in each of the first regions (R1) may be greater than the number of pixels (P) arranged in each of the second regions (R2). For example, the width of one of the first regions (R1) in a first direction (e.g., the x direction) may be greater than the width of one of the second regions (R2) in the first direction. Although FIG. 5 illustrates that the width of each of the first regions (R1) is greater than the width of each of the second regions (R2), the present invention is not limited thereto. In another embodiment, the number of pixels (P) arranged in each of the first regions (R1) may be smaller than the number of pixels (P) arranged in the second regions (R2), and the width of each of the first regions (R1) may be smaller than the width of each of the second regions (R2).

[0110] Each of the first regions (R1) may be defined as a region where a first contact portion (CTP1, FIG. 6) connecting a first write gate line (GWLa, FIG. 7) and a second write gate line (GWLb, FIG. 7) of a first gate line (GWL, hereinafter referred to as a write gate line) described later with reference to FIG. 7 is not disposed. Each of the second regions (R2) may be defined as a region where a first contact portion (CTP1, FIG. 6) is disposed.

[0111] The write gate line (GWL) can extend along a first direction (e.g., the x direction). The write gate line (GWL) is electrically connected to a gate driving circuit (13, FIG. 2) and can transmit a first gate signal (GW, FIGS. 3 and 4, hereinafter referred to as a write gate signal) to pixels (P) arranged in first regions (R1) and pixels (P) arranged in second regions (R2).

[0112] Referring to FIGS. 6 and 7, the display device (10) may include a substrate (100) and a write gate line (GWL) disposed on the substrate (100). A first insulating structure (IL1) may be disposed between the substrate (100) and the first write gate line (GWLa). A second insulating structure (IL2) may be disposed between the first write gate line (GWLa) and the second write gate line (GWLb). Each of the first insulating structure (IL1) and the second insulating structure (IL2) may include one or a plurality of insulating layers.

[0113] The write gate line (GWL) may include a first write gate line (GWLa) and a second write gate line (GWLb) that overlaps the first write gate line (GWLa) on a plane. In one embodiment, the second write gate line (GWLb) may be disposed on the first write gate line (GWLa). Each of the first write gate line (GWLa) and the second write gate line (GWLb) may extend along a first direction (e.g., the x direction). For example, each of the first write gate line (GWLa) and the second write gate line (GWLb) may extend to pass through the first regions (R1) and the second regions (R2).

[0114] The display device (10) may include first contact portions (CTP1) disposed between a first write gate line (GWLa) and a second write gate line (GWLb) and electrically connecting the first write gate line (GWLa) and the second write gate line (GWLb). For example, the first contact portions (CTP1) may be in contact with each of the first write gate line (GWLa) and the second write gate line (GWLb). The first contact portions (CTP1) may be disposed within first contact holes (CNT1) defined as regions penetrating the second insulating structure (IL2). As illustrated in FIGS. 6 and 7, the first contact portions (CTP1) may be disposed only in the second regions (R2) among the first regions (R1) and the second regions (R2), and may be disposed spaced apart from each of the first regions (R1). That is, the first contact portions (CTP1) may be disposed only in the second regions (R2) and not in the first regions (R1). That is, the first contact portions (CTP1) may overlap the second regions (R2) on the plane and may not overlap the first regions (R1).

[0115] In each of the second regions (R2), the first contact portions (CTP1) may be arranged to correspond to each of the subpixels (e.g., the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3)) of the pixels (P) arranged in the second regions (R2). Accordingly, since the first contact portions (CTP1) are arranged only in the second regions (R2) excluding the first regions (R1), the number of first contact portions (CTP1) may be smaller than the number of subpixels arranged in the display region (DA). For example, the number of first contact portions (CTP1) arranged to correspond to the subpixels arranged in the second regions (R2) among the subpixels arranged along the same row may be smaller than the number of subpixels arranged along the same row.

[0116] In one embodiment, the first write gate line (GWLa) may be electrically connected to the gate driving circuit (13, FIG. 2), and the second write gate line (GWLb) may be electrically connected to subpixels of each pixel (P) (e.g., the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3)). In one embodiment, an end of the first write gate line (GWLa) connected to the gate driving circuit (13, FIG. 2) may be arranged closer to the gate driving circuit (13, FIG. 2) than an end of the second write gate line (GWLb). Accordingly, a write gate signal (GW, FIGS. 3 and 4) is transmitted from the gate driving circuit (13, FIG. 2) to the first write gate line (GWLa), a write gate signal (GW, FIGS. 3 and 4) is transmitted from the first write gate line (GWLa) to the second write gate line (GWLb) via the first contact portion (CTP1), and a write gate signal (GW, FIGS. 3 and 4) can be transmitted from the second write gate line (GWLb) to the subpixels of each pixel (P).

[0117] In the case of a comparative example in which the first contact portions (CTP1) are arranged to correspond to all of the sub-pixels in the display area (DA) (the first contact portions (CTP1) are also arranged in the first areas (R1)), the waveform deviation between the write gate signal (GW, FIGS. 3 and 4) transmitted to the sub-pixels arranged in the edge area of ​​the display area (DA) that is arranged close to the gate driving circuit (13, FIG. 2) and the write gate signal (GW, FIGS. 3 and 4) transmitted to the sub-pixels arranged in the center area of ​​the display area (DA) that is arranged far from the gate driving circuit (13, see FIG. 2) increases due to the resistance difference of the write gate line (GWL) according to the position, so that the quality of the display device (10) is deteriorated.

[0118] Unlike the comparative example, in one embodiment of the present invention, the first contact portions (CTP1) are not arranged in the first regions (R1), and in particular, the first contact portions (CTP1) are not arranged in the first-first region (R1a) and the first-second region (R1b) at both ends closest to the non-display region (NDA), so that the resistance of the write gate line (GWL) in the edge region of the display region (DA) can be relatively increased, thereby reducing the difference in resistance between the write gate line (GWL) in the center region of the display region (DA). Accordingly, one embodiment of the present invention can improve the quality of the display device (10) by reducing the waveform deviation between the write gate signal (GW, FIGS. 3 and 4) transmitted to the subpixels arranged in the edge region of the display region (DA) and the write gate signal (GW, FIGS. 3 and 4) transmitted to the subpixels arranged in the center region of the display region (DA). In one embodiment of the present invention, by alternately arranging first regions (R1) where the first contact portion (CTP1) is not arranged and second regions (R2) where the first contact portion (CTP1) is arranged, the resistance of the write gate line (GWL) can be relatively finely adjusted to further reduce the resistance difference between regions. Accordingly, the waveform difference of the write gate signal (GW, FIGS. 3 and 4) transmitted to subpixels arranged at different positions in the same row is effectively reduced, so that the quality of the display device (10) can be improved.

[0119] Fig. 8 is a cross-sectional view schematically showing a cross-section of one embodiment taken along the line II' of Fig. 6. Fig. 9 is a cross-sectional view schematically showing a cross-section of one embodiment taken along the line II' of Fig. 6. Since Fig. 8 is a modified embodiment of Fig. 7, redundant descriptions using the same or similar symbols as in Fig. 7 will be omitted and descriptions will be focused on changed parts.

[0120] Referring to FIG. 8, the write gate line (GWL) may include a plurality of write gate lines of three or more layers. For example, the write gate line (GWL) may include a first write gate line (GWLa) and a second write gate line (GWLb), and the first write gate line (GWLa) may include a first lower write gate line (GWLaa) and a first upper write gate line (GWLab). For example, the first upper write gate line (GWLab) may be arranged on the first lower write gate line (GWLaa).

[0121] In one embodiment, the first write gate line (GWLa) may be positioned below the second write gate line (GWLb). For example, the first upper write gate line (GWLab) may be positioned above the first lower write gate line (GWLaa), and the second write gate line (GWLb) may be positioned above the first upper write gate line (GWLab).

[0122] In one embodiment, a first insulating structure (IL1) may be disposed between the substrate (100) and the first lower write gate line (GWLaa). A second insulating structure (IL2) may be disposed between the first lower write gate line (GWLaa) and the first upper write gate line (GWLab). A third insulating structure (IL3) may be disposed between the first upper write gate line (GWLab) and the second write gate line (GWLb). Each of the first insulating structure (IL1), the second insulating structure (IL2), and the third insulating structure (IL3) may include one or more insulating layers.

[0123] In one embodiment, the display device (10) may include second contact portions (CTP2a) disposed between the first lower write gate line (GWLaa) and the first upper write gate line (GWLab) and electrically connecting the first lower write gate line (GWLaa) and the first upper write gate line (GWLab). For example, the second contact portions (CTP2a) may be in contact with each of the first lower write gate line (GWLaa) and the first upper write gate line (GWLab). The second contact portions (CTP2a) may be respectively disposed within second contact holes (CNT2a) defined as regions penetrating the second insulating structure (IL2). As illustrated in FIG. 8, the second contact portions (CTP2a) may be disposed in each of the first regions (R1) and the second regions (R2). That is, the second contact portions (CTP2a) can overlap both the first regions (R1) and the second regions (R2) on the plane.

[0124] Since the first contact portions (CTP1a) are arranged only in the second regions (R2) excluding the first regions (R1), and the second contact portions (CTP2a) are arranged in the entire first region (R1) and the second regions (R2), the number of the second contact portions (CTP2a) may be greater than the number of the first contact portions (CTP1a). In one embodiment, the number of subpixels arranged in the display area (DA) and the number of second contact portions (CTP2a) may be the same. For example, the number of subpixels arranged along the same row and the number of second contact portions (CTP2a) arranged along the same row may be the same.

[0125] Since Fig. 9 is a modified embodiment of Figs. 7 and 8, overlapping descriptions using the same or similar symbols as Figs. 7 and 8 will be omitted and descriptions will be focused on the changed parts.

[0126] Referring to Fig. 9, the first write gate line (GWLa) may be arranged over the second write gate line (GWLb). For example, the first lower write gate line (GWLaa) may be arranged over the second write gate line (GWLb), and the first upper write gate line (GWLab) may be arranged over the first lower write gate line (GWLaa).

[0127] In one embodiment, a first insulating structure (IL1) may be disposed between the substrate (100) and the second write gate line (GWLb). A second insulating structure (IL2) may be disposed between the second write gate line (GWLb) and the first lower write gate line (GWLaa). A third insulating structure (IL3) may be disposed between the first lower write gate line (GWLaa) and the first upper write gate line (GWLab).

[0128] Similar to the embodiment of FIG. 8, in the embodiment of FIG. 9, the display device (10) may include second contact portions (CTP2b) disposed between the first lower write gate line (GWLaa) and the first upper write gate line (GWLab), and electrically connecting the first lower write gate line (GWLaa) and the first upper write gate line (GWLab). The second contact portions (CTP2b) may be respectively disposed within second contact holes (CNT2b) defined as regions penetrating the third insulating structure (IL3). As illustrated in FIG. 9, the second contact portions (CTP2b) may be disposed throughout the first regions (R1) and the second regions (R2). That is, the second contact portions (CTP2b) may overlap both the first regions (R1) and the second regions (R2) on a plane.

[0129] Fig. 10 is a cross-sectional view showing a portion of a display area of ​​a display device according to one embodiment of the present invention.

[0130] Referring to Fig. 10, a display device (10) includes a light emitting diode (LED) arranged in a display area (DA). The light emitting diode (LED) is arranged on a substrate (100), and a subpixel circuit (SPC) may be arranged between the substrate (100) and the light emitting diode (LED). As an example, Fig. 10 illustrates some components of the subpixel circuit (SPC), including a first transistor (T1), a first capacitor (C1), and a second capacitor (C2).

[0131] The substrate (100) may include a glass material or a polymer resin. As an example, the substrate (100) may have an alternating laminated structure of a base layer including a polymer resin and a barrier layer including an inorganic insulating material such as silicon oxide or silicon nitride. The polymer resin may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0132] A first electrode (C21) of a second capacitor (C2) may be placed on a substrate (100). The first electrode (C21) of the second capacitor (C2) may include a conductive material such as a metal, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material.

[0133] The first insulating layer (111) may be disposed on the first electrode (C21) of the second capacitor (C2). The first insulating layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0134] The second lower electrode (C12b) of the first capacitor (C1) and the second electrode (C22) of the second capacitor (C2) may be disposed on the first insulating layer (111). In one embodiment, the second lower electrode (C12b) of the first capacitor (C1) and the second electrode (C22) of the second capacitor (C2) may be connected and provided as an integral body. Each of the second lower electrode (C12b) of the first capacitor (C1) and the second electrode (C22) of the second capacitor (C2) may include a conductive material such as a metal, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material.

[0135] The second insulating layer (112) may be disposed on the second electrode (C22) of the second capacitor (C2). The second insulating layer (112) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material. The second insulating layer (112) may be a type of buffer layer that prevents impurities from penetrating into a transistor, for example, the first transistor (T1).

[0136] The semiconductor layer may be disposed on the second insulating layer (112). In this regard, FIG. 10 illustrates that the first semiconductor layer (A1) of the first transistor (T1) is disposed on the second insulating layer (112). The first semiconductor layer (A1) may include a channel region and a source region and a drain region disposed on both sides of the channel region. The first semiconductor layer (A1) may include at least one oxide selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the first semiconductor layer (A1) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. At least a portion of the first semiconductor layer (A1) may undergo a conductive (or conductive) process by plasma treatment or the like.

[0137] The first gate electrode (G1) may overlap the channel region of the first semiconductor layer (A1) on a plane, and the third insulating layer (113) may be disposed between the first gate electrode (G1) and the first semiconductor layer (A1). The second electrode (C22) of the second capacitor (C2) faces the first gate electrode (G1), and the first semiconductor layer (A1) may be disposed between the second electrode (C22) of the second capacitor (C2) and the first gate electrode (G1). The second electrode (C22) of the second capacitor (C2) may be the lower gate electrode of the first transistor (T1), and the first gate electrode (G1) may be the upper gate electrode of the first transistor (T1). The first gate electrode (G1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials. The third insulating layer (113) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0138] The first electrode (C11) of the first capacitor (C1) overlaps the second lower electrode (C12b) on a plane, and the second insulating layer (112) and the third insulating layer (113) may each be disposed between the first electrode (C11) and the second lower electrode (C12b) of the first capacitor (C1). In Fig. 10, the first electrode (C11) of the first capacitor (C1) is illustrated as being separate from the first gate electrode (G1), but this is not limited thereto, and in another embodiment, the first electrode (C11) of the first capacitor (C1) may be connected to the first gate electrode (G1) and formed integrally with it.

[0139] The first electrode (C11) of the first capacitor (C1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material.

[0140] The fourth insulating layer (114) may be disposed on the first electrode (C11) and the first gate electrode (G1) of the first capacitor (C1). The fourth insulating layer (114) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0141] The data line (DL), the connection conductive pattern (CMP), and the second upper electrode (C12t) of the first capacitor (C1) may be disposed on the fourth insulating layer (114). The connection conductive pattern (CMP) may connect the first semiconductor layer (A1) of the first transistor (T1) and the second electrode (C22) of the second capacitor (C2). The second upper electrode (C12t) of the first capacitor (C1) overlaps the second lower electrode (C12b) of the first capacitor (C1) on a plane, and each of the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114) may be disposed between the second upper electrode (C12t) of the first capacitor (C1) and the second lower electrode (C12b) of the first capacitor (C1). The second upper electrode (C12t) of the first capacitor (C1) can be connected to the second lower electrode (C12b) of the first capacitor (C1) through a contact hole penetrating the second insulating layer (112), the third insulating layer (113), and the fourth insulating layer (114). The second upper electrode (C12t) of the first capacitor (C1) overlaps the first electrode (C11) of the first capacitor (C1) on a plane, and the fourth insulating layer (114) can be disposed between the second upper electrode (C12t) of the first capacitor (C1) and the first electrode (C11) of the first capacitor (C1). The data line (DL), the connection conductive pattern (CMP), and the second upper electrode (C12t) of the first capacitor (C1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials.

[0142] The fifth insulating layer (115) is disposed on the data line (DL), the connection conductive pattern (CMP), and the second upper electrode (C12t) of the first capacitor (C1), and may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0143] The upper conductive layer (UCL) may be disposed on the fifth insulating layer (115). The upper conductive pattern disposed on the same layer as the upper conductive layer (UCL) may be connected to a light emitting diode (LED), and the upper conductive pattern may be connected to a transistor of a subpixel circuit (SPC) (e.g., the sixth transistor (T6, FIG. 4)). Although not illustrated in FIG. 10, another voltage line, for example, a sustain voltage line (VSSL, FIG. 4), may be disposed on the same layer as the upper conductive layer (UCL), for example, the fifth insulating layer (115). The upper conductive layer (UCL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned material.

[0144] The sixth insulating layer (116) is disposed on the upper conductive layer (UCL) and may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0145] A light emitting diode (LED) may include a pixel electrode (210), a light emitting layer (222), and a counter electrode (230).

[0146] The pixel electrode (210) may be disposed on the sixth insulating layer (116). The pixel electrode (210) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the pixel electrode (210) may further include a conductive oxide layer on and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, the pixel electrode (210) may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0147] The bank layer (123) may be disposed on the pixel electrode (210). The bank layer (123) may include an opening (123OP) overlapping the pixel electrode (210) and covering an edge of the pixel electrode (210). The bank layer (123) may include an organic insulator. In some embodiments, the bank layer (123) may include a light-transmitting organic insulator. In other embodiments, the bank layer (123) may include an organic insulator including a light-blocking material. In some embodiments, the bank layer (123) may include a polyimide (PI)-based binder and a pigment mixed with red, green, and blue. Alternatively, the bank layer (123) may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. Alternatively, the bank layer (123) may include carbon black. The bank layer (123) can improve the contrast of the display device (10).

[0148] The spacer (125) may be disposed on the bank layer (123). The spacer (125) may include a different material from the material of the bank layer (123). For example, the bank layer (123) may include a negative photosensitive material, while the spacer (127) may include a positive photosensitive material, and the spacer (125) may include different materials, and each may be formed through a separate mask process. In another embodiment, the spacer (125) may include the same material as the bank layer (123) and may be formed together in the same mask process (e.g., a halftone mask process).

[0149] The light-emitting layer (222) may include a polymer or low-molecular organic material that emits light of a predetermined color. The light-emitting layer (222) may include a material that emits red light, green light, or blue light, depending on the light-emitting diode (LED).

[0150] A functional layer may be further included below and / or above the light-emitting layer (222). For example, a first functional layer (221) may be further included between the pixel electrode (210) and the light-emitting layer (222), and a second functional layer (223) may be further included between the light-emitting layer (222) and a counter electrode (230) to be described later. The first functional layer (221) may include a hole transport layer and / or a hole injection layer. The second functional layer (223) may include an electron transport layer and / or an electron injection layer.

[0151] The counter electrode (230) may be formed of a conductive material having a low work function. For example, the counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0152] Unlike the pixel electrodes (210) that are individually formed to correspond to the light emitting diodes (LEDs), the counter electrodes (230) may be extended to correspond to the pixel electrodes (210). For example, the pixel electrodes (210) of one light emitting diode (LED) and the pixel electrodes (210) of another light emitting diode (LED) may be separated and spaced from each other, but the counter electrodes (230) that overlap the pixel electrodes (210) on a plane may be extended to cover the pixel electrodes (210) described above.

[0153] The encapsulating layer (300) is disposed on a light-emitting diode (LED) and may include at least one inorganic encapsulating layer and at least one organic encapsulating layer. In one embodiment, FIG. 10 illustrates that the encapsulating layer (300) includes a first inorganic encapsulating layer (310), an organic encapsulating layer (320), and a second inorganic encapsulating layer (330).

[0154] Each of the first inorganic encapsulating layer (310) and the second inorganic encapsulating layer (330) may include one or more inorganic insulating materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulating layer (310) and the second inorganic encapsulating layer (330) may be a single layer or multiple layers including the aforementioned materials. The organic encapsulating layer (320) may include a polymer-based material. Examples of the polymer-based material include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic encapsulating layer (320) may include acrylate.

[0155] Fig. 11 is a plan view illustrating first to third subpixel circuit regions of first to third subpixels included in one pixel arranged in a first area of ​​a display device according to one embodiment of the present invention. Fig. 12 is a plan view illustrating first to third subpixel circuit regions of first to third subpixels included in one pixel arranged in a second area of ​​a display device according to one embodiment of the present invention.

[0156] Each of the first to third subpixel circuit areas (SPCA1, SPCA2, SPCA3) of FIG. 11 may be a planar structure in the first area (R1) of the subpixel circuit (SPC) of the display device (10) described with reference to FIGS. 4 and 10. Each of the first to third subpixel circuit areas (SPCA1, SPCA2, SPCA3) of FIG. 12 may be a planar structure in the second area (R2) of the subpixel circuit (SPC) of the display device (10) described with reference to FIGS. 4 and 10.

[0157] Fig. 13 is a cross-sectional view schematically showing a cross-section of one embodiment cut along the line II-II' of Fig. 11. Fig. 14 is a cross-sectional view schematically showing a cross-section of one embodiment cut along the line III-III' of Fig. 12.

[0158] Referring to FIGS. 11 to 14, a first subpixel circuit region (SPCA1) in which a first subpixel circuit of a first subpixel (SP1) is arranged, a second subpixel circuit region (SPCA2) in which a second subpixel circuit of a second subpixel (SP2) is arranged, and a third subpixel circuit region (SPCA3) in which a third subpixel circuit of a third subpixel (SP3) is arranged may be arranged adjacent to each other along a first direction (e.g., x direction). FIGS. 11 and 12 illustrate first to sixth transistors (T1, T2, T3, T4, T5, T6), a first capacitor (C1), and a second capacitor (C2) of the first subpixel (SP1), the second subpixel (SP2), and the third subpixel (SP3), respectively.

[0159] In one embodiment, the first transistor (T1) and the first capacitor (C1) may overlap on the plane.

[0160] In one embodiment, on a plane, the second transistor (T2) and the third transistor (T3) may be arranged on one side of the first transistor (T1), and the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be arranged on the other side of the first transistor (T1). For example, on a plane, the second transistor (T2) and the third transistor (T3) may be arranged on an upper side of the first transistor (T1), and the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be arranged on a lower side of the first transistor (T1).

[0161] The write gate line (GWL) may extend in a first direction (e.g., in the x direction) so as to pass through the first subpixel circuit region (SPCA1), the second subpixel circuit region (SPCA2), and the third subpixel circuit region (SPCA3). The write gate line (GWL) may include a first write gate line (GWLa) and a second write gate line (GWLb) that overlap each other on a plane. For example, each of the first write gate line (GWLa) and the second write gate line (GWLb) may extend in the first direction (e.g., in the x direction) so as to pass through the first subpixel circuit region (SPCA1), the second subpixel circuit region (SPCA2), and the third subpixel circuit region (SPCA3).

[0162] In one embodiment, a first write gate line (GWLa) may be disposed on a first insulating layer (111). The first insulating layer (111) may correspond to the first insulating structure (IL1) described with reference to FIG. 7. A second insulating layer (112) may be disposed on the first write gate line (GWLa), and a third insulating layer (113) may be disposed on the second insulating layer (112). The second insulating layer (112) and the third insulating layer (113) may correspond to the second insulating structure (IL2) described with reference to FIG. 7. A second write gate line (GWLb) may be disposed on the third insulating layer (113). A fourth insulating layer (114) may be disposed on the second write gate line (GWLb), and a data line (DL) and a second connection pattern (1320) may be disposed on the fourth insulating layer (114). A fifth insulating layer (115) may be placed on the data line (DL) and the second connection pattern (1320).

[0163] In each of the first region (R1) and the second region (R2), the second write gate line (GWLb) is connected to the second connection pattern (1320), and the second connection pattern (1320) is electrically connected to the second transistor (T2) (e.g., the second gate electrode of the second transistor (T2)), so that the second write gate line (GWLb) can be electrically connected to the second transistor (T2) (e.g., the second gate electrode of the second transistor (T2)). The second write gate line (GWLb) can be connected to the second connection pattern (1320) by a third contact portion (CNTP3) disposed in a third contact hole (CNT3) penetrating at least one insulating layer interposed between the second write gate line (GWLb) and the second connection pattern (1320). In each of the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3), a data line (DL) and a second transistor (T2) (e.g., a semiconductor layer of the second transistor (T2)) corresponding to each area are connected, so that a data signal (DATA, FIG. 2) can be transmitted to the second transistor (T2).

[0164] Referring to FIGS. 11 and 13, in the first region (R1), the first write gate line (GWLa) and the second write gate line (GWLb) may be spaced apart from each other with the second insulating layer (112) and the third insulating layer (113) therebetween. In the first region (R1), the first write gate line (GWLa) and the second write gate line (GWLb) may be spaced apart from each other in the third direction (e.g., the z direction) and may not be connected. For example, in each of the first subpixel circuit region (SPCA1), the second subpixel circuit region (SPCA2), and the third subpixel circuit region (SPCA3) of the first region (R1), the first write gate line (GWLa) and the second write gate line (GWLb) may be spaced apart from each other and may not be connected. In other words, unlike the second region (R2) described with reference to FIGS. 12 and 14, the first contact portion (CTP1) connecting the first writing gate line (GWLa) and the second writing gate line (GWLb) may not be arranged in the first region (R1).

[0165] Referring to FIGS. 12 and 14, in the second region (R2), the first write gate line (GWLa) and the second write gate line (GWLb) may be connected through a first contact portion (CTP1) disposed in a first contact hole (CNT1) penetrating the second insulating layer (112) and the third insulating layer (113). For example, in each of the first subpixel circuit region (SPCA1), the second subpixel circuit region (SPCA2), and the third subpixel circuit region (SPCA3) of the second region (R2), the first write gate line (GWLa) and the second write gate line (GWLb) may be connected through the first contact portion (CTP1). In other words, in the second regions (R2), the first contact portion (CTP1) connecting the first write gate line (GWLa) and the second write gate line (GWLb) may be disposed. The first contact portions (CTP1) may be arranged to correspond to each of the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3). In one embodiment, as illustrated in FIG. 12, the first contact portions (CTP1) and the third contact portions (CTP3) may be arranged along the first direction (e.g., the x direction) on a plane.

[0166] FIGS. 15 to 19 are plan views according to the stacking order of the components of each layer constituting the first to third subpixels in the second region of the display device illustrated in FIG. 12. The first region (R1) of FIG. 11 and the second region (R2) of FIG. 12 differ in the arrangement of the first contact portion (CTP1) connecting different layers of the write gate line (GWL), and the arrangement of the other components is the same or similar. Therefore, for convenience of explanation, the description will focus on the first subpixel circuit region (SPCA1), the second subpixel circuit region (SPCA2), and the third subpixel circuit region (SPCA3) in the second region (R2) of FIG. 12.

[0167] Referring to FIG. 15, a driving voltage line (PL), a reference voltage line (VRL), and a repair line (RL) can be arranged on a substrate (100, FIG. 10).

[0168] Each of the driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL) can extend in a first direction (e.g., the x direction) through the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3).

[0169] The driving voltage line (PL) may include the first electrode (C21) of the second capacitor (C2). For example, the driving voltage line (PL) may include the first electrode (C21) of the second capacitor (C2) of each of the first to third subpixels (SP1, SP2, SP3), and the first electrodes (C21) of the second capacitors (C2) of each of the first to third subpixels (SP1, SP2, SP3) may be connected to each other as one body.

[0170] The repair line (RL) may be a spare line that can be used when a defect occurs in a signal line or voltage line included in the subpixel circuits of the first to third subpixels (SP1, SP2, SP3).

[0171] The driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL) may include the same material. Each of the driving voltage line (PL), the reference voltage line (VRL), and the repair line (RL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned materials.

[0172] Referring to FIGS. 15 and 16, a first insulating layer (111, FIG. 10) may be disposed on a driving voltage line (PL), a reference voltage line (VRL), and a repair line (RL), and a first conductive pattern (1050), a first write gate line (GWLa), a second initialization voltage line (VAL2), and a third initialization voltage line (VAL3) may be disposed on the first insulating layer (111, FIG. 10).

[0173] The first conductive pattern (1050) may be an isolated shape. The first conductive pattern (1050) may be arranged to correspond to each of the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3). The first conductive pattern (1050) may include a second electrode (C22) of the second capacitor (C2) overlapping the first electrode (C21) of the second capacitor (C2) on a plane. The first conductive pattern (1050) may include a second lower electrode (C12b) of the first capacitor (C1). In one embodiment, the first conductive pattern (1050) may include a lower gate electrode (e.g., a first-second gate electrode) of the first transistor (T1, FIG. 18) that overlaps the first semiconductor layer (A1, FIGS. 17 and 18) of the first transistor (T1, FIG. 18) on a plane. The second electrode (C22) of the second capacitor (C2) and the second lower electrode (C12b) of the first capacitor (C1) may be provided integrally and connected to the second node (N2) described with reference to FIG. 4.

[0174] Each of the first write gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3) may extend in a first direction (e.g., the x direction) so as to pass through the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3).

[0175] The first write gate line (GWLa) may be arranged on one side of the first conductive pattern (1050), and the second initialization voltage line (VAL2) and the third initialization voltage line (VAL3) may each be arranged on the other side of the first conductive pattern (1050). For example, in a plane, the first write gate line (GWLa) may be arranged on an upper side of the first conductive pattern (1050), and the second initialization voltage line (VAL2) and the third initialization voltage line (VAL3) may each be arranged on a lower side of the first conductive pattern (1050). For example, the first conductive pattern (1050) may be located between the first write gate line (GWLa) and the second initialization voltage line (VAL2) in a plane.

[0176] The first conductive pattern (1050), the first write gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3) may include the same material. The first conductive pattern (1050), the first write gate line (GWLa), the second initialization voltage line (VAL2), and the third initialization voltage line (VAL3) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned material.

[0177] Referring to FIGS. 16 and 17, a second insulating layer (112, FIG. 10) may be disposed on a first conductive pattern (1050), a first write gate line (GWLa), a second initialization voltage line (VAL2), and a third initialization voltage line (VAL3), and a semiconductor layer including first to third semiconductor patterns (1110, 1120, 1130) may be disposed on the second insulating layer (112, FIG. 10).

[0178] Each of the first semiconductor pattern (1110), the second semiconductor pattern (1120), and the third semiconductor pattern (1130) may be an isolated shape. For example, the first semiconductor pattern (1110), the second semiconductor pattern (1120), and the third semiconductor pattern (1130) may be arranged to be spaced apart from each other. Each of the first semiconductor pattern (1110), the second semiconductor pattern (1120), and the third semiconductor pattern (1130) may be arranged to correspond to each of the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3).

[0179] The first semiconductor pattern (1110) may include a first semiconductor layer (A1) and a fifth semiconductor layer (A5). In other words, the first semiconductor layer (A1) and the fifth semiconductor layer (A5) may be integrally connected. The second semiconductor pattern (1120) may include a second semiconductor layer (A2) and a third semiconductor layer (A3). In other words, the second semiconductor layer (A2) and the third semiconductor layer (A3) may be integrally connected. The third semiconductor pattern (1130) may include a fourth semiconductor layer (A4) and a sixth semiconductor layer (A6). In other words, the fourth semiconductor layer (A4) and the sixth semiconductor layer (A6) may be integrally connected.

[0180] The first semiconductor layer (A1) may include a first channel region (CH1) overlapping with a first gate electrode (G1) of a first transistor (T1) described later with reference to FIG. 18, a first source region (S1) disposed on one side of the first channel region (CH1), and a first drain region (D1) disposed on the other side of the first channel region (CH1).

[0181] The second semiconductor layer (A2) may include a second channel region (CH2) overlapping with a second gate electrode (G2) of a second transistor (T2) described later with reference to FIG. 18, a second source region (S2) disposed on one side of the second channel region (CH2), and a second drain region (D2) disposed on the other side of the second channel region (CH2).

[0182] The third semiconductor layer (A3) may include a third channel region (CH3) overlapping with a third gate electrode (G3) of a third transistor (T3) described later with reference to FIG. 18, a third source region (S3) disposed on one side of the third channel region (CH3), and a third drain region (D3) disposed on the other side of the third channel region (CH3).

[0183] The fourth semiconductor layer (A4) may include a fourth channel region (CH4) overlapping with a fourth gate electrode (G4) of a fourth transistor (T4) described later with reference to FIG. 18, a fourth source region (S4) disposed on one side of the fourth channel region (CH4), and a fourth drain region (D4) disposed on the other side of the fourth channel region (CH4).

[0184] The fifth semiconductor layer (A5) may include a fifth channel region (CH5) overlapping with a fifth gate electrode (G5) of a fifth transistor (T5) described later with reference to FIG. 18, a fifth source region (S5) disposed on one side of the fifth channel region (CH5), and a fifth drain region (D5) disposed on the other side of the fifth channel region (CH5).

[0185] The sixth semiconductor layer (A6) may include a sixth channel region (CH6) overlapping with a sixth gate electrode (G6) of a sixth transistor (T6) described later with reference to FIG. 18, a sixth source region (S6) disposed on one side of the sixth channel region (CH6), and a sixth drain region (D6) disposed on the other side of the sixth channel region (CH6).

[0186] The first to third semiconductor patterns (1110, 1120, 1130) may include the same material. In one embodiment, the first to third semiconductor patterns (1110, 1120, 1130) may include an oxide semiconductor material. For example, each of the first to third semiconductor patterns (1110, 1120, 1130) may include at least one oxide semiconductor material selected from the group consisting of indium (In), gallium (Ga), stannium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). In another embodiment, each of the first to third semiconductor patterns (1110, 1120, 1130) may include polysilicon or amorphous silicon.

[0187] Referring to FIGS. 17 and 18, a third insulating layer (113, FIG. 10) may be disposed on the first to third semiconductor patterns (1110, 1120, 1130), and a second conductive pattern (1210), a third conductive pattern (1220), a fourth conductive pattern (1230), a second write gate line (GWLb), a second gate line (GRL), a third gate line (EML), a fourth gate line (GIL), a fifth gate line (EMBL), and a first initialization voltage line (VAL1) may be disposed on the third insulating layer (113, FIG. 10).

[0188] Each of the second conductive pattern (1210), the third conductive pattern (1220), and the fourth conductive pattern (1230) may be an isolated shape. For example, the second conductive pattern (1210), the third conductive pattern (1220), and the fourth conductive pattern (1230) may be arranged to be spaced apart from each other. Each of the second conductive pattern (1210), the third conductive pattern (1220), and the fourth conductive pattern (1230) may be arranged to correspond to each of the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3).

[0189] The second challenge pattern (1210) may include a first gate electrode (G1) of the first transistor (T1) overlapping the first semiconductor layer (A1) of the first transistor (T1) on a plane.

[0190] The second conductive pattern (1210) may overlap with the first conductive pattern (1050) on a plane. The second conductive pattern (1210) may include a first electrode (C11) of a first capacitor (C1) connected to the first node (N1) described with reference to FIG. 4. The first electrode (C11) of the first capacitor (C1) may overlap with the second lower electrode (C12b) of the first capacitor (C1) on a plane. The first capacitor (C1) may include a first electrode (C11), a second lower electrode (C12b), and a second upper electrode (C12t) described later with reference to FIG. 19. For example, the first gate electrode (G1) of the first transistor (T1) and the first electrode (C11) of the first capacitor (C1) may be provided integrally.

[0191] The third conductive pattern (1220) may overlap at least a portion of the second semiconductor pattern (1120) on a plane. The third conductive pattern (1220) may include a second gate electrode (G2) of the second transistor (T2) that overlaps the second semiconductor layer (A2) of the second transistor (T2) on a plane.

[0192] At least a portion of the fourth conductive pattern (1230) may overlap with the reference voltage line (VRL, FIG. 15) on a plane. The fourth conductive pattern (1230) may be connected to the reference voltage line (VRL, FIG. 15) through a contact hole penetrating at least one insulating layer interposed between the fourth conductive pattern (1230) and the reference voltage line (VRL, FIG. 15). The fourth conductive pattern (1230) may be connected to the fourth connection pattern (1340) described below with reference to FIG. 19. The fourth conductive pattern (1230) may be connected to the second semiconductor pattern (1120, FIG. 17) through the fourth connection pattern (1340).

[0193] Each of the second write gate line (GWLb), the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may extend in a first direction (e.g., the x direction) so as to pass through the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3).

[0194] On a plane, each of the second writing gate line (GWLb) and the second gate line (GRL) may be disposed on one side of the second conductive pattern (1210), and each of the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may be disposed on the other side of the second conductive pattern (1210). For example, on a plane, each of the second writing gate line (GWLb) and the second gate line (GRL) may be disposed on an upper side of the second conductive pattern (1210), and each of the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may be disposed on a lower side of the second conductive pattern (1210).

[0195] The second write gate line (GWLb) may be arranged to overlap the first write gate line (GWLa) on the first write gate line (GWLa) in a plane. Fig. 18 illustrates a plane of the second region (R2, Fig. 12), and illustrates that the first write gate line (GWLa) and the second write gate line (GWLb) are connected by a first contact portion (CTP1) arranged in the first contact hole (CNT1). As described above with reference to Figs. 11 to 14, the first contact portion (CTP1) and the first contact hole (CNT1) may not be arranged in the first region (R1).

[0196] The second gate line (GRL) may overlap at least a portion of the second semiconductor pattern (1120) on the plane. The second gate line (GRL) may include a third gate electrode (G3) of the third transistor (T3) that overlaps the third semiconductor layer (A3) of the third transistor (T3) on the plane.

[0197] The third gate line (EML) may overlap at least a portion of the first semiconductor pattern (1110) on a plane. The third gate line (EML) may include a fifth gate electrode (G5) of the fifth transistor (T5) that overlaps the fifth semiconductor layer (A5) of the fifth transistor (T5) on a plane.

[0198] The fifth gate line (EMBL) may overlap at least a portion of the third semiconductor pattern (1130) on a plane. The fifth gate line (EMBL) may include a sixth gate electrode (G6) of the sixth transistor (T6) that overlaps the sixth semiconductor layer (A6) of the sixth transistor (T6) on a plane.

[0199] The fourth gate line (GIL) may overlap at least a portion of the third semiconductor pattern (1130) on a plane. The fourth gate line (GIL) may include the sixth gate electrode (G4) of the fourth transistor (T4) that overlaps the fourth semiconductor layer (A4) of the fourth transistor (T4) on a plane.

[0200] The second conductive pattern (1210), the third conductive pattern (1220), the fourth conductive pattern (1230), the second writing gate line (GWLb), the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may include the same material. Each of the second conductive pattern (1210), the third conductive pattern (1220), the fourth conductive pattern (1230), the second writing gate line (GWLb), the second gate line (GRL), the third gate line (EML), the fourth gate line (GIL), the fifth gate line (EMBL), and the first initialization voltage line (VAL1) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned material.

[0201] Referring to FIGS. 18 and 19, a fourth insulating layer (114, FIG. 10) may be disposed on a second conductive pattern (1210), a third conductive pattern (1220), a fourth conductive pattern (1230), a second write gate line (GWLb), a second gate line (GRL), a third gate line (EML), a fourth gate line (GIL), a fifth gate line (EMBL), and a first initialization voltage line (VAL1), and a data line (DL), a first connection pattern (1310), a second connection pattern (1320), a third connection pattern (1330), a fourth connection pattern (1340), a fifth connection pattern (1350), and a sixth connection pattern (1360) may be disposed on the fourth insulating layer (114, FIG. 10).

[0202] Each of the data line (DL), the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), and the sixth connection pattern (1360) may be arranged to correspond to each of the first subpixel circuit area (SPCA1), the second subpixel circuit area (SPCA2), and the third subpixel circuit area (SPCA3).

[0203] The data line (DL) may extend along a second direction (e.g., the y direction) intersecting the first direction (e.g., the x direction). The data line (DL) may be electrically connected to a second drain region (D2, FIG. 17) of the second semiconductor layer (A2) of the second transistor (T2) through a contact hole penetrating at least one insulating layer interposed between the second semiconductor layer (A2) and the data line (DL). For example, the data lines (DL) respectively arranged in the first subpixel circuit region (SPCA1), the second subpixel circuit region (SPCA2), and the third subpixel circuit region (SPCA3) may be electrically connected to the second transistor (T2) of the first subpixel (SP1), the second transistor (T2) of the second subpixel (SP2), and the second transistor (T2) of the third subpixel (SP3), respectively.

[0204] The first connection pattern (1310) may be connected to the first semiconductor pattern (1110, FIG. 17) through a contact hole penetrating at least one insulating layer interposed between the first connection pattern (1310) and the first semiconductor pattern (1110, FIG. 17). For example, the first connection pattern (1310) may be connected to the first source region (S1, FIG. 17) of the first semiconductor layer (A1) of the first transistor (T1) through the contact hole.

[0205] The first connection pattern (1310) may be connected to the third semiconductor pattern (1130, FIG. 17) through a contact hole penetrating at least one insulating layer interposed between the first connection pattern (1310) and the first semiconductor pattern (1130, FIG. 17). For example, the first connection pattern (1310) may be connected to the sixth drain region (D6, FIG. 17) of the sixth semiconductor layer (A6) of the sixth transistor (T6) through a contact hole.

[0206] The first connection pattern (1310) may include a second upper electrode (C12t) of the first capacitor (C1). The second upper electrode (C12t) of the first capacitor (C1) may be connected by a contact hole penetrating at least one insulating layer interposed between the second lower electrode (C12b) of the first capacitor (C1) and the second upper electrode (C12t) of the first capacitor (C1) and the second lower electrode (C12b) of the first capacitor (C1). The second upper electrode (C12t) of the first capacitor (C1) may overlap the first electrode (C11) of the first capacitor (C1) on a plane.

[0207] The first connection pattern (1310) can connect the first semiconductor layer (A1), the sixth semiconductor layer (A6), the second upper electrode (C12t) of the first capacitor (C1), and the second lower electrode (C12b) of the first capacitor (C1). The first connection pattern (1310) can correspond to the connection conductive pattern (CMP) described with reference to FIG. 10.

[0208] The second connection pattern (1320) can connect the second gate electrode (G2) of the second transistor (T2) and the second write gate line (GWLb). The second connection pattern (1320) can be connected to the second write gate line (GWLb) through a third contact hole (CNT3) penetrating at least one insulating layer interposed between the second connection pattern (1320) and the second write gate line (GWLb). For example, the second connection pattern (1320) can be connected to the second write gate line (GWLb) through a third contact portion (CTP3) disposed within the third contact hole (CNT3). The third contact portion (CTP3) can be disposed between the second connection pattern (1320) and the second write gate line (GWLb).

[0209] Fig. 19 illustrates a plane of a second region (R2, Fig. 12), in which a third contact portion (CTP3) and a first contact portion (CTP1) are arranged along a first direction (e.g., an x-direction or a row direction). As described above with reference to Figs. 11 to 14, the first contact portion (CTP1) and the first contact hole (CNT1) may not be arranged in the first region (R1), and thus, the first contact portion (CTP1) may not be arranged in the region along the first direction from the third contact portion (CTP3).

[0210] The third connection pattern (1330) can connect the second semiconductor pattern (1120) and the second conductive pattern (1210). The third connection pattern (1330) can connect the second drain region (D2, FIG. 17) of the second semiconductor layer (A2) of the second transistor (T2), the third drain region (D3, FIG. 17) of the third semiconductor layer (A3) of the third transistor (T3), and the first gate electrode (G1) of the first transistor (T1). The third connection pattern (1330) can connect the second drain region (D2, FIG. 17) of the second semiconductor layer (A2) of the second transistor (T2), the third drain region (D3, FIG. 17) of the third semiconductor layer (A3) of the third transistor (T3), and the first electrode (C11) of the first capacitor (C1).

[0211] The fourth connection pattern (1340) is connected to the fourth conductive pattern (1230) and the second semiconductor pattern (1120, FIG. 17) through contact holes, and the fourth conductive pattern (1230) can be connected to the reference voltage line (VRL). For example, the fourth connection pattern (1340) and the fourth conductive pattern (1230) can connect the reference voltage line (VRL) and the third semiconductor layer (A3) of the third transistor (T3).

[0212] The fifth connection pattern (1350) may be a pattern arranged so that a repair line (RL, FIG. 15) and the sub-pixel circuit can be connected when a defect occurs in a signal line or voltage line included in the sub-pixel circuit. For example, the fifth connection pattern (1350) is connected to the repair pattern (1060) and the third semiconductor pattern (1130) illustrated in FIG. 16, and when a defect occurs in the signal line or voltage line, the repair pattern (1060) may be arranged so that it can be connected by joining with the repair line (RL, FIG. 15). The repair pattern (1060) may be arranged on the same layer as the first conductive pattern (1050).

[0213] The sixth connection pattern (1360) arranged in the first subpixel circuit area (SPCA1) can connect the first initialization voltage line (VAL1) and the fourth source area (S4) of the fourth semiconductor layer (A4) of the fourth transistor (T4) of the first subpixel circuit area (SPCA1). The sixth connection pattern (1360) arranged in the second subpixel circuit area (SPCA2) can connect the second initialization voltage line (VAL2) and the fourth source area (S4) of the fourth semiconductor layer (A4) of the fourth transistor (T4) of the second subpixel circuit area (SPCA2). The sixth connection pattern (1360) arranged in the third subpixel circuit area (SPCA3) can connect the third initialization voltage line (VAL3) and the fourth source area (S4) of the fourth semiconductor layer (A4) of the fourth transistor (T4) of the third subpixel circuit area (SPCA3).

[0214] The data line (DL), the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), and the sixth connection pattern (1360) may include the same material. The data line (DL), the first connection pattern (1310), the second connection pattern (1320), the third connection pattern (1330), the fourth connection pattern (1340), the fifth connection pattern (1350), and the sixth connection pattern (1360) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may include a single-layer or multi-layer structure including the aforementioned material.

[0215] While the above description has been made with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A substrate including a display area including a plurality of first areas and a plurality of second areas and a non-display area surrounding at least a portion of the display area; A gate driving circuit arranged in the above non-display area; A first write gate line extending in the first direction and electrically connected to the gate driving circuit; A second write gate line extending in the first direction through the first regions and the second regions and overlapping the first write gate line on a plane; First contact parts arranged between the first write gate line and the second write gate line and electrically connecting the first write gate line and the second write gate line; and The display area includes pixels including subpixels arranged in each of the first areas and the second areas, each of which is electrically connected to the second writing gate line, A display device, wherein the first contact portions are arranged in the second regions and are not arranged in the first regions.

2. In paragraph 1, A display device, wherein the second regions are spaced apart from the non-display region in the first direction, and at least one of the first regions is disposed between the non-display region and the plurality of second regions in the first direction.

3. In paragraph 2, A display device wherein the first regions and the second regions are arranged alternately along the first direction.

4. In paragraph 1, Each of the above pixels includes a first subpixel, a second subpixel, and a third subpixel, A first subpixel circuit region in which the first subpixel circuit of the first subpixel is arranged, a second subpixel circuit region in which the second subpixel circuit of the second subpixel is arranged, and a third subpixel circuit region in which the third subpixel circuit of the third subpixel is arranged are arranged adjacent to each other in the first direction. A display device, wherein in each of the second regions, the first contact portions are arranged corresponding to each of the first subpixel circuit region, the second subpixel circuit region, and the third subpixel circuit region.

5. In paragraph 1, A display device, wherein the width of one of the first regions in the first direction is greater than the width of one of the second regions in the first direction.

6. In paragraph 1, A display device, wherein the total number of pixels arranged in each of the first regions is greater than the total number of pixels arranged in each of the second regions.

7. In paragraph 1, Further comprising an insulating layer disposed between the first writing gate line and the second writing gate line, A display device, wherein the insulating layer defines contact holes penetrating the insulating layer, and the first contact portions are respectively positioned within the contact holes.

8. In paragraph 1, A display device, wherein the first write gate line includes a first lower write gate line and a first upper write gate line, and the first upper write gate line is disposed on the first lower write gate line and overlaps the first lower write gate line on a plane.

9. In paragraph 8, It further includes second contact parts arranged between the first lower write gate line and the first upper write gate line and electrically connecting the first lower write gate line and the first upper write gate line, A display device, wherein the second contact portions are arranged in each of the first regions and the second regions.

10. In paragraph 8, A display device wherein the second writing gate line is positioned above the first writing gate line.

11. In paragraph 8, A display device wherein the second write gate line is positioned below the first write gate line.

12. In paragraph 1, Each of the above subpixels includes a data write transistor to which a data voltage is applied, A display device, wherein the second write gate line is electrically connected to the gate electrode of the data write transistor.

13. In paragraph 12, Further comprising a data line extending along a second direction intersecting the first direction, A display device in which the above data line is electrically connected to the above data writing transistor.

14. A substrate including a display area and a non-display area surrounding at least a portion of the display area; A gate driving circuit arranged in the above non-display area; A first write gate line extending in the first direction and electrically connected to the gate driving circuit; A second writing gate line extending in the first direction and overlapping the first writing gate line on a plane; First contact parts arranged between the first write gate line and the second write gate line and electrically connecting the first write gate line and the second write gate line; and It includes pixels arranged in the above display area and each including subpixels electrically connected to the second write gate line, A display device, wherein the total number of the first contact portions is smaller than the total number of the subpixels electrically connected to the second write gate line.

15. In paragraph 14, The above display area includes a plurality of first areas and a plurality of second areas, At least one of the pixels is arranged in each of the first regions and the second regions, Each of the first writing gate line and the second writing gate line extends through the first areas and the second areas, A display device, wherein the first contact portions are arranged in the second regions and are not arranged in the first regions.

16. In paragraph 15, A display device, wherein the second regions are spaced apart from the non-display region in the first direction, and at least one of the first regions is disposed between the non-display region and the plurality of second regions in the first direction.

17. In paragraph 15, A display device wherein the first regions and the second regions are arranged alternately along the first direction.

18. In paragraph 15, Each of the above pixels includes a first subpixel, a second subpixel, and a third subpixel, A first subpixel circuit region in which the first subpixel circuit of the first subpixel is arranged, a second subpixel circuit region in which the second subpixel circuit of the second subpixel is arranged, and a third subpixel circuit region in which the third subpixel circuit of the third subpixel is arranged are arranged adjacent to each other in the first direction. A display device, wherein the first contact portions are arranged in correspondence with each of the first subpixel circuit region, the second subpixel circuit region, and the third subpixel circuit region in each of the second regions.

19. Processor; and A display device including a controller that receives a control signal from the processor and outputs a scan control signal based on the control signal, The above display device, A substrate comprising a display area including first areas and second areas and a non-display area surrounding at least a portion of the display area; A gate driving circuit arranged in the above non-display area and receiving the scan control signal; A first write gate line extending in the first direction and electrically connected to the gate driving circuit; A second write gate line extending in the first direction through the first regions and the second regions and overlapping the first write gate line on a plane; First contact parts arranged between the first write gate line and the second write gate line and electrically connecting the first write gate line and the second write gate line; and The display area includes pixels including subpixels arranged in each of the first areas and the second areas, each of which is electrically connected to the second writing gate line, An electronic device wherein the first contact portions are arranged in the second regions and are not arranged in the first regions.

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