Latency control through clock domain crossing

Abstract

The invention relates to a method, a computer implemented method and a storage medium configured to perform a method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd); b. If ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. If ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

Description

Latency control through Clock Domain CrossingTechnical field

[0001] The disclosure relates to clock domain crossing, and in particular to propagation delay control through clock domain crossing.Background

[0002] A source wants to send data to a destination in which the source and the destination have different clock domains, this is known as Clock Domain Crossing or CDC.

[0003] The interaction between different clock domains presents unique challenges, primarily when data is transferred from one domain to another.

[0004] CDC involves the transfer of data from a source that is clocked by one clock domain to a destination clocked by another clock domain. These two clock domains may have unrelated or asynchronous frequencies, which can lead to setup and hold time violations causing metastability, data loss, or data incoherence.

[0005] Metastability is a state where the output of a flip-flop is unpredictable. It occurs when the data signal changes too close to the clock edge, violating the setup or hold times. This can lead to system failures if not correctly managed.

[0006] Data loss can occur when the destination clock domain is slower than the source clock domain. If the source domain updates the data before the destination domain can latch it, the data is lost.

[0007] Data incoherence, on the other hand, happens when multiple bits of data are crossing the clock domain boundary. If these bits are not synchronised, the destination domain may capture a mix of old and new data, leading to data corruption.

[0008] In the context of Clock Domain Crossing, validity signals and availability signals play a crucial role in ensuring reliable data transfer between different clock domains.

[0009] Validity signals are used to indicate when the data on the bus or communication channel is valid and can be safely read by the receiving domain. The purpose of a validity signal is to prevent the destination domain from reading data that is not yet stable or valid, which could lead to incorrect operation or data corruption.

[0010] On the other hand, availability signals are used to indicate when data is available for reading. This is particularly important when the source and destination domains operate at different frequencies. The availability signal ensures that the destination domain does not attempt to read the data before it is available, which could lead to data loss.

[0011] The time it takes for the validity and availability-signals, to propagate from the source domain to the destination domain and vice versa is known as the propagation delay. The propagation delay is influenced by several factors, including the physical characteristics of the communication channel (such as length and material), the operating frequencies of the source and destination domains, and the design of the CDC logic.

[0012] The subject of clock domain crossing have been addressed in several patent documents among them in US11347917B2 which discloses a computer-implemented method of determining or verifying metastability for a clock domain crossing (CDC), where the method comprising: identifying a first element in the circuit design as a source of the CDC, selecting a second element in the circuit design to be a qualifier that corresponds to the source, and verifying whether metastability is present in clock domain crossing in electronic circuits.

[0013] The patent publication US10042810B2 describes a host controller designed to minimize data jitter in high-speed data interfaces. It employs a logical physical layer (LPHY) to manage low-speed data groups and usesa clock-domain-crossing transmitter (TXCDC) to convert and transmit these data groups to electrical physical layers (EPHYs). The EPHYs then convert the low-speed data into high-speed data for external devices. A multiplexer coordinates the clock signals from the EPHYs to ensure synchronized data output. The TXCDC uses specific clock signals for each EPHY to manage data transmission effectively. The system aims to enhance data integrity and transmission efficiency across different clock domains.

[0014] The patent US8611178B2 The patent describes a device and method for performing memory operations at a clock domain crossing. It involves using a first clock signal to write data to a memory and a second clock signal, different from the first, to read data from the memory. A third clock signal, with a frequency that is an integer multiple of the second clock signal's frequency, is used for the read clock input. This method ensures efficient data transfer across different clock domains, improving performance in systems with varying clock frequencies.

[0015] It is the goal of the present invention to reduce propagation delay through clock domain crossing.Summary of the invention

[0016] In a first aspect of the invention, the invention provides a method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd) ; b. If ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. If ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

[0017] And further if the data transfer capacity of the source domain (ds) is faster than the data transfer capacity of the destination side (dd) the source domain continuously sends data, including neutral data, to thedestination domain when no valid data is available to ensure continuous data flow.

[0018] The method may further comprise: a. utilizing a FIFO buffer between the source domain and the destination domain to temporarily store data during transfer. The FIFO buffer can have a length (L) and a width (W) that are configured based on the data path width and the clock frequencies of the source and destination domains.

[0019] The intermediate metastability buffer may comprise a chain of flip-flops to mitigate the effects of metastability during data transfer. The number of flip-flops in the metastability buffer chain can be adjustable based on the clock frequencies and data width of the source and destination domains.

[0020] In one aspect of the invention the source domain and destination domain operate at asynchronous frequencies, and the method ensures error-free data transfer by managing propagation delays of validity and availability signals.

[0021] The method may further comprise: a. synchronizing the data transfer by ensuring that the faster domain operates at the pace of the slower domain.

[0022] In one aspect of the invention the source domain data width is larger than that of the destination domain the method includes segmenting the data into smaller chunks to match the width of the receiver domain. The segmented data can be reassembled at the destination domain to reconstruct the original data.

[0023] The method may further comprise: at the destination domain draining messages as fast as they are received through the CDC layer to maintain synchronization with the source domain.

[0024] The present invention also provides a computer-implemented method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd) ;b. if ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. if ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

[0025] Wherein the computer -implemented method may carry out all the steps related to the method above.

[0026] The present invention also provides a storage medium configured to perform a method for optimizing clock domain crossing data transfer between a source domain and a destination domain, the method comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd); b. if ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. if ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

[0027] Other advantageous features will be apparent from the accompanying claims.Brief description of the drawings

[0028] To make the invention more readily understandable, the discussion that follows will refer to the accompanying drawings, in which:

[0029] Figure la shows the principle of clock domain crossing according to state of the art;

[0030] Figure 2 shows the principle of clock domain crossing according to state of the art;

[0031] Figure 3a shows a principle of clock domain crossing where a source domain is faster than a destination domain, and

[0032] Figure 3b shows the principle of clock domain crossing where the source domain is slower than the destination domain.Detailed description of the Invention

[0033] In the following, general embodiments as well as exemplary embodiments of the invention will be described. References and possible numerals will be made to the accompanying drawings. It shall be noted, however, that the drawings are exemplary embodiments only, and that other features and embodiments may well be within the scope of the invention as described.

[0034] The present invention relates to CDC and in particular to reducing propagation delay for the time it takes for the validity and / or availabilitysignals, to propagate from the source domain to the destination domain and from the destination domain to the source domain. The aim behind the use of validity signals sent by a source domain and availability signals sent by a destination domain is to ensure secure and loss free data transfer over CDC.

[0035] Normally a source domain which is a sender of data sends a validity signal via a metastability structure to the destination domain, when the destination domain receives this signal, the destination domain knows that the data in a buffer between source domain and destination domain are valid. The destination domain, on the other hand, sends an availability signal via a metastability structure to the source domain to indicate that the buffer is ready to receive data. The buffer is typically a FIFO buffer with a length L and a width of data path W. The time used to send and receive validity and availability signals is a delay in a CDC system that is traditionally considered necessary to ensure error-free data transfer in Clock Domain Crossings - CDC. If one could shorten the propagation delay for validity / availa bility signalling, data transmission could go faster. The trick here is to achieve this without compromising secure data transfer in CDC. If the source domain operates at a clock frequency, fs, that is higher than the destination domain's, fd, the destination domain will never be able to empty the buffer between source domain and destination domain (i.e. fs>fd), conversely if the destination domain has a clock frequency, fd, that is faster than the source domain's, fs, the sourcedomain will never be able to overflow the buffer (i.e. fs<fd)- Only taking into consideration the frequency of the source and the receiver is a simplification as the width of the data path affects the sending speed and / or the receiving speed. The more bits the data width, the higher the data transfer capacity.

[0036] The relationship between clock frequency, data width, and data transfer capacity can be expressed by the formula:

[0037] Data Transfer Capacity=Clock Frequency* Data Width

[0038] This means that the data transfer capacity increases linearly with both the clock frequency and the data width. This is a simplified model, other factors like latency, overhead, and the specific architecture of the system can also have significant effects on the data transfer rate.

[0039] So, while the relationship between frequency, width, and data transfer capacity is generally fixed, the actual throughput can vary based on a number of other factors. In what follows, it must be understood that the fast side is the side with the highest data transfer capacity.

[0040] The recognition of this leads to the present invention - in the case of a fast source domain and a slower destination domain, it is not necessary to send a validity signal from the source domain since there will always be data in the buffer between the fast source domain and the slower destination domain. In the case where the destination domain is faster than the source domain, the destination domain will not need to send an availability signal to the source domain, as there will always be space in the buffer between source domain and destination domain since the destination domain reads faster than the source domain can send. Whether the source domain is the faster or the destination domain is the fastest is a static situation, hence a setup which takes the above into consideration will be decided once and for all before a circuit with CDC is put into use.

[0041] In the context of Clock Domain Crossing (CDC) the data width at the source can be larger than that of the receiver. This scenario introduces additional complexities.

[0042] When the source data width is larger than the receiver, you would typically need to divide the data into smaller chunks that match the receiver's width. This process is often referred to as data slicing or segmentation. The segmented data is then sent over multiple clock cycles.

[0043] For instance, if the sender is 32 bits wide and the receiver is 16 bits wide, you could divide the 32- bit data into two 16- bit segments. Each segment would then be sent over a separate clock cycle.

[0044] However, it's important to note that this approach can introduce latency, as the complete data transfer now takes multiple clock cycles. Also, the receiver needs to be able to reassemble the data segments in the correct order to reconstruct the original data.

[0045] Moreover, each segment of data is subject to the same CDC challenges as any other data transfer across different clock domains. Therefore, standard CDC strategies and techniques, such as synchronization, metastability handling, etc., should be applied.

[0046] If the receiver's data width is the larger one then the process is somewhat simpler than the reverse scenario.

[0047] When the sender's data width is smaller than the receiver's, the sender's data can be sent in its entirety in a single clock cycle. The receiver can then store this data in a portion of its wider register. For instance, if the sender is 16 bits wide and the receiver is 32 bits wide, the 16-bit data from the sender can be stored in the lower or upper 16 bits of the receiver's 32-bit register.

[0048] However, it's important to note that the receiver must be designed to handle this situation correctly. It needs to know which bits of its register contain valid data and which do not. This can be achieved by using additional control signals or by implementing a protocol between the sender and receiver.

[0049] As indicated above the relationship between source and destination is not only about the frequency difference, but the width of the data path on both sides, so combined this becomes "throughput". A distinction is madehere between data transfer capacity, which is the capacity of the source and the destination side separately, while throughput is the combined speed, i.e. the real transfer speed between source and destination.

[0050] In the context of Clock Domain Crossing (CDC), a metastability structure, plays a crucial role in managing the transfer of data between different clock domains, such as the source domain and destination domain described above.

[0051] The metastability structure is typically a chain of two or more flip-flops used to mitigate the effects of metastability. When data is transferred from a source domain to a destination domain, there is a risk that the data may change state at the same time as the clock edge of the destination domain. This can lead to a condition known as metastability, where the output of the flip-flop becomes unpredictable, potentially leading to system failures.

[0052] The purpose of the metastability structure is to provide a buffer period, allowing the metastable condition to resolve itself before the data is used. The first flip-flop in the chain captures the incoming data, and if a metastable event occurs, the subsequent flip-flops in the chain provide extra time for the metastability to resolve. This is known as the metastability resolution time.

[0053] No metastability structure can completely eliminate the risk of metastability, but they can reduce the probability to a level that is acceptable for the specific application. The design of the metastability structure, including the number of flip-flops in the chain and the clock frequency, can be adjusted to manage this trade-off.

[0054] Thus, the metastability structure in CDC is a critical component in ensuring reliable data transfer between different clock domains, helping to manage and mitigate the risks associated with metastability.

[0055] The buffer between the source domain and the destination domain is a place where the data transferred from the source domain to the destination domain is temporarily stored, waiting to be consumed. Its purpose is to maintain performance despite distance between source anddestination. Distance in the general sense is latency, and it should be remembered that one side has always guaranteed the highest data transfer capacity (faster) of the two sides, i.e. sender and receiver, where Data Transfer Capacity =Ciock Frequency*. Data Width, it will be the side with the lowest data transfer capacity which dictates the throughput.

[0056] If width match, then it directly translates into guaranteed strictly higher frequency of usage. The core throughput is guaranteed higher than the link throughput in both directions.

[0057] The buffer is used to store data while transferring flow control through CDC. The buffer must have enough entries to cover the roundtrip latency across the buffer.

[0058] If the faster side is the source domain, the CDC buffer (FIFO-buffer) will be filled which makes latency dependent on the size of the buffer storage.

[0059] Based on the faster / slower guaranteed assumption, the following simplifications can be made to the CDC transfer of flow control:

[0060] Faster source to slower destination domain transfer, ref. fig. 3a: a. no CDC transfer of flow control. b. The slower side assumes it can always act. c. Fast to slow CDC - source to destination: the destination domain assumes that data are always valid.

[0061] If the source domain has nothing to send, the source domain will still send something neutral, which may be discarded by the destination domain.

[0062] And the simplification related to the slower source domain to faster destination domain transfer, ref. fig 3b the source domain assumes always available: a. progress of validity signal b. The faster destination domain acts whenever the slower source domain does, 1 for 1 (synced pace) c. No need to exchange explicit buffer pointers. d. Validity signals (Flow control) to faster destination domain generated out of the validity signals.

[0063] The outcome of the slow source domain to faster destination domain:

[0064] Consequence: the faster side always moves at the pace of the slower side. Each "faster side" clock cycle, the faster side assesses if the slower side moved based on the validity signals of progress sent through the CDC. They are "in sync" as much as they can be (some uncertainty left because of CDC).

[0065] The destination domain must drain messages as fast as they go through the CDC layer (at least).

[0066] The source domain always sends something, even if the source domain has nothing to send, the source domain may still send something neutral which can be discarded by the destination domain.

Claims

Claims1. A method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd) ; b. If ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. If ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

2. The method of claim 1, wherein the data transfer capacity of the source domain is faster than the data transfer capacity of the destination side the source domain continuously sends data, including neutral data, to the destination domain when no valid data is available to ensure continuous data flow.

3. The method of claim 1, further comprising: a. utilizing a FIFO buffer between the source domain and the destination domain to temporarily store data during transfer.

4. The method of claim 3, wherein the FIFO buffer has a length (L) and a width (W) that are configured based on the data path width and the clock frequencies of the source and destination domains.

5. The method of claim 1, wherein the intermediate metastability buffer comprises a chain of flip-flops to mitigate the effects of metastability during data transfer.

6. The method of claim 5, wherein the number of flip-flops in the metastability buffer chain is adjustable based on the clock frequencies and data width of the source and destination domains.

7. The method of claim 1, wherein the source domain and destination domain operate at asynchronous frequencies, and the method ensures error-free data transfer by managing propagation delays of validity and availability signals.

8. The method of claim 1, further comprising the step of:a. synchronizing the data transfer by ensuring that the faster domain operates at the pace of the slower domain.

9. The method of claim 1, wherein the source domain data width is larger than that of the destination domain the method includes segmenting the data into smaller chunks to match the width of the receiver domain.

10. The method of claim 9, wherein the segmented data is reassembled at the destination domain to reconstruct the original data.

11. The method of claim 1, wherein the destination domain drains messages as fast as they are received through the CDC layer to maintain synchronization with the source domain.

12. A computer-implemented method for optimizing clock domain crossing data transfer between a source domain and a destination domain, comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd) ; b. if ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. if ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

13. The computer-implemented method of claim 12, wherein the computer - implemented method carries out the methods of claim 2 - 11.

14. A storage medium configured to perform a method for optimizing clock domain crossing data transfer between a source domain and a destination domain, the method comprising: a. determining the data transfer capacity of the source domain (ds) and the data transfer capacity of the destination domain (dd); b. if ds > dd, transmitting an availability signal from the destination domain to the source domain via an intermediate metastability buffer; c. if ds < dd, transmitting a validity signal from the source domain to the destination domain via the intermediate metastability buffer.

15. The storage medium of claim 14, configured to perform a method according to claim 2 - 11.

Images