Communication method, first devices, chip, storage medium, program and program product

Abstract

Provided in the embodiments of the present application are a communication method, first devices, a chip, a storage medium, a program and a program product. The communication method comprises: a first device transmits a preamble, wherein the preamble comprises a synchronization information portion, and the synchronization information portion is used for at least one of the following: acquiring time synchronization, acquiring frequency synchronization and indicating the chip length of a first chip, the first chip being a chip used for transmitting control information and / or data information.

Description

Communication methods, first devices, chips, storage media, programs, and program products Technical Field

[0001] This application relates to the field of mobile communication technology, specifically to a communication method, a first device, a chip, a computer storage medium, a computer program, and a computer program product. Background Technology

[0002] In environmental IoT systems, the preamble of a transmission frame includes a start indication section and a synchronization section. Currently, there is no clear method for using the synchronization section of the preamble to indicate the chip length corresponding to the control information and / or data information included in the transmission frame.

[0003] Summary of the Invention

[0004] This application provides a communication method, a first device, a chip, a computer storage medium, a computer program, and a computer program product.

[0005] Firstly, a communication method is provided, the method comprising:

[0006] The first device transmits a preamble; the preamble includes a synchronization information portion, which is used for at least one of the following: obtaining time synchronization, obtaining frequency synchronization, and indicating the chip length of the first chip;

[0007] The first chip is a chip used to transmit control information and / or data information.

[0008] Secondly, a first device is provided, comprising:

[0009] A communication unit is configured to transmit a preamble; the preamble includes a synchronization information portion, which is used for at least one of the following: acquiring time synchronization, acquiring frequency synchronization, and indicating the chip length of a first chip;

[0010] The first chip is a chip used to transmit control information and / or data information.

[0011] Thirdly, the first device provided in the embodiments of this application includes a processor and a memory. The memory is used to store computer programs, and the processor is used to call and run the computer programs stored in the memory to perform the aforementioned communication method.

[0012] Fourthly, the chip provided in the embodiments of this application is used to implement the above-described communication method.

[0013] Specifically, the chip includes a processor for retrieving and running a computer program from memory, causing a device equipped with the chip to perform the aforementioned communication method.

[0014] Fifthly, the computer-readable storage medium provided in the embodiments of this application is used to store a computer program that causes a computer to perform the above-described communication method.

[0015] Sixthly, the computer program product provided in the embodiments of this application includes computer program instructions that cause a computer to execute the above-described communication method.

[0016] Seventhly, the computer program provided in the embodiments of this application, when run on a computer, causes the computer to execute the above-described communication method.

[0017] This application provides a communication method in which a first device transmits a preamble; the preamble includes a synchronization information portion, which is used for at least one of the following: obtaining time synchronization, obtaining frequency synchronization, and indicating the chip length of a first chip; wherein the first chip is a chip used to transmit control information and / or data information. Thus, a method is clarified for indicating the chip length corresponding to control information and / or data information included in a transmission frame through the synchronization information portion of the preamble. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 is a schematic diagram of an environmental Internet of Things (IoT) communication system architecture provided in an embodiment of this application;

[0020] Figure 2 is a schematic diagram of the structure of a radio frequency energy harvesting module provided in an embodiment of this application;

[0021] Figure 3 is a schematic diagram of a backscatter communication principle provided in an embodiment of this application;

[0022] Figure 4 is a schematic diagram of a resistive load modulation principle provided in an embodiment of this application;

[0023] Figure 5 is a schematic diagram of an environmental Internet of Things topology provided in an embodiment of this application;

[0024] Figure 6 is a schematic diagram of an environmental Internet of Things topology provided in an embodiment of this application;

[0025] Figure 7 is a flowchart illustrating a communication method provided in an embodiment of this application;

[0026] Figure 8 is a schematic diagram of a signal structure provided in an embodiment of this application;

[0027] Figure 9 is a schematic diagram of a Manchester encoding provided in an embodiment of this application;

[0028] Figure 10A is a schematic diagram of a reference chip provided in an embodiment of this application;

[0029] Figure 10B is a schematic diagram of a reference chip provided in an embodiment of this application;

[0030] Figure 11 is a schematic diagram of a reference chip provided in an embodiment of this application;

[0031] Figure 12 is a schematic diagram of a reference chip provided in an embodiment of this application;

[0032] Figure 13 is a schematic diagram of a reference chip provided in an embodiment of this application;

[0033] Figure 14 is a schematic diagram of a reference chip provided in an embodiment of this application;

[0034] Figure 15 is a schematic diagram of a reference chip provided in an embodiment of this application;

[0035] Figure 16 is a block diagram of a signal modulation method provided in an embodiment of this application;

[0036] Figure 17 is a block diagram of a signal processing method provided in an embodiment of this application;

[0037] Figure 18A is a schematic diagram of a synchronization information section provided in an embodiment of this application;

[0038] Figure 18B is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0039] Figure 18C is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0040] Figure 18D is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0041] Figure 19A is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0042] Figure 19B is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0043] Figure 19C is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0044] Figure 19D is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0045] Figure 20 is a schematic diagram nine of a synchronization information section provided in an embodiment of this application;

[0046] Figure 21 is a schematic diagram of a synchronization information portion provided in an embodiment of this application;

[0047] Figure 22 is a schematic diagram of the structure of a first device provided in an embodiment of this application;

[0048] Figure 23 is a schematic structural diagram of a first device provided in an embodiment of this application;

[0049] Figure 24 is a schematic structural diagram of a chip according to an embodiment of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] Currently, cellular IoT is booming, and the 3rd Generation Partnership Project (3GPP) has standardized IoT technologies such as Narrow Band Internet of Things (NB-IoT), Machine Type Communication (MTC), and Reduced Capability (RedCap). However, there are still many IoT communication needs in various scenarios that cannot be met by existing technologies, such as harsh communication environments (high temperature, extremely low temperature, high humidity, high pressure, high radiation, or high speed movement, etc.), the need for extremely small terminal form factors, and extremely low cost.

[0052] Ambient IoT (A-IoT) can cover the unmet IoT communication needs mentioned above due to its ultra-low cost, extremely small size, and battery-free / maintenance-free characteristics.

[0053] A-IoT communication employs energy harvesting and backscatter communication technologies. A-IoT devices are IoT devices powered by various environmental energy sources, such as radio frequency energy, light energy, solar energy, thermal energy, and mechanical energy. These devices may have no energy storage capacity or very limited energy storage capacity (e.g., using capacitors with a capacitance of tens of microfarads (µF)). Compared to existing IoT devices, A-IoT devices offer numerous advantages, including no need for conventional batteries, no maintenance, small size, low complexity and low cost, and long lifespan.

[0054] Referring to the schematic diagram of the environmental IoT communication system in Figure 1, the environmental IoT can consist of network devices and A-IoT devices. The network devices are used to send power signals and / or downlink communication signals to the A-IoT devices, and also to receive backscattered signals from the A-IoT devices. A basic A-IoT device may include an energy harvesting module, a backscattered communication module, a low-power computing module, and a sensor module. In addition, the A-IoT device may also have a memory to store basic information (such as object identification) and sensor data such as ambient temperature and humidity.

[0055] In the embodiments of this application, the A-IoT system can also be called a zero-power system, and the A-IoT device can also be called a zero-power device.

[0056] Key technologies for the Internet of Things (IoT) in the environment mainly include radio frequency power harvesting (RF Power Harvesting) and back scattering communication.

[0057] Referring to Figure 2, which shows a schematic diagram of the radio frequency (RF) energy harvesting module, the module includes a diode, a capacitor C, and a resistor RL. In practical applications, the RF energy harvesting module harvests electromagnetic wave energy from space based on the principle of electromagnetic induction, thereby obtaining the energy required to drive A-IoT devices, such as low-power demodulation and modulation modules, sensors, and memory access. This means that A-IoT devices may not require a traditional battery module.

[0058] Referring to Figure 3, which illustrates the principle of backscatter communication, an A-IoT device receives wireless signals from network devices, modulates these signals, loads the information to be transmitted, and radiates the modulated signal from the antenna. This information transmission process is called backscatter communication.

[0059] It should be noted that backscattering and load modulation are inseparable. Load modulation adjusts and controls the circuit parameters of the A-IoT device's oscillation circuit according to the data flow rhythm, thereby changing parameters such as the electronic tag's impedance, thus completing the modulation process.

[0060] Load modulation techniques can include two methods: resistive load modulation and capacitive load modulation. Referring to Figure 4, which illustrates the principle of resistive load modulation, the load RL can be connected in parallel with a resistor R3. This resistor R3 can be switched on or off based on the control of the binary data stream. The switching on and off of resistor R3 causes a change in the circuit voltage, thus achieving Amplitude Shift Keying (ASK), i.e., signal modulation and transmission are achieved by adjusting the amplitude of the backscattered signal from the zero-power terminal. Similarly, in capacitive load modulation, the switching on and off of the capacitor can change the circuit's resonant frequency, achieving Frequency Shift Keying (FSK), i.e., signal modulation and transmission are achieved by adjusting the operating frequency of the backscattered signal from the A-IoT device.

[0061] As can be seen, A-IoT devices utilize load modulation to modulate the incoming signal, thereby achieving backscatter communication. Therefore, A-IoT devices have the following significant advantages:

[0062] (1) A-IoT devices do not actively transmit signals, so they do not require complex radio frequency links, such as power amplifiers (PA) and radio frequency filters;

[0063] (2) A-IoT devices do not need to actively generate high-frequency signals, therefore they do not need high-frequency crystal oscillators;

[0064] (3) With the help of backscatter communication, A-IoT devices do not need to consume the terminal's own energy for signal transmission.

[0065] A-IoT devices include the following types:

[0066] Device Type 1: With a peak power consumption of approximately 1 microwatt (~1 μW), it has energy storage capabilities and an initial sampling frequency offset (SFO) of up to 10. X ppm (parts per million) has neither a downlink amplifier nor an uplink amplifier, and uplink transmission is achieved through backscattering of the carrier wave.

[0067] Device type 2a: With peak power consumption of less than or equal to several hundred microwatts (≤ a few hundred μW), energy storage capability, and initial sampling frequency deviation up to 10. X ppm, with a downlink amplifier and / or an uplink amplifier, performs uplink transmission by backscattering the carrier.

[0068] Device type 2b: Peak power consumption of less than or equal to several hundred microwatts (μW), with energy storage capability, and initial sampling frequency deviation up to 10. X ppm, which has a downlink amplifier and / or an uplink amplifier, is generated internally during uplink transmission and can also be referred to as being based on active transmission.

[0069] Based on the discussion of A-IoT application scenarios according to the 3GPP system architecture (SA)1, A-IoT can be used in at least the following four types of scenarios:

[0070] Object recognition, such as in logistics, production line product management, and supply chain management.

[0071] Environmental monitoring, such as monitoring of temperature, humidity, and harmful gases in the working environment and natural environment.

[0072] Location tracking, such as indoor positioning, smart item finding, and production line item location.

[0073] Intelligent control, such as the intelligent control of various electrical appliances in smart homes (turning on and off air conditioners, adjusting temperature), and the intelligent control of various facilities in agricultural greenhouses (automatic irrigation, fertilization).

[0074] In cellular network-based IoT environments, A-IoT devices can communicate directly with base station devices or through intermediate nodes. Referring to Figure 5, which illustrates the first cellular IoT topology, A-IoT devices can directly transmit and receive carrier waves, data, or signals from the base station, and send or backscatter data or channels to the base station. Alternatively, referring to Figure 6, which illustrates the second cellular IoT topology, communication between A-IoT devices and the base station is achieved through intermediate nodes. In this case, the intermediate node sends carrier waves, data, or signals to the A-IoT device, and the A-IoT device sends or backscatters data or signals to the intermediate node. The intermediate node can be a terminal device, a base station device, or an Integrated Access and Backhaul (IAB) node.

[0075] It should be noted that in the two topologies mentioned above, the base station in the first topology and the intermediate UE in the second topology are called readers, and the A-IoT device can be called a device. The transmission from the reader to the device is called Reader to Device (R2D) transmission, and the transmission from the device to the reader is called Device to Reader (D2R) transmission.

[0076] The preamble portion of an A-IoT system includes a start indication section and a synchronization information section. Currently, there is no clear method for using the synchronization information section of the preamble to indicate the chip length corresponding to the control information and / or data information included in the transmission frame.

[0077] This application provides a communication method in which a first device transmits a preamble; the preamble includes a synchronization information portion, which is used for at least one of the following: obtaining time synchronization, obtaining frequency synchronization, and indicating the chip length of a first chip; wherein the first chip is a chip used to transmit control information and / or data information. It is understood that this application clarifies a method for indicating the chip length corresponding to control information and / or data information included in a transmission frame through the synchronization information portion of the preamble.

[0078] To facilitate understanding of the technical solutions of the embodiments of this application, the technical solutions of this application are described in detail below through specific embodiments. The above-mentioned related technologies are optional solutions and can be arbitrarily combined with the technical solutions of the embodiments of this application, all of which fall within the protection scope of the embodiments of this application. The embodiments of this application include at least some of the following contents.

[0079] It should be noted that the synchronization information in the embodiments of this application can be understood as synchronization signal, and the two are equivalent or interchangeable.

[0080] Figure 7 illustrates a communication method provided in an embodiment of this application, which may include:

[0081] S710, The first device transmits a preamble; the preamble includes a synchronization information portion, which is used for at least one of the following: obtaining time synchronization, obtaining frequency synchronization, and indicating the chip length of the first chip; wherein, the first chip is a chip used to transmit control information and / or data information.

[0082] It should be noted that the communication method provided in this application embodiment can be applied to cellular networks, Internet of Things and other communication networks, and this application embodiment does not limit it.

[0083] It should also be noted that the first device can be a network device, a reader, etc. For example, the first device can be a base station as shown in Figure 5 or Figure 6. In addition, the first device can also be a terminal device. For example, the first device can be an IoT device, an A-IoT device, a zero-power device, a low-power device, etc., and the embodiments of this application do not limit this.

[0084] In this embodiment of the application, the first device can transmit a preamble.

[0085] It should be noted that the preamble can be reader-to-device (R2D) or device-to-reader (D2R).

[0086] It should also be noted that a reader can also be called a reader; the two are equivalent or interchangeable.

[0087] It should also be noted that the first device can transmit frames, which may carry control information such as resource configuration, resource indication, and resource scheduling. It should be understood that, to ensure correct frame reception, referring to the signal structure diagram in Figure 8, a preamble may be transmitted before the control information and / or data information. The preamble can be used to indicate the start position of the frame in the time domain, and / or for the frame receiver to obtain time synchronization or frequency synchronization information. Additionally, the frame may also include a postamble, which can be used to determine the end position of the frame. It should be noted that the postamble is optional; that is, the frame may or may not include a postamble.

[0088] In some embodiments, the preamble may include a start-indicator (SI) part and a clock-acquisition part (CAP) part, wherein the clock-acquisition part may also be referred to as the clock acquisition part.

[0089] The start indication information portion can be used to indicate the time-domain start position of the frame. The synchronization information portion can be used to obtain at least one of time synchronization, frequency synchronization, and indicating the chip length of the first chip. Specifically, the synchronization information portion can be used by the receiving end to obtain at least one of time synchronization, frequency synchronization, and indicating the chip length of the first chip.

[0090] Understandably, the first device can determine the time-domain start position of the frame based on the start indication information in the frame preamble, and receive the frame according to the time-domain start position. Then, the first device can obtain time synchronization and / or frequency synchronization based on the synchronization information in the preamble. In this way, the first device can correctly receive control information and / or data information.

[0091] It should be noted that, in addition to the start indication information part and the synchronization information part, the preamble part may also include other parts, and the embodiments of this application do not limit this.

[0092] In the above embodiments, the chip length of the first chip is indicated by the synchronization information section, which improves the convenience of determining the chip length of the first chip.

[0093] In some embodiments, the first position where the synchronization information portion is located is mapped based on a first time unit; the first time unit includes: a cyclic prefix length and a first symbol.

[0094] It should be noted that the first position refers to the position in the synchronization information section where the reference chip begins to be mapped based on the first time unit. The first time unit can be a time unit composed of a cyclic prefix length (CP) and a first symbol. The first symbol can be an orthogonal frequency division multiplexing (OFDM) symbol. The cyclic prefix length refers to a complete cyclic prefix in the first symbol.

[0095] In some embodiments, the first position of the synchronization information portion can be determined based on the position of the cyclic prefix length in the first time unit, and the reference chip can be mapped according to the first position of the synchronization information portion.

[0096] In some embodiments, the synchronization information portion includes one or more reference chips, which are used to indicate the chip length of the first chip.

[0097] It should be noted that the reference chip can be the chip used in the synchronization information section to indicate the chip length of the first chip. Here, a chip is an coded signal in digital signal transmission and is the smallest unit of the digital signal carrier.

[0098] It should also be noted that chip length can be the number of bits contained in a chip or the length of time.

[0099] In some embodiments, the synchronization information portion may include one or more reference chips, wherein the chip lengths of the multiple reference chips may be the same or different, and the chip length of the first chip may be indicated by the reference chips.

[0100] In the above embodiments, the chip length of the first chip is indicated by one or more reference chips, which improves the convenience and accuracy of determining the chip length of the first chip.

[0101] In some embodiments, the chip length of the reference chip is the same as the chip length of the first chip.

[0102] For example, if the synchronization information section includes only one first chip among a reference chip, control information, and / or data information, the chip length of the reference chip is the same as the chip length of the first chip, and the chip length of the control information and / or data information can be determined by the chip length of the reference chip. If the synchronization information section includes multiple reference chips, and the control information and / or data information includes the same number of first chips as the reference chip, the chip length of each reference chip can correspond one-to-one with the chip length of each first chip, and the chip length of the control information and / or data information can be determined by the sum of the chip lengths of the reference chips. If the synchronization information section includes multiple reference chips, and the control information and / or data information includes a different number of first chips than the reference chip, the sum of the chip lengths of the multiple reference chips can be the same as the chip length of a single first chip. Understandably, when the chip length of the reference chip does not correspond one-to-one with the chip length of each first chip, the correspondence between the position of the reference chip and the position of the first chip can be determined by matching the chip length of the reference chip with the chip length of the first chip, and thus the chip length of the first chip can be determined based on the chip length of the reference chip.

[0103] In some embodiments, the length of the cyclic prefix in each first time unit may be different. Different lengths of the cyclic prefix may affect the chip length of the reference chip, thereby affecting the accuracy of the chip length of the detected first chip.

[0104] In the above embodiments, the chip length of the reference chip is the same as the chip length of the first chip, so as to facilitate the determination of the chip length of the first chip based on the chip length of the reference chip, thereby improving computational efficiency and accuracy.

[0105] In some embodiments, a first position of a reference chip may be set. When one or more reference chips are mapped from a first position of a first time unit, the first position includes at least one of the following: a position after the cyclic prefix length; a starting position of the cyclic prefix length; or a position between the starting and ending positions of the cyclic prefix length.

[0106] In some embodiments, one or more reference chips are mapped within a first symbol; adjacent reference chips have opposite voltage levels.

[0107] In some embodiments, one or more reference chips occupy a first time unit, and each reference chip has the same length; when the first position is the starting position of the cyclic prefix length, the level of the first H reference chips is the same as the level of the last H chips; wherein, H is an integer that is the first length divided by the second length and then rounded up, and H is an integer greater than or equal to 1; the first length is the cyclic prefix length; and the second length is the length of a reference chip.

[0108] It should be noted that the first length can be greater than, equal to or less than the second length, and this application does not impose any special restrictions on this.

[0109] In the above embodiments, the level of the first H reference chips in the synchronization information section is the same as the level of the last H chips. This can reduce the phenomenon that the reference chip section in the synchronization information section is misjudged as part of the first symbol or cyclic prefix length, resulting in inaccurate chip length of the indicated first chip, and improve the accuracy of determining the chip length of the first chip.

[0110] In some embodiments, one or more reference chips include: a first signal and a fifth signal; the fifth signal is a signal mapped to the position after the cyclic prefix length after deleting P sampling points of the synchronization information portion; wherein, P is the number of sampling points corresponding to the first length; P is a positive integer greater than or equal to 1; the first signal is the signal in the fifth signal corresponding to the last P sampling points.

[0111] For example, the first H (H = CEIL(L / C)) chips and the last H chips of the synchronization information section are the same, where L represents the length of the cyclic prefix, C represents the length of a reference chip in the synchronization information section, and CEIL() represents rounding up. When generating the synchronization information section, the Pth sample point of the sampled value corresponding to the synchronization information section is first mapped to the end of the cyclic prefix length, and the last P sample points of the synchronization information section are mapped to the beginning of the cyclic prefix length of the first symbol.

[0112] It is understandable that the signal corresponding to the last P sampling points mapped to the starting position of the cyclic prefix length has the same signal level as the signal corresponding to the last P sampling values ​​of the synchronization information part. In the specific mapping process, assuming that the sampling point sequence corresponding to the synchronization information part is x(n), the first P sampling points of the sampling point sequence x(n) are deleted, then an N'-point DFT (Discrete Fourier Transform) is performed on x(n), then it is mapped to X subcarriers, and finally a K-point IFFT is performed and a cyclic prefix is ​​added, as shown in Figure 17. In the above embodiment, when the chip length used in the synchronization information part and PRDCH is relatively short, the lengths of the chip and the cyclic prefix length are close, which can avoid the influence of the cyclic prefix length on the detection of the synchronization information part.

[0113] In some embodiments, when the first position is after the cyclic prefix length, the level of the first reference chip is opposite to the level of the first signal, the level of the last reference chip is the same as the level of the first signal, and the level of the first signal is the same as the level of the second signal; wherein, the first signal refers to the signal of the cyclic prefix portion; and the second signal refers to the signal of the start indication information portion in the preamble.

[0114] It should be noted that the loop prefix part refers to a portion within the loop prefix length, which can be the loop prefix length itself.

[0115] It should also be noted that the position after the cycle prefix length can be the end position of the cycle prefix length or the position after the end position.

[0116] It is understood that if the level of the first reference chip in the synchronization information section is opposite to the level of the first signal, and the level of the last reference chip is the same as the level of the first signal, then the level of the first reference chip in the synchronization information section is opposite to the level of the last reference chip. When the levels of adjacent reference chips are opposite, the synchronization information section in the above embodiment should contain an even number of reference chips.

[0117] In some embodiments, the synchronization information portion is mapped starting after the cyclic prefix length of a first time unit (i.e., the first reference chip for the synchronization information portion, after signal processing, is transmitted starting after the cyclic prefix length of a first time unit, or the sampling point of the first reference chip in the synchronization information portion is mapped after the cyclic prefix length of a first time unit). This means the location of the synchronization information portion does not include the cyclic prefix length, and it is guaranteed that the synchronization information portion includes an even number of reference chips, such as 2, 4, or 6, etc., and the level of the last reference chip is the same as the level of the signal in the start indication information portion. It is understood that when the level of the last reference chip in the synchronization information portion is the same as the level of the signal in the start indication information portion, the level of the signal in the start indication information portion is the same as the level of the signal in the cyclic prefix portion before the first reference chip in the synchronization information portion. Therefore, during level detection, the cyclic prefix length can be treated as part of the start indication information portion, without generating additional edges, reducing the possibility of misjudging the cyclic prefix portion as part of a reference chip due to additional edges.

[0118] Taking a synchronization information section containing two reference chips as an example, as shown in Figure 11, the synchronization information section contains two reference chips located within a first symbol of a first time unit. The first chip starts mapping from the position after the cyclic prefix length (CP), and the second chip is low-level, with the same level as the signal in the cyclic prefix section before the first chip. It should be emphasized that this embodiment is applicable to the case where the signal in the cyclic prefix section includes only one level. That is, the chip length of the cyclic prefix section cannot be too short, resulting in the cyclic prefix section signal including different levels.

[0119] In the above embodiments, when the synchronization information section includes an even number of reference chips, if the level of the last reference chip is the same as that of the first signal, then the level of the first reference chip is opposite to that of the first signal. This can prevent the first reference chip from being misjudged as part of the first signal and improve the accuracy of the determined chip length.

[0120] In some embodiments, when the first position is between the start and end positions of the cyclic prefix length, the levels of the first and last reference chips are opposite to the level of the third signal, and the level of the last part of the synchronization information portion is the same as the level of the third signal; wherein, the third signal refers to the signal of the cyclic prefix portion before the first position.

[0121] It should be noted that the end of the synchronization information section refers to the part within the first symbol, after the last reference chip in the synchronization information section; the end of the synchronization information section is not within the synchronization information section itself.

[0122] The synchronization information section is mapped between the start and end positions of the cyclic prefix length of a first time unit, and ensures that the synchronization information section includes an odd number of reference chips, such as 1, 3, 5, etc., and the level of the end part after the last reference chip of the synchronization information section is the same as the level of the start indication information section before the synchronization information section.

[0123] Taking a synchronization information section containing one reference chip as an example, as shown in Figure 12, the synchronization information section contains one reference chip, located within the first symbol of a first time unit. This reference chip is mapped from the start and end positions of the cyclic prefix length (CP), occupying the duration of one first symbol. The end portion after the synchronization information section is at a low level, and its length is at least the minimum easily detectable length, thus ensuring that the level after the synchronization information section is the same as the level of the starting indication information section before the first reference chip of the synchronization information section. It can be understood that the start and end positions of the cyclic prefix length can be from 1 / 3 or 2 / 3 of the cyclic prefix length, etc., and do not solely refer to 1 / 2 of the cyclic prefix length.

[0124] In the above embodiments, when the synchronization information section includes an odd number of reference chips, the first reference chip and the last reference chip have the same level, and the level of the first reference chip and the last reference chip is opposite to the level of the signal in the cyclic prefix section and the end of the synchronization information section. This can prevent the first reference chip from being misjudged as the cyclic prefix section or the end of the synchronization information section, thereby improving the accuracy of the determined chip length.

[0125] In some embodiments, when the first position is after the cyclic prefix length, the level of the first reference chip is the same as the level of the first signal; the sum of the chip length of the first reference chip and the length of the cyclic prefix is ​​the same as the chip length of the other reference chips; the level of the last chip is the same as the level of the first reference chip; wherein, the first signal refers to the signal of the cyclic prefix portion.

[0126] In some embodiments, the synchronization information portion can be mapped starting from the position after the cyclic prefix length of a first time unit, ensuring that the synchronization information portion includes an odd number of reference chips, and that the length of the first reference chip in the synchronization information portion is shorter than the length of the other reference chips by L, where L is the length of the cyclic prefix length. Starting from the second reference chip, the voltage level of each reference chip is opposite to that of the previous reference chip. The synchronization information portion occupies a first symbol, that is, the sum of the lengths of all reference chips in the synchronization information portion is the same as the length of the first symbol.

[0127] Taking a synchronization information section containing three reference chips as an example, as shown in Figure 13, the synchronization information section contains three reference chips, all located within the first symbol of a first time unit. Starting from the second reference chip, the voltage level of each chip is opposite to that of the previous reference chip. The length of the first reference chip is L shorter than the lengths of the other two reference chips. The first chip is mapped starting from the position after the cyclic prefix length. Since the voltage level of the last chip in the synchronization information section is the same as that of the first chip, the cyclic prefix length is increased before the first reference chip. The combined chip length is the same as the length of the other chips, therefore the cyclic prefix length can be used to transmit useful information.

[0128] In the above embodiments, the length of the first reference chip in the synchronization information section is shorter than the length of the cyclic prefix than the length of the other reference chips. This not only allows the transmission of useful information through the cyclic prefix length, but also avoids the impact of the cyclic prefix length on the terminal's reception of the synchronization information section, thereby improving resource utilization.

[0129] In some embodiments, one or more reference chips are mapped within at least one first symbol; each reference chip is mapped starting from a position after the cyclic prefix length of a first symbol; the length of each reference chip is the same as the length of a first symbol; the level of each reference chip is the same as the level of a first signal and opposite to the level of the next first signal; wherein, the first signal refers to the signal of the cyclic prefix portion of a first symbol; the next first signal refers to the signal of the cyclic prefix portion of the next first symbol.

[0130] In some embodiments, a first symbol contains only one reference chip, which is mapped starting from the cyclic prefix length of the first symbol. The chip length of the reference chip is the same as the length of the first symbol, and the level of the reference chip is the same as the level of the signal in the cyclic prefix portion of the first symbol.

[0131] In some embodiments, two reference chips can be mapped within two consecutive first symbols, with the signal levels of the cyclic prefix portions of the two consecutive first symbols being opposite, and the level of the reference chip mapped within each first symbol being the same as the signal level of the cyclic prefix portion. In this case, within the two consecutive first symbols, the level of the reference chip mapped within the preceding first symbol is opposite to the signal level of the cyclic prefix portion of the following first symbol.

[0132] For example, as shown in Figure 14, Figure 14 contains two first time units, each containing one first symbol. The synchronization information portion contains two reference chips, located in two different first symbols. Each reference chip is mapped starting after the CP of a first symbol. After adding the CP, the length of the reference chip detected by the terminal is equal to the length of a complete first symbol containing the CP (corresponding to the first time unit in the above embodiment). It can be understood that a first symbol contains only one reference chip, and A first symbols contain a total of A reference chips, where A is a positive integer.

[0133] In the above embodiments, the cyclic prefix length can be used to send valid information, thereby improving resource utilization.

[0134] In some embodiments, when the first position is the starting position of the cyclic prefix length, one or more reference chips occupy the first time unit, each reference chip having the same length, and the level of the first reference chip being opposite to the level of the second signal; wherein, the second signal refers to the signal of the start indication information portion in the preamble.

[0135] In some embodiments, the synchronization information portion can be mapped starting from the beginning of the cyclic prefix length of a first time unit. The sum of the chip lengths of one or more reference chips in the synchronization information portion is the same as the length of the first time unit, and there is no limit to the number of reference chips in the synchronization information portion. The level of the first reference chip in the synchronization information portion is opposite to the level of the signal in the start indication information portion of the preamble, in order to reduce the possibility of misidentifying a reference chip as part of the start indication information portion of the preamble.

[0136] As shown in Figure 15, the synchronization information section is mapped starting from the beginning of the cyclic prefix length of a first time unit, and the sum of the chip lengths of the multiple reference chips in the synchronization information section is the same as the length of the first time unit.

[0137] In the above embodiments, the level of the first reference chip is opposite to that of the first signal, which can prevent the first reference chip from being misjudged as part of the first signal and improve the accuracy of the determined chip length.

[0138] In some embodiments, one or more reference chips are mapped to one or more subcarriers, and the one or more subcarriers are individually OFDM modulated to generate an output signal.

[0139] As shown in Figure 16, when transmitting the synchronization information part, one or more reference chips of the synchronization information part are mapped to one or more subcarriers. The subcarriers carrying the reference chips of the synchronization information part are individually modulated by orthogonal frequency division multiplexing (OFDM) to generate an N-point output signal.

[0140] In the presence of non-A-IOT signals, other subcarriers (i.e., non-A-IOT signal subcarriers) are individually OFDM modulated, and the cyclic prefix length is increased after OFDM modulation. The output is still an N-point signal, and the two parts are finally superimposed to generate the final complete output signal.

[0141] In the above embodiments, on the one hand, no CP is needed when transmitting A-IoT signals, which avoids the impact of CP on A-IoT signals and simplifies the transmission of A-IoT signals. On the other hand, when the carrier transmitted through the Physical Reader to Device Channel (PRDCH) is configured as an extended cyclic prefix, application method five can make full use of the extended cyclic prefix and improve resource utilization. The extended cyclic prefix is ​​longer than the cyclic prefix and occupies more space, therefore it needs to be fully utilized.

[0142] In some embodiments, the synchronization information portion includes a first portion and a second portion, with the second portion following the first portion; the first portion is used to indicate a basic duration; and the second portion is used to indicate the relationship between the chip length of the first chip and the basic duration.

[0143] It should be noted that the base duration refers to a fixed duration. In one example, the base duration is the same duration.

[0144] In some embodiments, the synchronization information portion may include two parts: a first part and a second part. The first part is used to indicate the basic duration, and the second part is used to indicate the relationship between the chip length of the first chip and the basic duration.

[0145] In some embodiments, the first portion includes: one or more second chips; the chip length of the one or more second chips is used to indicate a basic duration; the level of the first second chip of the first portion is opposite to the level of the second signal; the second signal refers to the signal of the start indication information portion in the preamble.

[0146] It should be noted that the second chip refers to the chip contained in the first part.

[0147] In some embodiments, the first portion includes at least one second chip, and the chip length of the one or more second chips is used to indicate a basic duration. For example, when the first portion includes one second chip, the length of that one second chip can be used to indicate a basic duration; when the first portion includes multiple second chips, the sum of the lengths of the multiple second chips, i.e., the length of the first portion, can be used to indicate a basic duration; when the first portion includes multiple second chips, the length of each second chip can be the same as the basic duration, and the length of one second chip can be used to indicate one basic duration. That is, multiple second chips in the first portion can be used to indicate multiple basic durations. The number of basic durations indicated by the chip length of the second chip can also be determined through other correspondences, and this application does not make any special limitations on this.

[0148] In some embodiments, the level of the first second chip in the first portion is opposite to the signal of the start indication information portion in the preamble.

[0149] In the above embodiments, the level of the first second chip in the first part is opposite to the level of the signal in the start indication information part. This can avoid misjudging the second chip in the first part as the start indication information part, improve the accuracy of the chip length in the first part, and thus improve the accuracy of the relationship between the determined chip length and the basic duration.

[0150] In some embodiments, the second portion includes: one or more third chips; the second portion includes a first partition, a second partition, and an end indication area; the level of the first third chip in the first partition is opposite to the level of the last second chip in the first portion, and the level of the third chip in the second partition is opposite to the level of the third chip in the first partition.

[0151] It should be noted that the third chip refers to the chip contained in the second part.

[0152] In some embodiments, the second part includes at least a first partition, a second partition, and an end indicator area.

[0153] For example, as shown in Figures 18A to 18D, the first part (P1) includes one second chip, the length of which corresponds to the basic duration. This second chip is high-level to distinguish it from the low-level signal in the start indication information portion of the preamble. The second part (P2) follows the first part, with the first partition of the second part being low-level and the second partition being high-level.

[0154] In the above embodiments, the level of the first third chip in the first partition is opposite to the level of the last second chip in the first part, and the level of the third chip in the second partition is opposite to the level of the third chip in the first partition. This can avoid misjudging the third chip in the first partition, the third chip in the second partition, and the second chip in the first part, and improve the accuracy of the relationship between the determined chip length and the basic duration.

[0155] In some embodiments, the ratio of the first chip length to the second chip length is used to indicate the relationship between the chip length of the first chip and the basic duration; the first chip length is less than the second chip length; the first chip length is the length of the first partition; and the second chip length is the length of the second partition.

[0156] As shown in Figures 18A to 18D, the length of the first partition of the second part is less than or equal to the length of the second partition of the second part. The ratio of the first partition to the second partition of the second part is used to represent the correspondence between the chip length and the basic duration of the first chip. For example, in Figure 18A, the second partition of the second part is approximately three times the length of the first partition. Therefore, the established correspondence can indicate that the chip length of the first chip is 2^3 basic durations, or 3 basic durations, etc. It is understood that the established correspondence can be that the second partition of the second part is approximately three times the length of the first partition to represent the chip length of the first chip is 2^3 basic durations, or it can be that the second partition of the second part is approximately three times the length of the first partition to represent the chip length of the first chip is 3 basic durations. The ratio of the chip length to the basic duration represented by the ratio of the first partition to the second partition of the second part depends on the established correspondence. In some embodiments, the established correspondence may differ from the above example. For example, the second partition of the second part may be approximately three times the length of the first partition to represent the chip length of the PRDCH is 3^3 basic durations, etc. This application does not impose any special limitations on this. The end indication area of ​​the second part shown in Figures 18A and 18D is entirely low-level and its length is equal to the basic duration, which facilitates terminal detection and differentiation from the first chip sent subsequently.

[0157] In some embodiments, in the example corresponding to FIG18A, the end indication area can be replaced with the structure shown in FIG18B or FIG18C. The structure shown in FIG18B includes two third chips. The first third chip is low-level to distinguish it from the high-level portion of the preceding second partition, and the other third chip is high-level. The total length of the two third chips is equal to the basic duration, allowing the terminal to detect and distinguish them from the subsequently transmitted first chip. The structure shown in FIG18C also includes two chips. The levels of the first and second third chips are the same as those shown in FIG18B, except that the total length of these two third chips may not be equal to the basic duration. The device can determine the length of the second third chip from the first third chip. The above examples allow the total length of the two third chips to be less than the basic duration, thereby reducing resource overhead in this part. FIG18D also includes only one low-level third chip, but the length of this third chip is equal to the length of the low-level portion in the second partition, rather than the basic duration. Thus, the device can determine the length of the end indication area from the length of the low level in the second part.

[0158] In some embodiments, the first chip length and the second chip length are the same; the first chip length is the length of the first partition; and the second chip length is the length of the second partition.

[0159] As shown in Figures 19A to 19D, the length of the first partition in the second part (P2) is the same as the length of the second partition.

[0160] In some embodiments, the level of the third chip in the end indicator area is opposite to the level of the last third chip in the second partition.

[0161] As shown in Figures 19A and 19D, when the end indicator area contains a third chip, the level of the third chip in the end indicator area is opposite to the level of the last third chip in the second partition. In Figure 19A, if the second partition contains only one third chip (low level), then the level of the third chip in the end indicator area is high; in Figure 19D, if the second partition contains only one third chip (high level), then the level of the third chip in the end indicator area is low.

[0162] In some embodiments, when the end indication area contains multiple third chips, the level of the first third chip in the end indication area is opposite to the level of the last third chip in the second partition.

[0163] As shown in Figures 19B and 19C, if the second partition contains only one third chip at a low level, then the level of the first third chip in the end indicator area is high.

[0164] In the above embodiments, the level of the third chip in the end indication area is opposite to the level of the last third chip in the second partition, which can avoid misjudging the end indication area as the second partition and improve the accuracy of the relationship between the determined chip length and the basic duration.

[0165] In some embodiments, the length of the third chip is the same as the basic duration or the same as the length of the first chip; the length of the third chip is the total chip length of the end indication area.

[0166] As shown in Figures 19A and 19B, the total chip length of the end indicator area in the second part can be the same as the basic duration. As shown in Figure 19D, the total chip length of the end indicator area in the second part can be the same as the length of the first partition.

[0167] In some embodiments, the end indication area includes K third chips; where K is an even number; the level of the first third chip is opposite to the level of the third chip in the second partition; and the level of the last third chip is the same as the level of the third chip in the second partition.

[0168] In some embodiments, when the second partition includes only one third chip and the end indication area includes an even number of third chips, the level of the first third chip in the end indication area is opposite to the level of the third chip in the second partition, and the level of the last third chip in the end indication area is the same as the level of the third chip in the second partition; when the second partition includes multiple third chips and the end indication area includes an even number of third chips, the level of the first third chip in the end indication area is opposite to the level of the last third chip in the second partition, and the level of the last third chip in the end indication area is the same as the level of the last third chip in the second partition.

[0169] Taking the end indicator area as an example, which includes two third chips, as shown in Figures 19B and 19C, the second partition includes only one third chip, while the end indicator area includes two third chips. The third chip in the second partition is at a low level. The level of the first third chip in the end indicator area is opposite to that of the third chip in the second partition, which is a high level. The level of the last third chip in the end indicator area is the same as that of the third chip in the second partition, which is a low level.

[0170] In some embodiments, when the end indication area includes an even number of third chips, the length of the third chips may be the same as or different from the basic duration; the length of the third chips is the total chip length of the end indication area.

[0171] Taking the end indication area as an example, as shown in Figure 19B, the end indication area includes two third chips, and the total chip length of the end indication area can be the same as the basic duration; as shown in Figure 19C, the end indication area includes two third chips, and the total chip length of the end indication area can be different from the basic duration.

[0172] In some embodiments, the second part includes M fourth chips, where M is an even number; the chip length of the fourth chip is the same as the basic duration; the bit value is used to indicate the relationship between the chip length of the first chip and the basic duration; the bit value is the value that encodes the bit information of the M fourth chips.

[0173] In some embodiments, the first portion includes at least one second chip, the length of which is equal to the basic duration. The second portion follows the second chip included in the first portion and includes an even number of fourth chips with a length equal to the basic duration, the plurality of fourth chips indicating the relationship between the chip length of the first chip and the basic duration indicated by the first portion.

[0174] Taking the first part, which contains two second chips, as an example, as shown in Figure 20, the first part contains two second chips, each with a length corresponding to the basic duration. The first second chip is high-level to distinguish it from the low-level signal in the start indication information part of the preamble. The second part contains four fourth chips with a length equal to the basic duration. These four fourth chips carry 2 bits of information through Manchester encoding. The value of these 2 bits represents the relationship between the chip length of the first chip and the basic duration.

[0175] In the above embodiments, the bit value obtained by encoding the fourth chip indicates the relationship between the chip length of the first chip and the basic duration, which improves the convenience and efficiency of determining the chip length of the first chip.

[0176] In some embodiments, different bit values ​​indicate different relationships between the chip length of the first chip and the basic duration.

[0177] In some embodiments, if the bit values ​​carried by the fourth chip in the second part are different, the relationship between the chip length and the basic duration of the corresponding indicated first chip will be different. The bit values ​​carried by the fourth chip in the second part can be 00, 01, 10, 11, etc.

[0178] For example, in the example given in Figure 20, the four fourth chips in the second part represent 0 and 1 bits. Therefore, the chip length of the first chip can be indicated as 2^2 basic durations or 2 basic durations, etc., according to the set correspondence.

[0179] It is understood that in the above example, the established correspondence includes the relationship between the chip length and the basic duration represented by different bit values ​​of the four chips in the second part. For example, if the four chips in the second part represent 00 bits, the chip length of the first chip can be determined as 1 basic duration; if the four chips in the second part represent 10 bits, the chip length of the first chip can be determined as 3 basic durations; if the four chips in the second part represent 11 bits, the chip length of the first chip can be determined as 4 basic durations, and so on. In some embodiments, the established correspondence may differ from the above example, and this application does not impose any special limitations on it.

[0180] In some embodiments, where the synchronization information portion includes a first portion and a second portion, the influence of the loop prefix length on the detection of the synchronization information portion can be avoided in the following ways.

[0181] In some embodiments, the first part and the second part begin mapping at a position after the cyclic prefix length.

[0182] In some embodiments, the first part and the second part may begin mapping at a position after the cyclic prefix length, and the synchronization information part does not cross the boundary of the first symbol. The level of the first second chip of the first part is opposite to the level of the signal of the start indication information part in the preamble, so as to avoid the device misinterpreting a part of the first part as a part of the start indication information part.

[0183] In some embodiments, the first part and the second part are mapped at the beginning of the loop prefix length; the output signal of the synchronization information part does not include the first signal; the first signal refers to the signal of the loop prefix part.

[0184] In some embodiments, the first and second portions are mapped starting at the beginning of the cyclic prefix length, and the synchronization information portion does not cross the boundary of the first symbol. When transmitting the synchronization information portion, the output signal of the synchronization information portion does not include the signal of the cyclic prefix portion, thus avoiding the influence of the cyclic prefix length on the detection of the synchronization information portion.

[0185] In some embodiments, the first part and the second part begin mapping at a position after the cyclic prefix length, and the first second chip of the first part has the same level as the last third chip of the end indicator area of ​​the second part.

[0186] In some embodiments, after the first second chip of the first part is truncated by the length of the cyclic prefix from the start position of the first part, the first part and the second part are mapped from the start position of the cyclic prefix length within a first time unit. The level of the last third chip in the end indication area of ​​the second part is the same as the level of the first second chip of the first part, so that after adding the synchronization information part, the first second chip of the first part can be restored to the basic duration, as shown in Figure 21. The above embodiments can avoid the reference chip part in the synchronization information part being misjudged as part of the cyclic prefix length, and avoid the influence of the cyclic prefix length on the detection of the synchronization information part.

[0187] In some embodiments, the start information portion is used to indicate the basic duration; the synchronization information portion indicates the relationship between the chip length of the first chip and the basic duration.

[0188] It should be noted that the starting information section refers to the starting indication information section in the preamble.

[0189] In some embodiments, the synchronization information portion may be mapped from a position after the start information portion, so that the start information portion indicates the basic duration and the synchronization information portion indicates the relationship between the chip length of the first chip and the basic duration.

[0190] In some embodiments, when transmitting data and / or control information, the following methods can be used to avoid the influence of the cyclic prefix length on the detection of data and / or control information.

[0191] In the above embodiments, the relationship between the chip length and the basic duration of the first chip is indicated by the synchronization information section, which improves the convenience and efficiency of determining the chip length of the first chip.

[0192] In some embodiments, the first device transmits data and / or control information in one or more first time units; wherein the first time unit includes one or more first chips; and the synchronization information portion in the preamble indicates the length of the first chip.

[0193] It should be noted that the preamble can be sent / received from the reader to the device, or from the device to the reader. It should also be noted that a reader can also be called a reader; the two are equivalent or interchangeable.

[0194] It should also be noted that the first device can also transmit control information and / or data information between the device and the reader. For example, when the first device is a reader, it sends frames to the terminal device, and the frames may carry control information such as resource configuration, resource indication, and resource scheduling. When the first device is a terminal device, it sends frames to the reader, and the frames may transmit data information of the terminal device, such as the terminal device's ambient temperature, humidity, location information, and cargo information.

[0195] It should also be noted that the first time unit is a time unit consisting of the cyclic prefix length (CP) and the first symbol. The first symbol can be an orthogonal frequency division multiplexing (OFDM) symbol, and the cyclic prefix length refers to a complete cyclic prefix in the first symbol.

[0196] In some embodiments, the length of the first chip can be indicated by the synchronization information portion in the preamble, thereby determining the chip length of data and / or control information based on the length of the first chip.

[0197] In some embodiments, the last first chip is a redundant chip; the other first chips are used to carry...

[0198] Data and / or control information; the level of the first chip is the same as the level of the last chip.

[0199] In some embodiments, a redundant chip may be added at the end of a first time unit, the level of which is the same as the level of the first chip in the first time unit.

[0200] Taking a first time unit containing three first chips as an example, assuming the data and / or control information contains one bit 1, it is mapped to {chip 0, chip 1} according to Manchester encoding. During actual data and / or control information transmission, chip 0 is mapped to the first first chip in the first time unit, chip 1 is mapped to the second first chip, and then a chip 0 is added. Taking a first time unit containing five first chips as an example, assuming the data and / or control information contains two bits 0 and 1, it is mapped to {chip 1, chip 0, chip 0, chip 1} according to Manchester encoding. During actual transmission, {chip 1, chip 0, chip 0, chip 1} are mapped to the first to fourth chips in the first time unit, and then a chip 1 is added at the end. This method ensures that the level of the added cyclic prefix length is the same as the level of the first chip in the first symbol, thus avoiding the influence of the cyclic prefix length on the decoding of data and / or control information.

[0201] In some embodiments, the last T first chips are redundant chips; the other first chips are used to carry data and / or control information; T is a positive integer greater than or equal to 1; the first T first chips have the same level as the last T first chips.

[0202] In some embodiments, during the actual transmission of data and / or control information, CEIL(L / C) redundant chips are added at the end of a first time unit. The level of these redundant chips is the same as the level of the CEIL(L / C) chips starting from the first symbol. When performing OFDM modulation on the data and / or control information, assuming the original bit sequence of the data and control information is y(n), the first M values ​​of y(n) are copied to the end of y(n) to obtain an extended sequence y(n). The M values ​​represent the number of bits corresponding to the redundant chips. Then, y(n) is OFDM modulated according to the process in Figure 17. Here, L represents the length of the cyclic prefix, C represents the length of a reference chip in the synchronization information section, and CEIL() represents rounding up. This method ensures that the level of the added cyclic prefix is ​​the same as the level of the first chip in the first symbol, thereby avoiding the influence of the cyclic prefix length on the decoding of data and / or control information.

[0203] The following section, using an IoT scenario and R2D transmission frames as an example, elaborates on the communication method provided in the embodiments of this application.

[0204] Referring to Figure 8, the structure of an R2D transmission frame includes the following parts:

[0205] Preamble: Used to indicate the start position in the time domain of R2D transmission, and / or for A-IoT devices to obtain time synchronization or frequency synchronization information.

[0206] The preamble may include a start indication information (SI) portion and a synchronization information (CAP) portion. It should be noted that the preamble portion may also include other parts, which are not limited in the embodiments of this application.

[0207] The start indication information section is used to indicate the time-domain start position of the R2D transmission. The synchronization information section is used by A-IoT devices to obtain time synchronization and / or frequency synchronization, and / or to indicate chip length or chip duration; wherein, frequency synchronization includes, for example, sampling frequency synchronization and carrier frequency synchronization.

[0208] R2D transmission frames may include data information and / or control information, including data information and / or control information sent by the reader to the device.

[0209] In some embodiments, data information and control information can be carried through the same channel, such as through a PRDCH, and the chip length of the data information and control information can be used as the chip length of the PRDCH.

[0210] In some embodiments, the synchronization information portion may include at least one reference chip, which can be used to indicate the chip length of the PRDCH. The reference chips can be identified by two adjacent edges, and the chip length of the one or more reference chips included in the synchronization information portion is the same as the chip length of the PRDCH. It is understood that including multiple reference chips in the synchronization information portion can improve the accuracy of detecting the chip length of the PRDCH.

[0211] In some embodiments, the PRDCH can employ Manchester encoding. In Manchester encoding, one bit is represented by two chips, either {chip 1, chip 0} or {chip 0, chip 1}, where the length of chip 0 / 1 is the same as the length of the reference chip. In this case, the reference chip in the CAP can be one or more {chip 1, chip 0} or {chip 0, chip 1}. An example is shown in Figure 10A, where the CAP part includes four reference chips: chip 1, chip 0, chip 1, and chip 0. Another example is shown in Figure 10B, where the CAP part includes four reference chips: chip 1, chip 0, chip 0, and chip 1.

[0212] In some embodiments, the CP (corresponding to the cyclic prefix length in the above embodiments) lengths of Orthogonal Frequency Division Multiplexing (OFDM) symbols (corresponding to the first symbol in the above embodiments) under different indices of a subframe in New Radio (NR) and Long Term Evolution (LTE) systems are different. For example, a subframe contains 14 × 2^μ OFDM symbols with conventional CPs, where μ = 0, 1, 2, ..., is the subcarrier spacing index; for the LTE system, μ = 0. The CP lengths (in time units (Ts)) of OFDM#0 and OFDM#7 × 2^μ in a subframe are the same (denoted as the first CP length), and the CP lengths of the remaining OFDM symbols are the same (denoted as the second CP length), and the first CP length is greater than the second CP length. Taking a 15kHz subcarrier (μ=0) interval as an example, the length of the first CP is approximately 5.21 microseconds (=160 / (2048×15×10^3)), the length of the second CP is approximately 4.69 microseconds (=144 / (2048×15×10^3)); the duration of OFDM#0 and OFDM#7 is 71.9 microseconds (=(2048+160) / (2048×15×10^3)), and the duration of the remaining 12 OFDM symbols is approximately 71.4 microseconds (=(2048+144) / (2048×15×10^3)).

[0213] It should be understood that since the CP length of different OFDM symbols may be different, different CP lengths may affect the length of the reference chip, and thus affect the accuracy of the chip length of the detected PRDCH.

[0214] In some embodiments, one or more of the following methods can be used to avoid the influence of CPs of different lengths on the reference chip length:

[0215] Method 1: CAP is mapped starting after the CP of an OFDM symbol (corresponding to the position after the cyclic prefix in the above embodiments). (That is, the first reference chip implemented by signal processing for CAP is transmitted starting after the CP of an OFDM symbol, or the sampling point of the first reference chip of CAP is mapped to after the CP of an OFDM symbol). In other words, the position of CAP does not include the CP, and it is guaranteed that CAP includes an even number of reference chips, and the level of the last reference chip is the same as the level of SI. It can be understood that when the level of the last reference chip of CAP is the same as the level of SI, the level of SI is the same as the level of the CP part before the first reference chip of CAP (corresponding to the cyclic prefix part in the above embodiments). Therefore, during level detection, CP can be treated as part of SI without generating additional edges, reducing the possibility of misjudging CP as part of a reference chip due to additional edges. Here, "after CP" can be the end position of CP or the position after the end position; this application does not make any special limitations on this.

[0216] For example, as shown in Figure 11, the CAP contains two reference chips located within an OFDM symbol (first symbol). The first chip is mapped starting after the CP, and the second chip is low, with the same level as the CP signal preceding the first chip. It is important to emphasize that this method is suitable for cases where the CP signal includes only one level; that is, the chip length of the CP cannot be too short, resulting in the CP signal including different levels.

[0217] In the above embodiments, CP is not included in CAP, which can avoid the impact of CP of different lengths on CAP reception.

[0218] Method 2: CAP is mapped from the middle of the CP of an OFDM symbol (between the start and end positions of the cyclic prefix in the above embodiment), and ensures that CAP includes an odd number of reference chips, and that the level of the last reference chip in CAP is the same as the level of the SI before CAP.

[0219] For example, as shown in Figure 12, the CAP contains one reference chip located within an OFDM symbol (first symbol). This chip is mapped starting from the middle of the CP location and occupies the duration of one OFDM symbol. A low level follows the CAP, with a length at least the minimum easily detectable length, thus ensuring that the level after the CAP is the same as the level of the SI before the first reference chip of the CAP. It is understood that the middle of the CP location can be one-third or two-thirds of the way from the start to the end of the CP, and does not solely refer to the halfway point from the start to the end of the CP.

[0220] Method 3: CAP starts mapping from the CP of an OFDM symbol, ensuring that CAP includes an odd number of reference chips, and the length of the first reference chip in CAP is shorter than the length of the other reference chips in an OFDM symbol by L, where L is the CP length. Starting from the second reference chip, the voltage level of each reference chip is opposite to that of the previous reference chip. CAP occupies one OFDM symbol, that is, the sum of the lengths of all reference chips in CAP is the same as the chip length of the OFDM symbol.

[0221] For example, as shown in Figure 13, the CAP contains three reference chips, all located within the same OFDM symbol (first symbol). Starting from the second reference chip, the voltage level of each chip is opposite to that of the previous reference chip. The length of the first reference chip is L shorter than the lengths of the other two reference chips. Mapping begins after the CP. Since the voltage level of the last chip in the CAP is the same as that of the first chip, the CP is added before the first reference chip. The combined chip length is the same as the length of the other chips, so the CP can be used to transmit useful information. In the above embodiment, it is suitable for cases where an OFDM symbol contains an odd number of chips, thus avoiding the impact of the CP on the terminal's reception of the CAP and improving resource utilization.

[0222] Method 4: Only one CAP reference chip is contained within an OFDM symbol. The CAP is mapped starting after the CP of an OFDM symbol. For example, as shown in Figure 14, Figure 14 contains two OFDM symbols (the first symbol). The CAP contains two reference chips, located within the two different OFDM symbols. Each reference chip is mapped starting after the CP of an OFDM symbol. After adding the CP, the length of the reference chip detected by the terminal is equal to the length of a complete OFDM symbol containing the CP (corresponding to the first time unit in the above embodiment). It can be understood that only one CAP reference chip is contained within an OFDM symbol, and A OFDM symbols contain a total of A CAP reference chips, where A is a positive integer. In the above embodiment, the CP can be used to transmit valid information, improving resource utilization.

[0223] Method 5: CAP mapping begins from the start position of the CP (corresponding to the start position of the cyclic prefix in the above embodiments) in a complete OFDM symbol (first time unit) containing the CP. CAP can start mapping from the start position of the CP. The sum of the chip lengths of one or more reference chips in CAP is the same as the length of the complete OFDM symbol containing the CP, and there is no limit to the number of reference chips in CAP. The level of the first reference chip in CAP is opposite to the level of the start indication information (SI) signal in the preamble to reduce the possibility of misjudging a reference chip as part of the start indication information (SI) in the preamble. An example is shown in Figure 15.

[0224] As shown in Figure 16, when transmitting CAP, the subcarrier carrying CAP is individually OFDM modulated, generating an N-point output signal. In the presence of non-A-IoT signals, other subcarriers (i.e., non-A-IoT signal subcarriers) are individually OFDM modulated, and a CP is added after OFDM modulation, still resulting in an N-point signal output. Finally, the two parts are superimposed to generate the final complete output signal. In the above embodiment, on the one hand, no CP needs to be added when transmitting A-IoT signals, avoiding the influence of CP on A-IoT signals and simplifying A-IoT signal transmission; on the other hand, when the carrier transmitted by PRDCH is configured with extended CP, the extended CP occupies more space. Application method five can fully utilize the extended CP, improving resource utilization.

[0225] It should be noted that without multiplexing, and without the superposition of non-A-IOT signals, OFDM symbol modulation without CP can be used directly.

[0226] Method 6: The first CEIL(L / C) chips and the last CEIL(L / C) chips of the CAP are the same. When generating the CAP, first, the CAP is mapped from the Pth sampling point to the CP, and then the last P sampling points of the CAP are mapped to the CP position of the OFDM symbol. Here, L represents the length of the CP, C represents the length of the CAP reference chip, and CEIL(·) represents rounding up. In the specific mapping process, assuming the sampling point sequence corresponding to the CAP is x(n), after cutting off the CP at sampling point x(n), the first P sampling points of x(n) are cyclically shifted to the end, x(n) = x(mod(n+L,N)), where mod(·) represents the modulo operation. Then, an N'-point DFT (Discrete Fourier Transform) is performed on x(n), mapping it to X subcarriers. Finally, a K-point IFFT is performed and the CP is added, as shown in Figure 17. In the above embodiments, when the chip lengths used in CAP and PRDCH are relatively short, the chip lengths are close to those of CP, which can avoid the influence of CP on CAP detection.

[0227] In some embodiments, when sending PRDCH, it is also necessary to avoid the influence of CP on PRDCH detection. To achieve this, one of the following methods can be adopted:

[0228] Method 1: What is the relationship between the level of the redundant chip added at the end of an OFDM symbol and the level of the subsequent added CP? The level of the redundant chip is the same as the level of the first chip in an OFDM symbol. For example, if an OFDM symbol contains 3 chips, assuming the PRDCH contains one bit 1, it is mapped to {chip 0, chip 1} according to Manchester encoding. During actual transmission, chip 0 is mapped to the first chip in an OFDM symbol, chip 1 is mapped to the second chip, and then chip 0 is added. For example, if an OFDM symbol contains 5 chips, assuming the PRDCH contains two bits 0 and 1, it is mapped to {chip 1, chip 0, chip 0, chip 1} according to Manchester encoding. During actual transmission, {chip 1, chip 0, chip 0, chip 1} are mapped to the 1st to 4th chips in the OFDM symbol, and then chip 1 is added at the end. In this way, the level of the added CP can be guaranteed to be the same as the level of the first chip in the OFDM symbol, thereby avoiding the impact of CP on PRDCH decoding.

[0229] Method 2: When actually transmitting the PRDCH, CEIL(L / C) redundant chips are added to the end of an OFDM symbol. The level of these redundant chips is the same as the level of the first CEIL(L / C) chips in the OFDM symbol. When performing OFDM modulation on the PRDCH, assuming the original bit sequence of the PRDCH is y(n), the first M values ​​of y(n) are copied to the end of y(n) to obtain the extended sequence y(n). The M values ​​are the number of bits corresponding to the redundant chips. Then, OFDM modulation of the PRDCH is performed according to the process shown in Figure 17. This method ensures that the level of the added CP is the same as the level of the first chip in the OFDM symbol, thus avoiding the influence of CP on PRDCH decoding.

[0230] In some embodiments, CAP includes two parts: P1 (corresponding to the first part in the above embodiments) and P2 (corresponding to the second part in the above embodiments). P1 is used to indicate the basic duration, and P2 is used to indicate the correspondence between the chip length of PRDCH and the basic duration indicated by P1.

[0231] In some embodiments, P1 contains at least one chip (corresponding to the second chip in the above embodiments), and the length of the chip is equal to the basic duration. P2 is located after the chip contained in P1. P2 contains at least a first partition, a second partition, and an end indicator area. The level of the first partition is opposite to the level of the last chip in P1, and the level of the second partition is opposite to the level of the first partition. The ratio of the first partition to the second partition indicates the relationship between the PRDCH chip length and the basic duration indicated by P1.

[0232] For example, as shown in Figure 18A, P1 contains one chip, the length of which corresponds to the basic duration. This chip is high-level to distinguish it from the low level of SI. P2 follows P1. The first partition of P2 is low-level, and the second partition of P2 is high-level. The length of the first partition of P2 is less than or equal to the length of the second partition of P2. The ratio of the first and second partitions of P2 is used to represent the correspondence between the chip length and the basic duration of the PRDCH. For example, in Figure 18A, the second partition of P2 is approximately three times the length of the first partition. Therefore, the chip length of the PRDCH can be indicated by the set correspondence as 2^3 basic durations, or 3 basic durations, etc. It is understood that the established correspondence can be that the second partition of P2 is approximately three times the first partition to indicate that the chip length of the PRDCH is 2^3 basic durations, or it can be that the second partition of P2 is approximately three times the first partition to indicate that the chip length of the PRDCH is 3 basic durations. The ratio of the chip length to the basic duration represented by the ratio of the first and second partitions of P2 depends on the established correspondence. In some embodiments, the established correspondence may differ from the above example. For example, the second partition of P2 may be approximately three times the first partition to indicate that the chip length of the PRDCH is 3^3 basic durations, etc. This application does not impose any special limitations on this. The P2 end indicator shown in Figure 18A is all low level, and its length is equal to the basic duration, which facilitates the terminal to detect and distinguish it from the PRDCH transmitted subsequently.

[0233] In some embodiments, in the example corresponding to FIG18A, the end indication area can be replaced with the structure shown in FIG18B or FIG18C. In the structure shown in FIG18B, the end indication area contains two chips (corresponding to the third chip in the above embodiments). The first chip is low-level to distinguish it from the previous high-level portion of P2, and the other chip is high-level. The total length of the two chips is equal to the basic duration, so that the terminal can detect and distinguish it from the subsequently transmitted PRDCH. In the structure shown in FIG18C, the end indication area also contains two chips. The levels of the first and second chips are the same as those shown in FIG18B. The difference is that the total length of these two chips may not be equal to the basic duration. The first device can determine the length of the second chip through the first chip. The above examples allow the total length of the two chips to be less than the basic duration, thereby reducing the resource overhead in this part. FIG18D also contains only one low-level chip, but the duration of this chip is equal to the duration of the low-level portion of P2 instead of the basic duration. Thus, the device can determine the duration of the end indication area through the duration of the low level of P2.

[0234] In some embodiments, P1 may contain two chips. The first chip is high to distinguish it from the low level of SI, and the second chip is both high and low. The length of both chips is the basic duration. Increasing the number of chips in P1 helps the device obtain the basic duration more accurately. Because the last chip of P1 is low, the first partition of P2 is high, and the second partition is low. In this example, the duration of the first partition of P2 is approximately equal to the duration of the second partition. The chip length of PRDCH can be indicated to be equal to the basic duration, or two basic durations, etc., according to the set correspondence. The ratio of the first and second partitions of P2 shown in Figures 18A to 18D also applies to the P1 structure given in Figures 19A to 19D, and vice versa. It should be emphasized that the ratio of the first and second partitions of P2 given in Figures 18A to 18D and Figures 19A to 19D are examples. Those skilled in the art can easily deduce other feasible ratios, which are not exhaustively listed here, but are also within the scope of protection of this application. The design method of the P2 end indicator in the structure shown in Figures 19A to 19D is similar to the example given in Figures 18A to 18D, the difference being that the chip level is different from the example in Figures 18A to 18D.

[0235] In some embodiments, P1 contains at least one chip, the length of which is equal to the basic duration. P2 follows the chip contained in P1 and contains multiple chips of the basic duration, the multiple chips indicating the relationship between the PRDCH chip length and the basic duration indicated by P1. For example, as shown in FIG20, P1 contains two chips, each chip's length corresponding to the basic duration, the first chip being high to distinguish it from the low level of SI. P2 contains four chips of the basic duration (corresponding to the fourth chip in the above embodiments), these four chips carrying 2 bits of information via Manchester encoding, the value of which represents the relationship between the PRDCH chip length and the basic duration. For example, in the example given in FIG20, the four chips of P2 represent 0 and 1 bits, which can indicate that the PRDCH chip length is 2^2 basic durations, or 2 basic durations, etc., according to the set correspondence. The two bits indicated by P2 can be other bit values, such as 00, 10, and 11. Each bit value can correspond to a different relationship between the PRDCH chip length and the basic duration. It is understood that in the above example, the established correspondence includes the relationship between the chip length and the basic duration represented by different bit values ​​of the four chips of P2. For example, when the four chips of P2 represent 00 bits, the chip length indicating the PRDCH can be 1 basic duration; when the four chips of P2 represent 10 bits, the chip length indicating the PRDCH can be 3 basic durations; when the four chips of P2 represent 11 bits, the chip length indicating the PRDCH can be 4 basic durations, and so on. In some embodiments, the established correspondence may differ from the above example, and this application does not impose any special limitations on it.

[0236] In some embodiments, the impact of CP on CAP detection can be avoided by one or more of the following methods:

[0237] Method 1: CAP starts mapping after CP. CAP does not cross the boundary of OFDM symbol. The last chip of the CAP end indicator is low to ensure that the signal level of the CP part is the same as that of SI, avoiding the introduction of additional rising or falling edges.

[0238] Method 2: CAP starts mapping from before CP. CAP does not cross the boundary of OFDM symbols, and CP is not added when sending CAP.

[0239] Method 3: After the first chip of CAP is truncated to the part corresponding to the length of CP, mapping begins from after CP. The level of the last chip in the CAP end indicator area is the same as the level of the first chip of CAP, thus ensuring that the first chip is restored to the basic duration after adding CAP, as shown in Figure 21.

[0240] Figure 22 is a schematic diagram of the structure of the first device provided in an embodiment of this application. The first device includes:

[0241] The communication unit 2210 is configured to transmit a preamble; the preamble includes a synchronization information portion, which is used for at least one of the following: obtaining time synchronization, obtaining frequency synchronization, and indicating the chip length of the first chip;

[0242] The first chip is a chip used to transmit control information and / or data information.

[0243] In some embodiments, the first position where the synchronization information portion is located is mapped based on a first time unit; the first time unit includes: a cyclic prefix length and a first symbol.

[0244] In some embodiments, the synchronization information portion includes one or more reference chips, the one or more reference chips being used to indicate the chip length of the first chip.

[0245] In some embodiments, the chip length of the reference chip is the same as the chip length of the first chip.

[0246] In some embodiments, one or more of the reference chips are mapped starting from a first position in the first time unit;

[0247] The first position includes at least one of the following:

[0248] The position following the length of the cyclic prefix;

[0249] The starting position of the cyclic prefix length;

[0250] The length of the cyclic prefix is ​​between the start and end positions.

[0251] In some embodiments, the one or more reference chips are mapped within a first symbol; adjacent reference chips have opposite levels.

[0252] In some embodiments, when the first position is after the cyclic prefix length, the level of the first reference chip is opposite to the level of the first signal, the level of the last reference chip is the same as the level of the first signal, and the level of the first signal is the same as the level of the second signal.

[0253] Wherein, the first signal refers to the signal of the cyclic prefix portion; the second signal refers to the signal of the start indication information portion in the preamble.

[0254] In some embodiments, when the first position is between the start and end positions of the cyclic prefix length, the levels of the first and last reference chips are opposite to the level of the third signal, and the level of the last part of the synchronization information portion is the same as the level of the third signal.

[0255] The third signal refers to the signal of the cyclic prefix portion preceding the first position.

[0256] In some embodiments, when the first position is after the cyclic prefix length, the level of the first reference chip is the same as the level of the first signal; the sum of the chip length of the first reference chip and the cyclic prefix length is the same as the chip length of the other reference chips; the level of the last chip is the same as the level of the first reference chip.

[0257] The first signal refers to the signal in the cyclic prefix portion.

[0258] In some embodiments, the one or more reference chips are mapped within at least one first symbol; each reference chip is mapped starting from a position after the cyclic prefix length of a first symbol;

[0259] The length of each reference chip is the same as the length of a first symbol;

[0260] The level of each reference chip is the same as the level of the first signal and opposite to the level of the next first signal;

[0261] Wherein, the first signal refers to the signal of the cyclic prefix portion of the first symbol; the next first signal refers to the signal of the cyclic prefix portion of the next first symbol.

[0262] In some embodiments, when the first position is the starting position of the cyclic prefix length, the one or more reference chips occupy the first time unit, each of the reference chips has the same length, and the level of the first reference chip is opposite to the level of the second signal;

[0263] The second signal refers to the signal in the start indication information portion of the preamble.

[0264] In some embodiments, the one or more reference chips are mapped to one or more subcarriers, and the one or more subcarriers are individually OFDM modulated to generate an output signal.

[0265] In some embodiments, the one or more reference chips occupy the first time unit, and each reference chip has the same length.

[0266] When the first position is the starting position of the cyclic prefix length, the level of the first H reference chips is the same as the level of the last H chips.

[0267] Where H is the integer obtained by dividing the first length by the second length and then rounding up, and H is an integer greater than or equal to 1;

[0268] The first length is the length of the cyclic prefix;

[0269] The second length is the length of a reference chip.

[0270] In some embodiments, the one or more reference chips include: a first signal and a fifth signal;

[0271] The fifth signal is a signal mapped to the position after the cyclic prefix length after deleting P sampling points of the synchronization information part; where P is the number of sampling points corresponding to the first length; and P is a positive integer greater than or equal to 1.

[0272] The first signal is the signal in the fifth signal that corresponds to the last P sampling points.

[0273] In some embodiments, the synchronization information portion includes a first portion and a second portion, wherein the second portion is located after the first portion;

[0274] The first part is used to indicate the basic duration;

[0275] The second part is used to indicate the relationship between the chip length of the first chip and the basic duration.

[0276] In some embodiments, the first portion includes: one or more second chips;

[0277] The chip length of one or more of the second chips is used to indicate the basic duration;

[0278] The level of the first second chip in the first part is opposite to the level of the second signal;

[0279] The second signal refers to the signal in the start indication information portion of the preamble.

[0280] In some embodiments, the second portion includes: one or more third chips;

[0281] The second part includes a first partition, a second partition, and an end indicator area;

[0282] The level of the first third chip in the first partition is opposite to the level of the last second chip in the first part, and the level of the third chip in the second partition is opposite to the level of the third chip in the first partition.

[0283] In some embodiments, the ratio of the first chip length to the second chip length is used to indicate the relationship between the chip length of the first chip and the basic duration; the first chip length is less than the second chip length.

[0284] The length of the first chip is the length of the first partition;

[0285] The second chip length is the length of the second partition.

[0286] In some embodiments, the first chip length and the second chip length are the same;

[0287] The length of the first chip is the length of the first partition;

[0288] The second chip length is the length of the second partition.

[0289] In some embodiments, the level of the third chip in the end indication area is opposite to the level of the last third chip in the second partition.

[0290] In some embodiments, the length of the third chip is the same as the basic duration, or the same as the length of the first chip;

[0291] The length of the third chip is the total chip length of the end indicator area.

[0292] In some embodiments, the end indication area includes K third chips; where K is an even number;

[0293] The voltage level of the first third chip is opposite to the voltage level of the third chip of the second partition;

[0294] The level of the last third chip is the same as the level of the third chip in the second partition.

[0295] In some embodiments, the length of the third chip may be the same as or different from the basic duration;

[0296] The length of the third chip is the total chip length of the end indicator area.

[0297] In some embodiments, the second portion includes M fourth chips, where M is an even number;

[0298] The chip length of the fourth chip is the same as the basic duration;

[0299] The bit value is used to indicate the relationship between the chip length of the first chip and the basic duration; the bit value is the value that encodes the bit information of M of the fourth chips.

[0300] In some embodiments, different bit values ​​indicate different relationships between the chip length and the basic duration of the first chip.

[0301] In some embodiments, the first portion and the second portion begin mapping at a position after the cyclic prefix length.

[0302] In some embodiments, the first portion and the second portion are mapped at the beginning of the loop prefix length;

[0303] The output signal of the synchronization information section does not include the first signal;

[0304] The first signal refers to the signal in the cyclic prefix portion.

[0305] In some embodiments, the first portion and the second portion begin mapping at a position after the cyclic prefix length, and the first second chip of the first portion has the same level as the last third chip of the end indicator area of ​​the second portion.

[0306] In some embodiments, the start information portion is used to indicate the basic duration;

[0307] The synchronization information section indicates the relationship between the chip length of the first chip and the basic duration.

[0308] In some embodiments, the first device transmits data and / or control information in one or more first time units; wherein...

[0309] The first time unit includes one or more first chips;

[0310] The synchronization information portion of the preamble indicates the length of the first chip.

[0311] In some embodiments, the last first chip is a redundant chip; the other first chips are used to carry data and / or control information.

[0312] The voltage level of the first chip is the same as that of the last chip.

[0313] In some embodiments, the last T first chips are redundant chips; the other first chips are used to carry the data and / or control information; T is a positive integer greater than or equal to 1;

[0314] The first T chips have the same voltage level as the last T chips.

[0315] Those skilled in the art should understand that the description of the first device in the embodiments of this application can be understood with reference to the description of the communication method in the embodiments of this application.

[0316] Figure 23 is a schematic structural diagram of a first device 2300 provided in an embodiment of this application. This first device can be a first device. The first device 2300 shown in Figure 23 includes a processor 2310, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0317] In some embodiments of this application, as shown in FIG23, the first device 2300 may further include a memory 2320. The processor 2310 may call and run computer programs from the memory 2320 to implement the methods in the embodiments of this application.

[0318] The memory 2320 can be a separate device independent of the processor 2310, or it can be integrated into the processor 2310.

[0319] In some embodiments of this application, as shown in FIG23, the first device 2300 may further include a transceiver 2330, and the processor 2310 may control the transceiver 2330 to communicate with other devices. Specifically, it may send information or data to other devices or receive information or data sent by other devices.

[0320] The transceiver 2330 may include a transmitter and a receiver. The transceiver 2330 may further include an antenna, and the number of antennas may be one or more.

[0321] In some embodiments of this application, the first device 2300 may specifically be the first device of the embodiments of this application, and the first device 2300 may implement the corresponding processes implemented by the first device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0322] Figure 24 is a schematic structural diagram of a chip according to an embodiment of this application. The chip 2400 shown in Figure 24 includes a processor 2410, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0323] In some embodiments of this application, as shown in FIG24, chip 2400 may further include memory 2420. Processor 2410 may call and run computer programs from memory 2420 to implement the methods in the embodiments of this application.

[0324] The memory 2420 can be a separate device independent of the processor 2410, or it can be integrated into the processor 2410.

[0325] In some embodiments of this application, the chip 2400 may further include an input interface 2430. The processor 2410 can control the input interface 2430 to communicate with other devices or chips; specifically, it can acquire information or data sent by other devices or chips.

[0326] In some embodiments of this application, the chip 2400 may further include an output interface 2440. The processor 2410 can control the output interface 2440 to communicate with other devices or chips; specifically, it can output information or data to other devices or chips.

[0327] In some embodiments of this application, the chip can be applied to the first device in the embodiments of this application, and the chip can implement the corresponding processes implemented by the first device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0328] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0329] This application also provides a computer storage medium storing one or more programs, which can be executed by one or more processors to implement the methods in this application.

[0330] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0331] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0332] It should be understood that the above-described memory is exemplary and not a limiting description. For example, the memory in the embodiments of this application may also be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM), etc. That is to say, the memory in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0333] This application also provides a computer-readable storage medium for storing computer programs.

[0334] In some embodiments of this application, the computer-readable storage medium can be applied to the first device in the embodiments of this application, and the computer program causes the computer to execute the corresponding processes implemented by the first device in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0335] This application also provides a computer program product, including computer program instructions.

[0336] In some embodiments of this application, the computer program product can be applied to the first device in the embodiments of this application, and the computer program instructions cause the computer to execute the corresponding processes implemented by the first device in the various methods of the embodiments of this application. For the sake of brevity, they will not be described in detail here.

[0337] This application also provides a computer program.

[0338] In some embodiments of this application, the computer program can be applied to the first device in the embodiments of this application. When the computer program is run on a computer, it causes the computer to execute the corresponding processes implemented by the first device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0339] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0340] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0341] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0342] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0343] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0344] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0345] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of communication, the method comprising: transmitting, by a first device, a preamble; the preamble comprising a synchronization information part, the synchronization information part being used for at least one of: obtaining time synchronization, obtaining frequency synchronization, and indicating a chip length of a first chip; wherein the first chip is a chip used for transmitting control information and / or data information. 2.The method of claim 1, wherein: a first position where the synchronization information part is mapped is based on a first time unit; and the first time unit comprises a cyclic prefix length and a first symbol. 3.The method of claim 1 or 2, wherein: the synchronization information part comprises one or more reference chips, the one or more reference chips being used for indicating the chip length of the first chip. 4.The method of claim 3, wherein: a chip length of the reference chip is the same as a chip length of the first chip. 5.The method of claim 3 or 4, wherein: the one or more reference chips are mapped from a first position of the first time unit; and the first position comprises at least one of: a position after the cyclic prefix length; a start position of the cyclic prefix length; a position between a start position and an end position of the cyclic prefix length. 6.The method of claim 4 or 5, wherein: the one or more reference chips are mapped within one first symbol; and a level of an adjacent two reference chips are opposite. 7.The method of any one of claims 4 to 6, wherein: in a case that the first position is a position after the cyclic prefix length, a level of a first reference chip is opposite to a level of a first signal, a level of a last reference chip is the same as the level of the first signal, and the level of the first signal is the same as a level of a second signal; wherein the first signal refers to a signal of a cyclic prefix part; and the second signal refers to a signal of a start indication information part in the preamble. 8.The method of any one of claims 4 to 6, wherein: in a case that the first position is a position between a start position and an end position of the cyclic prefix length, a level of a first reference chip and a level of a last reference chip are opposite to a level of a third signal, and a level of a tail part of the synchronization information part is the same as the level of the third signal; wherein the third signal refers to a signal of a cyclic prefix part before the first position. 9.The method of any one of claims 4 to 6, wherein: in a case that the first position is a position after the cyclic prefix length, a level of a first reference chip is the same as a level of a first signal, a sum of a chip length of the first reference chip and a length of the cyclic prefix length is the same as chip lengths of other reference chips, and a level of a last chip is the same as the level of the first reference chip; wherein the first signal refers to a signal of a cyclic prefix part. 10.The method of claim 4 or 5, wherein: the one or more reference chips are mapped within at least one first symbol; and each of the reference chips is mapped from a position after a cyclic prefix length of a first symbol. Each of the reference chips has the same length as a first symbol; Each of the reference chips has the same level as a first signal and an opposite level as a next first signal; The first signal refers to a signal of a cyclic prefix part of the first symbol; the next first signal refers to a signal of a cyclic prefix part of a next first symbol.

11. The method of any one of claims 4 to 6, wherein, In a case where the first position is a start position of the cyclic prefix length, the one or more reference chips occupy the first time unit, each of the reference chips has the same length, and a first reference chip has an opposite level to a second signal; The second signal refers to a signal of a start indication information part in the preamble.

12. The method of claim 11, wherein, The one or more reference chips are mapped to one or more subcarriers, and the one or more subcarriers are individually OFDM modulated to generate an output signal.

13. The method of any one of claims 4 to 6, wherein, The one or more reference chips occupy the first time unit, each of the reference chips has the same length; In a case where the first position is a start position of the cyclic prefix length, the first H reference chips have the same level as the last H chips; H is an integer obtained by dividing the first length by the second length and then rounding up, and H is an integer greater than or equal to 1; The first length is the cyclic prefix length. The second length is a length of a reference chip.

14. The method of claim 13, wherein, The one or more reference chips include a first signal and a fifth signal; The fifth signal is a signal mapped to a position after the cyclic prefix length after P samples of the synchronization information part are deleted, and P is a number of samples corresponding to the first length, and P is a positive integer greater than or equal to 1; The first signal is a signal corresponding to the last P samples in the fifth signal.

15. The method of claim 1 or 2, wherein, The synchronization information part includes a first part and a second part, and the second part is located after the first part; The first part is used to indicate a basic time length; The second part is used to indicate a relationship between a chip length of a first chip and the basic time length.

16. The method of claim 15, wherein, The first part includes one or more second chips; A chip length of the one or more second chips is used to indicate the basic time length; A first second chip of the first part has an opposite level to a second signal; The second signal refers to a signal of a start indication information part in the preamble.

17. The method of claim 15 or 16, wherein, The second part includes one or more third chips; The second part includes a first subzone, a second subzone, and an end indication zone; A first third chip of the first subzone has an opposite level to a last second chip in the first part, and a third chip of the second subzone has an opposite level to a third chip of the first subzone.

18. The method of claim 17, wherein, a ratio between the first chip length and the second chip length is used to indicate a relationship between the chip length of the first chip and the basic duration; the first chip length is smaller than the second chip length; the first chip length is a length of the first partition; the second chip length is a length of the second partition.

19. The method of claim 17, wherein, the first chip length is the same as the second chip length; the first chip length is a length of the first partition; the second chip length is a length of the second partition.

20. The method of any one of claims 17 to 19, wherein, a level of a third chip of the end indication region is opposite to a level of a last third chip of the second partition.

21. The method of claim 20, wherein, the third chip length is the same as the basic duration or the same as the first chip length; the third chip length is a total chip length of the end indication region.

22. The method of any one of claims 21 to 23, wherein, the end indication region comprises K third chips; wherein K is an even number; a level of a first third chip is opposite to a level of a third chip of the second partition; a level of a last third chip is the same as a level of a third chip of the second partition.

23. The method of claim 22, wherein, the third chip length is the same as or different from the basic duration; the third chip length is a total chip length of the end indication region.

24. The method of claim 15 or 16, wherein, the second part comprises M fourth chips, M is an even number; a chip length of the fourth chip is the same as the basic duration; a bit value is used to indicate a relationship between a chip length of the first chip and the basic duration; the bit value is a value of bit information encoding the M fourth chips.

25. The method of claim 24, wherein, different bit values indicate different relationships between the chip length of the first chip and the basic duration.

26. The method of any one of claims 15 to 25, wherein, the first part and the second part are mapped starting at a position after a cyclic prefix length.

27. The method of any one of claims 15 to 25, wherein, the first part and the second part are mapped starting at a beginning position of a cyclic prefix length; an output signal of the synchronization information part does not comprise a first signal; the first signal refers to a signal of a cyclic prefix part.

28. The method of any one of claims 15 to 25, wherein, the first part and the second part are mapped starting at a position after a cyclic prefix length, a first second chip of the first part has a same level as a last third chip of an end indication region of the second part.

29. The method of claim 1 or 2, wherein, the start information part is used to indicate a basic duration; the synchronization information part indicates a relationship between a chip length of a first chip and the basic duration.

30. A communication method, the method comprising: The first device transmits data and / or control information in one or more first time units; wherein, The first time unit comprises one or more first chips; The synchronization information part in the preamble indicates the length of the first chips.

31. The method of claim 30, wherein, The last first chip is a redundant chip; and the other first chips are used to carry the data and / or control information; The first first chip has the same level as the last first chip.

32. The method of claim 31, wherein, The last T first chips are redundant chips; and the other first chips are used to carry the data and / or control information; T is a positive integer greater than or equal to 1; The first T first chips respectively have the same level as the last T first chips.

33. A first device, comprising: a communication unit configured to transmit a preamble; the preamble comprises a synchronization information part, the synchronization information part is used for at least one of the following: obtaining time synchronization, obtaining frequency synchronization, and indicating the chip length of first chips; wherein the first chips are chips used to transmit control information and / or data information.

34. A first device comprising: a processor and a memory, the memory is used to store a computer program, the processor is used to invoke and run the computer program stored in the memory to perform the method of any one of claims 1 to 32.

35. A chip comprising: a processor configured to invoke and run a computer program from a memory, so that the device installed with the chip performs the method of any one of claims 1 to 32.

36. A computer readable storage medium, configured to store a computer program, the computer program causes a computer to perform the method of any one of claims 1 to 32.

37. A computer program product, comprising computer program instructions, the computer program instructions cause a computer to perform the method of any one of claims 1 to 32.

38. A computer program, the computer program causes a computer to perform the method of any one of claims 1 to 32.

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