Array substrate, display panel and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel and a display apparatus. The array substrate comprises: a base substrate; a plurality of pixel electrodes, arranged in an array on the base substrate; a plurality of transistors, located between the layer where the plurality of pixel electrodes are located and the base substrate; a first insulating layer, located between the layer where the plurality of transistors are located and the layer where the plurality of pixel electrodes are located, the first insulating layer comprising first via holes overlapping first electrodes of the transistors; and a second insulating layer, located between the first insulating layer and the layer where the first electrodes of the plurality of transistors are located, the second insulating layer comprising second via holes that overlap the first electrodes of the transistors and are communicated with the first via holes. The pixel electrodes are electrically connected to the first electrodes of the transistors by means of the first via holes and the second via holes, and the orthographic projections of the first via holes on the base substrate are away from the orthographic projections of the pixel electrodes on the base substrate with respect to the orthographic projections of the second via holes on the base substrate.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation and convenient carrying, and has been rapidly developed in recent years, and has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual reality displays, etc.

[0003] SUMMARY

[0004] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions.

[0005] In one aspect, the array substrate provided by the embodiments of the present disclosure comprises:

[0006] a substrate substrate;

[0007] a plurality of pixel electrodes arranged in an array on the substrate substrate;

[0008] a plurality of transistors located between the layer where the plurality of pixel electrodes are located and the substrate substrate;

[0009] a first insulating layer located between the layer where the first poles of the plurality of transistors are located and the layer where the plurality of pixel electrodes are located, the first insulating layer comprising first vias mutually overlapping with the first poles of the transistors;

[0010] a second insulating layer located between the first insulating layer and the layer where the first poles of the plurality of transistors are located, the second insulating layer comprising second vias mutually overlapping with the first poles of the transistors and communicating with the first vias; the pixel electrodes are electrically connected with the first poles of the transistors through the first vias and the second vias; and the orthographic projection of the first vias on the substrate substrate is arranged away from the orthographic projection of the second vias on the substrate substrate relative to the orthographic projection of the pixel electrodes on the substrate substrate.

[0011] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first insulating layer covers the sidewall of the second via which is covered by the pixel electrode.

[0012] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the orthographic projection of the first via on the substrate substrate overlaps with the orthographic projection of the sidewall of the second insulating layer away from the pixel electrode on the substrate substrate.

[0013] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the bottom of the first via includes a first boundary and a second boundary extending along the row direction, and the orthographic projection of the first boundary on the substrate substrate is located on the side of the orthographic projection of the second boundary on the substrate substrate close to the orthographic projection of the pixel electrode on the substrate substrate.

[0014] the bottom of the second via includes a third boundary and a fourth boundary extending along the row direction, and the orthographic projection of the third boundary on the substrate substrate is located on the side of the orthographic projection of the fourth boundary on the substrate substrate close to the orthographic projection of the pixel electrode on the substrate substrate.

[0015] and the orthographic projection of the first boundary on the substrate substrate is located between the orthographic projection of the third boundary on the substrate substrate and the orthographic projection of the fourth boundary on the substrate substrate, and the orthographic projection of the fourth boundary on the substrate substrate is located between the orthographic projection of the first boundary on the substrate substrate and the orthographic projection of the second boundary on the substrate substrate.

[0016] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first vias corresponding to the pixel electrodes in the same row are in communication to form a first trench, and the second vias corresponding to the pixel electrodes in the same row are in communication to form a second trench.

[0017] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a first common electrode is further included, which is located on the side of the layer where the plurality of pixel electrodes are located away from the substrate substrate.

[0018] The pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode located between the layer where the first sub-pixel electrode is located and the layer where the first common electrode is located, and the first sub-pixel electrode and the second sub-pixel electrode are electrically connected.

[0019] The partial orthographic projection of the first sub-pixel electrode on the substrate substrate and the partial orthographic projection of the second sub-pixel electrode on the substrate substrate overlap with each other.

[0020] The first sub-pixel electrode has a first overlapping area with the first common electrode on the substrate, and the second sub-pixel electrode has a second overlapping area with the first common electrode on the substrate, and the second overlapping area at most partially overlaps with the first overlapping area.

[0021] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second common electrodes between the first insulating layer and the second insulating layer, and the second common electrodes on the substrate have a projection that intersects with the projection of the pixel electrodes in the same row on the substrate.

[0022] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second common electrodes between the first insulating layer and the second insulating layer, and the second common electrodes on the substrate have a projection that intersects with the projection of the pixel electrodes in the same row on the substrate.

[0023] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second common electrodes between the first insulating layer and the second insulating layer, and the second common electrodes on the substrate have a projection that intersects with the projection of the pixel electrodes in the same row on the substrate.

[0024] The first common electrode comprises a slit, and on one side of the extending direction of the slit, the first overlapping area and the second overlapping area substantially coincide; on the other side of the extending direction of the slit, the first overlapping area is substantially located in the second overlapping area.

[0025] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second common electrodes between the first insulating layer and the second insulating layer, and the second common electrodes on the substrate have a projection that intersects with the projection of the pixel electrodes in the same row on the substrate.

[0026] The first common electrode comprises a slit, and the first overlapping area and the second overlapping area are located on both sides of the extending direction of the slit.

[0027] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second common electrodes between the first insulating layer and the second insulating layer, and the second common electrodes on the substrate have a projection that intersects with the projection of the pixel electrodes in the same row on the substrate.

[0028] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second common electrodes between the first insulating layer and the second insulating layer, and the second common electrodes on the substrate have a projection that intersects with the projection of the pixel electrodes in the same row on the substrate.

[0029] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first sub-pixel electrode and the second sub-pixel electrode extend to the area where the slit is located.

[0030] In the column direction, the length of the first sub-pixel electrode is greater than half the length of the slit, and the length of the second sub-pixel electrode is greater than the length of the slit.

[0031] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the orthographic projection of the second common electrode on the substrate substrate is located between the orthographic projections of the first via and / or the second via on the substrate substrate in the column direction.

[0032] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising: a conductive pattern disposed in the same layer as the second electrode of the transistor, and the first common electrode is electrically connected to the second common electrode through the conductive pattern.

[0033] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first sub-pixel electrode comprises a pixel part and a lap part disposed integrally, wherein the lap part is located in the second via, the pixel part is located outside the second via, and the width of the lap part is less than the width of the pixel part.

[0034] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first sub-pixel electrode further comprises a transition part connecting the pixel part and the lap part, and in the direction from the pixel part to the lap part, the width of the transition part is reduced at least once, the width of the transition part is greater than the width of the lap part, and less than the width of the pixel part.

[0035] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the transition part is located on the plane of the first insulating layer, and / or the transition part is located on the first insulating layer at the sidewall of the second via.

[0036] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising a third insulating layer, the third insulating layer fills the first via and the second via;

[0037] The orthographic projection of the second sub-pixel electrode on the substrate substrate partially overlaps the orthographic projection of the first sub-pixel electrode of the previous row on the substrate substrate, and the orthographic projection of the second sub-pixel electrode on the substrate substrate partially overlaps the orthographic projection of the second via of the previous row on the substrate substrate.

[0038] In some embodiments, the array substrate provided in the embodiments of the present disclosure further comprises a fourth insulating layer between the layer where the first sub-pixel electrode is located and the layer where the second sub-pixel electrode is located.

[0039] The first sub-pixel electrode is electrically connected with the second sub-pixel electrode through a third via hole penetrating through the fourth insulating layer, and the orthographic projection of the third via hole on the substrate substrate is located within the orthographic projection of the second via hole on the substrate substrate.

[0040] In some embodiments, the array substrate provided in the embodiments of the present disclosure further comprises a first common electrode located on the side of the layer where the plurality of pixel electrodes are located away from the substrate substrate, and the first common electrode comprises a slit.

[0041] In the slit area, the length of the first sub-pixel electrode in the column direction is greater than half the length of the slit in the column direction and less than the length of the second sub-pixel electrode in the column direction, and the length of the second sub-pixel electrode in the column direction is less than the length of the slit in the column direction.

[0042] In some embodiments, the array substrate provided in the embodiments of the present disclosure further comprises a data line, a first light shielding pattern and a second light shielding pattern; wherein,

[0043] The first light shielding pattern is multiplexed as the bottom gate of the transistor, and the orthographic projection of the first light shielding pattern on the substrate substrate covers the channel region of the active layer of the transistor.

[0044] The second pole of the transistor is multiplexed with the data line, and a fifth insulating layer is arranged between the layer where the data line is located and the active layer of the transistor, and the data line is electrically connected with the active layer of the transistor through a fourth via hole penetrating through the fifth insulating layer.

[0045] The second light shielding pattern is located on the side of the layer where the first light shielding pattern is located close to the substrate substrate, and the orthographic projection of the second light shielding pattern on the substrate substrate covers the orthographic projection of the fourth via hole on the substrate substrate.

[0046] In some embodiments, the array substrate provided in the embodiments of the present disclosure further comprises a transfer electrode and a color resistance layer, wherein the transfer electrode is located between the active layer of the transistor and the second insulating layer, and the transfer electrode is multiplexed with the first pole of the transistor, and the color resistance layer is located between the layer where the transfer electrode is located and the second insulating layer.

[0047] On the other hand, the embodiments of the present disclosure provide a display panel comprising the array substrate provided in the embodiments of the present disclosure and an opposite substrate opposite to the array substrate.

[0048] In another aspect, the display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure, and a backlight module located at the light-in side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0049] FIG. 1A is a schematic structural diagram of three sub-pixels in an array substrate provided by the embodiments of the present disclosure;

[0050] FIG. 1B is a schematic structural diagram of a layer where data lines in FIG. 1A are located;

[0051] FIG. 1C is a schematic structural diagram of a layer where a transfer electrode in FIG. 1A is located;

[0052] FIG. 1D is a schematic structural diagram of a layer where a second via in FIG. 1A is located;

[0053] FIG. 1E is a schematic structural diagram of a layer where a second common electrode in FIG. 1A is located;

[0054] FIG. 1F is a schematic structural diagram of a layer where a first via in FIG. 1A is located;

[0055] FIG. 1G is a schematic structural diagram of a layer where a first sub-pixel electrode in FIG. 1A is located;

[0056] FIG. 1H is a schematic structural diagram of a layer where a second sub-pixel electrode in FIG. 1A is located;

[0057] FIG. 1I is a schematic structural diagram of a layer where a first common electrode in FIG. 1A is located;

[0058] FIG. 2 is a schematic structural diagram of a cross section along the array substrate shown in FIG. 1A;

[0059] FIG. 3A is another schematic structural diagram of three sub-pixels in an array substrate provided by the embodiments of the present disclosure;

[0060] FIG. 3B is a schematic structural diagram of a layer where data lines in FIG. 3A are located;

[0061] FIG. 3C is a schematic structural diagram of a layer where a transfer electrode in FIG. 3A is located;

[0062] FIG. 3D is a schematic structural diagram of a layer where a second via in FIG. 3A is located;

[0063] FIG. 3E is a schematic structural diagram of a layer where a second common electrode in FIG. 3A is located;

[0064] FIG. 3F is a schematic structural diagram of a layer where a first via and a third via in FIG. 3A are located;

[0065] FIG. 3G is a schematic structural diagram of a layer where a first sub-pixel electrode in FIG. 3A is located;

[0066] FIG. 3H is a schematic structural diagram of a layer where a second sub-pixel electrode in FIG. 3A is located;

[0067] FIG. 3I is a structural schematic diagram of a layer where the first common electrode in FIG. 3A is located;

[0068] FIG. 4 is a cross-sectional structural schematic diagram of the array substrate shown in FIG. 3A;

[0069] FIG. 5 is a structural schematic diagram of about three sub-pixels in an array substrate provided by an embodiment of the present disclosure;

[0070] FIG. 6 is another structural schematic diagram of three sub-pixels in an array substrate provided by an embodiment of the present disclosure;

[0071] FIG. 7 is another cross-sectional structural schematic diagram of the array substrate shown in FIG. 1A;

[0072] FIG. 8 is a schematic diagram of a first sub-pixel electrode breaking provided by an embodiment of the present disclosure;

[0073] FIG. 9 is another structural schematic diagram of about three sub-pixels in an array substrate provided by an embodiment of the present disclosure;

[0074] FIG. 10 is a cross-sectional structural schematic diagram of the array substrate shown in FIG. 9;

[0075] FIG. 11A is a structural schematic diagram of a first sub-pixel electrode provided by an embodiment of the present disclosure;

[0076] FIG. 11B is another structural schematic diagram of a first sub-pixel electrode provided by an embodiment of the present disclosure;

[0077] FIG. 11C is another structural schematic diagram of a first sub-pixel electrode provided by an embodiment of the present disclosure;

[0078] FIG. 12 is a schematic diagram of a connection between a first common electrode and a second common electrode provided by an embodiment of the present disclosure;

[0079] FIG. 13 is another structural schematic diagram of three sub-pixels in an array substrate provided by an embodiment of the present disclosure;

[0080] FIG. 14 is a cross-sectional structural schematic diagram of the array substrate shown in FIG. 13;

[0081] FIG. 15 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure;

[0082] FIG. 16 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0083] FIG. 17 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] For the purposes of the present disclosure, the goals, technical solutions, and advantages of the embodiments will be more clearly understood from the following description of the embodiments of the present disclosure, taken in conjunction with the accompanying drawings. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. A sharp angle illustrated can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not to be construed as limiting to the region. The purpose of the regions illustrated in the figures is to more conceptually illustrate the logical proximity between illustrated regions for an intraoperative tool to be used in the surgical procedure. Furthermore, the same or similar reference numerals are used in different drawings to denote the same or similar elements or components having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and structures incorporated herein will be omitted.

[0085] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish one element from another, and the terms "comprises", "comprising", "includes", "including" and the like can be used herein. Such terms indicate, unless otherwise defined, that the elements encompass the elements listed thereafter and their equivalents. The terms "connected", "coupled", and similar terms are not limited to a direct connection or coupling, but can include an indirect connection or coupling, whether or not it is physical, mechanical, electrical, or otherwise. The terms "inner", "outer", "upper", "lower", and the like are used only to indicate relative positions, and can change when the absolute positions of the described objects change.

[0086] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, or be indirectly on the other element or layer with intervening elements or layers. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, or be indirectly on the side of the other element or layer with intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, or "directly connected to" another element or layer, there are no intervening elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0087] In some embodiments, the picture resolution (PPI) of TFT-LCD products such as VR, AR, etc. is constantly increasing. In the future, VR products need to be upgraded to 1500PPI or even 2000PPI or above to meet the visual experience of the human eye. However, the increase in PPI corresponds to the continuous reduction in the size of a single pixel. For example, the sub-pixel size of a 2.5-inch 1500PPI product is about 5μm*15μm, and the sub-pixel size of a 2.5-inch 2000PPI product is only 4μm*12μm. In VR products based on LTPO and LTPS architectures, the pixel storage capacitance is designed with reference to the common electrode, that is, the pixel electrode and the single-layer common electrode (VCOM signal) in the sub-pixel vertically overlap and laterally couple in the physical space to form a storage capacitance to maintain the sub-pixel charge in a frame. As mentioned above, the implementation of ultra-high PPI is based on the continuous reduction of the size of the sub-pixel, which means that the area of the vertical overlap and lateral coupling between the pixel electrode and the common electrode in the physical space of the sub-pixel is also continuously reduced, and the sub-pixel storage capacitance is continuously reduced, which accordingly causes the pixel charge to be unable to be maintained in a frame, resulting in problems such as flicker and crosstalk.

[0088] To improve the above technical problems, the present disclosure provides an array substrate. FIG. 1A is a schematic diagram of a structure of three sub-pixels in an array substrate provided by an embodiment of the present disclosure, FIGS. 1B-1I are schematic diagrams of structures of each single film layer in FIG. 1, FIG. 2 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG. 1A, FIG. 3A is another schematic diagram of a structure of three sub-pixels in an array substrate provided by an embodiment of the present disclosure, FIGS. 3B-3I are schematic diagrams of structures of each single film layer in FIG. 1, and FIG. 4 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG. 3A. For the sake of clear illustration, FIGS. 1A and 3A omit the transistor film layers below the transfer electrode 105. As can be seen from FIGS. 1A-1I, 2, 3A-3I, and 4, the above array substrate provided by an embodiment of the present disclosure can include:

[0089] The substrate 101, optionally, includes a display area AA and a non-display area BB located at least one side of the display area AA; in some embodiments, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc.; the substrate 101 is a substrate allowing visible light to pass through, for example, a glass, quartz, plastic, etc.

[0090] The first common electrode 102 is located in the display area AA of the substrate 101; in some embodiments, the first common electrode 102 can be a slit electrode, and the material of the first common electrode 102 can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc.

[0091] The plurality of pixel electrodes 103 is located between the layer where the first common electrode 102 is located and the substrate 101; the plurality of pixel electrodes 103 is arranged in an array in the display area AA, the pixel electrode 103 includes a first sub-pixel electrode 1031 and a second sub-pixel electrode 1032 located between the layer where the first sub-pixel electrode 1031 is located and the layer where the first common electrode 102 is located, and the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 are electrically connected. In some embodiments, the material of the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc.

[0092] Optionally, to ensure that the overall area of the pixel electrode 103 is large, thereby facilitating the formation of a large storage capacitance with the common electrode, the present disclosure can be configured such that the partial orthogonal projection of the first sub-pixel electrode 1031 on the substrate 101 and the partial orthogonal projection of the second sub-pixel electrode 1032 on the substrate 101 overlap each other. In some embodiments, the orthogonal projection of the first sub-pixel electrode 1031 on the substrate 101 and the orthogonal projection of the first common electrode 102 on the substrate 101 have a first overlap region OL1, the orthogonal projection of the second sub-pixel electrode 1032 on the substrate 101 and the orthogonal projection of the first common electrode 102 on the substrate 101 have a second overlap region OL2, and the second overlap region OL2 at most partially overlaps the first overlap region OL1; for example, in FIG. 1A, on one side (left side) of the direction in which the slit S extends, the first overlap region OL1 and the second overlap region OL2 substantially coincide; on the other side (right side) of the direction in which the slit S extends, the first overlap region OL1 is substantially located within the second overlap region OL2; for another example, in FIG. 3A, the first overlap region OL1 and the second overlap region OL2 do not overlap each other, and optionally, the first overlap region OL1 and the second overlap region OL2 are located on the left and right sides of the direction in which the slit S extends, respectively. In this way, the first common electrode 102 and the first sub-pixel electrode 1031 can form a first storage capacitance in the first overlap region OL1 outside the second overlap region OL2, and the first common electrode 102 and the second sub-pixel electrode 1032 can form a second storage capacitance in the second overlap region OL2.

[0093] It should be noted that in the embodiments provided by the present disclosure, due to the influence of process conditions or other factors such as measurement, the “substantial coincidence” may be exact coincidence or may have some deviation (for example, with a deviation of ±1 μm), and therefore the relationship between the related features “substantially coincides” as long as the error is allowed, all belong to the protection scope of the present disclosure.

[0094] In some embodiments, the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 can be block electrodes extending to the area where the slit S is located. In the embodiment shown in FIG. 1A, when the first sub-pixel electrode 1031 is made, the second via V2 is not filled flat, and the first sub-pixel electrode 1031 continues to extend in the arrow direction Y, and can be made to be in the second via V2 of the pixel in the previous row, and short-circuit with the first sub-pixel electrode 1031 of the previous row; but when the second sub-pixel electrode 1032 is made, the second via V2 is filled flat by the third insulating layer 108, so the second sub-pixel electrode 1032 can continue to extend in the arrow direction Y to the area where the normal projection of the second sub-pixel electrode 1032 overlaps with the normal projection of the first sub-pixel electrode 1031 of the previous row and the normal projection of the second via V2 of the previous row. In the embodiment shown in FIG. 3A, when the first sub-pixel electrode 1031 is made, the second via V2 is not filled flat, and the first sub-pixel electrode 1031 continues to extend in the arrow direction Y, and can be made to be in the second via V2 of the pixel in the previous row, and short-circuit with the first sub-pixel electrode 1031 of the previous row; when the second sub-pixel electrode 1032 is made, the sidewall of the second via V2 is covered by the fourth insulating layer 109 but not filled flat by the fourth insulating layer 109, so the second sub-pixel electrode 1032 continues to extend in the arrow direction Y to the area where the normal projection of the second sub-pixel electrode 1032 overlaps with the normal projection of the second via V2 of the previous row. Since the second via V2 is deep, it will cause exposure failure when the second sub-pixel electrode 1032 continues to extend in the arrow direction Y to the area where the normal projection of the second sub-pixel electrode 1032 overlaps with the normal projection of the second via V2 of the previous row, and finally cause short-circuit between the second sub-pixel electrodes 1032 of adjacent two rows. Based on this, in order to prevent short-circuit between the pixel electrodes 103 of adjacent two rows and take into account that the area of the pixel electrode 103 is large, the present disclosure can be set that, in the column direction Y, the length of the first sub-pixel electrode 1301 is greater than half (for example, 3 / 4) of the length of the slit S, and the length of the second sub-pixel electrode 1032 is greater than the length of the slit S. Specifically, in the slit S area of the embodiment shown in FIG. 1A: the length of the first sub-pixel electrode 1301 in the column direction Y is greater than half (for example, 3 / 4) of the length of the slit S in the column direction Y, and less than the length of the second sub-pixel electrode 1032 in the column direction Y, and the length of the second sub-pixel electrode 1032 in the column direction Y is equal to the length of the slit S; in the slit S area of the embodiment shown in FIG. 3A: the length of the first sub-pixel electrode 1301 in the column direction Y is greater than half (for example, 3 / 4) of the length of the slit S in the column direction Y, and less than the length of the second sub-pixel electrode 1032 in the column direction Y, and the length of the second sub-pixel electrode 1032 in the column direction Y is less than the length of the slit S in the column direction Y, for example, the length of the second sub-pixel electrode 1032 in the column direction Y is equal to 4 / 5 of the length of the slit S in the column direction Y.

[0095] A plurality of second common electrodes 104 are located between the layer where the first sub-pixel electrode 1031 is located and the substrate 101, and the orthogonal projection of the second common electrode 104 on the substrate 101 and the orthogonal projection of the pixel electrode 103 in the same row on the substrate 101 intersect with each other; in other words, the orthogonal projection of the second common electrode 104 on the substrate 101 and the orthogonal projection of the pixel electrode 103 in the same row on the substrate 101 overlap with each other, and the extension direction of the second common electrode 104 intersects with the extension direction of the pixel electrode 103. In some embodiments, the orthogonal projection of the second common electrode 104 on the substrate 101 and the orthogonal projection of the first sub-pixel electrode 1031 on the substrate 101 have a third overlap region OL3, and the orthogonal projection of the second common electrode 104 on the substrate 101 and the orthogonal projection of the second sub-pixel electrode 1032 on the substrate 101 have a fourth overlap region OL4, and the third overlap region OL3 and the fourth overlap region OL4 at most partially overlap; as shown in FIG. 1A, the third overlap region OL3 can be located substantially within the fourth overlap region OL4, or as shown in FIG. 3A, the third overlap region OL3 and the fourth overlap region OL4 partially overlap; of course, in some embodiments, the third overlap region OL3 and the fourth overlap region OL4 can also be staggered with each other. Thus, the second common electrode 104 and the first sub-pixel electrode 1031 form a third storage capacitor in the third overlap region OL3, and the second common electrode 104 and the second sub-pixel electrode 1032 form a fourth storage capacitor in the fourth overlap region OL4 outside the third overlap region OL3. In some embodiments, the material of the second common electrode 104 can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc.

[0096] In the array substrate provided in the embodiments of the present disclosure, by setting the part of the first sub-pixel electrode 1031 to overlap with the part of the second sub-pixel electrode 1032, the first sub-pixel electrode 1031 and the first common electrode 102 form a first storage capacitor, and the second sub-pixel electrode 1032 and the first common electrode 102 form a second storage capacitor; at the same time, the present disclosure also provides a second common electrode 104, and the second common electrode 104 and the first sub-pixel electrode 1031 form a third storage capacitor, and the second common electrode 104 and the second sub-pixel electrode 1032 form a fourth storage capacitor. Therefore, the storage capacitor between the pixel electrode 103 and the common electrode (including the first common electrode 102 and the second common electrode 104) in the present disclosure includes the first storage capacitor, the second storage capacitor, the third storage capacitor and the fourth storage capacitor, thereby ensuring that the overall storage capacitor in a single sub-pixel is large, so that the pixel charge can be maintained within a frame, effectively improving the problems of picture flicker and crosstalk, etc.

[0097] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. II and FIG. 3I, the first common electrode 102 can be a single-layer structure. Limited by the exposure process, the width of the slit S is at least 2 μm to 3 μm, for example, 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, 3 μm, etc.

[0098] In order to further reduce the width of the slit and increase the area of the first common electrode 102, thereby increasing the storage capacitance of the first common electrode 102 and the pixel electrode 103. The present disclosure can solve the problem that the slit is limited by the exposure process by using the first normal exposure and the second shift exposure. In the process, the transparent conductive film layer can be coated first, the photoresist is coated, then the first exposure, development and etching are performed using the mask of the single-layer structure first common electrode 102 to form the first sub-common electrode 1021; then the transparent conductive film layer is coated again, the photoresist is coated, and the second exposure, development and etching are performed using the mask of the single-layer structure first common electrode 102 which is offset from the first sub-common electrode 1021 by a limited distance (for example, greater than or equal to 0.5 μm and less than 3 μm) to form the second sub-common electrode 1022. The slit S of the first common electrode 102 composed of the first sub-common electrode 1021 and the second sub-common electrode 1022 is smaller.

[0099] Based on this, FIG. 5 shows a structural schematic diagram of about three sub-pixels in an array substrate provided by an embodiment of the present disclosure, FIG. 6 shows another structural schematic diagram of three sub-pixels in an array substrate provided by an embodiment of the present disclosure, and for the sake of clear illustration, FIG. 5 and FIG. 6 only show the first sub-pixel electrode 1031, the second sub-pixel electrode 1032, the first sub-common electrode 1021, the second sub-common electrode 1022, and the second trench PLN1, and the setting mode of the omitted transfer electrode 105, the first trench SPVX, etc. can refer to the embodiments shown in FIG. 1A and FIG. 3A, which will not be described herein. As shown in FIG. 5 and FIG. 6, the first common electrode 102 of the present disclosure can include the first sub-common electrode 1021, and the second sub-common electrode 1022 which is in contact with and partially overlaps the first sub-common electrode 1021 on the side of the first sub-common electrode 1021 away from the layer where the pixel electrode 103 is located. Optionally, the structure of the first sub-common electrode 1021 and the second sub-common electrode 1022 can be the same as that of the single-layer first common electrode 104, in other words, the slit width of the first sub-common electrode 1021 and the slit width of the second sub-common electrode 1022 can be 2 μm to 3 μm. However, due to the partial overlap between the first sub-common electrode 1021 and the second sub-common electrode 1022, the slit S width of the first common electrode 102 becomes smaller, and in some embodiments, the slit S width of the first common electrode 1021 is 0.8 μm to 2 μm, for example, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2 μm, etc.

[0100] In some embodiments, in the above-mentioned array substrate provided by an embodiment of the present disclosure, as shown in FIG. 1A to FIG. 1I, FIG. 2, FIG. 3A to FIG. 3I, and FIG. 4, a plurality of transistors (for example, oxide transistors TO) can be further included between the layer where the plurality of second common electrodes 104 is located and the substrate 101, a first insulating layer 106 can be further included between the layer where the plurality of second common electrodes 104 is located and the layer where the plurality of pixel electrodes 103 is located, and a second insulating layer 107 can be further included between the layer where the plurality of second common electrodes 104 is located and the layer where the plurality of transistors (for example, oxide transistors TO) is located; the first insulating layer 106 includes a first via V1 which mutually overlaps with the transfer electrode 105, the second insulating layer 107 includes a second via V2 which mutually overlaps with the transistors (for example, oxide transistors TO) and communicates with the first via V1, and the throughly arranged first via V1 and second via V2 constitute a sleeve hole structure, and the sleeve hole structure is electrically connected with the first pole (for example, the transfer electrode 105) of the transistors (for example, oxide transistors TO) of the first sub-pixel electrode 1031.

[0101] It should be noted that the first electrode of the transistor (for example, the oxide transistor TO) can refer to the conductorized part of the active layer, or can refer to the transfer electrode 105 electrically connected with the active layer. The disclosure is illustratively described by taking the transfer electrode 105 as the first electrode of the transistor (for example, the oxide transistor TO). Alternatively, the first electrode of the transistor (for example, the oxide transistor TO) is the source electrode or the drain electrode, which is not limited by the disclosure.

[0102] In some embodiments, the material of the transfer electrode 105 can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc., and / or at least one metal material such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc.; the material of the first insulating layer 106 can be an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., which can be a single layer or a stack; the material of the second insulating layer 107 can be an organic insulating material such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., which can be a single layer or a stack, which is not limited herein.

[0103] In some embodiments, in the array substrate provided in the embodiments of the disclosure, as shown in FIGS. 1A, 1E and 1F, the first via V1 corresponding to the first sub-pixel electrode 1031 in the same row can be connected to form a first trench SPVX, and the second via V2 corresponding to the first sub-pixel electrode 1031 in the same row can be connected to form a second trench PLN1, and the orthographic projection of the first trench SPVX on the substrate 101 can be located within the orthographic projection of the second trench PLN1 on the substrate 101. The higher the resolution is, the smaller the sub-pixel size is, and the more difficult the punching process is. By connecting the vias in the same row to form the trenches, the process difficulty is reduced, and at the same time, the first sub-pixel electrode 1031 and the transfer electrode 105 can be normally conducted.

[0104] FIG. 7 and FIG. 8 are cross-sectional structure schematic diagrams of an array substrate provided by an embodiment of the present disclosure, respectively. As shown in FIG. 7, when the profile angle of the second via V2 in the second insulating layer 107 is large, the second common electrode 104 can fall on the sidewall of the second via V2. However, the first via V1 and the second via V2 are a through-hole structure, and when there is a deviation in process alignment, the first via V1 and the second via V2 can be misaligned, for example, the first via V1 is misaligned to the left side of the second via V2, and when etching the first insulating layer 106, there can be a condition of drilling the sidewall of the second via V2, causing an undercut phenomenon on the left side of the second via V2, at this time, the first sub-pixel electrode 1031 on the left side of the second via V2 will be broken, as shown in FIG. 8.

[0105] FIG. 9 is another structure schematic diagram of about three sub-pixels in an array substrate provided by an embodiment of the present disclosure, and FIG. 10 is a cross-sectional structure schematic diagram of the array substrate shown in FIG. 9. For the sake of clear illustration, FIG. 9 only shows the first sub-pixel electrode 1031, the second common electrode 105, the first trench SPVX and the second trench PLN1, and the omitted setting mode of the second sub-pixel electrode 1032, the first common electrode 102, the transfer electrode 105 and the like can refer to the embodiments shown in FIG. 1A and FIG. 3A, which will not be described here. As shown in FIG. 9 and FIG. 10, the present disclosure can misalign the first via V1 and the second via V2, so that the orthographic projection of the first via V1 on the substrate substrate 101 is offset relative to the orthographic projection of the second via V2 on the substrate substrate 101 by a certain distance (which can be equal to the alignment deviation of the first via V1 and the second via V2, for example, 0.5 μm-2 μm) away from the first sub-pixel electrode 1031, to ensure that the distance between the upper side of the first via V1 and the second via V2 in FIG. 9 (i.e. the distance between the first boundary BL1 and the third boundary BL3) meets the process deviation of the first via V1 aligning the second via V2, so that the first insulating layer 106 covers the sidewall of the second via V2 covered by the first sub-pixel electrode 1031 (for example, the left sidewall of the second via V2 shown in FIG. 10), to ensure that when etching the first insulating layer 106, the sidewall of the second via V2 is not drilled badly, avoiding the condition that the first sub-pixel electrode 1031 is broken at the sidewall drilling position.

[0106] Based on this, as shown in FIG. 9, in the present disclosure, the bottom of the first via V1 (equivalent to the bottom of the first trench SPVX) includes a first boundary BL1 and a second boundary BL2 extending along the row direction X, the orthographic projection of the first boundary BL1 on the substrate substrate 101 is located on one side of the orthographic projection of the second boundary BL2 on the substrate substrate 101 close to the orthographic projection of the pixel electrode 103 on the substrate substrate 101; the bottom of the second via V2 (equivalent to the bottom of the second trench PLN1) includes a third boundary BL3 and a fourth boundary BL4 extending along the row direction X, the orthographic projection of the third boundary BL3 on the substrate substrate 101 is located on one side of the orthographic projection of the fourth boundary BL4 on the substrate substrate 101 close to the orthographic projection of the pixel electrode 103 on the substrate substrate 101; in order to prevent the first sub-pixel electrode 1031 from being broken due to the side wall drilling of the second via V2, the orthographic projection of the first boundary BL1 on the substrate substrate 101 can be located between the orthographic projection of the third boundary BL3 on the substrate substrate 101 and the orthographic projection of the fourth boundary BL4 on the substrate substrate 101, and the orthographic projection of the fourth boundary BL4 on the substrate substrate 101 is located between the orthographic projection of the first boundary BL1 on the substrate substrate 101 and the orthographic projection of the second boundary BL2 on the substrate substrate 101. In some embodiments, the distance between the first boundary BL1 and the third boundary BL3 is equal to the alignment deviation of the first via V1 and the second via V2.

[0107] It should be noted that, as shown in FIG. 1A, FIG. 2, FIG. 3A and FIG. 4, in the case that the Profile angle of the second via PLN1 is small, the second common electrode 104 is located outside the second via V2, that is, the second common electrode 104 can be located only on the plane of the second insulating layer 107 and will not extend to the sidewall of the second via V2. In addition, in the case that there is no alignment deviation or the alignment deviation is small enough to be negligible, the etching process of the first insulating layer 106 will not cause drilling on the sidewall of the second via V2, or the etching process of the first insulating layer 106 will cause drilling on the sidewall near the bottom of the second via V2, but will not affect the electrical connection relationship between the first sub-pixel electrode 1031 and the transfer electrode 105. At this time, the bottom of the first via V1 can be located in the bottom of the second via V2, without the need for misalignment design.

[0108] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, as shown in FIG. 1A, FIG. 3A and FIG. 9, in order to avoid the short circuit between the second common electrode 104 and the transfer electrode 105 in the second via V2, the present disclosure can be configured such that the orthographic projection of the second common electrode 104 on the substrate substrate 101 is located between the orthographic projection of the bottom of the adjacent first via V1 and / or the bottom of the second via V2 on the substrate substrate 101 in the column direction Y. In some embodiments, the second common electrode 104 can cover only the plane of the second insulating layer 107, or can cover both the plane of the second insulating layer 107 and the sidewall of the second via V2.

[0109] In some embodiments, since the second via V2 is deeper, about 3-4 μm, the first sub-pixel electrode 1031 is susceptible to shorting with the same-row first sub-pixel electrode 1031 in the deeper second via V2 due to the exposure limit, and therefore, to improve the exposure yield and avoid shorting of the same-row first sub-pixel electrode 1031, the width of the first sub-pixel electrode 1031 in the second via V2 can be reduced. Specifically, as shown in FIGS. 11A, 11B and 11C, the first sub-pixel electrode 1031 includes a pixel portion P and a lapping portion L arranged integrally, wherein the lapping portion L is located in the second via V2, the pixel portion P is located outside the second via V2, and the width of the lapping portion L is smaller than the width of the pixel portion P. Alternatively, as shown in FIGS. 11A and 11B, the first sub-pixel electrode 1031 can further include a transition portion T connecting the pixel portion P and the lapping portion L, and in the direction from the pixel portion P to the lapping portion L, the width of the transition portion T is reduced at least once, for example, the width of the transition portion T can be linearly smaller or reduced in gradient. In some embodiments, the transition portion T can be located on the plane of the first insulating layer 106, or the transition portion T is located on the first insulating layer 106 at the plane of the first insulating layer 106 and the sidewall of the second via V2, or the transition portion T is located on the first insulating layer 106 at the sidewall of the second via V2. It should be understood that in some embodiments, the transition portion T can also not be provided, in which case the pixel portion P and the lapping portion L are directly in contact, as shown in FIG. 11C.

[0110] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 2 and 10, the first sub-pixel electrode 1031 and the second sub-pixel electrode 1032 can be directly in contact and electrically connected, and the first via V1 and the second via V2 can be filled flat by the third insulating layer 108. It should be understood that in the case where the same-row first via V1 is communicated as the first groove SPVX, the third insulating layer 108 can fill the first groove SPVX and the second groove PLN1. Optionally, the material of the third insulating layer 108 can be an organic insulating material such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., which is not limited herein.

[0111] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 3A-3I and FIG. 4, a fourth insulating layer 109 can be further included between the layer where the first sub-pixel electrode 1031 is located and the layer where the second sub-pixel electrode 1032 is located; the first sub-pixel electrode 1031 is electrically connected with the second sub-pixel electrode 1032 through a third via V3 penetrating through the fourth insulating layer 109, and the orthographic projection of the third via V3 on the substrate 101 is located within the orthographic projection of the second via V2 on the substrate 101. In some embodiments, the fourth insulating layer 109 can share a mask with the first insulating layer 106, and the fourth insulating layer 109 can further avoid short circuit between the first sub-pixel electrode 1031, the second sub-pixel electrode 1032 and the first sub-pixel electrodes 1031 and the second sub-pixel electrodes 1032 adjacent to the left and right sides. Optionally, the material of the fourth insulating layer 109 can be inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., which can be a single layer or a stack.

[0112] FIG. 13 shows another structure of three sub-pixels in an array substrate provided by the embodiments of the present disclosure, and FIG. 14 is a schematic view of the cross-sectional structure of the array substrate shown in FIG. 13. For the sake of clarity, FIG. 13 only shows the first sub-pixel electrode 1031, the second sub-pixel electrode 1032, the second light shielding pattern LS2 and the second trench PLN1, and the omitted setting modes of the transfer electrode 105, the first common electrode 102, the second common electrode 104, the first trench SPVX, etc. can refer to the embodiments shown in FIGS. 1A and 3A, which will not be described here.

[0113] As shown in FIGS. 13 and 14, the orthographic projection of the second sub-pixel electrode 1032 on the substrate 101 partially overlaps with the orthographic projection of the first sub-pixel electrode 1031 of the previous row on the substrate 101, and the orthographic projection of the second sub-pixel electrode 1032 on the substrate 101 partially overlaps with the orthographic projection of the second via V2 of the previous row on the substrate 101. Since the second via V2 is filled flat by the third insulating layer 108, the second sub-pixel electrode 1032 and the first sub-pixel electrode 1031 of the previous row are insulated from each other by the third insulating layer 108 and will not be connected. By overlapping the second sub-pixel electrode 1032 and the first sub-pixel electrode 1031 of the previous row, the overall area of the pixel electrode 103 can be increased, which is beneficial to form a larger storage capacitance between the pixel electrode 103 and the common electrode (including the first common electrode 102 and / or the second common electrode 103).

[0114] Continuing to refer to FIGS. 13 and 14, in the array substrate provided in the embodiments of the present disclosure, the array substrate can further include a data line DL, a first light shielding pattern LS1, and a second light shielding pattern LS2; a second electrode S of a transistor (e.g., an oxide transistor TO) is multiplexed with the data line DL, a fifth insulating layer is arranged between a layer where the data line DL is located and an active layer AC of the transistor (e.g., the oxide transistor TO), optionally, the fifth insulating layer has a double-layer structure including a first sub-insulating layer 110 and a second sub-insulating layer 111, and the data line DL is electrically connected to the active layer AC of the transistor (e.g., the oxide transistor TO) through a fourth via V4 penetrating the first sub-insulating layer 110 and the second sub-insulating layer 111; the second light shielding pattern LS2 is located on a side of the layer where the first light shielding pattern LS1 is located close to the substrate 101, and a projection of the second light shielding pattern LS2 on the substrate 101 covers a projection of the fourth via V4 on the substrate 101; a first electrode D (which can be multiplexed with the transfer electrode 105) of the transistor (e.g., the oxide transistor TO) is electrically connected to the active layer AC of the transistor (e.g., the oxide transistor TO) through a fifth via V5 penetrating the first sub-insulating layer 110, the second sub-insulating layer 111, and a seventh insulating layer 112; the first light shielding pattern LS1 can be multiplexed as a bottom gate LG of the transistor (e.g., the oxide transistor TO), and the transistor (e.g., the oxide transistor TO) can further include a top gate UG, optionally, a projection of the first light shielding pattern LS1 on the substrate 101 covers a channel region of the active layer AC of the transistor (e.g., the oxide transistor TO) and the fifth via V5. As shown in FIG. 13, the fourth via V4 is located on the data line DL between the pixel electrodes 103 and cannot be shielded by the black matrix (BM), and the fourth via V4 can be shielded by the second light shielding pattern LS2 to avoid light leakage at the fourth via V4. At the same time, by arranging the first light shielding pattern LS1 and the second light shielding pattern LS2 in different layers, the vertical space of the array substrate can be reasonably utilized to improve the aperture ratio. It should be noted that in some embodiments, only the first light shielding pattern LS1 can be arranged, and the first light shielding pattern LS1 can be used to shield the channel region of the active layer AC, the fourth via V4, and the fifth via V5.

[0115] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 2, 4, 7, 10, and 14, a color resistance layer 113 can be further arranged between the layer where the plurality of transfer electrodes 105 are located and the second insulating layer 107, and optionally, the color resistance layer 113 includes a red color resistance, a green color resistance, a blue color resistance, and the like, so that the present disclosure is applicable to products with a COA structure. Of course, in some embodiments, the color resistance layer 110 can also be arranged on a counter substrate (also referred to as a color filter substrate CF), and the present disclosure is not limited in this regard.

[0116] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 2, 4, 7, 10, 12 and 14, the array substrate can further include a low-temperature polysilicon transistor TL in the non-display area BB and belonging to a multiplexer MUX, a shift register GOA, etc., and a conductive pattern 114 disposed in the same layer as the data line DL and located in the non-display area BB. The first common electrode 102 is electrically connected to the second common electrode 104 through the conductive pattern 114. The first electrode D and the second electrode S of the low-temperature polysilicon transistor TL are disposed in the same layer as the data line DL, the gate electrode G of the low-temperature polysilicon transistor TL is disposed in the same layer as the first light shielding pattern LS1, and the gate electrode G of the low-temperature polysilicon transistor TL can be located above the active layer AC of the low-temperature polysilicon transistor TL (i.e., the low-temperature polysilicon transistor TL can be a top-gate transistor). In some embodiments, as shown in FIGS. 1A, 1B, 3A, 3B and 13, the data line DL can be a straight line or a broken line, and in the case where the data line DL is a broken line, the inclined direction of the data line DL can be the same as the inclined direction of the pixel electrode 103 and the inclined direction of the slit S in the first common electrode 102.

[0117] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 2, 4, 7, 10 and 13, the array substrate can further include an eighth insulating layer 115 located between the layer where the first common electrode 102 is located and the layer where the second sub-pixel electrode 1032 is located, and the thickness of the eighth insulating layer 115 can be Accordingly, the thickness of the first insulating layer 106 can be For example, the thickness of the eighth insulating layer 115 is The thickness of the first insulating layer 106 is Alternatively, the thickness of the eighth insulating layer 115 is The thickness of the first insulating layer 106 is In this way, by matching the thickness of the insulating layer between the common electrode and the pixel electrode, the storage capacitance between the common electrode and the pixel electrode can also be increased. In some embodiments, the material of the eighth insulating layer 115 can be an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., which can be a single layer or a stack.

[0118] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 2, 4, 7 and 10, a buffer layer 116, a ninth insulating layer 117, a tenth insulating layer 118, and an auxiliary electrode 119 can also be included. Optionally, the materials of the first sub-insulating layer 110, the second sub-insulating layer 111, the seventh insulating layer 112, the eighth insulating layer 115, the buffer layer 116, the ninth insulating layer 117 and the tenth insulating layer 118 can be inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., which can be single layer or stacked layer. The auxiliary electrode 119 is in direct contact with the first common electrode 102, which is used to prevent pixel color mixing or enhance the transmission capability of the common voltage signal. In addition, the auxiliary electrode 119 can shield the data line 102, and the reflectivity of the auxiliary electrode 119 is less than that of the data line 102, so as to reduce the reflection of ambient light and improve the display effect. The material of the auxiliary electrode 119 can include at least one metal material such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. For example, the material of the auxiliary electrode 119 is molybdenum metal. The other essential components in the array substrate are understood by those skilled in the art, and are not described here in detail, nor should they be considered as a limitation on the present disclosure.

[0119] Based on the same inventive concept, the embodiments of the present disclosure provide a manufacturing method of the above-mentioned array substrate. Since the problem-solving principle of the manufacturing method is similar to that of the above-mentioned array substrate, the implementation of the manufacturing method provided by the embodiments of the present disclosure can be referred to the implementation of the above-mentioned array substrate provided by the embodiments of the present disclosure, and the repeated parts will not be described here again.

[0120] In some embodiments, FIG. 15 shows a flowchart of the above-mentioned manufacturing method provided by the present disclosure. As shown in FIG. 15, the manufacturing method of the above-mentioned array substrate provided by the embodiments of the present disclosure can include the following steps:

[0121] S1501, providing a substrate substrate;

[0122] S1502, patterning to form a plurality of transistors on the substrate substrate;

[0123] S1503, patterning to form a second insulating layer including a second via on the layer where the plurality of transistors are located, the second via and the first electrode of the transistor overlap each other;

[0124] S1504. Forming a first insulating layer including a first via on the second insulating layer, the first via and the first electrode of the transistor mutually overlap and communicate with the second via, and a partial orthogonal projection of the first via on the substrate substrate and a partial orthogonal projection of the second via on the substrate substrate mutually overlap;

[0125] S1505. Forming a plurality of pixel electrodes on the first insulating layer, the pixel electrodes are electrically connected to the first electrode of the transistor through the first via and the second via, and an orthogonal projection of the first via on the substrate substrate is arranged away from an orthogonal projection of the pixel electrode on the substrate substrate relative to an orthogonal projection of the second via on the substrate substrate.

[0126] In some embodiments, in the manufacturing method provided in the embodiments of the present disclosure, the step S1505 of forming a plurality of pixel electrodes can be implemented by the following manner:

[0127] forming a plurality of first sub-pixel electrodes by patterning;

[0128] forming a plurality of second sub-pixel electrodes on the layer where the first sub-pixel electrodes are located and electrically connected to the first sub-pixel electrodes, and a partial orthogonal projection of the second sub-pixel electrodes on the substrate substrate and a partial orthogonal projection of the first sub-pixel electrodes on the substrate substrate mutually overlap.

[0129] In some embodiments, in the manufacturing method provided in the embodiments of the present disclosure, after the step S1505 of forming a plurality of pixel electrodes, a first common electrode can be formed on the layer where the plurality of second sub-pixel electrodes are located, an orthogonal projection of the first common electrode on the substrate substrate and an orthogonal projection of the first sub-pixel electrodes on the substrate substrate have a first overlapping area, an orthogonal projection of the first common electrode on the substrate substrate and an orthogonal projection of the second sub-pixel electrodes on the substrate substrate have a second overlapping area, and the second overlapping area at most partially overlaps with the first overlapping area.

[0130] In some embodiments, in the manufacturing method provided in the embodiments of the present disclosure, the first common electrode formed on the layer where the plurality of second sub-pixel electrodes are located can be implemented by the following manner:

[0131] forming a first sub-common electrode on the layer where the plurality of second sub-pixel electrodes are located by patterning;

[0132] forming a second sub-common electrode offset relative to the first sub-common electrode and overlapping with the first sub-common electrode by patterning using a mask plate of the first sub-common electrode, and the second sub-common electrode and the first sub-common electrode jointly constitute the first common electrode.

[0133] In some embodiments, in the manufacturing method provided in the embodiments of the present disclosure, after the plurality of first sub-pixel electrodes are formed by patterning, and before the plurality of second sub-pixel electrodes are formed by patterning, a mask of the first insulating layer can be used to form a fourth insulating layer having a third via hole, so as to connect the first sub-pixel electrode and the second sub-pixel electrode through the third via hole.

[0134] It should be noted that, in the manufacturing method provided in the embodiments of the present disclosure, the patterning process involved in forming each layer structure can include some or all of the following processes: deposition, photoresist coating, mask plate masking, exposure, development, etching, and photoresist stripping, or can include other processes, and the specific processes for forming the required pattern in the actual manufacturing process are subject to the actual manufacturing process, which is not limited herein. For example, the post-baking process can be included after development and before etching. The deposition process can be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, which is not limited herein; and the etching can be dry etching or wet etching, which is not limited herein.

[0135] Based on the same inventive concept, the embodiments of the present disclosure provide a display panel. FIG. 16 is a structural schematic diagram of a display panel provided in an embodiment of the present disclosure. As shown in FIG. 16, the display panel of the present disclosure includes the array substrate 001 provided in the above embodiments of the present disclosure, and an opposite substrate 002 opposite to the array substrate 001. Since the display panel solves the problem by the similar principle as the array substrate, the implementation of the display panel can refer to the embodiments of the array substrate, and the repeated parts will not be described herein.

[0136] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the array substrate 001 can further include a gate line (Gate line) extending at the row gap of the pixel electrode 103, and the opposite substrate 002 can further include a black matrix (BM) covering the gate line (Gate line). Since the data line DL is shielded by the auxiliary electrode 119, the display panel of the present disclosure does not need to set a longitudinal black matrix to shield the data line DL, thereby effectively increasing the transmittance.

[0137] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 16, a liquid crystal layer 003 can also be arranged between the array substrate 001 and the opposite substrate 002, a first polarizer 004 can be arranged on the side of the array substrate 001 away from the opposite substrate 002, a second polarizer 005 can be arranged on the side of the opposite substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. It should be understood by those skilled in the art that other essential components in the display panel are also understood, and are not described here in detail, and should not be regarded as a limitation on the present disclosure.

[0138] Based on the same inventive concept, the embodiments of the present disclosure provide a display device. FIG. 17 is a structural schematic diagram of a display device provided in the embodiments of the present disclosure. As shown in FIG. 17, the display device provided in the embodiments of the present disclosure can include the above-mentioned display panel PNL provided in the embodiments of the present disclosure, and a backlight module BLU located on the light-in side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can include a lamp strip, a reflector sheet, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflector sheet, a diffusion plate, and a brightness enhancement film, etc., which are arranged in a stacked manner on the light-out side of the matrix light source, and the reflector sheet includes openings corresponding to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp strip and the lamp beads in the matrix light source can be light emitting devices (LEDs), such as quantum dot light emitting devices.

[0139] In some embodiments, the lamp beads can also be micro light emitting devices (such as Mini LED, Micro LED), etc. The micro light emitting devices in the order of sub-millimeter or even micrometer, like organic light emitting devices (OLED), are also self-luminous devices. Like organic light emitting devices, they have a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle. Moreover, since the inorganic light emitting devices emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared to organic light emitting devices that emit light based on organic matter. When the micro light emitting devices are used as a backlight source, they can achieve more precise dynamic backlight effects, effectively improve the brightness and contrast of the screen, and solve the glare phenomenon caused by traditional dynamic backlights between bright and dark areas of the screen, thereby optimizing the visual experience.

[0140] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a television, a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, the display device provided by the embodiments of the present disclosure can include more or fewer components, or combine certain components, or arrange different components.

[0141] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who are informed of the basic inventive concept can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0142] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The display panel comprises: a substrate; a plurality of pixel electrodes arranged in an array on the substrate; a plurality of transistors between the layer where the plurality of pixel electrodes are located and the substrate; a first insulating layer between the layer where the plurality of transistors are located and the layer where the plurality of pixel electrodes are located, the first insulating layer comprising a first via hole overlapping the first electrode of the transistor; a second insulating layer between the first insulating layer and the layer where the first electrode of the transistor is located, the second insulating layer comprising a second via hole overlapping the first electrode of the transistor and communicating with the first via hole; the pixel electrode is electrically connected to the first electrode of the transistor through the first via hole and the second via hole; and the orthogonal projection of the first via hole on the substrate is arranged away from the orthogonal projection of the second via hole on the substrate relative to the orthogonal projection of the pixel electrode on the substrate.

2. The array substrate of claim 1, wherein, The first insulating layer covers the sidewall of the second via hole covered by the pixel electrode.

3. The array substrate of claim 1 or 2, wherein, The orthogonal projection of the first via hole on the substrate overlaps the sidewall of the second insulating layer away from the pixel electrode.

4. The array substrate according to any one of claims 1 to 3, wherein, The bottom of the first via hole comprises a first boundary and a second boundary extending in the row direction, the orthogonal projection of the first boundary on the substrate is located on the side of the orthogonal projection of the second boundary on the substrate close to the orthogonal projection of the pixel electrode on the substrate; The bottom of the second via hole comprises a third boundary and a fourth boundary extending in the row direction, the orthogonal projection of the third boundary on the substrate is located on the side of the orthogonal projection of the fourth boundary on the substrate close to the orthogonal projection of the pixel electrode on the substrate; And the orthogonal projection of the first boundary on the substrate is located between the orthogonal projection of the third boundary on the substrate and the orthogonal projection of the fourth boundary on the substrate, the orthogonal projection of the fourth boundary on the substrate is located between the orthogonal projection of the first boundary on the substrate and the orthogonal projection of the second boundary on the substrate. The first via holes corresponding to the pixel electrodes in the same row communicate to form a first groove, and the second via holes corresponding to the pixel electrodes in the same row communicate to form a second groove.

5. The array substrate of claim 4, wherein, Further comprising a first common electrode on the side of the layer where the plurality of pixel electrodes are located away from the substrate; 6. The array substrate according to any one of claims 1 to 5, wherein, The pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode between the layer where the first sub-pixel electrode is located and the layer where the first common electrode is located, and the first sub-pixel electrode is electrically connected to the second sub-pixel electrode; The partial orthogonal projection of the first sub-pixel electrode on the substrate overlaps the partial orthogonal projection of the second sub-pixel electrode on the substrate. ​ The first sub-pixel electrode has a first overlapping area with the first common electrode on the substrate, and the second sub-pixel electrode has a second overlapping area with the first common electrode on the substrate, and the second overlapping area at most partially overlaps with the first overlapping area.

7. The array substrate of claim 6, wherein, A plurality of second common electrodes are further included between the first insulating layer and the second insulating layer, and the second common electrodes have projections on the substrate which cross the projections of the pixel electrodes on the substrate.

8. The array substrate of claim 7, wherein, The second common electrode has a third overlapping area with the first sub-pixel electrode on the substrate, and a fourth overlapping area with the second sub-pixel electrode on the substrate, and the third overlapping area at most partially overlaps with the fourth overlapping area.

9. The array substrate of claim 8, wherein, The third overlapping area is substantially located in the fourth overlapping area. The first common electrode includes a slit, and on one side of the extending direction of the slit, the first overlapping area substantially coincides with the second overlapping area, and on the other side of the extending direction of the slit, the first overlapping area is substantially located in the second overlapping area.

10. The array substrate of claim 8, wherein, The third overlapping area partially overlaps with the fourth overlapping area or is staggered with the fourth overlapping area. The first common electrode includes a slit, and the first overlapping area and the second overlapping area are located on both sides of the extending direction of the slit.

11. The array substrate of claim 9, wherein, The first common electrode is a single-layer structure, and the width of the slit is 2-3 μm.

12. The array substrate of claim 10, wherein, The first common electrode includes a first sub-common electrode and a second sub-common electrode which is in contact with and partially overlaps with the first sub-common electrode on the side away from the layer where the pixel electrode is located, and the width of the slit is 0.8-2 μm.

13. The array substrate according to any one of claims 9 to 12, wherein, The first sub-pixel electrode and the second sub-pixel electrode extend to the area where the slit is located. In the column direction, the length of the first sub-pixel electrode is greater than half the length of the slit, and the length of the second sub-pixel electrode is greater than the length of the slit.

14. The array substrate of any one of claims 7 to 13, wherein, The projection of the second common electrode on the substrate is located between the projections of the first via and / or the second via on the substrate in the column direction.

15. The array substrate according to any one of claims 7 to 14, wherein, Further comprising: A conductive pattern arranged in the same layer as the second electrode of the transistor, and the first common electrode is electrically connected with the second common electrode through the conductive pattern.

16. The array substrate according to any one of claims 6 to 15, wherein, The first sub-pixel electrode includes a pixel part and a lap part arranged integrally, wherein the lap part is located in the second via, the pixel part is located outside the second via, and the width of the lap part is smaller than the width of the pixel part.

17. The array substrate of claim 16, wherein, The first sub-pixel electrode further includes a transition part connecting the pixel part and the lap part, and in the direction from the pixel part to the lap part, the width of the transition part is reduced at least once, and the width of the transition part is greater than the width of the lap part and smaller than the width of the pixel part.

18. The array substrate of claim 17, wherein, The transition portion is located on a plane of the first insulating layer, and / or the transition portion is located on the first insulating layer at a sidewall of the second via.

19. The array substrate of any one of claims 6 to 18, wherein, A third insulating layer is further included, and the third insulating layer fills the first via and the second via. A projection of the second sub-pixel electrode on the substrate substrate partially overlaps with a projection of the first sub-pixel electrode on the substrate substrate of the previous row, and a projection of the second sub-pixel electrode on the substrate substrate partially overlaps with a projection of the second via on the substrate substrate of the previous row.

20. The array substrate of any one of claims 6 to 18, wherein, A fourth insulating layer is further included between the layer where the first sub-pixel electrode is located and the layer where the second sub-pixel electrode is located. The first sub-pixel electrode is electrically connected with the second sub-pixel electrode through a third via penetrating through the fourth insulating layer, and a projection of the third via on the substrate substrate is located within a projection of the second via on the substrate substrate.

21. The array substrate of claim 20, wherein, A first common electrode is further included on a side of the layer where the plurality of pixel electrodes are located away from the substrate substrate, and the first common electrode includes a slit. In the slit area: a length of the first sub-pixel electrode in the column direction is greater than half of a length of the slit in the column direction, and less than a length of the second sub-pixel electrode in the column direction, and the length of the second sub-pixel electrode in the column direction is less than the length of the slit in the column direction.

22. The array substrate of any one of claims 1 to 21, wherein, A data line, a first light shielding pattern and a second light shielding pattern are further included, wherein The first light shielding pattern is multiplexed as a bottom gate of the transistor, and a projection of the first light shielding pattern on the substrate substrate covers a channel region of the active layer of the transistor. A second electrode of the first transistor is multiplexed as the data line, and a fifth insulating layer is arranged between the layer where the data line is located and the active layer of the transistor, and the data line is electrically connected with the active layer of the transistor through a fourth via penetrating through the fifth insulating layer. The second light shielding pattern is located on a side of the layer where the first light shielding pattern is located close to the substrate substrate, and a projection of the second light shielding pattern on the substrate substrate covers a projection of the fourth via on the substrate substrate. An adapter electrode and a color resist layer are further included, wherein the adapter electrode is located between the active layer of the transistor and the second insulating layer, and the adapter electrode is multiplexed as the first electrode of the transistor, and the color resist layer is located between the layer where the adapter electrode is located and the second insulating layer.

23. The array substrate of any one of claims 1-22, wherein, The array substrate as claimed in any one of claims 1-23 is included, and a counter substrate is arranged opposite to the array substrate.

24. A display panel, wherein, The display panel as claimed in claim 24 is included, and a backlight module is arranged on a light-incident side of the display panel.

25. A display device comprising: ​

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