Display panel and display apparatus

Abstract

The embodiments of the present invention relate to the field of display and improve the circuit performance of pixel circuits. Provided are a display panel and a display apparatus. The display panel comprises: pixel circuits, each of which comprises a drive transistor and a first transistor, wherein an active layer of each first transistor comprises a metal oxide semiconductor material; circuit columns; a plurality of first circuit groups, wherein each first circuit group comprises two circuit columns, and in each first circuit group, the first transistors in two pixel circuits, which are adjacent in a first direction, are adjacent; data lines, which comprise first data lines and second data lines; and power signal lines, wherein with regard to the first data line, second data line and power signal line connected to a single circuit column, the first data line and the second data line are both located on the side of the drive transistor that is away from the first transistor in the circuit column, the power signal line is located on the side of the first data line and second data line that is close to the first transistor in the circuit column, and the power signal line overlaps with a connection line between the drive transistor and the first transistor, and the first transistor.

Description

Display panel and display device

[0001] This invention claims priority to Chinese Patent Application No. 202411046463.1, filed with the State Intellectual Property Office of China on July 31, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] The display panel includes pixel circuitry and light-emitting elements. The pixel circuitry provides driving current to the light-emitting elements to drive them to emit light.

[0004] Pixel circuits consist of driving transistors and multiple switching transistors. To improve the leakage current problem of driving transistors, some switching transistors are typically made of metal-oxide-semiconductor transistors (MOSTs). However, the active layer of these transistors is susceptible to light exposure, which can generate free electrons, leading to a negative threshold voltage bias and consequently affecting the performance of the pixel circuit.

[0005] Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a display panel and a display device to improve the circuit performance of pixel circuits.

[0007] On one hand, embodiments of the present invention provide a display panel, including:

[0008] Substrate;

[0009] A pixel circuit includes a driving transistor and at least one first transistor, wherein the active layer of the first transistor comprises a metal-oxide-semiconductor material, and the gate of the driving transistor is electrically connected to the first transistor via a connection line.

[0010] A plurality of circuit columns arranged along a first direction, the circuit columns including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction;

[0011] A plurality of first circuit groups are arranged along the first direction, each first circuit group comprising two adjacent circuit columns, and in the first circuit group, the first transistors in two adjacent pixel circuits in the first direction are arranged adjacently.

[0012] The data line includes a first data line and a second data line, wherein one of the first data line and the second data line is electrically connected to an odd number of the pixel circuits in the circuit column, and the other is electrically connected to an even number of the pixel circuits in the circuit column.

[0013] The power signal line is electrically connected to the circuit array;

[0014] Specifically, for the first data line, the second data line, and the power signal line connected to a single circuit array, the first data line and the second data line are both located on the side of the circuit array away from the first transistor of the driving transistor, and the power signal line is located on the side of the first data line and the second data line close to the first transistor of the circuit array. Furthermore, in a direction perpendicular to the plane of the substrate, the power signal line overlaps with the connection line and the active layer of the first transistor, respectively.

[0015] On the other hand, embodiments of the present invention provide a display device including the above-described display panel.

[0016] One of the above technical solutions has the following beneficial effects:

[0017] This invention proposes a technical solution for dual-data-line panel structures with a large number of signal lines: by matching the arrangement of pixel circuits and data lines, the wiring design of power signal lines can be optimized, thereby using electrical signal lines to shield the metal-oxide transistor (first transistor) in the pixel circuit and the connection line connecting the metal-oxide transistor and the driving transistor.

[0018] Specifically, firstly, this embodiment of the invention adjusts the arrangement of pixel circuits in the two circuit columns of the first circuit group. By placing the first transistors of adjacent pixel circuits in the two circuit columns next to each other, the arrangement of the first transistors in these two adjacent pixel circuits can be more concentrated and closer to the interval area between the two circuit columns. Correspondingly, the distribution of connecting lines in the two pixel circuits is also more concentrated. Secondly, this embodiment of the invention places the first data line and the second data line connected to a single circuit column on the side of the circuit column away from the first transistor of the driving transistor. Thus, for a single first circuit group, the data lines corresponding to the two circuit columns are distributed on both sides and are far apart, thereby freeing up wiring space for power signal lines in the middle, so that the two power signal lines corresponding to the two circuit columns are located in the middle of the data lines on both sides. Furthermore, the power signal lines can better cover the first transistors and connecting lines.

[0019] Covering the first transistor with the power signal line reduces the risk of light shining onto the active layer of the first transistor, thus improving the device stability of the first transistor. Covering the connection line with the power signal line allows the stable power supply voltage on the power signal line to stabilize the gate potential of the driven transistor, thereby improving the voltage stability of the first node.

[0020] In summary, by matching the arrangement of pixel circuits and data lines, the embodiments of the present invention can free up more wiring space for power signal lines in complex dual-data-line panel structures, thereby providing more convenient conditions for shielding the first transistor and connecting lines, enabling better shielding of the first transistor and connecting lines, and optimizing the circuit performance of the pixel circuit. Attached Figure Description

[0021] Figure 1 is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of a data line, power signal line and light-emitting element provided in an embodiment of the present invention;

[0027] Figure 7 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0028] Figure 8 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0029] Figure 9 is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0030] Figure 10 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0031] Figure 11 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0032] Figure 12 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0033] Figure 13 is a timing diagram corresponding to the display panel provided in an embodiment of the present invention;

[0034] Figure 14 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0035] Figure 15 is a simplified structural schematic diagram of a display panel provided in an embodiment of the present invention;

[0036] Figure 16 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0037] Figure 17 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0038] Figure 18 is a simplified structural diagram of the display panel provided in an embodiment of the present invention;

[0039] Figure 19 is a simplified structural diagram of the display panel provided in an embodiment of the present invention;

[0040] Figure 20 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0041] Figure 21 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0042] Figure 22 is a simplified structural diagram of the display panel provided in an embodiment of the present invention;

[0043] Figure 23 is a schematic diagram of a data line, power signal line, data lead and light-emitting element provided in an embodiment of the present invention;

[0044] Figure 24 is another schematic diagram of the data line, power signal line, data lead and light-emitting element provided in the embodiment of the present invention;

[0045] Figure 25 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0046] Figure 26 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0047] Figure 27 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0048] Figure 28 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0049] Figure 29 is a cross-sectional view of Figure 28 along the A1-A2 direction;

[0050] Figure 30 is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0051] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0053] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0054] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0055] The present invention provides a display panel, as shown in Figures 1 to 3. Figure 1 is a schematic diagram of a structure of the display panel provided in the present invention, Figure 2 is a schematic diagram of a structure of a pixel circuit provided in the present invention, and Figure 3 is a schematic diagram of a film layer structure of the display panel provided in the present invention. The display panel includes a substrate 1, which can be a rigid substrate such as glass or a flexible substrate such as polyimide (PI).

[0056] The display panel also includes a pixel circuit 2. The pixel circuit 2 includes a driving transistor M0 and at least one first transistor M. The gate of the driving transistor M0 is electrically connected to the first transistor M via a connection line 3. The active layer of the first transistor M comprises a metal-oxide-semiconductor material, i.e., the first transistor M is a metal-oxide-semiconductor transistor. This type of transistor has low off-state leakage current, which can effectively improve the leakage current problem of the gate of the driving transistor M0, i.e., the first node N1. In this embodiment of the invention, the first transistor M can be an indium gallium zinc oxide (IGZO) transistor. Optionally, the metal-oxide-semiconductor layer may also contain indium, gallium, zinc, tin, and oxygen; optionally, the metal-oxide-semiconductor layer may also include binary compounds (ABx), ternary compounds (ABxCy), and quaternary compounds (ABxCyDz) containing, for example, indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), and magnesium (Mg).

[0057] The display panel also includes a plurality of circuit columns 4 arranged along a first direction x, and the circuit columns 4 include a plurality of pixel circuits 2 arranged along a second direction y, wherein the first direction x and the second direction y intersect.

[0058] The display panel also includes a plurality of first circuit groups 5 arranged along a first direction x. Each first circuit group 5 includes two adjacent circuit columns 4. Furthermore, in each first circuit group 5, the first transistors M in two adjacent pixel circuits 2 along the first direction x are arranged adjacently. In this embodiment of the invention, two adjacent pixel circuits 2 in the first circuit group 5 along the first direction x can be symmetrically arranged along a second direction y, thereby bringing the first transistors M in these two pixel circuits 2 closer to each other.

[0059] The display panel also includes a data line Data, including a first data line Data1 and a second data line Data2, wherein one of the first data line Data1 and the second data line Data2 is electrically connected to the odd-numbered pixel circuit 2 in the circuit column 4, and the other is electrically connected to the even-numbered pixel circuit 2 in the circuit column 4.

[0060] The display panel also includes a power signal line PVDD, which is electrically connected to circuit array 4. Specifically, one power signal line is electrically connected to multiple pixel circuits 2 in one circuit array 4.

[0061] Specifically, for the first data line Data1, the second data line Data2, and the power signal line PVDD connected to a single circuit array 4, both the first data line Data1 and the second data line Data2 are located on the side of the driving transistor M0 in circuit array 4 away from the first transistor M, while the power signal line PVDD is located on the side of the first data line Data1 and the second data line Data2 closer to the first transistor M in circuit array 4. It can be understood that the first data line and the second data line are both located on the same side of the power signal line.

[0062] Furthermore, in the direction perpendicular to the plane of substrate 1, the power signal line PVDD overlaps with the active layer of the connecting line 3 and the first transistor M, respectively.

[0063] This invention proposes a technical solution for dual-data-line panel structures with a large number of signal lines:

[0064] By matching the layout of the pixel circuit 2 and the data line Data, the wiring design of the power signal line PVDD can be optimized, thereby enabling the electrical signal line to block the metal oxide transistor (first transistor M) in the pixel circuit 2 and the connection line 3 connecting the metal oxide transistor and the driving transistor M0.

[0065] Specifically, firstly, this embodiment of the invention adjusts the arrangement of pixel circuits 2 in the two circuit columns 4 of the first circuit group 5. By arranging the first transistors M of adjacent pixel circuits 2 in the two circuit columns 4 adjacent to each other, the first transistors M in these two adjacent pixel circuits 2 can be arranged more densely and closer to the interval area between the two circuit columns 4. Correspondingly, the distribution of connecting lines 3 in the two pixel circuits 2 is also more dense. Then, this embodiment of the invention places the first data line Data1 and the second data line Data2 connected to a single circuit column 4 on the side of the circuit column 4 away from the first transistor M0. In this way, for a single first circuit group 5, the data lines Data corresponding to the two circuit columns 4 will be distributed on both sides and far apart, thereby freeing up wiring space for the power signal line PVDD in the middle position, so that the two power signal lines PVDD corresponding to the two circuit columns 4 are located in the middle of the data lines Data on both sides. Furthermore, the power signal line PVDD can better cover the first transistor M and the connecting line 3.

[0066] The power signal line PVDD covers the first transistor M, which can reduce the risk of light shining on the active layer of the first transistor M and improve the device stability of the first transistor M; the power signal line PVDD covers the connection line 3, which can use the stable power supply voltage on the power signal line PVDD to stabilize the gate potential of the transistor M0, thereby improving the voltage stability of the first node N1.

[0067] In summary, by matching the arrangement of the pixel circuit 2 and the data line Data, the embodiments of the present invention can free up more wiring space for the power signal line PVDD in the complex double data line panel structure, thereby providing more convenient conditions for it to shield the first transistor M and the connecting line 3, so as to better shield the first transistor M and the connecting line 3 and optimize the circuit performance of the pixel circuit 2.

[0068] In one feasible implementation, as shown in FIG4, FIG4 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention. The power signal line PVDD includes a first line segment 6 and a second line segment 7 that are alternately arranged and sequentially connected in the second direction y. Along the first direction x, the width of the first line segment 6 is smaller than the width of the second line segment 7. In the direction perpendicular to the plane where the substrate 1 is located, the second line segment 7 overlaps with the active layer of the connecting line 3 and the first transistor M respectively.

[0069] In the two power signal lines PVDD connected to the first circuit group 5, the second segment 7 of the two power signal lines PVDD is connected.

[0070] Since the voltage on the power signal lines PVDD is consistent, there is no need to consider short circuit issues between the power signal lines PVDD. Therefore, when the two power signal lines PVDD corresponding to the first circuit group 5 are arranged adjacently, the two power signal lines PVDD can be connected to each other, thereby giving them a larger shielding area to better shield the first transistor M and shield the first node N1. At the same time, it can also reduce the voltage drop of the power signal lines PVDD and ensure the display effect of the display panel.

[0071] Furthermore, in this embodiment of the invention, the power signal line PVDD is not directly designed as a thick signal line of equal width. Instead, a design is adopted in which a narrower first segment 6 and a wider second segment 7 are arranged alternately. In this way, while using the wider second segment 7 to achieve the purpose of shielding the first transistor M and shielding the first node N1, a portion of space can be freed up on one side of the first segment 6 so that some other traces on the same layer can be set at that position, thus optimizing the layout design.

[0072] In one feasible implementation, as shown in FIG5, FIG5 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention. The display panel further includes a plurality of light-emitting elements 8, including a green light-emitting element 8-G. In a direction perpendicular to the plane of the substrate 1, the green light-emitting element 8-G overlaps with the two power signal lines PVDD connected to the first circuit group 5.

[0073] Green light is brighter and has a more significant impact on display performance. Therefore, in this embodiment of the invention, the green light-emitting element 8-G is placed in the wiring area where the power signal line PVDD is located. This allows the overlap between the power signal line PVDD and the anode of the green light-emitting element 8-G to shield the anode potential of the green light-emitting element 8-G from interference from other signals, making the potential of this part of the anode more stable and thus improving the luminous effect of the green light-emitting element 8-G.

[0074] In addition, the power signal line PVDD has a large line width. Therefore, when the metal layer where the power signal line PVDD is located is close to the metal layer where the anode of the light-emitting element 8 is located, the green light-emitting element 8-G is placed above the power signal line PVDD. The power signal line PVDD also plays a certain role in improving the flatness of the anode of the green light-emitting element 8-G.

[0075] Furthermore, referring to Figure 4 and again to Figure 5, in the direction perpendicular to the plane of the substrate 1, the green light-emitting element 8-G overlaps with the second segment 7 in the power signal line PVDD, thereby increasing the overlap area between the power signal line PVDD and the green light-emitting element 8-G, further shielding the interference of other signals on the anode signal of the green light-emitting element 8-G, and improving the light-emitting reliability of the green light-emitting element 8-G.

[0076] In one feasible implementation, as shown in FIG6, FIG6 is a schematic diagram of a data line Data, a power signal line PVDD and a light-emitting element 8 provided in an embodiment of the present invention. The light-emitting element 8 further includes a red light-emitting element 8-R and a blue light-emitting element 8-B.

[0077] The display panel also includes a first light-emitting element group 9 and a second light-emitting element group 10 arranged alternately along a first direction x. The first light-emitting element group 9 includes red light-emitting elements 8-R and blue light-emitting elements 8-B arranged alternately along a second direction y, and the second light-emitting element group 10 includes green light-emitting elements 8-G arranged along the second direction y. More specifically, in one arrangement, in adjacent first light-emitting element groups 9, the red light-emitting element 8-R of one first light-emitting element group 9 is aligned with the blue light-emitting element 8-B of the other first light-emitting element group 9.

[0078] In the direction perpendicular to the plane of substrate 1, the two power signal lines PVDD connected to the second light-emitting element group 10 and the first circuit group 5 overlap, and the first light-emitting element group 9 overlaps with the four adjacent data lines Data of the unspaced driving transistor M0. The four adjacent data lines Data of the unspaced driving transistor M0 refer to the four data lines Data corresponding to the two closest circuit columns 4 in two adjacent first circuit groups 5.

[0079] With the green light-emitting element 8-G overlapping with the power signal line PVDD, the red light-emitting element 8-R and the blue light-emitting element 8-B further overlap with the four adjacent data lines Data of the unspaced driving transistor M0. On the one hand, this makes the overlap of the light-emitting element 8 with the data lines Data and the power signal line PVDD more regular. On the other hand, when the metal layer where the data line Data is located is relatively close to the metal layer where the anode is located, these four adjacent data lines Data can also have a certain effect on the flatness of the anode of the red light-emitting element 8-R and the blue light-emitting element 8-B.

[0080] In one feasible implementation, the display panel of the present invention may further employ a design that arranges a portion of the fanout lines in the display area (Fanout in AA, FIAA):

[0081] As shown in Figure 7, which is another structural schematic diagram of the display panel provided in an embodiment of the present invention, the display panel further includes a display area 11 and a first non-display area 12. The display area 11 includes a first display area 13 and a second display area 14. The first display area 13 is located on at least one side of the second display area 14 in the first direction x, that is, the first display area 13 is closer to the outer edge of the display panel and is an edge display area. Optionally, the sum of the number of data lines in the first display area 13 can be substantially the same as the sum of the number of data lines in the second display area 14. Optionally, the sum of the number of data lines in the first display area 13 is M, and the sum of the number of data lines in the second display area 14 is N, where 0.8 ≤ M / N ≤ 1.5. Optionally, M / N can be 1, 1.2, 1.25, 1.3, etc.

[0082] The first non-display area 12 includes multiple data connection lines 15, which are electrically connected to the data line Data.

[0083] In the first display area 13, the data line Data is electrically connected to the data connection trace 15 via data lead 16. The data lead 16 includes a first data lead 17 and a second data lead 18. The first data lead 17 extends along a first direction x, and the second data lead 18 extends along a second direction y. Optionally, the data lead 16 may also include multiple first data leads 17 extending along the first direction x and multiple second data leads 18 extending along the second direction y.

[0084] In the above structure, the data line Data in the edge display area can be led to the middle display area through the data lead 16, and then the data lead 16 connected to this part of the data line Data is led out from the lower middle position of the display area 11, so as to avoid this part of the data connection line 15 occupying a large space in the corner bezel, which helps to optimize the narrow bezel design.

[0085] It should be noted that the extension of the trace along the first direction x or the second direction y in the embodiments of the present invention refers only to one extension direction of the trace as a whole. Specifically, the trace may extend in a straight line in this direction or it may extend in a broken line in this direction.

[0086] In one feasible implementation, as shown in Figures 8 and 9, Figure 8 is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention, and Figure 9 is a schematic diagram of a cross-sectional structure of the display panel provided in an embodiment of the present invention. The display panel includes a source / drain layer sd1, a first wiring layer sd2, and a second wiring layer sd3. The first wiring layer sd2 is located on the side of the source / drain layer sd1 away from the substrate 1, and the second wiring layer sd3 is located on the side of the first wiring layer sd2 away from the substrate 1.

[0087] Among them, the connecting line 3 is located in the source-drain layer sd1, the data line Data and the power signal line PVDD are located in the first wiring layer sd2, and the data lead 16 is located in the second wiring layer sd3.

[0088] It should be noted that the doped regions of the active layer in a transistor are typically led out to the upper metal layer via connection electrodes, and then electrically connected to other structures such as wiring. The source-drain layer sd1 is the metal layer used to form the connection electrodes in the display panel.

[0089] In the above structure, the first data lead 17 and the second data lead 18 of data lead 16 are both arranged in the second wiring layer sd3, and the data line Data and the power signal line PVDD are arranged in the first wiring layer sd2. On the one hand, the second wiring layer sd3 is closer to the source-drain layer sd1, so the power signal line PVDD can be closer to the active layer of the first transistor M and to the connecting line 3, thereby improving the light-shielding effect of the power signal line PVDD on the first transistor M and the shielding effect on the first node N1. On the other hand, the first data lead 17 and the second data lead 18 of data lead 16 are located on the same layer, and the first data lead 17 and the second data lead 18 do not need to be connected by vias, reducing the number of vias.

[0090] In one possible implementation, referring again to FIG7, the data line Data is electrically connected to the first data lead 17 via a first via 21.

[0091] The four adjacent data lines Data of the uninterrupted driving transistor M0 form a data line group 50, and the four first vias 21 connected to a data line group 50 form a via group 22.

[0092] Along the direction from the first display area 13 to the second display area 14, the distance between the plurality of via groups 22 and the first edge 23 decreases, while the distance between the first via 21 in a single via group 22 and the first edge 23 increases. The first edge 23 is an outer edge of the display panel extending along the first direction x.

[0093] Based on this via arrangement, the data leads 16 connected to multiple data lines Data in the first display area 13 can avoid each other, thus preventing short circuits.

[0094] In one feasible implementation, as shown in FIG10, FIG10 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention. The second data lead 18 includes the first lead 20. In the direction perpendicular to the plane of the substrate 1, the first lead 20 overlaps with the data line Data. At this time, the wiring space occupied by the first lead 20 is almost the same as the wiring space occupied by the data line Data, which can reduce the overall reflectivity of the display panel.

[0095] Furthermore, as shown in FIG11, FIG11 is another structural schematic diagram of the display panel provided in the embodiment of the present invention. Among the four data lines Data connected by two adjacent circuit columns 4, at most two data lines Data overlap with the first lead 20.

[0096] The four adjacent data lines Data of the uninterrupted driving transistor M0 are arranged relatively densely. When at most two of the data lines Data connected to two adjacent circuit columns 4 overlap with the first lead 20, it means that at most two of the four densely arranged data lines Data also overlap with the first lead 20, thereby reducing the coupling between these data lines Data and the first lead 20 and reducing signal interference.

[0097] In one feasible implementation, to reduce the number of pins and lower costs, the display panel of the present invention can further adopt a Demux design:

[0098] As shown in Figure 12, Figure 12 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention. The display panel also includes multiple gating circuits 24 and 4m clock lines mux. The gating circuit 24 includes 4m gating switches 25, where m is a positive integer greater than or equal to 1.

[0099] In the gating circuit 24, the control terminals of 4m gating switches 25 are electrically connected to 4m clock lines mux, and the output terminals of 4m gating switches 25 are electrically connected to a source signal line source. The output terminals of 2m gating switches 25 are coupled to 2m first data lines Data1, and the output terminals of the other 2m second gating switches 25 are coupled to 2m second data lines Data2.

[0100] It should be noted that in the FIAA design, for the data lines Data in the second display area 14, these data lines Data can be directly connected to the corresponding selector switch 25 via the data connection trace 15. When the selector switch 25 is turned on, the signal on the source signal line source is transmitted to the data line Data via the selector switch 25 and the data connection trace 15. However, for the data lines Data in the first display area 13, these data lines Data need to be connected to the data lead 16 first, and then connected to the corresponding selector switch 25 via the data connection trace 15. When the selector switch 25 is turned on, the signal on the source signal line source is transmitted to the data line Data via the selector switch 25, the data connection trace 15, and the data lead 16.

[0101] Furthermore, it should be noted that Figure 12 is only intended to illustrate the connection relationship between the data line Data and the gating circuit 24, and does not represent a limitation on the distribution position of the data lead 16.

[0102] The following embodiment of the present invention uses m=1 as an example to illustrate the working process of the display panel.

[0103] In the attached diagram, the four gating switches in the gating circuit 24 are represented by reference numerals 25-1 to 25-4, and the four clock lines are represented by reference numerals mux-1 to mux-4.

[0104] Referring to Figures 2, 12, and 13, Figure 13 is a timing diagram corresponding to a display panel provided in an embodiment of the present invention, wherein S1P_i in Figure 13 represents the signal provided by the third scan line S1P connected to the i-th row pixel circuit 2.

[0105] Before the scan signal S1P_1 corresponding to the first row pixel circuit 2 is set low, clock lines mux-1 and mux-2 are sequentially set low. When clock line mux-1 is low, the gating switch 25-1 is turned on, and the data voltage on the source signal line is written into the first data line Data1 coupled to the gating switch 25-1. Then, when clock line mux-2 is low, the gating switch 25-2 is turned on, and the data voltage on the source signal line is written into the first data line Data1 coupled to the gating switch 25-2. Consequently, when the scan signal S1P_1 is low, the data voltage in this part of the first data line Data1 will be further written into the first row pixel circuit 2, thereby charging the first row pixel circuit 2.

[0106] Before the scan signal S1P_2 corresponding to the second row pixel circuit 2 is set low, clock lines mux-3 and mux-4 are sequentially set low. When clock line mux-3 is low, the gating switch 25-3 is turned on, and the data voltage on the source signal line is written into the second data line Data2 coupled to the gating switch 25-3. Then, when clock line mux-4 is low, the gating switch 25-4 is turned on, and the data voltage on the source signal line is written into the second data line Data2 coupled to the gating switch 25-4. Consequently, when the scan signal S1P_2 is low, the data voltage in this part of the second data line Data2 will be further written into the second row pixel circuit 2, thereby charging the second row pixel circuit 2.

[0107] Before the scan signal S1P_3 corresponding to the third row pixel circuit 2 is set low, clock lines mux-1 and mux-2 are sequentially set low. When clock line mux-1 is low, the gating switch 25-1 is turned on, and the data voltage on the source signal line is written into the first data line Data1 coupled to the gating switch 25-1. Then, when clock line mux-2 is low, the gating switch 25-2 is turned on, and the data voltage on the source signal line is written into the first data line Data1 coupled to the gating switch 25-2. Consequently, when the scan signal S1P_3 is low, the data voltage in this part of the first data line Data1 will be further written into the third row pixel circuit 2, thereby charging the pixel circuit 2 in that row.

[0108] Before the scan signal S1P_4 corresponding to the 4th row pixel circuit 2 is set low, clock lines mux-3 and mux-4 are sequentially set low. When clock line mux-3 is low, gating switch 25-3 is turned on, and the data voltage on the source signal line is written into the second data line Data2 coupled to gating switch 25-3. Then, when clock line mux-4 is low, gating switch 25-4 is turned on, and the data voltage on the source signal line is written into the second data line Data2 coupled to gating switch 25-4. Consequently, when the scan signal S1P_4 is low, the data voltage in this part of the second data line Data2 will be further written into the 4th row pixel circuit 2, realizing the charging of the pixel circuit 2 in this row.

[0109] And so on.

[0110] After the display panel adopts the Demux design, regarding the first lead 20, in one feasible implementation, as shown in Figure 14, Figure 14 is another structural schematic diagram of the display panel provided by the embodiment of the present invention. For the first lead 20 and the data line Data that overlaps with it, the gating switch 25 coupled to the two is electrically connected to the same clock line mux.

[0111] For a clearer illustration, please refer to Figure 15. Figure 15 is a simplified structural schematic diagram of a display panel provided in an embodiment of the present invention. In Figure 15, the clock line mux marked below the data line Data refers to the clock line mux connected to the selector switch 25 coupled to the data line Data. Specifically, the clock line mux corresponding to the data line Data in the first display area 13 refers to the clock line mux corresponding to the first lead 20 connected to the data line Data. It can be clearly seen in Figure 15 that the first lead 20 and the overlapping data line Data correspond to the same clock line mux.

[0112] Based on the foregoing explanation of the display panel's operation, when the selector switch 25 is turned on, the data voltage on the source signal line is further transmitted to the data line Data coupled to it via the selector switch 25. Since the selector switches 25 connected to the same clock line mux are simultaneously turned on and off, when the selector switches 25 coupled to the first lead 20 and its overlapping data line Data are connected to the same clock line mux, it means that the first lead 20 and its overlapping data line Data will simultaneously write data voltage and simultaneously stop writing data voltage, making the voltage transition times on these signal lines consistent. This reduces crosstalk between the first lead 20 and its overlapping data line Data, lowering their coupling effect.

[0113] Furthermore, for the first lead 20 and the data line Data that overlaps with it, the pixel circuit 2 coupled to them can be electrically connected to the light-emitting element of the same color. Thus, when the selection switch 25 is turned on, the first lead 20 and the data line Data transmit the data voltage required by the light-emitting element of the same color, which can further reduce the impact of coupling on the display effect.

[0114] For example, referring again to Figure 14, pixel circuit 2 includes a first pixel circuit 2-1, a second pixel circuit 2-2, and a third pixel circuit 2-3. The first pixel circuit 2-1 is electrically connected to the red light-emitting element 8-R (not shown in the figure), the second pixel circuit 2-2 is electrically connected to the green light-emitting element 8-G (not shown in the figure), and the third pixel circuit 2-3 is electrically connected to the blue light-emitting element 8-B (not shown in the figure). For easy distinction, the figure labels the first pixel circuit 2-1 as R, the second pixel circuit 2-2 as G, and the third pixel circuit 2-3 as B.

[0115] The multiple circuit columns 4 include a first sub-circuit column 4-1, a second sub-circuit column 4-2, a third sub-circuit column 4-3, and a fourth sub-circuit column 4-4 arranged alternately along a first direction x. The first sub-circuit column 4-1 includes a first pixel circuit 2-1 and a third pixel circuit 2-3 arranged alternately along a second direction y. The third sub-circuit column 4-3 includes a third pixel circuit 2-3 and a first pixel circuit 2-1 arranged alternately along the second direction y. Furthermore, the first pixel circuit 2-1 in the first sub-circuit column 4-1 and the third pixel circuit 2-3 in the third sub-circuit column 4-3 are aligned. The second sub-circuit columns 4-2 and 4-4 each include a second pixel circuit 2-2 arranged along the second direction y.

[0116] Wherein, at least a portion of the first lead 20 and the overlapping data line Data therewith are coupled to the first sub-circuit column 4-1, and / or, at least a portion of the first lead 20 and the overlapping data line Data therewith are coupled to the second sub-circuit column 4-2, and / or, at least a portion of the first lead 20 and the overlapping data line Data therewith are coupled to the third sub-circuit column 4-3, and / or, at least a portion of the first lead 20 and the overlapping data line Data therewith are coupled to the fourth sub-circuit column 4-3.

[0117] For a more specific structure of the first lead 20, please refer again to Figure 14. The first lead 20 includes a first sub-lead 26. The first sub-lead 26 is electrically connected to a first data line Data1 in the first display area 13 and overlaps with a first data line Data1 in the second display area 14. Furthermore, the gating switch 25 coupled to the first sub-lead 26 and the first data line Data1 that overlaps with it is electrically connected to the same clock line mux, thereby reducing the crosstalk between the first sub-lead 26 and the first data line Data1 that overlaps with it and reducing the coupling effect between the two.

[0118] And / or, the first lead 20 also includes a second sub-lead 27, which is electrically connected to a second data line Data2 in the first display area 13 and overlaps with a second data line Data2 in the second display area 14. The gating switch 25 coupled to the second sub-lead 27 and the overlapping second data line Data2 is electrically connected to the same clock line mux, thereby reducing crosstalk between the second sub-lead 27 and the overlapping second data line Data2 and reducing their coupling effect.

[0119] In one feasible implementation, as shown in FIG16, FIG16 is another structural schematic diagram of the display panel provided in the embodiment of the present invention. The second data lead 18 includes a second lead 28. The second lead 28 is located between adjacent data lines Data of the unspaced driving transistor M0. The second lead 28 does not overlap with the data line Data. The coupling between the second lead 28 and the data line Data is small, thus reducing the signal interference between them.

[0120] Furthermore, referring again to Figure 16, the second lead 28 is located between the first data line Data1 and the second data line Data2 connected in the same circuit column 4. In this way, for four adjacent data lines Data that are not separated by the driving transistor M0, there are at most two second leads 28 between these four data lines Data, thereby further reducing the coupling between the data lead 16 and the data lines Data.

[0121] In one feasible implementation, as shown in FIG17, FIG17 is another structural schematic diagram of the display panel provided in the embodiment of the present invention. The display panel further includes multiple gating circuits 24 and 4m clock lines mux. The gating circuits 24 include 4m gating switches 25, where m is a positive integer greater than or equal to 1.

[0122] In the gating circuit 24, the control terminals of 4m gating switches 25 are electrically connected to 4m clock lines mux, and the output terminals of 4m gating switches 25 are electrically connected to a source signal line source. The output terminals of 2m gating switches 25 are coupled to 2m first data lines Data1, and the output terminals of the other 2m second gating switches 25 are coupled to 2m second data lines Data2.

[0123] For the second lead 28 and one of its adjacent data lines, the gating switch 25 coupled to both is electrically connected to the same clock line mux.

[0124] For a clearer illustration, please refer to Figure 18. Figure 18 is a simplified structural diagram of the display panel provided in an embodiment of the present invention. In Figure 18, the clock line mux marked below the data line Data refers to the clock line mux connected to the selector switch 25 coupled to the data line Data. Specifically, the clock line mux corresponding to the data line Data in the first display area 13 also refers to the clock line mux corresponding to the second lead 28 connected to the data line Data. It can be clearly seen in Figure 18 that the second lead 28 and one of the adjacent data lines Data correspond to the same clock line mux.

[0125] Based on the foregoing explanation of the display panel's operation, when the selector switch 25 is turned on, the data voltage on the source signal line is transmitted to the data line Data coupled to it through the selector switch 25. Since multiple selector switches 25 connected to the same clock line mux are simultaneously turned on and off, when the selector switch 25 coupled to the second lead 28 and one of its adjacent data lines Data is connected to the same clock line mux, the second lead 28 and the data line Data will simultaneously write data voltage and simultaneously stop writing data voltage, making the voltage transition times on these signal lines consistent. This reduces crosstalk between the second lead 28 and its adjacent data line Data, lowering their coupling impact.

[0126] Furthermore, for the second lead 28 and one of the adjacent data lines Data, the pixel circuit 2 coupled to them can be electrically connected to the light-emitting element of the same color. Thus, when the selection switch 25 is turned on, the data voltage required by the light-emitting element of the same color is transmitted on the first lead 20 and the data line Data, which can further reduce the impact of coupling on the display effect.

[0127] It should be noted that, in the above embodiments, there are multiple ways to connect the data line Data to the gating switch 25 in the gating circuit 24.

[0128] For example, as shown in FIG19, FIG19 is a simplified structural schematic diagram of the display panel provided in an embodiment of the present invention. The circuit column 4 includes a first circuit column 31 and a second circuit column 32. The first data line Data1 connected to the first circuit column 31 is located on the side of the second data line Data2 close to the driving transistor M0. The second data line Data2 connected to the second circuit column 32 is located on the side of the first data line Data1 close to the driving transistor M0.

[0129] In the above structure, the data line group 50 includes an alternating first data line group 50-1 and a second data line group 50-2. Specifically, in the first data line group 50-1, the clock lines (mux) corresponding to the four data lines (Data) are arranged in the order of mux4-mux2-mux1-mux3, and in the second data line group 50-2, the clock lines (mux) corresponding to the four data lines (Data) are arranged in the order of mux2-mux4-mux3-mux1. This arrangement still allows the second lead 28 and the selector switch 25 coupled to one of its adjacent data lines (Data) to be electrically connected to the same clock line (mux).

[0130] In one feasible implementation, as shown in FIG20, FIG20 is another structural schematic diagram of the display panel provided in the embodiment of the present invention, wherein four adjacent data lines Data without spacing between the driving transistor M0 constitute a data line group 50.

[0131] The second data lead 18 includes a third lead 30, which is located on at least one side of the data line group 50, that is, the third lead 30 is located outside the four data lines Data of the unspaced driving transistor M0 in the middle.

[0132] Furthermore, as shown in Figure 21, which is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, the display panel also includes multiple gating circuits 24 and 4m clock lines mux. The gating circuit 24 includes 4m gating switches 25, where m is a positive integer greater than or equal to 1.

[0133] In the gating circuit 24, the control terminals of 4m gating switches 25 are electrically connected to 4m clock lines mux, and the output terminals of 4m gating switches 25 are electrically connected to a source signal line source. The output terminals of 2m gating switches 25 are coupled to 2m first data lines Data1, and the output terminals of the other 2m second gating switches 25 are coupled to 2m second data lines Data2.

[0134] In this embodiment of the invention, the circuit column 4 includes a first circuit column 31 and a second circuit column 32. The first data line Data1 connected to the first circuit column 31 is located on the side of the second data line Data2 close to the driving transistor M0, and the second data line Data2 connected to the second circuit column 32 is located on the side of the first data line Data1 close to the driving transistor M0.

[0135] Furthermore, the gating switch 25 coupled to the third lead 30 and its adjacent data line Data is electrically connected to the same clock line mux.

[0136] For a clearer illustration, please refer to Figure 22. Figure 22 is a simplified structural diagram of the display panel provided in an embodiment of the present invention. In Figure 22, the clock line mux marked below the data line Data refers to the clock line mux connected to the selector switch 25 coupled to the data line Data. Specifically, the clock line mux corresponding to the data line Data in the first display area 13 also refers to the clock line mux corresponding to the second lead 28 connected to the data line Data. It can be clearly seen in Figure 22 that the third lead 30 and the adjacent data line Data correspond to the same clock line mux.

[0137] By differentiating the arrangement of the data lines Data corresponding to the first circuit column 31 and the second circuit column 32, the data line Data corresponding to any clock line mux can be located on the outermost side of the data line group 50. This allows the third lead 30 corresponding to any clock line mux to be located next to the data line Data corresponding to the same clock line mux.

[0138] Among them, the data line Data corresponding to the clock line mux is the data line Data coupled to the selector switch 25 connected to the clock line mux, and the third lead 30 corresponding to the clock line mux is the third lead 30 coupled to the selector switch 25 connected to the clock line mux.

[0139] As can be seen from the above description of the operation process of the display panel, when the gating switch 25 coupled to the third lead 30 and the adjacent data line Data is electrically connected to the same clock line mux, it means that the voltage jumps on the third lead 30 and the adjacent data line Data are synchronized. This can reduce the crosstalk between the third lead 30 and the adjacent data line Data and reduce the coupling effect between the two.

[0140] More specifically, referring again to Figure 21, the third lead 30 includes a third sub-lead 33, which is electrically connected to the first data line Data1 and adjacent to another first data line Data1. Furthermore, for the two first data lines Data1 that are connected to and adjacent to the third sub-lead 33, the gating switch 25 connected to the two first data lines Data1 is electrically connected to the same clock line mux to reduce crosstalk between the third sub-lead 33 and the adjacent first data line Data1, thereby reducing their coupling effect.

[0141] And / or, the third lead 30 also includes a fourth sub-lead 34, which is electrically connected to the second data line Data2 and adjacent to another second data line Data2. Furthermore, for the two second data lines Data2 that are respectively connected to and adjacent to the fourth sub-lead 34, the gating switch 25 connected to the two second data lines Data2 is electrically connected to the same clock line mux to reduce crosstalk between the fourth sub-lead 34 and the adjacent second data line Data2 and reduce their coupling effect.

[0142] In one feasible implementation, as shown in FIG23, FIG23 is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. The display panel further includes a light-emitting element 8, which includes an anode 35. The display panel may also include a pixel definition layer (not shown in the figure). The pixel definition layer may at least partially cover the anode of the light-emitting element, and the pixel definition layer may include multiple openings that expose at least a portion of the anode. It is understood that the light-emitting material of the light-emitting element is at least partially located within the opening of the pixel definition layer corresponding to its anode.

[0143] The display panel also includes a first trace 36 and a second trace 37. The first trace 36 is disposed on the same layer as the first data lead 17 and extends in the same direction. The second trace 37 is disposed on the same layer as the second data lead 18 and extends in the same direction. Furthermore, there is a break 38 between the first trace 36 and the first data lead 17, and between the second trace 37 and the second data lead 18. Since the data lead 16 is usually only distributed in a local display area, the first trace 36 and the second trace 37 can also be disposed in areas other than the data lead 16 to improve etching uniformity in the manufacturing process.

[0144] The display panel also includes a shielding portion 39, which is on the same layer as and connected to the anode 35. Understandably, the shielding portion 39 does not overlap with the opening of the pixel definition layer of the light-emitting element. In the direction perpendicular to the plane of the substrate 1, the shielding portion 39 overlaps with the break 38 so that there is a metal film layer above the break 38 to improve the uniformity of reflection between the location of the break 38 and other locations.

[0145] In one feasible implementation, as shown in FIG24, FIG24 is another structural schematic diagram of the display panel provided in the embodiment of the present invention. The power signal line PVDD includes a first line segment 6 and a second line segment 7 that are alternately arranged and sequentially connected in the second direction y. In the direction perpendicular to the plane where the substrate 1 is located, the second line segment 7 overlaps with the active layer of the connecting line 3 and the first transistor M. Furthermore, the width of the second line segment 7 in the first direction x is greater than the width of the first line segment 6 in the first direction x.

[0146] For the two power signal lines PVDD connected to the first circuit group 5, a first auxiliary power line 40 is connected between the first segment 6 of the two power signal lines PVDD, and / or a second auxiliary power line 41 is connected in parallel on the first segment 6.

[0147] Because the first segment 6 in the power signal line PVDD is thinner, the load at that location differs from the load at the location of the second segment 7. By setting up a first auxiliary power line 40 and / or a second auxiliary power line 41, these auxiliary power lines can be used to reduce the load at the location of the first segment 6, thereby improving the load uniformity of the power signal line PVDD at different locations.

[0148] Furthermore, the first auxiliary power line 40 extends along the first direction x and can be disposed on the same layer as the first data lead 17; the second auxiliary power line 41 extends along the second direction y and can be disposed on the same layer as the second data lead 18. When both the first data lead 17 and the second data lead 18 are located on the second wiring layer sd3, the first auxiliary power line 40 and the second auxiliary power line 41 are also located on the second wiring layer sd3.

[0149] In one feasible implementation, referring to FIG2, and as shown in FIG25 to FIG27, FIG25 is a schematic diagram of another structure of the display panel provided in the embodiment of the present invention, FIG26 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and FIG27 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention. The first transistor M includes a gate reset transistor M1, which is electrically connected between the first reset line Ref1 and the gate of the driving transistor M0.

[0150] In this circuit, a first circuit group 5 is provided with a first reset line Ref1. The first reset line Ref1 extends along the second direction y and is disposed on the same layer as the connecting line 3. The first poles of two adjacent gate reset transistors M1 in the first circuit group 5 in the first direction x are connected to the corresponding first reset line Ref1.

[0151] Because the first transistors M in the two circuit columns 4 of the first circuit group 5 are arranged adjacently, even if only a vertically extending first reset line Ref1 is set for these two circuit columns 4, the first reset line Ref1 can be easily connected to the first transistors M in these two circuit columns 4, which greatly saves the number of first reset lines Ref1 required in the display panel and optimizes the layout design.

[0152] Furthermore, since the data line and the power signal line PVDD are located in a large number of film layers, the first reset line Ref1 can be set to be on the same layer as the connecting line 3, so that it does not occupy the wiring space of the first wiring layer sd2. When designing the power signal line PVDD, its line width does not need to take into account the influence of the first reset line Ref1, so that the power signal line PVDD can be designed to be wider to better shield the connecting line 3 and the first transistor M.

[0153] In one feasible implementation, referring to Figures 2, 25 to 27, the pixel circuit 2 further includes an anode reset transistor M6, which is electrically connected between the second reset line Ref2 and the light-emitting element 8. The second reset line Ref2 includes a first sub-reset line Ref21 and a second sub-reset line Ref22 that are electrically connected. The first sub-reset line Ref21 extends along a first direction x, and the second sub-reset line Ref22 is connected between two adjacent first sub-reset lines Ref21.

[0154] The pixel circuit 2 also includes a bias transistor M7, which is electrically connected between the bias signal line DVH and the driving transistor M0. The bias signal line DVH includes a first sub-bias line DVH1 and a second sub-bias line DVH2. The first sub-bias line DVH1 extends along a first direction x, and the second sub-bias line DVH2 is connected between two adjacent first sub-bias lines DVH1.

[0155] The second sub-reset line Ref22 and the second sub-bias line DVH2 are arranged on the same layer. Along the first direction x, the second sub-reset line Ref22 and the second sub-bias line DVH2 are arranged alternately. Along the second direction y, the second sub-reset line Ref22 and the second sub-bias line DVH2 are arranged alternately.

[0156] In the above configuration, both the second reset line Ref2 and the bias signal line DVH adopt a dual-line design, which can effectively reduce their respective loads.

[0157] Furthermore, this embodiment of the invention also includes a matching design for the longitudinally extending traces in the second reset line Ref2 and the bias signal line DVH. The longitudinally extending traces in the second reset line Ref2 and the bias signal line DVH are on the same layer and are alternately arranged in both the first direction x and the second direction y. That is, the longitudinally extending traces in the second reset line Ref2 and the bias signal line DVH are not a single trace running through the display area 11, but rather a structure of multiple trace segments. This saves the overall space occupied by the longitudinal traces in both signal lines, achieving the goal of reducing load while optimizing the trace layout.

[0158] Furthermore, referring to Figures 2 and 25-27, the first transistor M includes a gate reset transistor M1, which is electrically connected between the first reset line Ref1 and the gate of the driving transistor M0; a first circuit group 5 is provided with a corresponding first reset line Ref1, which extends along the second direction y and is disposed on the same layer as the connecting line 3, and the first poles of two adjacent gate reset transistors M1 in the first circuit group 5 in the first direction x are connected to the corresponding first reset line Ref1.

[0159] The first reset line Ref1, the second sub-reset line Ref22, and the second sub-bias line DVH2 are arranged on the same layer. There is a first reset line Ref1 between the two adjacent second sub-reset lines Ref22 and second sub-bias line DVH2 in the first direction x. A reasonable routing method is assigned to the first reset line Ref1, the second reset line Ref2, and the bias signal line DVH, thus optimizing the layout design.

[0160] In one feasible implementation, referring to Figures 2, 25 to 27, and as shown in Figures 28 and 29, Figure 28 is a schematic diagram of another film layer structure of the display panel provided in the embodiment of the present invention, and Figure 29 is a cross-sectional view of Figure 28 along the A1-A2 direction. The pixel circuit 2 further includes a storage capacitor Cst, and the first plate c1 of the storage capacitor Cst is multiplexed with the gate of the driving transistor M0.

[0161] Among them, the first sub-reset line Ref21 is set on the same layer as the second plate c2 of the storage capacitor Cst, the first sub-bias line DVH1 is set on the same layer as the top gate of the first transistor M, and the second sub-reset line Ref22 and the second sub-bias line DVH2 are set on the same layer as the connecting line 3.

[0162] The metal layers containing the second plate c2 of the storage capacitor Cst and the top gate of the first transistor M have relatively few wirings. By placing the first sub-reset line Ref21 and the first sub-bias line DVH1 in these two metal layers respectively, a rational design of the overall wiring can be achieved. At the same time, the second sub-reset line Ref22 and the second sub-bias line DVH2 are set in the same layer as the connecting line 3, and they do not require additional film layers, resulting in better wiring.

[0163] In one feasible implementation, referring to Figures 2 and 28, the pixel circuit 2 further includes a storage capacitor Cst, the first plate c1 of which is multiplexed with the gate of the driving transistor M0.

[0164] The first transistor M includes a gate reset transistor M1, the gate of which is electrically connected to a first scan line S1N. The gate of the gate reset transistor M1 may include a top gate and a bottom gate. The first scan line S1N includes a first sub-scan line S1N1 and a second sub-scan line S1N2 extending along a first direction x and electrically connected. The first sub-scan line S1N1 is disposed on the same layer as the second plate c2 of the storage capacitor Cst. A portion of the second sub-scan line S1N2 is multiplexed as the top gate of the gate reset transistor M1. The first sub-scan line S1N1 and the second sub-scan line S1N2 overlap in a direction perpendicular to the plane of the substrate 1.

[0165] And / or, the first transistor M includes a threshold compensation transistor M3, the gate of which is electrically connected to the second scan line S2N. The gate of the threshold compensation transistor M3 may include a top gate and a bottom gate. The second scan line S2N includes a third sub-scan line S2N1 and a fourth sub-scan line S2N2 extending along a first direction x and electrically connected. The third sub-scan line S2N1 is disposed on the same layer as the second plate c2 of the storage capacitor Cst. A portion of the fourth sub-scan line S2N2 is multiplexed as the top gate of the threshold compensation transistor M3. The third sub-scan line S2N1 and the fourth sub-scan line S2N2 overlap in a direction perpendicular to the plane of the substrate 1.

[0166] In the above configuration, both the first scan line S1N and the second scan line S2N are double-layered, which helps to reduce the load on these two scan lines and reduce voltage drop.

[0167] The following description uses the circuit structure shown in Figure 2 as an example to illustrate a specific structure of the pixel circuit 2 provided in this embodiment of the invention.

[0168] Pixel circuit 2 includes:

[0169] A driving transistor M0 is used. The gate of the driving transistor M0 is electrically connected to the first node N1, the first terminal of the driving transistor M0 is electrically connected to the second node N2, and the second terminal of the driving transistor M0 is electrically connected to the third node N3.

[0170] Gate reset transistor M1 has its first terminal electrically connected to the first scan line S1N, its second terminal electrically connected to the first reset line Ref1, and its second terminal electrically connected to the first node N1.

[0171] The data writing transistor M2 has its gate electrically connected to the third scan line S1P, its first terminal electrically connected to the data line Data, and its second terminal electrically connected to the second node N2.

[0172] Threshold compensation transistor M3 has its gate electrically connected to the second scan line S2N, its first terminal electrically connected to the third node N3, and its second terminal electrically connected to the first node N1.

[0173] The first light-emitting control transistor M4 has its gate electrically connected to the light-emitting control signal line Emit, its first terminal electrically connected to the power supply signal line PVDD, and its second terminal electrically connected to the second node N2.

[0174] The second light-emitting control transistor M5 has its gate electrically connected to the light-emitting control signal line Emit, its first electrode electrically connected to the third node N3, and its second electrode electrically connected to the light-emitting element 8.

[0175] The anode reset transistor M6 has its gate electrically connected to the fourth scan line S2P, its first electrode electrically connected to the second reset line Ref2, and its second electrode electrically connected to the light-emitting element 8.

[0176] Bias transistor M7 has its gate electrically connected to the fourth scan line S2P, its first terminal electrically connected to the bias signal line DVH, and its second terminal electrically connected to the second node N2.

[0177] The storage capacitor Cst has its first plate C1 electrically connected to the first node N1 and its second plate C2 electrically connected to the power signal line PVDD.

[0178] Based on the same inventive concept, this invention also provides a display device, as shown in FIG30. FIG30 is a schematic diagram of the structure of the display device provided in this invention, which includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, the display device shown in FIG30 is merely illustrative; the display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader, or television.

[0179] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a pixel circuit comprising a driving transistor and at least one first transistor, wherein an active layer of the first transistor comprises a metal oxide semiconductor material, and a gate of the driving transistor is electrically connected to the first transistor through a connection line; a plurality of circuit columns arranged along a first direction, each of the circuit columns comprising a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; a plurality of first circuit groups arranged along the first direction, each of the first circuit groups comprising two adjacent circuit columns, and in each of the first circuit groups, the first transistors in two adjacent pixel circuits along the first direction are arranged adjacently; data lines comprising a first data line and a second data line, one of the first data line and the second data line being electrically connected to odd-numbered pixel circuits in the circuit columns, and the other being electrically connected to even-numbered pixel circuits in the circuit columns; a power signal line electrically connected to the circuit columns; wherein for the first data line, the second data line and the power signal line connected to a single circuit column, the first data line and the second data line are located on a side of the driving transistor in the circuit column away from the first transistor, and the power signal line is located on a side of the first data line and the second data line close to the first transistor in the circuit column, and in a direction perpendicular to a plane where the substrate is located, the power signal line overlaps the connection line and the active layer of the first transistor respectively.

2. The display panel of claim 1, wherein the power signal line comprises a first line segment and a second line segment arranged alternately in the second direction and connected sequentially, and in a direction perpendicular to a plane where the substrate is located, the second line segment overlaps the connection line and the active layer of the first transistor respectively; in the two power signal lines connected to the first circuit group, the second line segments of the two power signal lines are arranged in communication.

3. The display panel of claim 1, wherein the display panel further comprises a plurality of light emitting elements, and the light emitting elements comprise green light emitting elements; in a direction perpendicular to a plane where the substrate is located, the green light emitting elements overlap the two power signal lines connected to the first circuit group.

4. The display panel of claim 3, wherein the power signal line comprises a first line segment and a second line segment arranged alternately in the second direction and connected sequentially, and a width of the second line segment in the first direction is greater than a width of the first line segment in the first direction; in a direction perpendicular to a plane where the substrate is located, the green light emitting elements overlap the second line segment.

5. The display panel of claim 3, wherein the light emitting elements further comprise red light emitting elements and blue light emitting elements. The display panel further comprises a first light emitting element group and a second light emitting element group arranged alternately along the first direction, the first light emitting element group comprises the red light emitting element and the blue light emitting element arranged alternately along the second direction, and the second light emitting element group comprises the green light emitting element arranged along the second direction; In a direction perpendicular to a plane where the substrate is located, the second light emitting element group overlaps with two power signal lines connected by the first circuit group, and the first light emitting element group overlaps with four adjacent data lines which are not spaced from the driving transistor.

6. The display panel of claim 1, wherein the display panel further comprises a display area and a first non-display area, the display area comprises a first display area and a second display area, the first display area is located at least one side of the second display area in the first direction, and the first non-display area comprises a plurality of data connection wires, and the data connection wires are electrically connected with the data lines. In the first display area, the data lines are electrically connected with the data connection wires through data leads, the data leads comprise first data leads and second data leads, the first data leads extend along the first direction, and the second data leads extend along the second direction.

7. The display panel of claim 6, wherein the display panel comprises a source-drain layer, a first wiring layer and a second wiring layer, the first wiring layer is located on a side of the source-drain layer away from the substrate, and the second wiring layer is located on a side of the first wiring layer away from the substrate. In the source-drain layer, the data lines and the power signal lines are located in the first wiring layer, and the data leads are located in the second wiring layer.

8. The display panel of claim 6, wherein the data lines are electrically connected with the first data leads through first vias. Four adjacent data lines which are not spaced from the driving transistor constitute a data line group, and four first vias connected by a data line group constitute a via group. In a direction from the first display area to the second display area, distances between a plurality of via groups and a first edge decrease, distances between the first vias in a single via group and the first edge increase, and the first edge is an outer edge of the display panel extending along the first direction.

9. The display panel of claim 6, wherein the second data leads comprise first leads, and in a direction perpendicular to a plane where the substrate is located, the first leads overlap with the data lines.

10. The display panel of claim 9, wherein in four data lines connected by two adjacent circuit columns, at most two data lines overlap with the first leads.

11. The display panel of claim 9, wherein the display panel further comprises a plurality of gate-on circuits and 4m clock lines, the gate-on circuit comprises 4m gate-on switches, and m is a positive integer greater than or equal to 1. ​ ​ ​ ​ ​ ​ ​ In the gate circuit, control terminals of the 4m gate switches are respectively electrically connected with the 4m clock lines, and output terminals of the 4m gate switches are electrically connected with a source signal line, wherein output terminals of 2m gate switches are respectively coupled with 2m first data lines, and output terminals of the other 2m second gate switches are respectively coupled with 2m second data lines. And for the first lead and the data line overlapping with the first lead, the gate switch coupled with the first lead and the data line is electrically connected with the same clock line.

12. The display panel of claim 6, wherein The second data lead includes a second lead, and the second lead is located between adjacent data lines which are not spaced by the driving transistor.

13. The display panel of claim 12, wherein The second lead is located between the first data line and the second data line connected by the same circuit column.

14. The display panel of claim 12, wherein The display panel further comprises a plurality of gate circuits and 4m clock lines, the gate circuit comprises 4m gate switches, and m is a positive integer greater than or equal to 1. In the gate circuit, control terminals of the 4m gate switches are respectively electrically connected with the 4m clock lines, and output terminals of the 4m gate switches are electrically connected with a source signal line, wherein output terminals of 2m gate switches are respectively coupled with 2m first data lines, and output terminals of the other 2m second gate switches are respectively coupled with 2m second data lines. And for the second lead and one of the data lines adjacent to the second lead, the gate switch coupled with the second lead and the data line is electrically connected with the same clock line.

15. The display panel of claim 6, wherein Four adjacent data lines which are not spaced by the driving transistor constitute a data line group. The second data lead includes a third lead, and the third lead is located on at least one side of the data line group.

16. The display panel of claim 15, wherein The display panel further comprises a plurality of gate circuits and 4m clock lines, the gate circuit comprises 4m gate switches, and m is a positive integer greater than or equal to 1. In the gate circuit, control terminals of the 4m gate switches are respectively electrically connected with the 4m clock lines, and output terminals of the 4m gate switches are electrically connected with a source signal line, wherein output terminals of 2m gate switches are respectively coupled with 2m first data lines, and output terminals of the other 2m second gate switches are respectively coupled with 2m second data lines. The circuit column includes a first circuit column and a second circuit column, the first data line connected by the first circuit column is located on one side of the second data line close to the driving transistor, and the second data line connected by the second circuit column is located on one side of the first data line close to the driving transistor. And for the third lead and the data line adjacent to the third lead, the gate switch coupled with the third lead and the data line is electrically connected with the same clock line.

17. The display panel of claim 6, wherein, The display panel further comprises: a light emitting element, the light emitting element comprising an anode; a first trace and a second trace, the first trace being arranged in the same layer as the first data lead and extending in the same direction, the second trace being arranged in the same layer as the second data lead and extending in the same direction, and the first trace and the first data lead and the second trace and the second data lead having a break therebetween; a shielding portion arranged in the same layer as the anode and connected thereto, the shielding portion overlapping the break in a direction perpendicular to a plane in which the substrate lies.

18. The display panel of claim 1, wherein the power signal line comprises a first segment and a second segment arranged alternately and connected sequentially in the second direction, the second segment overlapping the connection line and the active layer of the first transistor in a direction perpendicular to a plane in which the substrate lies, and a width of the second segment in the first direction is greater than a width of the first segment in the first direction; for two power signal lines connected by the first circuit group, a first auxiliary power line is connected between the first segments of the two power signal lines, and / or a second auxiliary power line is arranged in parallel on the first segment.

19. The display panel of claim 1, wherein the first transistor comprises a gate reset transistor, the gate reset transistor being electrically connected between a first reset line and a gate of the driving transistor; wherein one first circuit group is provided with one first reset line, the first reset line extending in the second direction and being arranged in the same layer as the connection line, and first poles of two gate reset transistors adjacent in the first direction in the first circuit group being connected to the corresponding first reset line.

20. The display panel of claim 1, wherein the pixel circuit further comprises an anode reset transistor, the anode reset transistor being electrically connected between a second reset line and a light emitting element, the second reset line comprising a first sub-reset line and a second sub-reset line electrically connected, the first sub-reset line extending in the first direction, and the second sub-reset line being connected between two adjacent first sub-reset lines; the pixel circuit further comprises a bias transistor, the bias transistor being electrically connected between a bias signal line and the driving transistor, the bias signal line comprising a first sub-bias line and a second sub-bias line, the first sub-bias line extending in the first direction, and the second sub-bias line being connected between two adjacent first sub-bias lines; wherein the second sub-reset line and the second sub-bias line are arranged in the same layer, the second sub-reset line and the second sub-bias line are arranged alternately in the first direction, and the second sub-reset line and the second sub-bias line are arranged alternately in the second direction.

21. The display panel of claim 20, wherein ​ The first transistor comprises a gate reset transistor electrically connected between a first reset line and a gate of the driving transistor; one of the first circuit groups is provided with one of the first reset lines, the first reset line extends along the second direction and is provided in the same layer as the connection line, and first poles of two of the gate reset transistors adjacent in the first direction in the first circuit group are connected to the corresponding first reset line. The first reset line, the second sub-reset line and the second sub-bias line are provided in the same layer, and two of the second sub-reset lines and the second sub-bias line adjacent in the first direction are separated by one of the first reset lines.

22. The display panel of claim 20, wherein The pixel circuit further comprises a storage capacitor, a first plate of the storage capacitor is multiplexed with the gate of the driving transistor; The first sub-reset line and a second plate of the storage capacitor are provided in the same layer, the first sub-bias line and the top gate of the first transistor are provided in the same layer, and the second sub-reset line and the second sub-bias line are provided in the same layer as the connection line.

23. The display panel of claim 1, wherein The pixel circuit further comprises a storage capacitor, a first plate of the storage capacitor is multiplexed with the gate of the driving transistor; The first transistor comprises a gate reset transistor, a gate of the gate reset transistor is electrically connected with a first scan line, the first scan line comprises a first sub-scan line and a second sub-scan line electrically connected and extending along the first direction, the first sub-scan line is provided in the same layer as a second plate of the storage capacitor, and part of the second sub-scan line is multiplexed as a top gate of the gate reset transistor, the first sub-scan line and the second sub-scan line overlap in a direction perpendicular to a plane in which the substrate is located; And / or, the first transistor comprises a threshold compensation transistor, a gate of the threshold compensation transistor is electrically connected with a second scan line, the second scan line comprises a third sub-scan line and a fourth sub-scan line electrically connected and extending along the first direction, the third sub-scan line is provided in the same layer as the second plate of the storage capacitor, and part of the fourth sub-scan line is multiplexed as a top gate of the threshold compensation transistor, the third sub-scan line and the fourth sub-scan line overlap in a direction perpendicular to a plane in which the substrate is located.

24. A display device comprising: The display panel comprises any one of the display panels of claims 1-23.

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