Full-region degradation representation method for IGBT

Abstract

Disclosed in the present invention is a full-region degradation representation method for an IGBT. The method comprises: applying, between a collector and an emitter of an IGBT, a negative voltage gradually increased from 0 V, and at each Vce, performing voltage scanning on a gate of the IGBT, and superimposing a small signal, the gate voltage scanning range being Vg1-Vg2; at each Vce, testing gate capacitance Cg within Vg1-Vg2, and drawing and partitioning a Cg-Vg curve; using the same voltage applying manner to retest the gate capacitance Cg value within Vg1-Vg2 for the degraded device, drawing the Cg-Vg curve, and using the same manner to partition the curve; and comparing drift conditions in different regions of the curve before and after degradation, and representing the degradation condition and damage degree of the whole area of the IGBT power device. The method allows to simply and quickly extract the degradation conditions of gate oxide layers and epitaxial layers of IGBT power devices, providing a rapid determination basis for the reliability analysis of the IGBT power devices.

Description

A method for characterizing full-area degradation of IGBTs Technical Field

[0001] This invention relates to the field of power device reliability testing, and specifically to a method for characterizing the full-area degradation of IGBTs. Background Technology

[0002] IGBT transistors, as important power semiconductor devices, offer higher power density and output capabilities, as well as faster switching speeds, and are widely used in high-voltage, high-power-density applications such as power systems, industrial automation, and new energy vehicles. However, due to the long-term operation of IGBTs under high temperature, high pressure, and radiation, defects can develop in their gate oxide and drift regions. This is especially true for silicon carbide-based IGBTs, where the gate oxide quality is poor, leading to more severe dislocation propagation and degradation in the drift region.

[0003] Currently, the most widely used methods for testing gate oxide defects in power semiconductor devices are the capacitance (CV) method and the charge pump method. However, neither of these methods can characterize defects in the epitaxial layer of IGBTs. This invention provides a testing method that can characterize both the gate oxide interface state defect charge and the epitaxial layer defect charge. Summary of the Invention

[0004] The purpose of this invention is to provide a method for characterizing the full-area degradation of IGBTs, which can characterize the types and charge densities of gate oxide interface states and the types and locations of epitaxial layer defects in IGBT power devices.

[0005] To achieve the above functions, this invention designs a full-area degradation characterization method for IGBTs, performing the following steps S1-S5 to characterize the degradation status and damage degree of the entire IGBT device under test:

[0006] Step S1: Set up the test circuit. For the IGBT device under test, apply a bias voltage that gradually increases from 0V between the collector and emitter of the IGBT device under test using a voltage source. Perform voltage scanning on the gate of the IGBT device under test and superimpose a small AC signal.

[0007] Step S2: Extract the gate voltage V during the gate voltage scan of the IGBT device under test. g Gate capacitance C g Plot the curve of gate capacitance as a function of gate voltage. g -V g ;

[0008] Step S3: Gradually increase the bias voltage applied between the collector and emitter of the IGBT device under test from 0V to negative voltage, and perform voltage scanning on the gate in the same way as in step S1, and superimpose an AC small signal.

[0009] Step S4: Repeat step S2;

[0010] Step S5: After the IGBT device under test undergoes stress-induced degradation, repeat steps S1-S4 to plot the gate capacitance versus gate voltage curve again. g -V g ;

[0011] Step S6: Based on the gate capacitance C g The change in gate capacitance versus gate voltage curve C g -V g The device is divided into sections, each representing a different region of the IGBT under test. The curves showing the gate capacitance versus gate voltage before and after degradation are compared. g -V g The lateral and longitudinal drift characteristics, based on curve C g -V g The drift amplitude analysis was used to determine the degree of damage in each region of the IGBT device under test.

[0012] As a preferred technical solution of the present invention: the amplitude range of the AC small signal voltage in step S1 is between 1mV and 1V, and the frequency is between 1KHz and 100MHz.

[0013] As a preferred technical solution of the present invention: the absolute value of the bias voltage applied between the collector and emitter in step S1 is not greater than the reverse breakdown voltage of the device, and its typical value range is between -10000V and 0V.

[0014] As a preferred technical solution of the present invention: the voltage application method in step S1 is as follows: a DC voltage source and an AC small signal are connected to the gate of the IGBT device under test. The AC small signal is superimposed on the DC power supply. The gate voltage is scanned. The gate voltage scan range should make the junction field-effect region below the gate oxide go through the three states of accumulation, depletion and inversion, and make the channel region below the gate oxide go through the three states of accumulation, depletion and inversion. During the gate voltage scan, the bias voltage between the collector and the emitter is kept constant.

[0015] As a preferred technical solution of the present invention: the stress characterized by the IGBT device under test in step S5 includes one or more of the following: short-circuit switching stress, non-clamping inductor switching stress, high-temperature gate voltage bias, on-state large current impact stress, hot carrier injection, and irradiation stress.

[0016] As a preferred technical solution of the present invention: in step S6, the curve C of gate capacitance versus gate voltage is... g -V g They are divided into zones I, II, III, IV, V, and VI in sequence.

[0017] Specifically, when a negative bias voltage is applied to the gate of the IGBT device under test, and the absolute value of the negative voltage is greater than a preset threshold, the gate capacitance C... g At a stable high value, this part of the curve C g -V g Divided into Zone I;

[0018] When the absolute value of the bias voltage applied to the gate of the IGBT device under test decreases, the gate capacitance C... g Reduce to the minimum value, and then reduce this part of the curve C. g -V g Divided into Zone II;

[0019] When a bias voltage is applied to the gate of the IGBT device under test from negative to positive, the gate capacitance C... g Increase this portion of curve C g -V g Divided into Zone III;

[0020] When the bias voltage applied to the gate of the IGBT device under test continues to increase from negative to positive, the gate capacitance C... g A plateau region appears; this part of the curve C... g -V g It is divided into zone IV;

[0021] When the bias voltage applied to the gate of the IGBT device under test is gradually increased from a low voltage, the gate capacitance C... g Increase this portion of curve C g -V g Divided into zone V;

[0022] When the bias voltage applied to the gate of the IGBT device under test continues to increase, the gate capacitance C... g At a stable high value, this part of the curve C g -V g It is divided into Zone VI.

[0023] As a preferred technical solution of the present invention: in step S6, curve C g -V g The lateral drift of region II characterizes the degradation of the gate oxide interface above the junction field-effect region of the IGBT device under test.

[0024] When a positive charge exists at the gate oxide interface above the junction field-effect region (JFET), compared to the case without defects at the gate oxide interface, the JFET transitions from a depletion state to an inversion state under a larger absolute negative gate voltage, as shown by curve C. g -V g Zone II along V g Negative axial drift; when a negative charge exists at the gate oxide interface above the junction field-effect region, compared to the case without defects in the gate oxide, the junction field-effect region transitions from a depletion state to an inversion state under a smaller absolute value of negative gate voltage, as shown by curve C. g -V g Zone II will follow V g Positive axis drift.

[0025] As a preferred technical solution of the present invention: in step S6, curve C g -V g The lateral drift of region IV characterizes the degradation of the gate oxide interface above the channel region of the IGBT device under test.

[0026] When a positive charge exists at the gate oxide interface above the channel region, compared to the case where there are no defects at the gate oxide interface, the channel region transitions from the depletion state to the inversion state at a lower positive gate voltage, as shown by curve C. g -V g IV zone to V g Negative axis drift; when there is a negative charge at the gate oxide interface above the channel region, compared to the case where there are no defects in the gate oxide, the channel region transitions from the depletion state to the inversion state under a larger positive gate voltage, as shown by curve C. g -V g IV zone to V g Positive axis drift.

[0027] As a preferred technical solution of the present invention: in step S6, curve C g -V g Zone III in C g On-axis drift characterizes defects in the epitaxial layer of the device;

[0028] When the defects in the epitaxial layer are positively charged, curve C g -V g Zone III towards C g Positive axis drift; when the defect in the epitaxial layer is negatively charged, curve C g -V g Zone III towards C g Negative axis drift.

[0029] As a preferred technical solution of the present invention: in step S6, the stress curve before and after C is extracted. g -V g Zones II and IV along V gFor axis drift, the gate oxide interface defect charge density ΔD caused by stress is calculated using the following formula. ot To characterize the degree of damage:

[0030] Among them, C ox The gate oxide capacitance per unit area is ΔV. g For curve C g -V g The voltage drift on the horizontal axis, where q is the electron charge.

[0031] Beneficial effects: Compared with the prior art, the advantages of the present invention include:

[0032] 1. The method of this invention can characterize the degradation of the entire IGBT device, through C g -V g The drift of each region of the curve can be used to extract the defect polarity and defect density of the gate oxide above the junction field-effect region and the channel region of the device, as well as the defect location and defect polarity in the epitaxial layer.

[0033] 2. This test method will use C g -V g The curve is divided into 6 regions, of which regions II, III, and IV can respectively characterize the gate oxide defects above the junction field-effect region, the epitaxial layer defects, and the gate oxide defects above the channel region.

[0034] 3. By analyzing C g -V g The drift patterns in regions II and IV of the curve can be used to extract the polarity and density of gate oxide interface defects above the junction field-effect region and above the channel region, respectively; by analyzing C g -V g The drift pattern in region III of the curve can be used to extract the location and type of defects in the epitaxial layer.

[0035] 4. The test circuit requirements of the method of this invention are relatively low; the extraction of defect location and polarity is also relatively intuitive and convenient, requiring only the extraction of C. g -V g The drift directions of curves II, III, and IV; this test method only needs to extract C to calculate the defect density in the gate oxide. g -V g Curves II and IV in V g The drift of the axis can be used to calculate the defect density in the gate oxide using a formula, which is simpler than traditional methods for extracting gate oxide defects.

[0036] In summary, the advantages provided by this invention demonstrate that the testing method can quickly and easily extract the degradation status of the gate oxide layer and epitaxial layer of IGBT power devices, providing a rapid basis for determining the reliability of IGBT power devices. Attached Figure Description

[0037] Figure 1 is a diagram of the IGBT device structure and capacitor configuration according to an embodiment of the present invention.

[0038] Figure 2 is a flowchart of a full-area degradation characterization method for IGBTs provided according to an embodiment of the present invention;

[0039] Figure 3 is a test circuit diagram provided according to an embodiment of the present invention;

[0040] Figure 4 shows the initial state C provided according to an embodiment of the present invention. g -V g Line graph;

[0041] Figure 5 shows the C-type gate oxide defects above the channel region after device degradation according to an embodiment of the present invention. g -V g Line graph;

[0042] Figure 6 shows the C-type gate oxide defect above the junction field-effect region after device degradation according to an embodiment of the present invention. g -V g Line graph;

[0043] Figure 7 shows the C-type epitaxial layer defects after device degradation according to an embodiment of the present invention. g -V g Line graph. Detailed Implementation

[0044] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0045] An Insulated-Gate Bipolar Transistor (IGBT) is a high-power electronic device that combines the characteristics of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a BJT (Bipolar Junction Transistor), achieving both low switching losses and high current density.

[0046] The structure and capacitance composition of an IGBT transistor are shown in Figure 1. Its gate capacitance mainly consists of the capacitance C between the gate and the collector. gc The capacitance C between the gate and emitter ge Two parts. Capacitor C gc It consists of four types of capacitors connected in series and parallel, namely the surface-mount MOS capacitor in the channel region C. oc Surface-mount MOS capacitors in the junction field-effect region (JFET) oj PN junction capacitance C j Substrate capacitance Csub Among them, the surface MOS capacitor C of the junction field-effect region oj With substrate capacitance C sub Series capacitance dominates. Capacitor C ge It consists of three types of capacitors connected in series and parallel, namely the surface-mount MOS capacitor in the channel region C. oc Surface MOS capacitor C in junction field-effect region oj PN junction capacitance C j C ge Mainly affected by C oc Impact. When the emitter and collector are short-circuited, the PN junction capacitance C... j The effect is shielded, gate capacitance C g From capacitor C gc and capacitor C ge Formed in parallel.

[0047] As the bias voltage applied to the gate of the IGBT continues to increase, the channel region below the gate electrode undergoes a process from depletion to inversion. Carrier accumulation occurs in the junction field-effect region, forming an inversion layer channel connecting the N+ emitter region and the N-base region. When a positive voltage is applied to the collector, electron current flows from the N+ emitter region to the N-base region, creating a voltage drop in the N-base region. This electron current acts as the base drive current of the PNP transistor, promoting the injection of holes from the P+ collector region into the N-type base region. The PNP transistor turns on, and the current density increases sharply.

[0048] Semiconductor surface inversion refers to the phenomenon where, when a voltage is applied to the gate, electrons or holes are attracted to the semiconductor surface, causing the semiconductor surface to change from n-type to p-type or vice versa. Semiconductor surface depletion refers to the phenomenon where, when a voltage is applied to the gate, electrons or holes are repelled, and the original donor or acceptor atoms lose electrons or holes, forming a space charge region on the semiconductor surface. Semiconductor surface accumulation refers to the phenomenon where, when a voltage is applied to the gate, electrons or holes accumulate on the semiconductor surface, making the electron concentration in the n-type region or the hole concentration in the p-type region of the semiconductor surface higher than the electron concentration in the n-type region or the hole concentration in the p-type region inside the semiconductor.

[0049] Because IGBTs operate under conditions such as high temperature, high current, and irradiation, defects can be introduced into the gate oxide and epitaxial layer of the IGBT. The introduction of defect charges in the gate oxide will seriously affect the gate control capability of the device, and the presence of defects in the substrate will seriously affect the current capability of the device.

[0050] This invention provides a method for characterizing the full-area degradation of IGBTs. Referring to Figure 2, the following steps S1-S5 are performed to characterize the degradation status and damage degree of the entire IGBT device under test:

[0051] Step S1: Construct the test circuit as shown in Figure 3. For the IGBT device under test, apply a bias voltage V, gradually increasing from 0V, between the collector and emitter of the IGBT device under test using a voltage source. ce The bias voltage applied between the collector and emitter is determined by the device's own breakdown voltage capability; a voltage scan is performed on the gate of the IGBT device under test, and a small AC signal is superimposed; the gate voltage scan range is V. g1 ~V g2 ;

[0052] In practical applications, the number and interval of multiple bias voltages can be determined based on the required test rate and accuracy. Generally, fewer bias voltages result in a faster test rate, and smaller intervals between multiple bias voltages result in higher test accuracy.

[0053] The amplitude range of the AC small signal voltage is between 1mV and 1V, and the frequency is between 1KHz and 1MHz.

[0054] The absolute value of the bias voltage applied between the collector and emitter should not exceed the reverse breakdown voltage of the device, with a typical range of -10000V to 0V.

[0055] The voltage application method in step S1 is as follows: a DC voltage source and an AC small signal are connected to the gate of the IGBT device under test. The AC small signal is superimposed on the DC power supply. The gate voltage is scanned. The gate voltage scan range should make the junction field-effect region below the gate oxide go through the three states of accumulation, depletion and inversion, and make the channel region below the gate oxide go through the three states of accumulation, depletion and inversion. During the gate voltage scan, the bias voltage between the collector and emitter is kept constant.

[0056] Step S2: Extract the gate voltage V during the gate voltage scan of the IGBT device under test. g Gate capacitance C g Plot the curve of gate capacitance as a function of gate voltage. g -V g ;

[0057] At each bias voltage V ce Below, test the gate voltage scan range V g1 ~V g2 The gate capacitance C g Gate voltage scan range V g1 ~V g2 (or V) g2 ~V g1 V g1 A typical value range is -50V to 0V; the corresponding V g2 A typical value range is 0V-50V.

[0058] Step S3: Gradually increase the bias voltage applied between the collector and emitter of the IGBT device under test from 0V to negative voltage, and perform voltage scanning on the gate in the same way as in step S1, and superimpose a small AC signal.

[0059] Step S4: Repeat step S2;

[0060] Step S5: After the IGBT device under test undergoes stress-induced degradation, repeat steps S1-S4. The gate voltage scan range and value interval step size remain the same before and after stress. The amplitude and frequency of the AC small signal remain the same before and after stress. The bias voltage V... ce The value is kept the same before and after stress, and the curve C of gate capacitance versus gate voltage is plotted again. g -V g ;

[0061] The stresses characterized by the IGBT device under test include, but are not limited to, high-temperature gate voltage bias stress, such as short-circuit switching stress, non-clamped inductor switching stress, on-state high current impact stress, hot carrier injection, and irradiation stress, among one or more of these.

[0062] High-temperature gate bias stress refers to the phenomenon where a voltage bias is applied to the gate at high temperatures, causing the gate oxide interface state charge traps to capture or release electrons, resulting in a shift in the device's threshold voltage. Under positive high-temperature gate bias stress, the gate is subjected to a positive bias voltage for an extended period, trapping electrons at the gate oxide interface and increasing the threshold voltage. Under negative high-temperature gate bias stress, the gate is subjected to a positive bias voltage for an extended period, trapping holes at the gate oxide interface and increasing the threshold voltage.

[0063] Step S6: Based on the gate capacitance C g The change in gate capacitance versus gate voltage curve C g -V g The device is divided into sections, each representing a different region of the IGBT under test. The curves showing the gate capacitance versus gate voltage before and after degradation are compared. g -V g The lateral and longitudinal drift characteristics, based on curve C g -V g The drift amplitude analysis was used to determine the degree of damage in each region of the IGBT device under test.

[0064] The curve C of gate capacitance versus gate voltage g -V g They are divided into zones I, II, III, IV, V, and VI in sequence.

[0065] Gate capacitance C after shorting the emitter and collector before device degradation g With gate voltage V gThe variation curve is shown in Figure 4. When a large negative voltage is applied to the gate, the channel region below the gate oxide is in an accumulation state, and the junction field-effect region is in an inversion state. At this time, the MOS capacitance C on the channel surface increases. oc and the surface MOS capacitor of the junction field-effect region C oj Approximating the gate oxide capacitance, when the voltage between the collector and emitter is constant, the substrate capacitance C is... sub The gate capacitance C remains constant. g It is at a stable high value; as shown in region I of Figure 4. When the absolute value of the negative voltage applied to the gate decreases to the point where the junction field-effect region transitions from the inversion state to the depletion state, the width of the depletion layer on the semiconductor surface increases, C oj It begins to decrease, leading to C gc Decrease. Because the channel region is still in a state of accumulation, C... oc If it is still approximately a gate oxide capacitor, then the capacitance C ge The gate capacitance C remains unchanged, ultimately leading to... g As shown in region II of Figure 4, when the gate bias voltage continues to increase from negative to positive, the channel region begins to transition from the accumulation state to the depletion state, and the capacitance C... oc It is formed by the series connection of gate oxide capacitance and space charge region capacitance, C oc It begins to decrease. Simultaneously, the junction field-effect region gradually transitions from a fully depleted state to an accumulated state, the width of the depletion layer on the semiconductor surface decreases, and the capacitance C... oj It begins to increase. Because the area of ​​the junction field-effect region below the gate oxide is much larger than the area of ​​the channel region, the capacitance C... oj The increase of [something] is dominant, and the overall capacitance C g The increase is shown in region III of Figure 4. As the gate voltage increases, due to the capacitance C... oj With substrate capacitance C sub Series and substrate capacitance C sub Smaller, C gc The capacitor is C sub Clamping. As the gate voltage increases from negative to positive, the channel region is further depleted, and the capacitance C... oc If it is further reduced, then the capacitance C g By C gc The dominant phase exhibits a plateau region, as shown in region IV of Figure 4. As the gate voltage gradually increases from a low voltage, the channel region begins to gradually transition from a depletion state to an inversion state, and the capacitance C... oc The overall capacitance C begins to increase. g Increase as shown in region V of Figure 4. When the gate voltage increases to the point of strong inversion in the channel region, the capacitance C... oc Close to C of MOS capacitor oj If it is also a gate oxide capacitor, then the capacitance C g It is in a stable high value, as shown in region VI of Figure 4.

[0066] When the gate oxide interface introduces defect charges due to stress, it changes the surface potential of the semiconductor beneath the gate oxide, thereby promoting or hindering inversion or depletion in the region beneath the gate oxide and altering the semiconductor surface capacitance. When the epitaxial layer introduces defects due to stress, the presence of defect charges changes the effective doping concentration of the epitaxial layer, thus affecting the device's conduction performance. Based on the above analysis, in Figure 4, C... g -V g Region II of the curve is mainly affected by the surface capacitance C of the junction field-effect region. oj The V region is mainly affected by the surface capacitance C of the channel region. oc Therefore, C can be used to determine the impact. g -V g Regions II and V of the curve along V g The drift of the axis characterizes the degradation of the gate oxide interface. As shown in Figure 5, when a positive charge is introduced into the gate oxide above the channel region, electrons are attracted to the channel region below the gate oxide. The device will invert under a smaller positive voltage, and the curve V region along V g Negative axis drift; when negative charge is introduced into the gate oxide above the channel region, the device will invert under a larger positive voltage, and the curve V region will drift along V. g Positive axis drift. As shown in Figure 6, when a positive charge is introduced into the gate oxide above the junction field-effect region, electrons are attracted to the junction field-effect region below the gate oxide. The device will undergo inversion under a larger absolute negative voltage, and the curve II region will drift along V. g Negative axis drift; when a negative charge is introduced into the gate oxide above the junction field-effect region, the device will invert under a smaller absolute negative voltage, and curve II will drift along V. g Positive axis drift. As shown in Figure 7, when the epitaxial layer introduces defects due to stress, the V-axis shifts. ce The value of C indicates that the depletion layer of the substrate PN junction widens, extending into the defect-containing region, affecting the substrate capacitance and causing a shift in the plateau region curve. If the defect is an acceptor-type defect, the effective doping concentration of the epitaxial layer decreases, the depletion layer width increases compared to the theoretical value, and the substrate capacitance decreases compared to before device degradation, with the plateau region shifting along C. g Negative axis drift; if the defect is a donor-type defect, the effective doping concentration of the epitaxial layer increases, the depletion layer width decreases compared to the theoretical value, the substrate capacitance increases compared to the device degradation, and the plateau region along C... g Positive axis drift.

[0067] Extracting the capacitance curve along V g The defect density at the gate oxide interface can be calculated using the formula based on the axis drift and the gate oxide capacitance value.

[0068] Based on this, we can use C g -V g The drift patterns in regions II and IV of the curve are used to calculate the types and densities of gate oxide defect charges above the junction field-effect region and above the channel region of the device, respectively; based on C g-V g The drift pattern in region III of the curve can be used to extract the location and polarity of the defect charge in the epitaxial layer of the device.

[0069] When a positive charge exists at the gate oxide interface above the junction field-effect region (JFET), compared to the case without defects at the gate oxide interface, the JFET transitions from a depletion state to an inversion state under a larger absolute negative gate voltage, as shown by curve C. g -V g Zone II along V g Negative axial drift; when a negative charge exists at the gate oxide interface above the junction field-effect region, compared to the case without defects in the gate oxide, the junction field-effect region transitions from a depletion state to an inversion state under a smaller absolute value of negative gate voltage, as shown by curve C. g -V g Zone II will follow V g Positive axis drift.

[0070] Curve C g -V g Zone III in C g On-axis drift characterizes defects in the epitaxial layer of the device;

[0071] When the defects in the epitaxial layer are positively charged, curve C g -V g Zone III towards C g Negative axial drift; when the defect in the epitaxial layer is negatively charged, curve C g -V g Zone III towards C g Positive axis drift.

[0072] Curve C g -V g The lateral drift of region IV characterizes the degradation of the gate oxide interface above the channel region of the IGBT device under test.

[0073] When a positive charge exists at the gate oxide interface above the channel region, compared to the case where there are no defects at the gate oxide interface, the channel region transitions from the depletion state to the inversion state at a lower positive gate voltage, as shown by curve C. g -V g IV zone to V g Negative axis drift; when there is a negative charge at the gate oxide interface above the channel region, compared to the case where there are no defects in the gate oxide, the channel region transitions from the depletion state to the inversion state under a larger positive gate voltage, as shown by curve C. g -V g IV zone to V g Positive axis drift.

[0074] Extract the stress curve C before and after in step S6. g -V g Zones II and IV along Vg For axis drift, the gate oxide interface defect charge density ΔD caused by stress is calculated using the following formula. ot To characterize the degree of damage:

[0075] Among them, C ox The gate oxide capacitance per unit area is ΔV. g For curve C g -V g The voltage drift on the horizontal axis, where q is the electron charge.

[0076] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

A full-area degradation characterization method for IGBTs, characterized in that, The following steps S1-S5 are performed to characterize the degradation and damage of the entire region of the IGBT device under test: Step S1: Build a test circuit, for the IGBT device under test, apply a bias voltage gradually increasing from 0V between the collector and emitter of the IGBT device under test, voltage scan the gate of the IGBT device under test and superimpose an AC small signal; Step S2: extract the gate capacitance C g of the IGBT device under test at each gate voltage V g in the gate voltage scanning process, and draw the curve of the gate capacitance C g -V g ; Step S3: gradually increase the bias voltage value applied between the collector and emitter of the IGBT device under test from 0V to negative voltage, voltage scan the gate in the same voltage application mode as step S1 and superimpose an AC small signal; Step S4: repeat step S2; Step S5: After the IGBT device under test has developed degradation induced by the stress, steps S1-S4 are repeated and the curve of gate capacitance as a function of gate voltage C is plotted again g - V g ; Step S6: According to the change of the gate capacitance C g , the gate capacitance-voltage curve C g -V g is divided into several parts, respectively representing the degradation of each region of the IGBT device to be tested, and the lateral and longitudinal drift of the gate capacitance-voltage curve C g -V g before and after the degradation of the IGBT device to be tested is compared, and the damage degree of each region of the IGBT device to be tested is analyzed based on the drift amplitude of the curve C g -V g . The method for full area degradation characterization of IGBT according to claim 1, wherein, The AC small signal voltage amplitude in step S1 is in the range of 1mV-1V, and the frequency is in the range of 1KHz-100MHz. The method for full-area degradation characterization of IGBT according to claim 1, wherein, The absolute value of the bias voltage applied between the collector and emitter in step S1 is not greater than the reverse breakdown voltage of the device, and its typical value range is-10000V-0V. The method for full area degradation characterization of IGBT according to claim 1, wherein, The voltage application mode in step S1 is: connect a DC voltage source and an AC small signal to the gate of the IGBT device under test, superimpose the AC small signal on the DC power source, voltage scan the gate, the gate voltage scan range should make the gate oxide below the junction field effect region go through accumulation, depletion, and reverse type three states, and make the gate oxide below the channel region go through accumulation, depletion, and reverse type three states, keep the bias voltage between the collector and emitter constant during gate voltage scan. The method for full area degradation characterization of IGBT according to claim 1, wherein, The stress that may introduce degradation to the IGBT device under test in step S5 includes one or more of short circuit switching stress, non-clamp inductance switching stress, high temperature gate voltage bias, on-state large current impact stress, hot carrier injection, and radiation stress. The method for full area degradation characterization of IGBT according to claim 1, wherein, The curve C of the gate capacitance as a function of the gate voltage in step S6 g -V g are sequentially divided into I region, II region, III region, IV region, V region, VI region; When a bias voltage of negative polarity is applied to the gate of the IGBT device under test and the absolute value of the negative voltage is greater than a preset threshold, the gate capacitance C g is at a stable high value, and this part of the curve C g -V g is divided into region I. When the absolute value of the bias voltage applied to the gate of the IGBT device under test is reduced, the gate capacitance C g to a minimum value, this part of the curve C g -V g is divided into region II. When a bias voltage is applied to the gate of the IGBT device under test from negative to positive, the gate capacitance C g increases, this part of the curve C g -V g is divided into region III. When the bias voltage applied to the gate of the IGBT device under test continues to increase from negative to positive, the gate capacitance C g A plateau region appears, and this part of the curve C g -V g is divided into the IV region; When the bias voltage applied to the gate of the IGBT device under test is gradually increased from a low voltage, the gate capacitance C... g Increase this portion of curve C g -V g Divided into zone V; When the bias voltage applied to the gate of the IGBT device under test continues to increase, the gate capacitance C g at the stable high value, this part of the curve C g -V g is divided into the VI region. The method for full area degradation characterization of IGBT according to claim 6, characterized in that, Curve C in step S6 g -V g The lateral drift of the II region characterizes the degradation of the gate oxide interface above the junction field effect region of the IGBT device under test; When there are positive charges at the gate oxide interface above the junction field effect region, compared to the case where there are no defects in the gate oxide, the junction field effect region transitions from depletion to inversion at a more negative gate voltage, curve C g -V g of II region will shift negatively along the V g axis; when there are negative charges at the gate oxide interface above the junction field effect region, compared to the case where there are no defects in the gate oxide, the junction field effect region transitions from depletion to inversion at a less negative gate voltage, curve C g -V g of II region will shift positively along the V g axis. The method for full area degradation characterization of IGBT according to claim 6, characterized in that, Curve C in step S6 g -V g The lateral drift of IV region of IGBT device under test characterizes the degradation of the gate oxide interface above the channel region of the IGBT device under test; When positive charges exist at the gate oxide interface above the channel region, the channel region transitions from depletion to inversion at a smaller positive gate voltage than if there were no defects in the gate oxide, and the IV curve C g -V g region IV shifts negatively along the V g axis. When negative charges exist at the gate oxide interface above the channel region, the channel region transitions from depletion to inversion at a larger positive gate voltage than if there were no defects in the gate oxide, and the IV curve C g -V g region IV shifts positively along the V g axis. The full area degradation characterization method for IGBT according to claim 6, characterized in that, Curve C in step S6 g -V g The drift of the III region in C g axis characterizes the defects of the device epitaxial layer; When the defects in the epitaxial layer are positively charged, the curve C g -V g of the III region shifts towards the C g axis in the positive direction; when the defects in the epitaxial layer are negatively charged, the curve C g -V g of the III region shifts towards the C g axis in the negative direction. The full area degradation characterization method for IGBT according to claim 6, characterized in that, The curve C before and after extraction of the stress in step S6 g -V g The II and IV regions of the V g axis shift, the gate oxide interface defect charge density ΔD generated by the stress is calculated according to the following formula: ot To characterize the damage degree: where C ox is the gate oxide capacitance per unit area, ΔV g is the curve C g -V g is the voltage shift on the horizontal axis, and q is the electronic charge.

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