Method for doping side wall of 3D memory device

Abstract

The present invention relates to the technical field of memory fabrication, and provides a method for doping a side wall of a 3D memory device. The main steps thereof comprise: performing a deposition treatment on the side wall of a 3D memory device; performing an annealing treatment by means of a longwave-light annealing process or a rapid thermal annealing process; and etching away a capping layer portion by means of a longitudinal etching process for the anisotropic selective specific etching of SiO2, and cyclically repeating the above steps of deposition, annealing and etching a predetermined number of times to finish the doping of the side wall. The present invention can complete the doping of the side wall of a deep trench of a 3D memory device at a deep-submicron-scale or nanometer-scale depth, and can form a buffer layer with an accurately controllable depth or concentration.

Description

A sidewall doping method of 3D memory device TECHNICAL FIELD

[0001] The present application relates to the technical field of memory preparation, in particular to a sidewall doping method of 3D memory device. BACKGROUND

[0002] 3D memory device often requires deep sub-micron, nanometer level thickness doping for deep trench sidewall to form a buffer zone with different conductivity type or same conductivity type but lower concentration than the high-doped low-resistance semiconductor (such as n+ polysilicon) in the sidewall, so as to optimize the performance of the device. However, the traditional ion implantation process cannot be used for impurity implantation for 3D device sidewall; and if the general gas phase diffusion method is used, it will require extremely high temperature and time, and it is difficult to ensure the controllability and accuracy of nanoscale diffusion for micron-level deep sidewall.

[0003] In Chinese patent application publication CN101615656A, a technical solution is disclosed that requires using isotropic etching method to selectively etch and refill the buffer layer on the sidewall of the prepared low-resistance semiconductor (highly doped silicon), which will leave damage and defects on the sidewall surface after etching, affecting the contact between the low-resistance semiconductor and the buffer layer, and the etching consistency is difficult to control.

[0004] Therefore, a new process that can precisely control the sidewall diffusion is needed to solve the above problems. TECHNICAL PROBLEM

[0005] Based on the above problems, the purpose of the present application is to provide a sidewall doping method for 3D memory device, which can complete the deep sub-micron, nanometer level thickness doping of the deep trench sidewall of 3D memory device, and form a depth or concentration precisely controllable buffer layer. TECHNICAL SOLUTION

[0006] The technical scheme adopted by the present application to achieve the purpose of the present application is a sidewall doping method of 3D memory device, comprising the following steps:

[0007] (1) performing deposition treatment on the sidewall of the 3D memory device, the specific steps are as follows:

[0008] (1.1) first, using wet treatment or dry treatment method, pre-treating the sidewall surface to form attachment points for subsequent deposition;

[0009] (1.2) second, using wet deposition or dry deposition to perform self-aligned monolayer deposition, uniformly depositing organic precursor containing the to-be-doped element on the pre-treated sidewall surface;

[0010] The doping concentration of a single cycle can be optimized by the impurity-containing precursor organic molecules in the monomolecular deposition process. Generally speaking, the longer the branched chain length or the larger the volume of the organic molecules, the smaller the initial concentration of impurities on the silicon sidewall surface due to the self-limitation of the deposition process. The initial concentration of impurities is generally 10 20 cm -3 or more.

[0011] (1.3) Then, by chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology, deposition or filling of the silicon dioxide protective layer material is performed.

[0012] The protective layer material (SiO2 or other insulating medium) can effectively prevent the escape of impurity-containing organic molecules from the silicon surface during annealing, thereby providing a stable impurity diffusion source and ensuring the diffusion of impurities into the sidewall.

[0013] (2) Annealing treatment is performed using a long-wave light annealing process or a rapid thermal annealing process.

[0014] The thickness of the doping region (5-20 nm) is determined by the process method and process parameters of the annealing process. Generally speaking, the thickness of the doping region obtained by microwave annealing and other long-wave light annealing processes is thinner, and the thickness of the doping region obtained by rapid thermal annealing and other thermal annealing processes is thicker.

[0015] (3) Partial etching of the protective layer is performed using an anisotropic SiO2 selective specific etching process.

[0016] The steps (1), (2), and (3) are repeated a predetermined number of times to complete the sidewall doping.

[0017] Preferably, in step (1.1), the wet treatment method is specifically: exposing the sidewall to a 1-5 wt% hydrofluoric acid (HF) solution for 1-2 minutes.

[0018] Preferably, in step (1.1), the dry treatment method is specifically: exposing the sidewall to an H2 plasma cleaning chamber.

[0019] Preferably, in step (1.2), the wet deposition method is specifically: immersing the substrate in a precursor-containing solution at 100-200°C for sufficient reaction.

[0020] Preferably, in step (1.2), the dry deposition method is specifically: filling the precursor molecule gas into an atomic layer deposition (ALD) reaction chamber, so that the reaction molecules react with the pretreated sidewall.

[0021] Preferably, in step (1.2), the organic precursor containing the element to be doped is vinylboronic acid dibutyl ester, or allylboronic acid pinacol ester, or diethyl vinylphosphonate, wherein vinylboronic acid dibutyl ester and allylboronic acid pinacol ester are boron-containing precursors forming p-type doping, and diethyl vinylphosphonate is a phosphorus-containing precursor forming n-type doping.

[0022] Preferably, in step (2), the long-wave optical annealing process uses a substrate temperature of 300-600°C, a light source frequency of 2-10 GHz, and a power of 2000-9000 W.

[0023] Preferably, in step (2), the rapid thermal annealing process uses a temperature of 1000°C.

[0024] As a preferred embodiment, in step (3), a mask definition is performed before etching to protect part of the original sidewall surface.

[0025] As another preferred embodiment, in step (3), the anisotropic SiO2 selective etching process is deep reactive ion etching (DRIE), which uses CF4 and O2 as chemical gases for selective etching of SiO2 to perform longitudinal etching, with a gas flow rate of 10-50 sccm, a plasma generation RF power of 100-500 W, a bias power of 20-200 W for regulating the longitudinal etching characteristics, a gas pressure of 10-50 mTorr, and a temperature of -100-25°C. Advantages

[0026] The present application has the following advantages:

[0027] The method of the present application can be used for sidewalls containing different materials such as silicon and SiO2 as substrates, and through the three steps of cyclic deposition, annealing, and etching of the protective layer, the deep submicron, nanoscale thickness doping of the sidewalls of 3D memory devices can be completed, thereby forming a buffer layer with precise depth and concentration control, solving the problem of difficulty in forming a sidewall buffer layer in such 3D devices.

[0028] All etching in the present application only etches to the surface of the buffer layer, and since the buffer layer itself is a high-resistance semiconductor region, it is not greatly affected by etching, and the consistency of the buffer layer width can be accurately controlled, and the diffusion concentration can be accurately regulated or the thickness of the buffer layer can be adjusted by controlling the number of cycles. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of the deposition step of Embodiment 1 of the present application;

[0030] Figure 2 is a schematic diagram of the annealing step of Embodiment 1 of the present application;

[0031] Figure 3 is a schematic diagram of the etching step of Embodiment 1 of the present application;

[0032] Figure 4 is a schematic diagram of the 3D memory device after repeating the deposition, annealing and etching steps N times of Embodiment 1 of the present application;

[0033] Figure 5 is a schematic diagram of the deposition step of Embodiment 2 of the present application;

[0034] Figure 6 is a schematic diagram of the annealing step of Embodiment 2 of the present application;

[0035] Figure 7 is a schematic diagram of the etching step of Embodiment 2 of the present application;

[0036] Figure 8 is a schematic diagram of the 3D memory device after repeating the deposition, annealing and etching steps N times of Embodiment 2 of the present application. Best Mode for Carrying Out the Invention

[0037] Embodiment 1

[0038] The 3D memory basic structure is generally formed by alternately stacking highly doped n-type polysilicon and silicon dioxide, so the sidewall is formed by repeating highly doped n-type polysilicon and silicon dioxide. For simplicity, only one layer of highly doped n-type polysilicon N+ poly-Si and one layer of silicon dioxide SiO2 are shown in the sidewall of Figure 1.

[0039] Figures 1-4 show a first specific embodiment of the sidewall doping method of the 3D memory device of the present application, which comprises the following steps:

[0040] (1) Depositing on the sidewall of the 3D memory device, the specific steps are as follows:

[0041] (1.1) First, the sidewall surface is pretreated by wet method, i.e. exposing the sidewall to a hydrofluoric acid HF solution with a concentration of 1-5 wt % for 1-2 minutes to form an attachment point for subsequent deposition;

[0042] (1.2) Secondly, self-aligned monolayer deposition is adopted by wet deposition, i.e. the substrate is immersed in a precursor solution and reacted at 100-200°C to deposit boron-containing organic precursors on the sidewall surface of the pretreated substrate; the organic precursor is vinylboronic acid dibutyl ester; the bending curve in FIG. 1 represents the organic branched part of the organic precursor molecule, the process is self-aligned and self-limited, and the process is a self-limited chemical reaction.

[0043] (1.3) Then, a silicon dioxide protective layer material is deposited by chemical vapor deposition (CVD) technology; the presence of the protective layer can effectively help the impurity boron to become a bonding impurity in the subsequent annealing process, forming effective doping.

[0044] The thickness of the protective layer depends on the preset vertical bit line width of the 3D memory array, and the thickness of the monolayer deposition layer depends on the molecular structure of the deposition precursor.

[0045] (2) Annealing is performed by long-wave light annealing process, the substrate temperature is 300-600°C, the light source frequency is 2-10GHz, and the power is 2000-9000W;

[0046] The concentration of bonding boron before annealing is concentrated on the original sidewall surface, and the concentration of bonding boron after annealing diffuses to a certain range of the original sidewall and the protective layer, respectively. The organic molecular part that loses boron atoms loses the connection with the original sidewall surface due to the diffusion of boron atoms and randomly diffuses into the protective layer. FIG. 2 shows the change of the concentration of bonding boron before and after annealing.

[0047] (3) In this embodiment, mask definition is performed before etching to protect part of the original sidewall surface, and then anisotropic SiO2 selective specific etching longitudinal etching process is adopted to etch and remove part of the protective layer;

[0048] The steps (1) deposition, (2) annealing, and (3) etching are repeated N times to complete the sidewall doping. FIG. 4 shows that after N times of repeated cycles, the doping region concentration is multiplied by N, and the thickness t changes little, remaining at about 5-20nm.

[0049] The doping region formed by a single cycle is called a buffer layer after multiple cycles.

[0050] Determination of the number of cycles N: for the case where the doping type of the buffer layer is opposite to the conduction type of the original sidewall low-resistance semiconductor layer, such as forming a p-type buffer layer with a thickness of 20nm in the same layer as the original n+ silicon (the depth of the n+-p type pn junction is generally 1018 cm -3 For limit), using the method of Example 1, if the concentration thereof at a depth of 20 nm is about 10 17 cm -3 after 10 cycles, the requirement can be met. Embodiment of the present application

[0051] Example 2

[0052] Different from Example 1, during the partial annealing process, oxygen atoms in the protective layer SiO2 will diffuse into the sidewall silicon to a certain extent, so that the Si / SiO2 interface will be offset by nanometers (generally 1-2 nm). For this case, a second specific embodiment of the sidewall doping method of the 3D memory device of the present application is proposed, as shown in FIGS. 5-8, including the following steps:

[0053] (1) Depositing the sidewall of the 3D memory device, the specific method of this step can be the same as step (1) of Example 1;

[0054] In FIG. 5, the sidewall only shows one layer of highly doped n-type polysilicon N+ poly-Si and one layer of silicon dioxide SiO2.

[0055] (2) Annealing, different from Example 1, during the annealing process, the oxygen concentration in different regions is not constant, and the boundary between silicon and the protective layer silicon dioxide will be offset. The Si / SiO2 interface generally selects an oxygen content of 10% as a reference, because if anisotropic SiO2 specific etching (for example, the sample after pretreatment and annealing on the silicon substrate is completely placed in an HF solution for wet etching), after the SiO2 is completely etched, the new surface corresponds to a position with an oxygen content of about 10%.

[0056] (3) The etching method of this embodiment needs to be anisotropic longitudinal etching, otherwise the SiO2 in the sidewall will be affected, and also needs to be a selective specific etching only for SiO2, so that etching can be performed according to the new Si / SiO2 boundary. This embodiment uses deep reactive ion etching (DRIE) technology, uses CF4 and O2 as the chemical gas for selective specific etching of SiO2 for longitudinal etching, the gas flow rate is 10-50 sccm, the plasma generation RF power is 100-500 W, the bias power for regulating the etching longitudinal characteristics is 20-200 W, the gas pressure is 10-50 mTorr, and the temperature is -100-25°C.

[0057] In this embodiment, no mask definition is required before etching; the etching range is defined by the new Si / SiO2 boundary after annealing. This etching will not reach a level where the oxygen content is only 0%, and therefore will not etch to the original Si / SiO2 interface, but rather to the new Si / SiO2 interface. Different specific etching methods for SiO2 will result in different new Si / SiO2 interfaces and different oxygen concentrations; therefore, 10% is only a reference value.

[0058] The three steps (1) deposition, (2) annealing, and (3) etching are repeated N times to complete the sidewall doping. Figure 8 shows that after repeating the cycle N times, the thickness of the doped region increases by N times, while the doping concentration distribution does not change much.

[0059] Using the method of Example 2, the doped region thickness is increased with each cycle, and the doping concentration distribution does not change significantly. Therefore, it can be used to precisely control the doped region thickness, i.e., the thickness of the impurity diffusion inward plus the sidewall thickness increased several times. Since the offset of the Si / SiO2 boundary is generally 1-2 nm, which is smaller than the typical thickness of the impurity diffusion inward (e.g., under microwave annealing, typically 10 nm), this method is suitable for precise control of the doped region thickness. 18 cm -3 As a standard for the measurement boundary (5 nm), the concentration of this doped region can uniformly reach 10. 18 cm -3 above.

[0060] The doped region formed in a single cycle eventually forms a buffer layer after multiple cycles.

[0061] Regarding the determination of the number of cycles N: If the Si / SiO2 interface shifts by 2nm in one cycle, and the inward diffusion depth in the first cycle is 5nm (with P-type impurities 10... 18 cm -3 If the limit is 8 cycles, the requirement of forming a 20nm thick buffer layer can be met.

[0062] In summary, for cases where the doping type of the buffer layer is opposite to the conductivity type of the original sidewall low-resistivity semiconductor layer, such as when a p-type buffer layer with a thickness of 20 nm needs to be formed on the original n+ polysilicon sidewall layer (the n+-p-type pn junction depth is generally based on 10 nm of p-type impurities), 18 cm -3 (For the limited purposes), the method of Example 1 or Example 2 can be selected;

[0063] For cases where the doping type of the buffer layer is the same as the conductivity type of the original sidewall low-resistivity semiconductor layer, such as when a p-type buffer layer with a thickness of 20 nm needs to be formed in the same layer as the original sidewall p+ polysilicon, the method of Example 2 is preferred.

[0064] The above embodiments of the present application are only used for illustrating the present application, but not for limiting the present application. Based on the above description, other different forms of changes and variations can be made by those skilled in the art. Here, all the embodiments cannot be enumerated. Any obvious changes or variations derived from the technical solutions of the present application are still within the protection scope of the present application.

Claims

1. A sidewall doping method for a 3D memory device, characterized in that, The method comprises the following steps: (1) performing deposition treatment on the sidewall of the 3D memory device, and the specific steps are: (1.1) first, performing pretreatment on the sidewall surface by using a wet treatment method or a dry treatment method to form an attachment point for subsequent deposition; (1.2) second, performing self-aligned monolayer deposition by using wet deposition or dry deposition to uniformly deposit an organic precursor containing a to-be-doped element on the pretreated sidewall surface; (1.3) then, performing deposition or filling of a silicon dioxide protective layer material by using chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology; (2) performing annealing treatment by using a long-wave light annealing process or a rapid thermal annealing process; (3) performing longitudinal etching by using an anisotropic SiO2 selective specific etching process to remove part of the protective layer; The steps (1), (2) and (3) are repeatedly performed for a predetermined number of times to complete sidewall doping. 2.The method of claim 1, wherein In step (1.1), the wet treatment method is specifically: exposing the sidewall to a hydrofluoric acid (HF) solution with a concentration of 1-5 wt % for 1-2 minutes. 3.The method of claim 1, wherein In step (1.1), the dry treatment method is specifically: exposing the sidewall to an H2 plasma cleaning cavity. 4.The method of claim 1, wherein In step (1.2), the wet deposition method is specifically: immersing the substrate into a precursor solution and performing sufficient reaction at 100-200 °C. 5.The method of Claim 1, wherein In step (1.2), the dry deposition method is specifically: filling a precursor molecule gas into an atomic layer deposition (ALD) reaction cavity to make the reaction molecules fully react with the pretreated sidewall. 6.The method of Claim 1, wherein In step (1.2), the organic precursor containing a to-be-doped element is vinylboronic acid dibutyl ester, or allylboronic acid pinacol ester, or diethyl vinylphosphonate. 7.The method of claim 1, wherein In step (2), the substrate temperature used in the long-wave light annealing process is 300-600 °C, the light source frequency is 2-10 GHz, and the power is 2000-9000 W. 8.The method of Claim 1, wherein In step (2), the temperature of the rapid thermal annealing process is 1000 °C. 9.The method of claim 1, wherein In step (3), a mask definition is further performed before etching to protect part of the original sidewall surface. 10.The method of Claim 1, wherein In step (3), the anisotropic SiO2 selective specific etching longitudinal etching process is specifically deep reactive ion etching (DRIE), and CF4 and O2 are used as chemical gases for selectively etching SiO2 to perform longitudinal etching, the gas flow rate is 10-50 sccm, the generated plasma RF power is 100-500 W, the bias power for controlling the longitudinal etching characteristics is 20-200 W, the gas pressure is 10-50 mTorr, and the temperature is -100-25 °C.

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