Display panel and display device

Abstract

Disclosed in the present disclosure are a display panel and a display device. The display panel comprises an array substrate and an opposing substrate, which are aligned with each other to form a cell, and a liquid crystal layer, which is located between the array substrate and the opposing substrate, wherein the array substrate comprises a first base, gate lines and data lines arranged on the side of the first base close to the liquid crystal layer and insulated from and intersecting each other, and a plurality of first sub PSs arranged on the side of the gate lines and the data lines close to the liquid crystal layer, the first sub PSs and the data lines extending in the same direction, and the orthographic projections of the first sub PSs on the first base overlapping with the orthographic projections of intersection regions of the gate lines and the data lines on the first base; and the opposing substrate comprises a second base and a plurality of second sub PSs arranged on the side of the second base close to the liquid crystal layer, the second sub PSs and the data lines extending in the same direction, the second sub PSs corresponding to the first sub PSs on a one-to-one basis, and the orthographic projections of the second sub PSs on the first base at least partially overlapping with the orthographic projections of the first sub PSs on the first base.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411046275.9, filed on July 31, 2024, and entitled "A display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and display device. BACKGROUND

[0004] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation and portability, and has been rapidly developed in recent years. It has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market.

[0005] A liquid crystal display panel includes an array substrate and a color film substrate arranged oppositely, and a liquid crystal layer between the array substrate and the color film substrate. In order to support the array substrate and the color film substrate when the liquid crystal display panel is boxed, so as to ensure that the required cell thickness is obtained, a spacer (PS) is generally arranged between the color film substrate and the array substrate. The spacer generally includes a main spacer (Main PS) and a sub spacer (Sub PS), the height of the main spacer is generally greater than the height of the sub spacer, and the area density of the main spacer and the sub spacer maintains a certain proportion. SUMMARY

[0006] The embodiments of the present disclosure provide a display panel and display device to improve the aperture ratio of the display panel.

[0007] The display panel provided by the embodiments of the present disclosure includes an array substrate and a facing substrate arranged in a box, and a liquid crystal layer between the array substrate and the facing substrate.

[0008] The array substrate comprises: a first substrate, a plurality of gate lines and a plurality of data lines which are arranged in an insulating cross manner on a side of the first substrate close to the liquid crystal layer, and a plurality of first auxiliary spacers arranged on a side of the gate lines and the data lines close to the liquid crystal layer; wherein the first auxiliary spacers are in the same extension direction as the data lines, and a projection of the first auxiliary spacers on the first substrate and a projection of the intersection area of the gate lines and the data lines on the first substrate overlap each other.

[0009] The opposite substrate comprises: a second substrate, and a plurality of second auxiliary spacers arranged on a side of the second substrate close to the liquid crystal layer; wherein the second auxiliary spacers are in the same extension direction as the data lines, each of the second auxiliary spacers corresponds to each of the first auxiliary spacers, and a projection of the second auxiliary spacers on the first substrate and a projection of the first auxiliary spacers on the first substrate at least partially overlap.

[0010] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the gate lines and the data lines cross to define a plurality of rows and a plurality of columns of pixel units, each of the pixel units comprises a plurality of sub-pixels of different color resist colors, the color resist colors of the sub-pixels in the same row are the same, the color resist colors of the sub-pixels in the same column are not completely the same, each of the sub-pixels in the same column is electrically connected to the same data line, the sub-pixels in different columns are electrically connected to different data lines, and each row of the pixel units arranged in the pixel row direction is electrically connected to three rows of the gate lines.

[0011] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the projections of the first auxiliary spacers and the second auxiliary spacers on the first substrate are all strip-shaped, and the length of the first auxiliary spacer along the extension direction of the data line is greater than the length of the second auxiliary spacer along the extension direction of the data line.

[0012] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the length of the first auxiliary spacer along the extension direction of the gate line is less than the length of the second auxiliary spacer along the extension direction of the gate line.

[0013] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the length of the first auxiliary spacer along the extension direction of the gate line is greater than the length of the second auxiliary spacer along the extension direction of the gate line.

[0014] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the first auxiliary spacers and the second auxiliary spacers are both in strip shape in the orthographic projection on the first substrate, and the length of the first auxiliary spacer along the extension direction of the data line is less than the length of the second auxiliary spacer along the extension direction of the data line.

[0015] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the length of the first auxiliary spacer along the extension direction of the gate line is greater than the length of the second auxiliary spacer along the extension direction of the gate line.

[0016] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the length of the first auxiliary spacer along the extension direction of the gate line is less than the length of the second auxiliary spacer along the extension direction of the gate line.

[0017] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the center line of the first auxiliary spacer along the extension direction of the data line coincides with the center line of the second auxiliary spacer along the extension direction of the data line.

[0018] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the array substrate further comprises: a black matrix and a filter layer between the second substrate and the second auxiliary spacer, a first planar layer between the black matrix, the filter layer and the second auxiliary spacer, and a first alignment layer on the side of the second auxiliary spacer close to the liquid crystal layer; the black matrix comprises a plurality of openings, and the filter layer comprises a plurality of filter pieces, and the orthographic projection of each filter piece on the second substrate covers the orthographic projection of the corresponding opening on the second substrate.

[0019] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the array substrate further comprises: a second planar layer between the gate line, the data line and the first auxiliary spacer, a first transparent electrode layer between the second planar layer and the first auxiliary spacer, a passivation layer between the first transparent electrode layer and the first auxiliary spacer, a second transparent electrode layer between the passivation layer and the first auxiliary spacer, and a second alignment layer on the side of the first auxiliary spacer close to the liquid crystal layer.

[0020] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the array substrate further comprises: a second planar layer between the gate lines, the data lines and the first auxiliary spacers; a first transparent electrode layer on a side of the second planar layer close to the liquid crystal layer; a passivation layer on a side of the first transparent electrode layer close to the liquid crystal layer; a second transparent electrode layer on a side of the passivation layer close to the liquid crystal layer; and a second alignment layer on a side of the second transparent electrode layer close to the liquid crystal layer; wherein

[0021] The first auxiliary spacer and the second planar layer are in an integrated structure.

[0022] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the array substrate further comprises a plurality of first main spacers arranged in the same layer as the first auxiliary spacers, and the opposite substrate further comprises a plurality of second main spacers arranged in the same layer as the second auxiliary spacers, and the sum of the thicknesses of the first main spacers and the second main spacers is greater than the sum of the thicknesses of the first auxiliary spacers and the second auxiliary spacers.

[0023] Each of the second main spacers corresponds to each of the first main spacers, the orthographic projection of the second main spacer on the first substrate intersects the orthographic projection of the first main spacer on the first substrate, and the orthographic projections of the first main spacers and the second main spacers on the first substrate respectively overlap the orthographic projections of the intersection regions of the gate lines and the data lines on the first substrate.

[0024] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the intersection regions on both sides of the gate lines adjacent to the pair of first main spacers and second main spacers are not provided with the first auxiliary spacers and the second auxiliary spacers, and are not provided with the first main spacers and the second main spacers.

[0025] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the orthographic projection of the black matrix on the first substrate covers the orthographic projections of the gate lines, the data lines, the first auxiliary spacers, the second auxiliary spacers, the first main spacers and the second main spacers on the first substrate.

[0026] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the width of the black matrix corresponding to the region where the first main separation wall and the second main separation wall are arranged in pairs along the extension direction of the gate line is greater than the width of the black matrix corresponding to the region where the first auxiliary separation wall and the second auxiliary separation wall are arranged in pairs along the extension direction of the gate line, and the width of the black matrix corresponding to the region where the first auxiliary separation wall and the second auxiliary separation wall are arranged in pairs along the extension direction of the gate line is greater than the width of the black matrix corresponding to the region where no separation wall is arranged along the extension direction of the gate line.

[0027] In some embodiments, in the display panel provided in the embodiments of the present disclosure, one of the first transparent electrode layer and the second transparent electrode layer is a planar electrode, and the other includes a plurality of slit electrodes.

[0028] Correspondingly, the embodiments of the present disclosure also provide a display device including the display panel provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0030] FIG. 1 is a schematic diagram of a pixel architecture of a display panel provided in the embodiments of the present disclosure;

[0031] FIG. 2 is a schematic diagram of a cross section of a display panel provided in the embodiments of the present disclosure;

[0032] FIG. 3 is a schematic diagram of a top view of some film layers of an array substrate and a counter substrate in FIG. 2;

[0033] FIG. 4 is an actual layout of the array substrate in FIG. 2 under a microscope;

[0034] FIG. 5 is an actual layout of the counter substrate in FIG. 2 under a microscope;

[0035] FIG. 6 is a schematic diagram of a top view of the first auxiliary separation wall and the second auxiliary separation wall in FIG. 2;

[0036] FIG. 7 is a schematic diagram of an alternative top view of the first auxiliary separation wall and the second auxiliary separation wall in FIG. 2;

[0037] FIG. 8 is a schematic diagram of another alternative top view of the first auxiliary separation wall and the second auxiliary separation wall in FIG. 2;

[0038] FIG. 9 is a top view of a schematic diagram of FIG. 2, showing an alternative arrangement of the first auxiliary spacers and the second auxiliary spacers;

[0039] FIG. 10 is a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0040] FIG. 11 is a top view of a schematic diagram of FIG. 10, showing the first auxiliary spacers and the second auxiliary spacers;

[0041] FIG. 12 is a top view of a schematic diagram of FIG. 10, showing an alternative arrangement of the first auxiliary spacers and the second auxiliary spacers;

[0042] FIG. 13 is a top view of a schematic diagram of FIG. 10, showing an alternative arrangement of the first auxiliary spacers and the second auxiliary spacers;

[0043] FIG. 14 is a top view of a schematic diagram of FIG. 10, showing an alternative arrangement of the first auxiliary spacers and the second auxiliary spacers;

[0044] FIG. 15 is a top view of a schematic diagram of FIGS. 2-5 and 10, showing the first main spacers and the second main spacers;

[0045] FIG. 16 is a plan view of the normal projection of the black matrix, the main spacers and the auxiliary spacers on the second substrate;

[0046] FIG. 17 is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0047] FIG. 18 is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0048] FIG. 19 is a structural view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict if possible. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0050] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "comprise", and similar terms are intended to mean that the elements or objects listed after the terms encompass the elements or objects recited after the terms, and equivalents thereof, without precluding other elements or objects. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect.

[0051] It should be noted that the size and shape of the various figures in the drawings are not intended to represent true proportions or dimensions, but are intended to be illustrative only. Like or similar designations in the drawings represent like or similar elements or elements having the same or similar function.

[0052] With the continuous maturity of liquid crystal display technology, the driving backplane of LCD has gradually developed towards low cost and low power consumption. At present, the driving backplane reduces the number of data line (Data) signal channels by increasing the gate driving circuit (GOA) and gate line (Gate) for time-sharing driving, thereby reducing the number of driving chips (IC) used, to realize the Multiple Gate technology of low cost and low power consumption, which is the focus of research.

[0053] The commonly used multiple gate pixel architecture is Triple Gate (three gates, each row of pixel units is driven by three rows of gate lines), as shown in FIG. 1, G1, G2, … are gate lines, D1, D2, … are data lines, and each pixel unit includes multiple color sub-pixels (such as R, G, B) of different color resist colors. Multiple gate driving can reduce power consumption and cost, but inevitably leads to a decrease in pixel aperture ratio, thereby causing a decrease in display effect.

[0054] In the related art, the most commonly used spacer is a columnar spacer abutting between the array substrate and the color film substrate. The columnar spacer can be scratched by sliding due to external force, further causing poor alignment of liquid crystal in the scratched area and accompanying light leakage problem. In order to solve the sub-pixel area light leakage problem caused by the columnar spacer scratching the liquid crystal alignment film when the array substrate and the color film substrate slide, the width of the black matrix pattern in the color film substrate often needs to be additionally increased to improve the shielding effect, but the aperture ratio of the liquid crystal display panel is reduced. With the increasing demand for high resolution and high transmittance display, the related art has proposed a design of using cross strip spacers (XPS) on both sides of the display panel, that is, spacers are arranged on both the array substrate and the color film substrate, and the spacers on the array substrate and the color film substrate are cross designed. The distance between the spacers on both sides is far away from the opposite substrate, and the single side spacer is relatively low. The top of the spacer is difficult to contact the alignment layer, and it is more difficult to scratch the substrate, so as not to increase the width of the additional black matrix pattern to improve the aperture ratio. However, since the spacers on the array substrate and the color film substrate are cross placed, the spacers on one side need to be shielded by additional black matrix based on the original black matrix design, which loses part of the aperture ratio.

[0055] Therefore, while reducing power consumption and cost by using Triple Gate, how to increase the aperture ratio as much as possible has become a direction that needs to be researched and solved in the field.

[0056] The display panel provided by the embodiments of the present disclosure is shown in FIG. 2, which is a cross-sectional schematic view of the display panel, and includes an array substrate 1 and a counter substrate 2 arranged in a cell, and a liquid crystal layer 3 located between the array substrate 1 and the counter substrate 2.

[0057] Specifically, as shown in FIGS. 2-4, FIG. 3 is a top view schematic diagram of part of the film layers of the array substrate 1 and the counter substrate 2 in FIG. 2, and FIG. 4 is an actual layout of the array substrate under a microscope in FIG. 2. The array substrate 1 includes a first substrate 11, a plurality of gate lines (G1, G2, …) and a plurality of data lines (D1, D2, …) arranged in an insulating cross manner on a side of the first substrate 11 close to the liquid crystal layer 3, and a plurality of first auxiliary spacers 12 arranged on a side of the gate lines (G1, G2, …) and the data lines (D1, D2, …) close to the liquid crystal layer.

[0058] Specifically, as shown in FIG. 2, FIG. 3 and FIG. 5, the opposite substrate 2 includes: a second substrate 21, and a plurality of second auxiliary spacers 22 arranged on the second substrate 21 close to the liquid crystal layer 3; wherein the second auxiliary spacers 22 are in the same extension direction as the data lines (D1, D2, …), each second auxiliary spacer 22 corresponds to each first auxiliary spacer 12 one by one, and the orthographic projection of the second auxiliary spacer 22 on the first substrate 11 at least partially overlaps the orthographic projection of the first auxiliary spacer 12 on the first substrate 11.

[0059] It should be noted that after the cell is assembled in FIG. 4 and FIG. 5, the first auxiliary spacer 12 in FIG. 4 and the second auxiliary spacer 22 in FIG. 5 correspond one by one to form the structure shown in FIG. 3 that the first auxiliary spacer 12 and the second auxiliary spacer 22 extend along the extension direction of the data line and the orthographic projection overlaps.

[0060] The display panel provided by the embodiments of the present disclosure is designed as an array substrate and an opposite substrate double-sided structure, and the auxiliary spacers on both sides extend along the extension direction of the data line, that is, the first auxiliary spacer and the second auxiliary spacer after the cell is assembled extend along the extension direction of the data line. Since the critical dimension (CD) of the black matrix along the extension direction of the data line is relatively wide, PSMura can be prevented. Therefore, the present disclosure does not need too many additional black matrices to shield the auxiliary spacers, which can reduce the area of the black matrix around the auxiliary spacers, increase the effective display area, improve the product transmittance, and improve the product competitiveness while preventing PSMura. In addition, the contact area between the auxiliary spacers is increased, the friction force is enhanced, and the auxiliary spacers are less likely to slide, which can further prevent PSMura. Compared with the XPS design in the related art, the size of the auxiliary spacer of the present disclosure is smaller under the same contact area. Therefore, the present disclosure can meet the supporting effect by using smaller auxiliary spacer size and narrower black matrix shielding distance, improve the pixel aperture ratio, and achieve high-transmittance specifications.

[0061] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1, 3-5, the gate lines (G1, G2, …) and the data lines (D1, D2, …) cross to define a plurality of rows and columns of pixel units P, each pixel unit P includes a plurality of sub-pixels (for example, R, G, B) of different color resist colors, the color resist colors of the sub-pixels in the same row are the same, the color resist colors of the sub-pixels in the same column are not completely the same (for example, the same column is arranged as RGBRGBRGB…), the sub-pixels in the same column are electrically connected to the same data line, the sub-pixels in different columns are electrically connected to different data lines, and each row of pixel units P arranged in the pixel row direction is electrically connected to three rows of gate lines, that is, the pixel architecture of the embodiments of the present disclosure is Triple Gate, and multi-gate driving can reduce power consumption and cost. For example, the first row of pixel units P is electrically connected to the gate lines (G1, G2, G3), the first row of sub-pixels R in the first row of pixel units P is electrically connected to G1, the second row of sub-pixels G in the first row of pixel units P is electrically connected to G2, the third row of sub-pixels B in the first row of pixel units P is electrically connected to G3, the second row of pixel units P is electrically connected to the gate lines (G4, G5, G6), the first row of sub-pixels R in the second row of pixel units P is electrically connected to G4, the second row of sub-pixels G in the second row of pixel units P is electrically connected to G5, and the third row of sub-pixels B in the second row of pixel units P is electrically connected to G6, and the like.

[0062] It should be noted that the present disclosure takes Triple Gate (three-gate) as an example, that is, each row of pixel units is driven by three rows of gate lines, but it is of course not limited thereto; for example, the pixel architecture of the present disclosure can also be single-gate driving, double-gate driving, or even more rows of gate line driving.

[0063] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 3-6, FIG. 6 is a top view of the first auxiliary spacer 12 and the second auxiliary spacer 22 in FIG. 2, the orthogonal projection of the first auxiliary spacer 12 and the second auxiliary spacer 22 on the first substrate 11 is a strip, the length a1 of the first auxiliary spacer 12 in the extension direction of the data line (D1, D2, …) can be greater than the length a2 of the second auxiliary spacer 22 in the extension direction of the data line (D1, D2, …), and the length b1 of the first auxiliary spacer 12 in the extension direction of the gate line (G1, G2, …) can be less than the length b2 of the second auxiliary spacer 22 in the extension direction of the gate line (G1, G2, …). Specifically, the present embodiment takes the first auxiliary spacer 12 as an example which is relatively long and thin, and the second auxiliary spacer 22 is relatively short and thick.

[0064] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 7, which is a top view of an alternative of the first auxiliary spacers 12 and the second auxiliary spacers 22 in the separate schematic view 2, the orthographic projections of the first auxiliary spacers 12 and the second auxiliary spacers 22 on the first substrate 11 are strips, the length a1 of the first auxiliary spacers 12 along the extension direction of the data lines (D1, D2, …) can be greater than the length a2 of the second auxiliary spacers 22 along the extension direction of the data lines (D1, D2, …), and the length b1 of the first auxiliary spacers 12 along the extension direction of the gate lines (G1, G2, …) can be greater than the length b2 of the second auxiliary spacers 22 along the extension direction of the gate lines (G1, G2, …). Specifically, this embodiment is an example in which the first auxiliary spacers 12 and the second auxiliary spacers 22 are both relatively long and thin.

[0065] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 8, which is a top view of another alternative of the first auxiliary spacers and the second auxiliary spacers in the separate schematic view 2, the orthographic projections of the first auxiliary spacers 12 and the second auxiliary spacers 22 on the first substrate 11 are strips, the length a1 of the first auxiliary spacers 12 along the extension direction of the data lines (D1, D2, …) can be less than the length a2 of the second auxiliary spacers 22 along the extension direction of the data lines (D1, D2, …), and the length b1 of the first auxiliary spacers 12 along the extension direction of the gate lines (G1, G2, …) can be greater than the length b2 of the second auxiliary spacers 22 along the extension direction of the gate lines (G1, G2, …). Specifically, this embodiment is an example in which the first auxiliary spacers 12 are relatively short and thick, and the second auxiliary spacers 22 are relatively long and thin.

[0066] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 9, which is a top view of another alternative of the first auxiliary spacers and the second auxiliary spacers in the separate schematic view 2, the orthographic projections of the first auxiliary spacers 12 and the second auxiliary spacers 22 on the first substrate 11 are strips, the length a1 of the first auxiliary spacers 12 along the extension direction of the data lines (D1, D2, …) can be less than the length a2 of the second auxiliary spacers 22 along the extension direction of the data lines (D1, D2, …), and the length b1 of the first auxiliary spacers 12 along the extension direction of the gate lines (G1, G2, …) can be less than the length b2 of the second auxiliary spacers 22 along the extension direction of the gate lines (G1, G2, …). Specifically, this embodiment is an example in which the first auxiliary spacers 12 and the second auxiliary spacers 22 are both relatively long and thin.

[0067] It should be noted that the shapes of the first auxiliary spacers 12 and the second auxiliary spacers 22 in FIGS. 3-5 can be replaced by any one of the shapes in FIGS. 7-9.

[0068] It should be noted that FIGS. 6-9 are all examples in which a1 is not equal to a2 and b1 is not equal to b2. Of course, a1 can be equal to a2 and b1 can be equal to b2.

[0069] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 6-9, the center line of the first auxiliary spacer 12 along the extension direction of the data line (D1, D2, …) coincides with the center line of the second auxiliary spacer 22 along the extension direction of the data line (D1, D2, …), which can further reduce the width of the black matrix along the extension direction of the gate line (G1, G2, …) and further improve the aperture ratio.

[0070] It should be noted that the above-mentioned center line coincidence refers to approximate coincidence. Due to the influence of the manufacturing process, the center line of the first auxiliary spacer 12 along the extension direction of the data line (D1, D2, …) can have a certain deviation from the center line of the second auxiliary spacer 22 along the extension direction of the data line (D1, D2, …).

[0071] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 2, 3 and 5, the facing substrate 2 further comprises: a black matrix 4 and a filter layer 5 located between the second substrate 21 and the second auxiliary spacer 22, a first planar layer 6 located between the black matrix 4 and the filter layer 5 and the second auxiliary spacer 22, and a first alignment layer 7 located on the side of the second auxiliary spacer 22 close to the liquid crystal layer 3; the black matrix 4 comprises a plurality of openings, the filter layer 5 comprises a plurality of filter pieces 51, and the orthographic projection of each filter piece 51 on the second substrate 21 covers the orthographic projection of the corresponding opening on the second substrate 21. Specifically, the filter piece 51 can comprise a red filter piece (R), a green filter piece (G) and a blue filter piece (B).

[0072] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 2-4, the array substrate 1 further comprises: a second planar layer 8 located between the gate line (G1, G2, …) and the data line (D1, D2, …) and the first auxiliary spacer 12, a first transparent electrode layer 9 located between the second planar layer 8 and the first auxiliary spacer 12, a passivation layer 10 located between the first transparent electrode layer 9 and the first auxiliary spacer 12, a second transparent electrode layer 20 located between the passivation layer 10 and the first auxiliary spacer 12, and a second alignment layer 29 located on the side of the first auxiliary spacer 12 close to the liquid crystal layer 3.

[0073] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 3, 4 and 10, the array substrate 1 further comprises: a second planar layer 8 between the gate lines (G1, G2, …) and the data lines (D1, D2, …) and the first auxiliary spacers 12, a first transparent electrode layer 9 on the side of the second planar layer 8 close to the liquid crystal layer 3, a passivation layer 10 on the side of the first transparent electrode layer 9 close to the liquid crystal layer 3, a second transparent electrode layer 20 on the side of the passivation layer 10 close to the liquid crystal layer 3, and a second alignment layer 29 on the side of the second transparent electrode layer 20 close to the liquid crystal layer 3; wherein,

[0074] The first auxiliary spacers 12 and the second planar layer 8 are in an integrated structure.

[0075] In this way, only the original patterning pattern needs to be changed when forming the second planar layer 8, that is, the pattern of the first auxiliary spacers 12 and the second planar layer 8 can be formed by one-time patterning process, without increasing the process of separately preparing the first auxiliary spacers 12, so that the preparation process flow can be simplified, the production cost can be saved, and the production efficiency can be improved.

[0076] Specifically, the material of the second planar layer 8 is an organic material, and the first auxiliary spacers 12 and the second planar layer 8 can be manufactured by a half tone mask (HTM) process.

[0077] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 10 and 11, FIG. 11 is a top view of the first auxiliary spacers 12 and the second auxiliary spacers 22 in FIG. 10, wherein the length a1 of the first auxiliary spacers 12 along the extension direction of the data lines (D1, D2, …) can be greater than the length a2 of the second auxiliary spacers 22 along the extension direction of the data lines (D1, D2, …), and the length b1 of the first auxiliary spacers 12 along the extension direction of the gate lines (G1, G2, …) can be less than the length b2 of the second auxiliary spacers 22 along the extension direction of the gate lines (G1, G2, …).

[0078] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 10 and 12, FIG. 12 is another top view of the first auxiliary spacers 12 and the second auxiliary spacers 22 in FIG. 10, wherein the length a1 of the first auxiliary spacers 12 along the extension direction of the data lines (D1, D2, …) can be greater than the length a2 of the second auxiliary spacers 22 along the extension direction of the data lines (D1, D2, …), and the length b1 of the first auxiliary spacers 12 along the extension direction of the gate lines (G1, G2, …) can be greater than the length b2 of the second auxiliary spacers 22 along the extension direction of the gate lines (G1, G2, …).

[0079] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 10 and FIG. 13, FIG. 13 is another top view of the first auxiliary spacer 12 and the second auxiliary spacer 22 in FIG. 10, wherein the length a1 of the first auxiliary spacer 12 along the extension direction of the data line (D1, D2, …) can be less than the length a2 of the second auxiliary spacer 22 along the extension direction of the data line (D1, D2, …), and the length b1 of the first auxiliary spacer 12 along the extension direction of the gate line (G1, G2, …) can be greater than the length b2 of the second auxiliary spacer 22 along the extension direction of the gate line (G1, G2, …).

[0080] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 10 and FIG. 14, FIG. 14 is another top view of the first auxiliary spacer 12 and the second auxiliary spacer 22 in FIG. 10, wherein the length a1 of the first auxiliary spacer 12 along the extension direction of the data line (D1, D2, …) can be less than the length a2 of the second auxiliary spacer 22 along the extension direction of the data line (D1, D2, …), and the length b1 of the first auxiliary spacer 12 along the extension direction of the gate line (G1, G2, …) can be less than the length b2 of the second auxiliary spacer 22 along the extension direction of the gate line (G1, G2, …).

[0081] It should be noted that FIGS. 11-14 are all examples in which a1 is not equal to a2 and b1 is not equal to b2. Of course, a1 can be equal to a2 and b1 can be equal to b2.

[0082] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 2 and FIG. 10, one of the first transparent electrode layer 9 and the second transparent electrode layer 20 is a surface electrode, and the other includes a plurality of slit electrodes. For example, the second transparent electrode layer 20 is a surface electrode, and the first transparent electrode layer 9 includes a plurality of slit electrodes. Exemplarily, one of the first transparent electrode layer 9 and the second transparent electrode layer 20 is a pixel electrode, and the other is a common electrode.

[0083] Specifically, as shown in FIGS. 2-4 and 10, the array substrate 1 further comprises: a light shielding layer 30 between the first substrate 11 and the second planar layer 8, a buffer layer 23 between the light shielding layer 30 and the second planar layer 8, an active layer 24 between the buffer layer 23 and the second planar layer 8, a gate insulating layer 25 between the active layer 24 and the second planar layer 8, a gate metal layer 26 between the gate insulating layer 25 and the second planar layer 8, an interlayer insulating layer 27 between the gate metal layer 26 and the second planar layer 8, and a source-drain metal layer 28 between the interlayer insulating layer 27 and the second planar layer 8; wherein the gate metal layer 26 can include a gate G, a gate line, etc., the source-drain metal layer 28 can include a source S, a drain D, a data line, a common signal line com, etc., the active layer 24, the gate G, the source S and the drain D constitute a thin film transistor, and each slit electrode of the first transparent electrode layer 9 is electrically connected with the drain D through a via hole penetrating through the second planar layer 8, so as to realize inputting of an electrical signal to the slit electrode through the thin film transistor.

[0084] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as shown in FIGS. 2-5, 10 and 15, FIG. 15 is a top view of the first main spacers 31 and the second main spacers 32 in FIGS. 2-5 and 10, the array substrate 1 further comprises a plurality of first main spacers 31 arranged in the same layer as the first auxiliary spacers 12, and the opposite substrate 2 further comprises a plurality of second main spacers 32 arranged in the same layer as the second auxiliary spacers 22.

[0085] Each second main spacer 32 corresponds to each first main spacer 31, the orthographic projection of the second main spacer 32 on the first substrate 11 intersects with the orthographic projection of the first main spacer 31 on the first substrate 11, and the orthographic projections of the first main spacer 31 and the second main spacer 32 on the first substrate 11 respectively overlap with the orthographic projections of the intersection areas of the gate lines (G1, G2,...) and the data lines (D1, D2,...) on the first substrate 11.

[0086] Specifically, as shown in FIGS. 2-5, 10 and 15, the main spacers of the embodiments of the present disclosure adopt a double-side spacer intersection design, for example, the second main spacers 32 and the first main spacers 31 are cross-shaped and overlapped, so that the distance from the first main spacer 31 to the edge of the second main spacer 32 is relatively far, and the distance from the second main spacer 32 to the edge of the first main spacer 31 is also relatively far. When the spacers slide, each side spacer is not easy to scratch the black matrix area and damage the opposite orientation layer, so the design of the main spacers provided by the embodiments of the present disclosure has good anti-PS Mura capability. At the same time, the main spacers do not affect the aperture ratio, so the product designed by the main spacers and the auxiliary spacers provided by the present disclosure has both good anti-PS Mura capability and high transmittance.

[0087] Specifically, as shown in FIG. 2 and FIG. 10, the sum of the thicknesses of the first main spacer 31 and the second main spacer 32 is greater than the sum of the thicknesses of the first auxiliary spacer 12 and the second auxiliary spacer 22. In normal circumstances, the cell thickness of the display panel is supported by the pair of the first main spacer 31 and the second main spacer 32. When the display panel is pressed by a vertical external force or is in a low-temperature condition, the cell thickness of the display panel is reduced, for example, the array substrate is close to the counter substrate, resulting in that the main spacer is excessively pressed and cannot provide sufficient support, or one side of the main spacer is cut off, and the main spacer cannot provide sufficient support because it is not in contact with the counter substrate. At this time, the auxiliary spacer gradually approaches and contacts the counter substrate to provide sufficient support and maintain the uniformity of the cell thickness.

[0088] It should be noted that the thickness of the first main spacer 31 can be greater than the thickness of the first auxiliary spacer 12, and the thickness of the second main spacer 32 can be greater than the thickness of the second auxiliary spacer 22; or the thickness of the first main spacer 31 can be the same as the thickness of the first auxiliary spacer 12, and the thickness of the second main spacer 32 can be greater than the thickness of the second auxiliary spacer 22; or the thickness of the second main spacer 32 can be the same as the thickness of the second auxiliary spacer 22, and the thickness of the first main spacer 31 can be greater than the thickness of the first auxiliary spacer 12.

[0089] Specifically, the embodiment of the present disclosure takes the first main spacer 31 and the first auxiliary spacer 12 as an example, and the thickness of the second main spacer 32 is greater than the thickness of the second auxiliary spacer 22.

[0090] In some embodiments, in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 4 and FIG. 5, the two side intersection regions (A1 region and A2 region) adjacent to the pair of the first main spacer 31 and the second main spacer 32 along the extension direction of the gate line (G1, G2…) are not provided with the first auxiliary spacer 12 and the second auxiliary spacer 22, and are not provided with the first main spacer 31 and the second main spacer 32. In this way, because the difference between the second main spacer 32 on the side of the counter substrate 2 and the second auxiliary spacer 22 is generally small, and the second main spacer 32 is a positioning PS, the left and right sides of the main spacer are generally not provided with auxiliary spacers, so as to realize better cell alignment of the array substrate 1 and the counter substrate 2.

[0091] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 3-5, the orthographic projection of the black matrix 4 on the first substrate 11 covers the orthographic projection of the gate lines (G1, G2…), the data lines (D1, D2…), the first auxiliary spacer 12, the second auxiliary spacer 22, the first main spacer 31, and the second main spacer 32 on the first substrate 11. Since the first auxiliary spacer 12 and the second auxiliary spacer 22 adopt the one-dimensional overlapping design along the extension direction of the data lines, the width of the black matrix 4 on the left and right sides of the first auxiliary spacer 12 and the second auxiliary spacer 22 can be reduced, thereby improving the aperture ratio of the display panel.

[0092] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 16, which is a schematic diagram of the orthographic projection of the black matrix 4, the main spacers (31 and 32), and the auxiliary spacers (12 and 22) on the second substrate 2, the width W1 of the black matrix 4 corresponding to the region where the first main spacer 31 and the second main spacer 32 are arranged in pairs along the extension direction of the gate lines (G1, G2…) is greater than the width W2 of the black matrix 4 corresponding to the region where the first auxiliary spacer 12 and the second auxiliary spacer 22 are arranged in pairs along the extension direction of the gate lines (G1, G2…), and the width W2 of the black matrix 4 corresponding to the region where the first auxiliary spacer 12 and the second auxiliary spacer 22 are arranged in pairs along the extension direction of the gate lines (G1, G2…) is greater than the width W3 of the black matrix 4 corresponding to the region where no spacer is arranged. In this way, the width of the black matrix 4 is designed according to whether there is a spacer and the shape of the spacer, which can further improve the aperture ratio.

[0093] Optionally, the design of the auxiliary spacer in the display panel provided in the embodiments of the present disclosure can be applied to curved screen products, especially the design of long strip curved screens. Since the PSs in the bending direction of the curved screen will relatively slide when the curved screen is bent, when the long side direction of the auxiliary spacer in the present disclosure is parallel to the bending direction of the curved screen, the relatively sliding distance of the PSs is large due to the large overlapping area of the spacers on both sides of this direction, and the PSs are not easy to slide when the screen is bent, and there is little risk of PS Mura.

[0094] It is found through tests by the inventors of the present case that, compared with the cross-shaped auxiliary spacer design in the related art, the aperture ratio of the present disclosure can be improved by about 5.1%; compared with the columnar auxiliary spacer design in the related art, the aperture ratio of the present disclosure can be improved by about 11.2%, so that the present disclosure can achieve a product specification with a higher transmittance.

[0095] It should be noted that other essential components in the display panel are understood by those skilled in the art, which will not be described here and should not be regarded as a limitation on the present disclosure.

[0096] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes the display panel provided by the embodiments of the present disclosure. Since the principle of solving the problem of the display device is similar to that of the display panel, the implementation of the display device provided by the embodiments of the present disclosure can be referred to the implementation of the display panel, and the repeated parts will not be described herein.

[0097] In some embodiments, in the display device provided by the embodiments of the present disclosure, as shown in FIGS. 17 and 18, a backlight module 100 is further included on the light entering side of the array substrate 1.

[0098] In some embodiments, in the display device provided by the embodiments of the present disclosure, the backlight module 100 can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can include a light bar, a reflection sheet, a light guide plate, a diffusion sheet, a prism group, etc., and the light bar is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflection sheet, a diffusion plate and a brightness enhancement film, etc., which are stacked on the light emitting side of the matrix light source, and the reflection sheet includes openings corresponding to the positions of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light emitting diodes (LEDs), such as micro light emitting diodes (Mini LED, Micro LED, etc.).

[0099] The micro light emitting diode in the order of sub-millimeter or even micrometer and the organic light emitting diode (OLED) are both self-luminous devices. They have a series of advantages such as high brightness, ultra-low delay, ultra-large viewing angle, etc. And because the inorganic light emitting diode emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared with the organic light emitting diode which emits light based on organic matter. And when the micro light emitting diode is used as a backlight source, it can achieve more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the light and dark areas of the screen, and optimize the visual experience.

[0100] In specific implementation, the display device provided by the embodiments of the present disclosure is a liquid crystal display device, which further includes other necessary components and compositions, such as a shell, a main circuit board, a power line, etc. Those skilled in the art can make corresponding supplements according to the specific use requirements of the display device, which will not be described herein and should not be regarded as a limitation of the present disclosure.

[0101] In specific implementation, the display device provided by the embodiments of the present disclosure can be a full-screen display device or a flexible display device, etc., which is not limited herein.

[0102] In specific implementations, the display device provided in this disclosure embodiment can be a full-screen mobile phone as shown in FIG19. Of course, the display device provided in this disclosure embodiment can also be any product or component with display function, such as an in-vehicle display, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure embodiment. In other words, the display device provided in this disclosure embodiment can include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0103] This disclosure provides a display panel and display device. By designing the auxiliary spacers as a dual-sided structure of an array substrate and a counter substrate, with both auxiliary spacers extending along the data line extension direction, the first and second auxiliary spacers overlap in a straight line along the data line extension direction after being aligned. Because the critical dimension (CD) of the black matrix along the data line extension direction is wider, PS Mura can be prevented. Therefore, this disclosure does not require much additional black matrix to shield the auxiliary spacers, reducing the area of ​​the black matrix around the auxiliary spacers. This increases the effective display area while preventing PS Mura, improving product transmittance and enhancing product competitiveness. Furthermore, the increased contact area between the auxiliary spacers enhances friction, making them less prone to slippage and further preventing PS Mura. Compared to the XPS design in related technologies, the auxiliary spacers of this disclosure are smaller for the same contact area. Therefore, this disclosure can achieve the desired support effect, increase pixel aperture ratio, and achieve high transmittance specifications by using smaller auxiliary spacer sizes and narrower black matrix shielding distances.

[0104] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0105] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, An array substrate and a counter substrate are provided in a cell, and a liquid crystal layer is located between the array substrate and the counter substrate; The array substrate comprises a first substrate, a plurality of gate lines and a plurality of data lines which are provided in an insulating crossing manner on a side of the first substrate close to the liquid crystal layer, and a plurality of first auxiliary spacers provided on a side of the gate lines and the data lines close to the liquid crystal layer; the first auxiliary spacers are in the same extension direction as the data lines, and the orthographic projection of the first auxiliary spacers on the first substrate and the orthographic projection of the crossing area of the gate lines and the data lines on the first substrate overlap each other. The counter substrate comprises a second substrate, and a plurality of second auxiliary spacers provided on a side of the second substrate close to the liquid crystal layer; the second auxiliary spacers are in the same extension direction as the data lines, each of the second auxiliary spacers corresponds to each of the first auxiliary spacers, and the orthographic projection of the second auxiliary spacers on the first substrate and the orthographic projection of the first auxiliary spacers on the first substrate at least partially overlap.

2. The display panel of claim 1, wherein, The gate lines and the data lines cross to define a plurality of rows and a plurality of columns of pixel units, each of the pixel units comprises a plurality of sub-pixels of different color resist colors, the color resist colors of the sub-pixels located in the same row are the same, the color resist colors of the sub-pixels located in the same column are not completely the same, each of the sub-pixels located in the same column is electrically connected to the same data line, the sub-pixels located in different columns are electrically connected to different data lines, and each row of the pixel units arranged in the pixel row direction is electrically connected to three rows of the gate lines.

3. The display panel of claim 2, wherein, The orthographic projection of the first auxiliary spacers and the second auxiliary spacers on the first substrate are both strip-shaped, and the length of the first auxiliary spacers in the extension direction of the data lines is greater than the length of the second auxiliary spacers in the extension direction of the data lines.

4. The display panel of claim 3, wherein, The length of the first auxiliary spacers in the extension direction of the gate lines is less than the length of the second auxiliary spacers in the extension direction of the gate lines.

5. The display panel of claim 3, wherein, The length of the first auxiliary spacers in the extension direction of the gate lines is greater than the length of the second auxiliary spacers in the extension direction of the gate lines.

6. The display panel of claim 2, wherein, The orthographic projection of the first auxiliary spacers and the second auxiliary spacers on the first substrate are both strip-shaped, and the length of the first auxiliary spacers in the extension direction of the data lines is less than the length of the second auxiliary spacers in the extension direction of the data lines.

7. The display panel of claim 6, wherein, The length of the first auxiliary spacers in the extension direction of the gate lines is greater than the length of the second auxiliary spacers in the extension direction of the gate lines.

8. The display panel of claim 6, wherein, The length of the first auxiliary spacers in the extension direction of the gate lines is less than the length of the second auxiliary spacers in the extension direction of the gate lines.

9. The display panel according to any one of claims 1-8, wherein, The center line of the first auxiliary spacers in the extension direction of the data lines coincides with the center line of the second auxiliary spacers in the extension direction of the data lines.

10. The display panel according to any one of claims 1-8, wherein, The opposite substrate further comprises a black matrix and a filter layer between the second substrate and the second auxiliary spacer, a first planar layer between the black matrix and the filter layer and the second auxiliary spacer, and a first alignment layer on the side of the second auxiliary spacer close to the liquid crystal layer; the black matrix comprises a plurality of openings, and the filter layer comprises a plurality of filter pieces, and the orthographic projection of each filter piece on the second substrate covers the orthographic projection of a corresponding opening on the second substrate.

11. The display panel of claim 10, wherein, The array substrate further comprises a second planar layer between the gate lines and the data lines and the first auxiliary spacer, a first transparent electrode layer between the second planar layer and the first auxiliary spacer, a passivation layer between the first transparent electrode layer and the first auxiliary spacer, a second transparent electrode layer between the passivation layer and the first auxiliary spacer, and a second alignment layer on the side of the first auxiliary spacer close to the liquid crystal layer.

12. The display panel of claim 10, wherein, The array substrate further comprises a second planar layer between the gate lines and the data lines and the first auxiliary spacer, a first transparent electrode layer on the side of the second planar layer close to the liquid crystal layer, a passivation layer on the side of the first transparent electrode layer close to the liquid crystal layer, a second transparent electrode layer on the side of the passivation layer close to the liquid crystal layer, and a second alignment layer on the side of the second transparent electrode layer close to the liquid crystal layer; wherein, The first auxiliary spacer and the second planar layer are an integral structure.

13. The display panel of claim 11 or 12, wherein, The array substrate further comprises a plurality of first main spacers arranged in the same layer as the first auxiliary spacer, and the opposite substrate further comprises a plurality of second main spacers arranged in the same layer as the second auxiliary spacer, and the sum of the thicknesses of the first main spacers and the second main spacers is greater than the sum of the thicknesses of the first auxiliary spacer and the second auxiliary spacer. Each second main spacer corresponds to each first main spacer, the orthographic projection of the second main spacer on the first substrate intersects the orthographic projection of the first main spacer on the first substrate, and the orthographic projections of the first main spacers and the second main spacers on the first substrate respectively overlap the orthographic projection of the intersection area of the gate lines and the data lines on the first substrate.

14. The display panel of claim 13, wherein, The intersection areas on both sides of the gate lines adjacent to the pair of first main spacers and second main spacers are not provided with the first auxiliary spacer and the second auxiliary spacer, and are not provided with the first main spacer and the second main spacer.

15. The display panel of claim 13, wherein, The orthographic projection of the black matrix on the first substrate covers the orthographic projections of the gate lines, the data lines, the first auxiliary spacer, the second auxiliary spacer, the first main spacer, and the second main spacer on the first substrate.

16. The display panel of claim 15, wherein, The black matrix corresponding to the region where the first main separation pad and the second main separation pad arranged in pairs is located has a width along the extension direction of the gate line greater than the width of the black matrix corresponding to the region where the first auxiliary separation pad and the second auxiliary separation pad arranged in pairs is located, and the width of the black matrix corresponding to the region where the first auxiliary separation pad and the second auxiliary separation pad arranged in pairs is located is greater than the width of the black matrix corresponding to the region where no separation pad is located along the extension direction of the gate line.

17. The display panel of any of claims 13-16, wherein, One of the first transparent electrode layer and the second transparent electrode layer is a planar electrode, and the other includes a plurality of slit electrodes.

18. A display device, wherein, A display panel comprising any one of the display panels according to claims 1-17.

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