Pixel circuit, pixel module, pixel driving method and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel module, a pixel driving method and a display apparatus. The pixel circuit comprises a driving circuit, a first light-emission control circuit and a first energy storage circuit, wherein a first end of the first energy storage circuit is electrically connected to a first node, and a second end of the first energy storage circuit is electrically connected to a third node; and the first light-emission control circuit is separately electrically connected to a first light-emission control end, a second end of the driving circuit and the third node, and is used for controlling the connection or disconnection between the second end of the driving circuit and the third node under the control of a first light-emission control signal provided by the first light-emission control end. By means of the present disclosure, when a data voltage is written into a first node, the effect of the parasitic capacitance of a driving transistor included in a driving circuit on the potential of a third node is shielded, such that the potential of the third node is only affected by changes in the potential of the first node, thereby improving the compensation accuracy.

Description

Pixel circuit, pixel module, pixel driving method and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411027685.9, filed on July 29, 2024 in China, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a pixel module, a pixel driving method and a display device. BACKGROUND

[0004] The current mature technology in the display field is LCD (Liquid Crystal Display) display and active matrix OLED (Organic Light Emitting Diode) display. In a complete display system, the general technology of OLED products is to excite various wavelengths of light spectrum by direct recombination of electrons and holes, thereby forming a pattern. The display device formed by OLED technology has a fast response speed and can maximize the contrast ratio, so OLED display devices are expected to become the mainstream products of the next generation of displays.

[0005] Generally, considering the process and cost, the optimal internal compensation circuit for OLED display should use all-oxide TFTs (Thin Film Transistors), but OLED display products themselves need light emitting devices to emit light, and the required light emitting current needs to be provided by a driving transistor. Therefore, in order to ensure the uniformity of product light emission, the consistency of device characteristics must be increased, and the threshold voltage of the driving transistor must be compensated.

[0006] The related pixel circuit is electrically connected to the second end of the driving circuit, and the potential of the third node is affected by the parasitic capacitance of the driving transistor in the driving circuit when the data voltage is written, thereby affecting the compensation accuracy. SUMMARY

[0007] The main purpose of the present disclosure is to provide a pixel circuit, a pixel module, a pixel driving method and a display device, which solve the problem that the potential of the third node is affected by the parasitic capacitance of the driving transistor in the driving circuit when the data voltage is written in the related pixel circuit, thereby affecting the compensation accuracy.

[0008] In one aspect, the present disclosure provides a pixel circuit, comprising a driving circuit, a first light emitting control circuit and a first energy storage circuit;

[0009] The control end of the driving circuit is electrically connected to the first node, and the first end of the driving circuit is electrically connected to the second node. The driving circuit is used to generate a driving current under the control of the potential of the first node.

[0010] The first end of the first energy storage circuit is electrically connected with the first node, and the second end of the first energy storage circuit is electrically connected with the third node, and the first energy storage circuit is used for storing electric energy.

[0011] The first light-emitting control circuit is electrically connected with the first light-emitting control end, the second end of the driving circuit and the third node respectively, and is used for controlling the second end of the driving circuit and the third node to be in communication or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control end.

[0012] Optionally, the pixel circuit provided in at least one embodiment of the present disclosure further comprises a light-emitting element and a second light-emitting control circuit.

[0013] The second light-emitting control circuit is electrically connected with the second light-emitting control end, the third node and the first electrode of the light-emitting element respectively, and is used for controlling the third node and the first electrode of the light-emitting element to be in communication or disconnected under the control of a second light-emitting control signal provided by the second light-emitting control end.

[0014] The second electrode of the light-emitting element is electrically connected with the first voltage end.

[0015] Optionally, the first light-emitting control end and the second light-emitting control end are electrically connected with light-emitting control signal output ends of light-emitting control signal generation circuits of different levels in the same light-emitting control signal generation module respectively.

[0016] Optionally, the pixel circuit provided in at least one embodiment of the present disclosure further comprises a data writing circuit and a second energy storage circuit.

[0017] The data writing circuit is electrically connected with a scanning end, a data line and the first node respectively, and is used for writing a data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning end.

[0018] The second energy storage circuit is electrically connected with the third node, and is used for maintaining the potential of the third node.

[0019] Optionally, the pixel circuit provided in at least one embodiment of the present disclosure further comprises a first initialization circuit.

[0020] The first initialization circuit is electrically connected with a first reset control end, a reference voltage end and the first node respectively, and is used for writing a reference voltage provided by the reference voltage end into the first node under the control of a first reset control signal provided by the first reset control end.

[0021] Optionally, the pixel circuit provided in at least one embodiment of the present disclosure further comprises a third light-emitting control circuit.

[0022] The third light-emitting control circuit is electrically connected with a third light-emitting control terminal, a power voltage terminal and the second node respectively, and is configured to control the power voltage terminal to be connected or disconnected with the second node under the control of a third light-emitting control signal provided by the third light-emitting control terminal.

[0023] Optionally, the pixel circuit further comprises a second initialization circuit.

[0024] The second initialization circuit is electrically connected with a second reset control terminal and an initial voltage terminal respectively, and is further electrically connected with the second node or the third node, and is configured to write an initial voltage provided by the initial voltage terminal into the second node or the third node under the control of a second reset control signal provided by the second reset control terminal.

[0025] Optionally, the driving circuit comprises a driving transistor, the first energy storage circuit comprises a first capacitor, and the first light-emitting control circuit comprises a first transistor.

[0026] The gate of the driving transistor is electrically connected with the first node, and the first electrode of the driving transistor is electrically connected with the second node.

[0027] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the third node.

[0028] The gate of the first transistor is electrically connected with the first light-emitting control terminal, the first electrode of the first transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the first transistor is electrically connected with the third node.

[0029] Optionally, the second light-emitting control circuit comprises a second transistor.

[0030] The gate of the second transistor is electrically connected with the second light-emitting control terminal, the first electrode of the second transistor is electrically connected with the third node, and the second electrode of the second transistor is electrically connected with the first electrode of the light-emitting element.

[0031] Optionally, the data writing circuit comprises a third transistor, and the second energy storage circuit comprises a second capacitor.

[0032] The gate of the third transistor is electrically connected with the scanning terminal, the first electrode of the third transistor is electrically connected with the data line, and the second electrode of the third transistor is electrically connected with the first node.

[0033] The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with a direct current voltage terminal.

[0034] Optionally, the first initialization circuit includes a fourth transistor.

[0035] A gate of the fourth transistor is electrically connected with the first reset control end, a first pole of the fourth transistor is electrically connected with the reference voltage end, and a second pole of the fourth transistor is electrically connected with the first node.

[0036] Optionally, the third light-emitting control circuit includes a fifth transistor.

[0037] A gate of the fifth transistor is electrically connected with the third light-emitting control end, a first pole of the fifth transistor is electrically connected with the power voltage end, and a second pole of the fifth transistor is electrically connected with the second node.

[0038] Optionally, the second initialization circuit includes a sixth transistor.

[0039] A gate of the sixth transistor is electrically connected with the second reset control end, a first pole of the sixth transistor is electrically connected with the initial voltage end, and a second pole of the sixth transistor is electrically connected with the second node or the third node.

[0040] In a second aspect, the embodiments of the present disclosure provide a pixel module, including a third light-emitting control circuit and N pixel circuits described above; N is an integer greater than 1.

[0041] The third light-emitting control circuit is electrically connected with a third light-emitting control end, a power voltage end and a second node respectively, and is used for controlling the power voltage end to be connected or disconnected with the second node under the control of a third light-emitting control signal provided by the third light-emitting control end.

[0042] Optionally, the pixel module provided by at least one embodiment of the present disclosure further includes a second initialization circuit.

[0043] The second initialization circuit is electrically connected with a second reset control end, an initial voltage end and the second node respectively, and is used for writing an initial voltage provided by the initial voltage end into the second node under the control of a second reset control signal provided by the second reset control end.

[0044] In a third aspect, the embodiments of the present disclosure provide a pixel driving method applied to the pixel circuit described above, and a display period includes a write-in stage; the pixel driving method includes:

[0045] In the write-in stage, the first light-emitting control circuit controls the second end of the driving circuit to be disconnected with the third node under the control of a first light-emitting control signal.

[0046] Optionally, the pixel circuit further comprises a light emitting element and a second light emitting control circuit; and the pixel driving method further comprises:

[0047] In the writing stage, the second light emitting control circuit controls the third node to be disconnected from the first electrode of the light emitting element under the control of a second light emitting control signal.

[0048] Optionally, the pixel circuit further comprises a data writing circuit; and the pixel driving method comprises:

[0049] In the writing stage, the data writing circuit writes the data voltage into the first node under the control of a scanning signal.

[0050] Optionally, the pixel circuit further comprises a first initialization circuit; the display cycle further comprises a compensation stage arranged before the writing stage; and the pixel driving method comprises:

[0051] In the compensation stage, the first initialization circuit writes a reference voltage into the first node under the control of a first reset control signal, and the first light emitting control circuit controls the second end of the driving circuit to be connected to the third node under the control of a first light emitting control signal.

[0052] In a fourth aspect, the embodiments of the present disclosure provide a display device comprising the pixel circuit.

[0053] In a fifth aspect, the embodiments of the present disclosure provide a display device comprising the pixel module.

[0054] In at least one embodiment of the present disclosure, the first light emitting control circuit is arranged between the second end of the driving circuit and the third node, and the first energy storage circuit is arranged between the first node and the third node, so that when the data voltage is written into the first node, the influence of the parasitic capacitance of the driving transistor included in the driving circuit on the potential of the third node is shielded, and the potential of the third node is only affected by the change in the potential of the first node, thereby improving the compensation accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0055] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0056] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0057] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0058] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] FIG. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] FIG. 10 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9;

[0065] FIG. 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] FIG. 12 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 11;

[0067] FIG. 13 is a structural diagram of a pixel module according to at least one embodiment of the present disclosure;

[0068] FIG. 14 is a structural diagram of a pixel module according to at least one embodiment of the present disclosure;

[0069] FIG. 15 is a circuit diagram of a pixel module according to at least one embodiment of the present disclosure;

[0070] FIG. 16 is a timing diagram of at least one embodiment of the pixel module shown in FIG. 15. DETAILED DESCRIPTION

[0071] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0072] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0073] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0074] As shown in FIG. 1, the pixel circuit according to at least one embodiment of the present disclosure comprises a driving circuit 10, a first light-emitting control circuit 11 and a first energy storage circuit 12.

[0075] The control end of the driving circuit 10 is electrically connected with the first node N1, and the first end of the driving circuit 10 is electrically connected with the second node N2. The driving circuit 10 is configured to generate a driving current under the control of the potential of the first node N1.

[0076] The first end of the first energy storage circuit 12 is electrically connected with the first node N1, and the second end of the first energy storage circuit 12 is electrically connected with the third node N3. The first energy storage circuit 12 is configured to store energy.

[0077] The first light-emitting control circuit 11 is electrically connected with the first light-emitting control end EM1, the second end of the driving circuit 10 and the third node N3, respectively. The first light-emitting control circuit 11 is configured to control the communication or disconnection between the second end of the driving circuit 10 and the third node N3 under the control of the first light-emitting control signal provided by the first light-emitting control end EM1.

[0078] In at least one embodiment of the pixel circuit shown in FIG. 1, the first light-emitting control circuit 11 is arranged between the second end of the driving circuit 10 and the third node N3, and the first energy storage circuit 12 is arranged between the first node N1 and the third node N3. In this way, when the data voltage is written into the first node N1, the influence of the parasitic capacitance of the driving transistor included in the driving circuit 10 on the potential of the third node N3 is shielded, so that the potential of the third node N3 is only affected by the change of the potential of the first node N1, thereby improving the compensation accuracy.

[0079] In at least one embodiment of the pixel circuit shown in FIG. 1, the second node N2 can be electrically connected with the power voltage end VDD.

[0080] The pixel circuit according to at least one embodiment of the present disclosure further comprises a light-emitting element and a second light-emitting control circuit.

[0081] The second light-emitting control circuit is electrically connected with the second light-emitting control end, the third node and the first pole of the light-emitting element, respectively. The second light-emitting control circuit is configured to control the communication or disconnection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control end.

[0082] The second pole of the light-emitting element is electrically connected with the first voltage end.

[0083] In a specific implementation, the pixel circuit can further comprise a light-emitting element and a second light-emitting control circuit. The second light-emitting control circuit controls the communication or disconnection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0084] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the pixel circuit in at least one embodiment of the present disclosure further comprises a light emitting element E1 and a second light emitting control circuit 20.

[0085] The second light emitting control circuit 20 is electrically connected with the second light emitting control end EM2, the third node N3 and the first pole of the light emitting element E1 respectively, and is used for controlling the communication or disconnection between the third node N3 and the first pole of the light emitting element E1 under the control of the second light emitting control signal provided by the second light emitting control end EM2.

[0086] The second pole of the light emitting element E1 is electrically connected with the first voltage end V1.

[0087] In at least one embodiment of the present disclosure, the second light emitting control circuit 20 is arranged between the third node N3 and the first pole of the light emitting element E1, so that when the data voltage is written into the first node N1, the influence of the light emitting element E1 on the potential of the third node N3 is shielded, so as to improve the compensation accuracy.

[0088] Optionally, the first voltage end can be a low voltage end.

[0089] In at least one embodiment of the present disclosure, the first light emitting control end and the second light emitting control end are respectively electrically connected with the light emitting control signal output ends of the light emitting control signal generation circuits of different stages in the same light emitting control signal generation module, so as to reduce the number of light emitting control signal generation modules used, and facilitate the realization of narrow frame.

[0090] The pixel circuit in at least one embodiment of the present disclosure further comprises a data writing circuit and a second energy storage circuit.

[0091] The data writing circuit is electrically connected with the scanning end, the data line and the first node respectively, and is used for writing the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end.

[0092] The second energy storage circuit is electrically connected with the third node, and is used for maintaining the potential of the third node.

[0093] In specific implementation, the pixel circuit can further comprise a data writing circuit and a second energy storage circuit. The data writing circuit writes the data voltage into the first node under the control of the scanning signal, so as to perform data voltage writing. The second energy storage circuit maintains the potential of the third node.

[0094] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure further comprises a data writing circuit 31 and a second energy storage circuit 32.

[0095] The data writing circuit 31 is electrically connected with the scan end G1, the data line DL and the first node N1 respectively, and is configured to write a data voltage Vdata provided by the data line DL into the first node N1 under the control of a scan signal provided by the scan end G1.

[0096] The second energy storage circuit 32 is electrically connected with the third node N3, and is configured to maintain the potential of the third node N3.

[0097] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a first initialization circuit.

[0098] The first initialization circuit is electrically connected with the first reset control end, the reference voltage end and the first node respectively, and is configured to write a reference voltage provided by the reference voltage end into the first node under the control of a first reset control signal provided by the first reset control end.

[0099] In specific implementation, the pixel circuit can further comprise a first initialization circuit, which writes a reference voltage into the first node under the control of a first reset control signal, so as to initialize the potential of the first node.

[0100] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit provided in at least one embodiment of the present disclosure further comprises a first initialization circuit 41.

[0101] The first initialization circuit 41 is electrically connected with the first reset control end G2, the reference voltage end REF and the first node N1 respectively, and is configured to write a reference voltage Vref provided by the reference voltage end REF into the first node N1 under the control of a first reset control signal provided by the first reset control end G2.

[0102] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a second initialization circuit.

[0103] The second initialization circuit is electrically connected with the second reset control end and the initial voltage end respectively, and is further electrically connected with the second node or the third node, and is configured to write an initial voltage provided by the initial voltage end into the second node or the third node under the control of a second reset control signal provided by the second reset control end.

[0104] In specific implementation, the pixel circuit can further comprise a second initialization circuit, which writes an initial voltage into the second node or the third node under the control of a second reset control signal, so as to initialize the potential of the second node or the potential of the third node.

[0105] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure further comprises a second initialization circuit 42.

[0106] The second initialization circuit 42 is electrically connected with the second reset control end G3 and the initial voltage end I1 respectively, and is further electrically connected with the second node N2. The second initialization circuit 42 is used for writing the initial voltage Vinit provided by the initial voltage end I1 into the second node N2 under the control of the second reset control signal provided by the second reset control end G3.

[0107] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure further comprises a second initialization circuit 42.

[0108] The second initialization circuit 42 is electrically connected with the second reset control end G3 and the initial voltage end I1 respectively, and is further electrically connected with the third node N3. The second initialization circuit 42 is used for writing the initial voltage Vinit provided by the initial voltage end I1 into the third node N3 under the control of the second reset control signal provided by the second reset control end G3.

[0109] The pixel circuit according to at least one embodiment of the present disclosure further comprises a third light-emitting control circuit.

[0110] The third light-emitting control circuit is electrically connected with the third light-emitting control end, the power voltage end and the second node respectively, and is used for controlling the power voltage end and the second node to be connected or disconnected under the control of the third light-emitting control signal provided by the third light-emitting control end.

[0111] In specific implementation, the pixel circuit can further comprise a third light-emitting control circuit. The third light-emitting control circuit controls the power voltage end and the second node to be connected or disconnected under the control of the third light-emitting control signal, so as to perform light-emitting control.

[0112] As shown in FIG. 7, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5, the pixel circuit according to at least one embodiment of the present disclosure further comprises a third light-emitting control circuit 71.

[0113] The third light-emitting control circuit is electrically connected with the third light-emitting control end EM3, the power voltage end VDD and the second node N2 respectively, and is used for controlling the power voltage end VDD and the second node N2 to be connected or disconnected under the control of the third light-emitting control signal provided by the third light-emitting control end EM3.

[0114] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the pixel circuit according to at least one embodiment of the present disclosure further comprises a third light-emitting control circuit 71.

[0115] The third light-emitting control circuit is electrically connected with a third light-emitting control terminal EM3, a power voltage terminal VDD and the second node N2 respectively, and is configured to control the power voltage terminal VDD to be in communication or disconnected with the second node N2 under the control of a third light-emitting control signal provided by the third light-emitting control terminal EM3.

[0116] Optionally, the driving circuit comprises a driving transistor, the first energy storage circuit comprises a first capacitor, and the first light-emitting control circuit comprises a first transistor.

[0117] The gate of the driving transistor is electrically connected with the first node, and the first electrode of the driving transistor is electrically connected with the second node.

[0118] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with a third node.

[0119] The gate of the first transistor is electrically connected with the first light-emitting control terminal, the first electrode of the first transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the first transistor is electrically connected with the third node.

[0120] Optionally, the second light-emitting control circuit comprises a second transistor.

[0121] The gate of the second transistor is electrically connected with the second light-emitting control terminal, the first electrode of the second transistor is electrically connected with the third node, and the second electrode of the second transistor is electrically connected with the first electrode of the light-emitting element.

[0122] Optionally, the data writing circuit comprises a third transistor, and the second energy storage circuit comprises a second capacitor.

[0123] The gate of the third transistor is electrically connected with the scanning terminal, the first electrode of the third transistor is electrically connected with the data line, and the second electrode of the third transistor is electrically connected with the first node.

[0124] The first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with a direct current voltage terminal.

[0125] Optionally, the direct current voltage terminal can be a power voltage terminal or a reference voltage terminal.

[0126] Optionally, the first initialization circuit comprises a fourth transistor.

[0127] A gate of the fourth transistor is electrically connected with the first reset control end, a first electrode of the fourth transistor is electrically connected with the reference voltage end, and a second electrode of the fourth transistor is electrically connected with the first node.

[0128] Optionally, the third light-emitting control circuit comprises a fifth transistor.

[0129] A gate of the fifth transistor is electrically connected with the third light-emitting control end, a first electrode of the fifth transistor is electrically connected with the power voltage end, and a second electrode of the fifth transistor is electrically connected with the second node.

[0130] Optionally, the second initialization circuit comprises a sixth transistor.

[0131] A gate of the sixth transistor is electrically connected with the second reset control end, a first electrode of the sixth transistor is electrically connected with the initial voltage end, and a second electrode of the sixth transistor is electrically connected with the second node or the third node.

[0132] As shown in FIG. 9, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the driving circuit comprises a driving transistor DT, the first energy storage circuit comprises a first capacitor C1, and the first light-emitting control circuit comprises a first transistor T1; and the light-emitting element is an organic light-emitting diode O1.

[0133] A gate of the driving transistor DT is electrically connected with the first node N1, and a drain of the driving transistor DT is electrically connected with the power voltage end VDD.

[0134] A first end of the first capacitor C1 is electrically connected with the first node N1, and a second end of the first capacitor C1 is electrically connected with the third node N3.

[0135] A gate of the first transistor T1 is electrically connected with an (n-1)th light-emitting control end EM(n-1), a drain of the first transistor T1 is electrically connected with a source of the driving transistor DT, and a source of the first transistor T1 is electrically connected with the third node N3.

[0136] The second light-emitting control circuit comprises a second transistor T2.

[0137] A gate of the second transistor T2 is electrically connected with an nth light-emitting control end EM(n), a drain of the second transistor T2 is electrically connected with the third node N3, and a source of the second transistor T2 is electrically connected with an anode of O1; a cathode of O1 is electrically connected with the low voltage end VSS.

[0138] The data writing circuit comprises a third transistor T3, and the second energy storage circuit comprises a second capacitor C2.

[0139] The gate of the third transistor T3 is electrically connected with the scanning terminal G1, the drain of the third transistor T3 is electrically connected with the data line DL, and the source of the third transistor T3 is electrically connected with the first node N1.

[0140] The first end of the second capacitor C2 is electrically connected with the third node N3, and the second end of the second capacitor C2 is electrically connected with the power voltage terminal VDD.

[0141] The first initialization circuit comprises a fourth transistor T4.

[0142] The gate of the fourth transistor T4 is electrically connected with the first reset control terminal G2, the drain of the fourth transistor T4 is electrically connected with the reference voltage terminal REF, and the source of the fourth transistor T4 is electrically connected with the first node N1.

[0143] The second initialization circuit comprises a sixth transistor T6.

[0144] The gate of the sixth transistor T6 is electrically connected with the second reset control terminal G3, the drain of the sixth transistor T6 is electrically connected with the initial voltage terminal I1, and the source of the sixth transistor T6 is electrically connected with the third node N3.

[0145] The initial voltage terminal I1 is configured to provide an initial voltage Vinit.

[0146] In at least one embodiment of the pixel circuit shown in FIG. 9, all the transistors are n-type transistors. In a specific implementation, the transistors can also be replaced by p-type transistors.

[0147] In FIG. 9, C0 is a capacitor arranged between the anode of O1 and the cathode of O1.

[0148] In at least one embodiment of the pixel circuit shown in FIG. 9, the first light-emitting control terminal can be an (n-1)th light-emitting control terminal EM(n-1), the second light-emitting control terminal can be an nth light-emitting control terminal EM(n), and the first light-emitting control signal and the second light-emitting control signal can be provided by the same light-emitting control signal generation module.

[0149] In at least one embodiment shown in FIG. 9, the voltage value of the reference voltage Vref can be greater than or equal to 3V and less than or equal to 4V.

[0150] The voltage value of Vinit can be 0V, or the voltage value of Vinit can be less than 0V.

[0151] In at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, T1 is controlled by EM(n-1) to reduce the number of GOA (Gate On Array) modules used.

[0152] In at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, the pixel circuit can reset the potential of N3 through T6 and reset the anode of O1 through T2 in the initialization stage, thereby having better reset capability.

[0153] At least one embodiment of the present disclosure provides an internal compensation pixel circuit, which can be particularly suitable for medium and large-sized oxide backplane OLED (Organic Light Emitting Diode) display panels.

[0154] As shown in FIG. 10, in at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, the display cycle can include an initialization stage S1, a compensation stage S2, a write stage S3 and an emission stage S4 arranged in sequence when the pixel circuit is in operation.

[0155] In the initialization stage S1, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a high voltage signal, EM(n-1) provides a low voltage signal, EM(n) provides a high voltage signal, T4 is turned on, REF provides a reference voltage Vref to N1, and the potential of N1 is Vref; T6 is turned on, I1 provides an initial voltage Vinit to N3, so that DT can be turned on at the beginning of the compensation stage S2; T2 is turned on, and I1 provides the initial voltage Vinit to the anode of O1 to clear the residual charge at the anode of O1.

[0156] In the compensation stage S2, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a low voltage signal, EM(n-1) provides a high voltage signal, EM(n) provides a low voltage signal, T1 is turned on, and T4 is turned on.

[0157] At the beginning of the compensation stage S2, DT is turned on, C1 is charged through Vref, the potential of N3 is changed, until the potential of N3 becomes Vref-Vth, DT is turned off, and threshold voltage compensation is performed; Vth is the threshold voltage of DT.

[0158] In the writing stage S3, G1 provides a high voltage signal, G2 and G3 both provide a low voltage signal, EM(n-1) and EM(n) both provide a low voltage signal, T3 is turned on, DL provides a data voltage Vdata to N1, the potential of N1 changes from Vref to Vdata, the potential of N3 is affected by the coupling of C1, and the potential of N3 changes, thus this stage determines the accuracy of compensation; since T1 shields the influence of the parasitic capacitance of DT on the potential of N3, and T2 shields the influence of O1 on the potential of N3, the potential of N3 is only affected by the coupling of C1, and finally the potential of N3 becomes Vref-Vth+(Vdata-Vref)xC1z / (C1z+C2z), the gate-source voltage Vgs of DT is equal to (Vdata-Vref)x(1-a)+Vth, wherein a is equal to C1z / (C1z+C2z), and the influence of DT and O1 can be isolated; wherein C1z is the capacitance value of C1, and C2z is the capacitance value of C2;

[0159] In the light-emitting stage S4, EM(n-1) and EM(n) both provide a high voltage signal, G1, G2 and G3 all provide a low voltage signal, T1 and T2 are turned on, and DT drives O1 to emit light.

[0160] As shown in FIG. 11, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the driving circuit includes a driving transistor DT, the first energy storage circuit includes a first capacitor C1, and the first light-emitting control circuit includes a first transistor T1; and the light-emitting element is an organic light-emitting diode O1.

[0161] The gate of the driving transistor DT is electrically connected with the first node N1, and the drain of the driving transistor DT is electrically connected with a power voltage terminal VDD.

[0162] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with a third node N3.

[0163] The gate of the first transistor T1 is electrically connected with a first light-emitting control terminal EM1, the drain of the first transistor T1 is electrically connected with the source of the driving transistor DT, and the source of the first transistor T1 is electrically connected with the third node N3.

[0164] The second light-emitting control circuit includes a second transistor T2.

[0165] The gate of the second transistor T2 is electrically connected with a second light-emitting control terminal EM2, the drain of the second transistor T2 is electrically connected with the third node N3, and the source of the second transistor T2 is electrically connected with the anode of O1; the cathode of O1 is electrically connected with a low voltage terminal VSS.

[0166] The data writing circuit comprises a third transistor T3, and the second energy storage circuit comprises a second capacitor C2.

[0167] The gate of the third transistor T3 is electrically connected with the scanning terminal G1, the drain of the third transistor T3 is electrically connected with the data line DL, and the source of the third transistor T3 is electrically connected with the first node N1.

[0168] The first end of the second capacitor C2 is electrically connected with the third node N3, and the second end of the second capacitor C2 is electrically connected with the power voltage terminal VDD.

[0169] The first initialization circuit comprises a fourth transistor T4.

[0170] The gate of the fourth transistor T4 is electrically connected with the first reset control terminal G2, the drain of the fourth transistor T4 is electrically connected with the reference voltage terminal REF, and the source of the fourth transistor T4 is electrically connected with the first node N1.

[0171] The second initialization circuit comprises a sixth transistor T6.

[0172] The gate of the sixth transistor T6 is electrically connected with the second reset control terminal G3, the drain of the sixth transistor T6 is electrically connected with the initial voltage terminal I1, and the source of the sixth transistor T6 is electrically connected with the third node N3.

[0173] The initial voltage terminal I1 is configured to provide an initial voltage Vinit.

[0174] In at least one embodiment of the pixel circuit shown in FIG. 11, all the transistors are n-type transistors. In a specific implementation, the transistors can also be replaced by p-type transistors.

[0175] In FIG. 11, C0 is a capacitor arranged between the anode of O1 and the cathode of O1.

[0176] In at least one embodiment shown in FIG. 11, the voltage value of the reference voltage Vref can be greater than or equal to 3V and less than or equal to 4V.

[0177] The voltage value of Vinit can be 0V, or the voltage value of Vinit can be less than 0V.

[0178] As shown in FIG. 12, in at least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure, during operation, the display period can comprise an initialization stage S1, a compensation stage S2, a writing stage S3 and a light emitting stage S4 arranged in sequence.

[0179] In the initialization stage S1, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a high voltage signal, EM1 provides a low voltage signal, EM2 provides a high voltage signal, T4 is open, REF provides a reference voltage Vref to N1, and the potential of N1 is Vref; T6 is open, and I1 provides an initial voltage Vinit to N3, so that DT can be turned on at the beginning of the compensation stage S2; T2 is turned on, and I1 provides the initial voltage Vinit to the anode of O1 to clear the residual charge at the anode of O1.

[0180] In the compensation stage S2, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a low voltage signal, EM1 provides a high voltage signal, EM2 provides a low voltage signal, T1 is open, and T4 is open.

[0181] At the beginning of the compensation stage S2, DT is turned on, C1 is charged by Vref, the potential of N3 is changed until the potential of N3 becomes Vref-Vth, and DT is turned off to perform threshold voltage compensation; Vth is the threshold voltage of DT.

[0182] In the write stage S3, G1 provides a high voltage signal, G2 and G3 both provide low voltage signals, EM1 and EM2 both provide low voltage signals, T3 is turned on, DL provides a data voltage Vdata to N1, the potential of N1 changes from Vref to Vdata, the potential of N3 is affected by the coupling of C1, and thus the potential of N3 changes, and thus this stage determines the accuracy of compensation; since T1 shields the influence of the parasitic capacitance of DT on the potential of N3, and T2 shields the influence of O1 on the potential of N3, the potential of N3 is only affected by the coupling of C1, and finally the potential of N3 becomes Vref-Vth+(Vdata-Vref)×C1z / (C1z+C2z), the gate-source voltage Vgs of DT is equal to (Vdata-Vref)×(1-a)+Vth, where a is equal to C1z / (C1z+C2z), and DT and O1 can be isolated; where C1z is the capacitance value of C1, and C2z is the capacitance value of C2.

[0183] In the light-emitting stage S4, EM1 and EM2 both provide high voltage signals, G1, G2 and G3 all provide low voltage signals, T1 and T2 are turned on, and DT drives O1 to emit light.

[0184] At least one embodiment of the pixel circuit shown in FIG. 11 of the present disclosure can reset the potential of N3 through T6 and reset the anode of O1 through T2 in the initialization stage, and has better reset capability.

[0185] The pixel module described in the embodiments of the present disclosure comprises a third light-emitting control circuit and N pixel circuits described above; N is an integer greater than 1.

[0186] The third light-emitting control circuit is electrically connected with the third light-emitting control end, the power voltage end and the second node respectively, and is configured to control the power voltage end to be in communication or disconnected with the second node under the control of a third light-emitting control signal provided by the third light-emitting control end.

[0187] In at least one embodiment of the present disclosure, N is taken as 3 for example.

[0188] As shown in FIG. 13, the pixel module according to at least one embodiment of the present disclosure includes a third light-emitting control circuit 71, a first pixel circuit, a second pixel circuit and a third pixel circuit.

[0189] The first pixel circuit includes a first light-emitting element E11, a first driving circuit 101, a first first light-emitting control circuit 211, a first first energy storage circuit 311, a first second light-emitting control circuit 412, a first data writing circuit 51, a first second energy storage circuit 612 and a first first initialization circuit 711.

[0190] The control end of the first driving circuit 101 is electrically connected with the first first node N11, and the first end of the first driving circuit 101 is electrically connected with the first second node N12. The first driving circuit 101 is configured to generate a first driving current under the control of the potential of the first first node N11.

[0191] The first end of the first first energy storage circuit 311 is electrically connected with the first first node N11, and the second end of the first first energy storage circuit 311 is electrically connected with the first third node N13. The first first energy storage circuit 311 is configured to store electrical energy.

[0192] The first first light-emitting control circuit 211 is electrically connected with the first light-emitting control end EM1, the second end of the first driving circuit 101 and the first third node N13 respectively. The first first light-emitting control circuit 211 is configured to control the second end of the first driving circuit 101 to be in communication or disconnected with the first third node N13 under the control of a first light-emitting control signal provided by the first light-emitting control end EM1.

[0193] The first second light-emitting control circuit 412 is electrically connected with the second light-emitting control end EM2, the first third node N13 and the first pole of the first light-emitting element E11 respectively. The first second light-emitting control circuit 412 is configured to control the first third node N13 to be in communication or disconnected with the first pole of the first light-emitting element E11 under the control of a second light-emitting control signal provided by the second light-emitting control end EM2.

[0194] The second pole of the first light-emitting element E11 is electrically connected with the first voltage end V1.

[0195] The first data writing circuit 51 is electrically connected to the scanning terminal G1, the first data line DL1 and the first node N11 respectively, and is used to write the first data voltage Vdata1 provided by the first data line DL1 into the first node N11 under the control of the scanning signal provided by the scanning terminal G1.

[0196] The first second energy storage circuit 612 is electrically connected to the first third node N13 to maintain the potential of the first third node N13;

[0197] The first initialization circuit 711 is electrically connected to the first reset control terminal G2, the reference voltage terminal REF and the first first node N11, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first first node N11 under the control of the first reset control signal provided by the first reset control terminal G2.

[0198] The second pixel circuit includes a second light-emitting element E12, a second driving circuit 102, a second first light-emitting control circuit 221, a second first energy storage circuit 321, a second second light-emitting control circuit 422, a second data writing circuit 52, a second second energy storage circuit 622, and a second first initialization circuit 721.

[0199] The control terminal of the second driving circuit 102 is electrically connected to the second first node N21, and the first terminal of the second driving circuit 102 is electrically connected to the second second node N22. The second driving circuit 102 is used to generate a second driving current under the control of the potential of the second first node N21.

[0200] The first end of the second first energy storage circuit 321 is electrically connected to the second first node N21, and the second end of the second first energy storage circuit 321 is electrically connected to the second third node N23. The second first energy storage circuit 321 is used to store electrical energy.

[0201] The second first light-emitting control circuit 221 is electrically connected to the first light-emitting control terminal EM1, the second terminal of the second driving circuit 102, and the second third node N23, respectively, and is used to control the connection or disconnection between the second terminal of the second driving circuit 102 and the second third node N23 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0202] The second second light-emitting control circuit 422 is electrically connected to the second light-emitting control terminal EM2, the second third node N23 and the first pole of the second light-emitting element E12, respectively, and is used to control the connection or disconnection between the second third node N23 and the first pole of the second light-emitting element E12 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0203] The second electrode of the second light-emitting element E12 is electrically connected to the first voltage terminal V1.

[0204] The second data writing circuit 52 is electrically connected to the scanning terminal G1, the second data line DL2 and the second first node N21 respectively, and is used to write the second data voltage Vdata2 provided by the second data line DL2 into the second first node N21 under the control of the scanning signal provided by the scanning terminal G1.

[0205] The second energy storage circuit 622 is electrically connected to the second third node N23 to maintain the potential of the second third node N23;

[0206] The second first initialization circuit 721 is electrically connected to the first reset control terminal G2, the reference voltage terminal REF and the second first node N21 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the second first node N21 under the control of the first reset control signal provided by the first reset control terminal G2.

[0207] The third pixel circuit includes a third light-emitting element E13, a third driving circuit 103, a third first light-emitting control circuit 231, a third first energy storage circuit 331, a third second light-emitting control circuit 432, a third data writing circuit 53, a third second energy storage circuit 632, and a third first initialization circuit 731.

[0208] The control terminal of the third driving circuit 103 is electrically connected to the third first node N31, and the first terminal of the third driving circuit 103 is electrically connected to the third second node N32. The third driving circuit 103 is used to generate a third driving current under the control of the potential of the third first node N31.

[0209] The first end of the third first energy storage circuit 331 is electrically connected to the third first node N31, and the second end of the third first energy storage circuit 331 is electrically connected to the third third node N33. The third first energy storage circuit 331 is used to store electrical energy.

[0210] The third first light-emitting control circuit 231 is electrically connected to the first light-emitting control terminal EM1, the second terminal of the third driving circuit 103, and the third third node N33, respectively, and is used to control the connection or disconnection between the second terminal of the third driving circuit 103 and the third third node N33 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0211] The third second light-emitting control circuit 432 is electrically connected to the second light-emitting control terminal EM2, the third third node N33 and the first pole of the first light-emitting element E11, respectively, and is used to control the connection or disconnection between the third third node N33 and the first pole of the third light-emitting element E13 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0212] The second electrode of the third light-emitting element E13 is electrically connected to the first voltage terminal V1.

[0213] The third data writing circuit 53 is electrically connected to the scanning terminal G1, the third data line DL3 and the third first node N31 respectively, and is used to write the third data voltage Vdata3 provided by the third data line DL3 into the third first node N31 under the control of the scanning signal provided by the scanning terminal G1.

[0214] The third second energy storage circuit 632 is electrically connected to the third third node N33 and is used to maintain the potential of the third third node N33;

[0215] The third first initialization circuit 731 is electrically connected to the first reset control terminal G2, the reference voltage terminal REF and the third first node N31 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the third first node N31 under the control of the first reset control signal provided by the first reset control terminal G2.

[0216] The third light-emitting control circuit 71 is electrically connected to the third light-emitting control terminal EM3, the power supply voltage terminal VDD, the first second node N12, the second second node N22, and the third second node N32, respectively. Under the control of the third light-emitting control signal provided by the third light-emitting control terminal EM3, it controls the connection or disconnection between the power supply voltage terminal VDD and the first second node N12, the connection or disconnection between the power supply voltage terminal VDD and the second second node N22, and the connection or disconnection between the power supply voltage terminal VDD and the third second node N32.

[0217] N12, N22 and N32 are electrically connected to each other.

[0218] The pixel module described in at least one embodiment of this disclosure further includes a second initialization circuit;

[0219] The second initialization circuit is electrically connected to the second reset control terminal, the initial voltage terminal, and the second node, respectively, and is used to write the initial voltage provided by the initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset control terminal, so as to initialize the potential of the second node.

[0220] As shown in FIG14, based on at least one embodiment of the pixel module shown in FIG13, the pixel module of at least one embodiment of the present disclosure further includes a second initialization circuit 42;

[0221] The second initialization circuit 42 is electrically connected to the second reset control terminal G3, the initial voltage terminal I1, and the first second node N12, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first second node N12 under the control of the second reset control signal provided by the second reset control terminal G3.

[0222] As shown in Figure 15, based on at least one embodiment of the pixel circuit shown in Figure 14,

[0223] The first driving circuit includes a first driving transistor DT1, the first energy storage circuit includes a first capacitor C11, the first light-emitting control circuit includes a first transistor T11; the first light-emitting element is a first organic light-emitting diode O11.

[0224] The gate of the first driving transistor DT1 is electrically connected to the first first node N11, and the drain of the first driving transistor DT1 is electrically connected to the first second node N12.

[0225] The first terminal of the first capacitor C11 is electrically connected to the first node N11, and the second terminal of the first capacitor C11 is electrically connected to the first third node N13.

[0226] The gate of the first transistor T11 is electrically connected to the first light-emitting control terminal EM1, the drain of the first transistor T11 is electrically connected to the source of the first driving transistor DT1, and the source of the first transistor T11 is electrically connected to the first third node N13.

[0227] The first second light-emitting control circuit includes a first second transistor T12;

[0228] The gate of the first second transistor T12 is connected to the second light-emitting control terminal EM2, the drain of the first second transistor T12 is electrically connected to the first third node N13, the source of the first second transistor T12 is electrically connected to the anode of O11, and the cathode of O11 is electrically connected to the low voltage terminal VSS.

[0229] The first data writing circuit includes a first third transistor T13, and the first second energy storage circuit includes a first second capacitor C12;

[0230] The gate of the first third transistor T13 is electrically connected to the scan terminal G1, the drain of the first third transistor T13 is electrically connected to the first data line DL1, and the source of the first third transistor T13 is electrically connected to the first first node N11.

[0231] The first terminal of the first second capacitor C12 is electrically connected to the first third node N13, and the second terminal of the first second capacitor C12 is electrically connected to the power supply voltage terminal VDD.

[0232] The first initialization circuit includes a first fourth transistor T14;

[0233] The gate of the first fourth transistor T14 is electrically connected to the first reset control terminal G2, the drain of the first fourth transistor T14 is electrically connected to the reference voltage terminal REF, and the source of the first fourth transistor T14 is electrically connected to the first first node N11.

[0234] The second driving circuit includes a second driving transistor DT2, the second first energy storage circuit includes a second first capacitor C21, the second first light-emitting control circuit includes a second first transistor T21; the second light-emitting element is a second organic light-emitting diode O12.

[0235] The gate of the second driving transistor DT2 is electrically connected to the second first node N21, and the drain of the second driving transistor DT2 is electrically connected to the second second node N22.

[0236] The first terminal of the second first capacitor C21 is electrically connected to the second first node N21, and the second terminal of the second first capacitor C21 is electrically connected to the second third node N23.

[0237] The gate of the second first transistor T21 is electrically connected to the first light-emitting control terminal EM1, the drain of the second first transistor T21 is electrically connected to the source of the second driving transistor DT2, and the source of the second first transistor T21 is electrically connected to the second third node N23.

[0238] The second light-emitting control circuit includes a second transistor T22;

[0239] The gate of the second transistor T22 is connected to the second light-emitting control terminal EM2, the drain of the second transistor T22 is electrically connected to the second third node N23, the source of the second transistor T22 is electrically connected to the anode of O12, and the cathode of O12 is electrically connected to the low voltage terminal VSS.

[0240] The second data writing circuit includes a second third transistor T23, and the second second energy storage circuit includes a second second capacitor C22;

[0241] The gate of the second third transistor T23 is electrically connected to the scan terminal G1, the drain of the second third transistor T23 is electrically connected to the second data line DL2, and the source of the second third transistor T23 is electrically connected to the second first node N21.

[0242] The first terminal of the second capacitor C22 is electrically connected to the second third node N23, and the second terminal of the second capacitor C22 is electrically connected to the power supply voltage terminal VDD.

[0243] The second first initialization circuit includes a second fourth transistor T24;

[0244] The gate of the second fourth transistor T24 is electrically connected to the first reset control terminal G2, the drain of the second fourth transistor T24 is electrically connected to the reference voltage terminal REF, and the source of the second fourth transistor T24 is electrically connected to the second first node N21.

[0245] The third driving circuit includes a third driving transistor DT3, the third first energy storage circuit includes a third first capacitor C31, the third first light-emitting control circuit includes a third first transistor T31; the third light-emitting element is a third organic light-emitting diode O13.

[0246] The gate of the third driving transistor DT3 is electrically connected to the third first node N31, and the drain of the third driving transistor DT3 is electrically connected to the third second node N32.

[0247] The first terminal of the third first capacitor C31 is electrically connected to the third first node N31, and the second terminal of the third first capacitor C31 is electrically connected to the third third node N33.

[0248] The gate of the third first transistor T31 is electrically connected to the first light-emitting control terminal EM1, the drain of the third first transistor T31 is electrically connected to the source of the third driving transistor DT3, and the source of the third first transistor T31 is electrically connected to the third third node N33.

[0249] The third second light-emitting control circuit includes a third second transistor T32;

[0250] The gate of the third second transistor T32 is connected to the second light-emitting control terminal EM2, the drain of the third second transistor T32 is electrically connected to the third third node N33, the source of the third second transistor T32 is electrically connected to the anode of O13, and the cathode of O13 is electrically connected to the low voltage terminal VSS.

[0251] The third data writing circuit includes a third third transistor T33, and the third second energy storage circuit includes a third second capacitor C32;

[0252] The gate of the third transistor T33 is electrically connected to the scan terminal G1, the drain of the third transistor T33 is electrically connected to the third data line DL3, and the source of the third transistor T33 is electrically connected to the third first node N31.

[0253] The first terminal of the third second capacitor C32 is electrically connected to the third third node N33, and the second terminal of the third second capacitor C32 is electrically connected to the power supply voltage terminal VDD.

[0254] The third first initialization circuit includes a third fourth transistor T34;

[0255] The gate of the third fourth transistor T34 is electrically connected to the first reset control terminal G2, the drain of the third fourth transistor T34 is electrically connected to the reference voltage terminal REF, and the source of the third fourth transistor T34 is electrically connected to the third first node N31.

[0256] The third light-emitting control circuit includes a fifth transistor T5;

[0257] The gate of the fifth transistor T5 is electrically connected to the third light-emitting control terminal EM3, the drain of the fifth transistor T5 is electrically connected to the power supply voltage terminal VDD, and the source of the fifth transistor T5 is electrically connected to the first second node N12.

[0258] The second initialization circuit includes a sixth transistor T6;

[0259] The gate of the sixth transistor T6 is electrically connected to the second reset control terminal G3, the drain of the sixth transistor T6 is electrically connected to the initial voltage terminal I1, and the source of the sixth transistor T6 is electrically connected to the first second node N12; the initial voltage terminal is used to provide the initial voltage Vinit.

[0260] In at least one embodiment shown in Figure 15, all transistors are n-type transistors;

[0261] The capacitor labeled C01 is the capacitor between the two terminals of O11, the capacitor labeled C02 is the capacitor between the two terminals of O12, and the capacitor labeled C03 is the capacitor between the two terminals of O13.

[0262] In at least one embodiment shown in Figure 15, the reference voltage Vref can be greater than or equal to 3V and less than or equal to 4V;

[0263] The voltage value of Vinit can be 0V, or the voltage value of Vinit can be less than 0V.

[0264] As shown in FIG16, when at least one embodiment of the pixel circuit shown in FIG15 of this disclosure is in operation, the display cycle may include an initialization stage S1, a compensation stage S2, a writing stage S3 and a light emission stage S4 set sequentially.

[0265] During the initialization phase S1, G2, G3, EM1, and EM2 all provide high voltage signals, G1 and EM3 both provide low voltage signals, T14, T24, and T34 are all turned on, REF provides the reference voltage Vref to N11, N21, and N31, T6 is turned on, and I1 provides the initial voltage Vinit to N12 so that DT1, DT2, and DT3 can all be turned on when the compensation phase S2 begins.

[0266] During the initialization phase, S1, T11, and T12 are all turned on, and DT1 is turned on, writing Vinit to the anode of O11 and clearing the residual charge on the anode of O11; T21 and T22 are all turned on, and DT2 is turned on, writing Vinit to the anode of O12 and clearing the residual charge on the anode of O12; T31 and T32 are all turned on, and DT3 is turned on, writing Vinit to the anode of O13 and clearing the residual charge on the anode of O13.

[0267] During the compensation phase S2, EM1 and EM3 provide high voltage signals, G2 provides a high voltage signal, G1, G3 and EM2 provide low voltage signals, T11, T21, T31 and T5 are all turned on, T14, T24 and T34 are all turned on, and REF provides a reference voltage Vref to N11, N21 and N31.

[0268] At the start of the compensation phase S2, DT1 is turned on, charging the capacitor through Vref and changing the potential of N13 until the potential of N13 becomes Vref-Vth1. Then DT1 is turned off, and Vth1 is the threshold voltage of DT1.

[0269] At the start of the compensation phase S2, DT2 is turned on, charging the capacitor through Vref and changing the potential of N23 until the potential of N23 becomes Vref-Vth2, at which point DT2 is turned off, and Vth2 is the threshold voltage of DT2.

[0270] At the start of the compensation phase S2, DT3 is turned on, charging the capacitor through Vref and changing the potential of N33 until the potential of N33 becomes Vref-Vth3, at which point DT3 is turned off, and Vth3 is the threshold voltage of DT3.

[0271] During the write phase S3, G1 provides a high voltage signal, while G2 and G3 both provide low voltage signals. EM1 and EM2 both provide low voltage signals, and EM3 provides a high voltage signal. T13 is turned on, and DL1 provides the first data voltage Vdata1 to N11. The potential of N11 changes from Vref to Vdata1. The potential of N13 is affected by the coupling of C11, causing a change in the potential of N13. Therefore, this stage determines the accuracy of the compensation. Since T11 shields the parasitic capacitance of DT1 from affecting the potential of N13, and T12 shields the parasitic capacitance of O11 from affecting N13... Due to the influence of the potential of N13, the potential of N13 is only affected by the coupling of C11. Finally, the potential of N13 becomes Vref-Vth1+(Vdata1-Vref)×C11z / (C11z+C12z). The gate-source voltage Vgs2 of DT1 is equal to (Vdata1-Vref)×(1-a1)+Vth1, where a1 is equal to C11z / (C11z+C12z), which can isolate the influence of DT1 and O11; where C11z is the capacitance value of C11 and C12z is the capacitance value of C12.

[0272] During the write phase S3, G1 provides a high voltage signal, while G2 and G3 both provide low voltage signals. EM1 and EM2 both provide low voltage signals, and EM3 provides a high voltage signal. T23 is turned on, and DL2 provides the second data voltage Vdata2 to N21. The potential of N21 changes from Vref to Vdata2. The potential of N23 is affected by the coupling of C21, causing a change in N23's potential. Therefore, this stage determines the accuracy of the compensation. Since T21 shields the parasitic capacitance of DT2 from affecting the potential of N13, and T22 shields O12 from affecting N13's potential... Due to the influence of the potential of N23, the potential of N23 is only affected by the coupling of C21. Finally, the potential of N23 becomes Vref-Vth2+(Vdata2-Vref)×C21z / (C21z+C22z). The gate-source voltage Vgs2 of DT2 is equal to (Vdata2-Vref)×(1-a2)+Vth2, where a2 is equal to C21z / (C21z+C22z), which can isolate the influence of DT2 and O21; where C21z is the capacitance value of C21 and C22z is the capacitance value of C22.

[0273] During the write phase S3, G1 provides a high voltage signal, while G2 and G3 both provide low voltage signals. EM1 and EM2 both provide low voltage signals, and EM3 provides a high voltage signal. T33 is turned on, and DL3 provides the third data voltage Vdata3 to N31. The potential of N31 changes from Vref to Vdata3. The potential of N33 is affected by the coupling of C31, causing a change in N33's potential. Therefore, this stage determines the accuracy of the compensation. Because T31 shields the parasitic capacitance of DT3 from affecting the potential of N33, and T12 shields O13 from affecting N33's potential... The potential of N33 is only affected by the coupling of C31, so the potential of N33 becomes Vref-Vth3+(Vdata3-Vref)×C31z / (C31z+C32z). The gate-source voltage Vgs3 of DT3 is equal to (Vdata3-Vref)×(1-a3)+Vth3, where a3 is equal to C31z / (C31z+C32z), which can isolate the influence of DT3 and O13; where C31z is the capacitance value of C31 and C32z is the capacitance value of C32.

[0274] During the light-emitting stage S4, G1, G2, and G3 all provide low-voltage signals, while EM1 and EM2 all provide high-voltage signals. When EM3 is turned on, T5, T11, T12, T21, T22, T31, and T32 are all turned on. DT1 drives O11 to emit light, DT2 drives O12 to emit light, and DT3 drives O13 to emit light.

[0275] During the light-emitting stage S4, the third light-emitting control signal provided by EM3 can turn T6 on or off as needed to perform PWM (pulse width modulation) dimming design.

[0276] The pixel driving method described in this embodiment is applied to the pixel circuit described above, and the display cycle includes a writing phase; the pixel driving method includes:

[0277] During the writing phase, the first light-emitting control circuit, under the control of the first light-emitting control signal, controls the second terminal of the driving circuit to disconnect from the third node, so as to shield the effect of the parasitic capacitance of the driving transistor included in the driving circuit on the potential of the third node.

[0278] In at least one embodiment of this disclosure, the pixel circuit further includes a light-emitting element and a second light-emitting control circuit; the pixel driving method further includes:

[0279] During the writing phase, the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the third node to disconnect from the first electrode of the light-emitting element, so as to shield the hard potential of the light-emitting element to the third node.

[0280] In at least one embodiment of this disclosure, the pixel circuit further includes a data writing circuit; the pixel driving method includes:

[0281] During the writing phase, the data writing circuit writes the data voltage to the first node under the control of the scanning signal.

[0282] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit; the display cycle further includes a compensation phase set before the writing phase; the pixel driving method includes:

[0283] During the compensation phase, the first initialization circuit, under the control of the first reset control signal, writes the reference voltage into the first node, and the first light emission control circuit, under the control of the first light emission control signal, controls the connection between the second terminal of the driving circuit and the third node.

[0284] The display device described in this disclosure includes the pixel circuit described above.

[0285] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

A pixel circuit comprises a driving circuit, a first light-emitting control circuit and a first energy storage circuit; a control end of the driving circuit is electrically connected with a first node, a first end of the driving circuit is electrically connected with a second node, and the driving circuit is configured to generate a driving current under the control of a potential of the first node; a first end of the first energy storage circuit is electrically connected with the first node, and a second end of the first energy storage circuit is electrically connected with a third node, and the first energy storage circuit is configured to store energy; the first light-emitting control circuit is electrically connected with a first light-emitting control end, a second end of the driving circuit and the third node respectively, and is configured to control the second end of the driving circuit and the third node to be connected or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control end. The pixel circuit as claimed in claim 1, wherein Further comprising a light-emitting element and a second light-emitting control circuit; the second light-emitting control circuit is electrically connected with a second light-emitting control end, the third node and a first electrode of the light-emitting element respectively, and is configured to control the third node and the first electrode of the light-emitting element to be connected or disconnected under the control of a second light-emitting control signal provided by the second light-emitting control end; a second electrode of the light-emitting element is electrically connected with a first voltage end. The pixel circuit as claimed in claim 2, wherein the first light-emitting control end and the second light-emitting control end are electrically connected with light-emitting control signal output ends of different-stage light-emitting control signal generation circuits in a same light-emitting control signal generation module respectively. The pixel circuit according to any one of claims 1 to 3, wherein Further comprising a data writing circuit and a second energy storage circuit; the data writing circuit is electrically connected with a scanning end, a data line and the first node respectively, and is configured to write a data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning end; the second energy storage circuit is electrically connected with the third node, and is configured to maintain a potential of the third node. The pixel circuit according to any one of claims 1 to 3, wherein Further comprising a first initialization circuit; the first initialization circuit is electrically connected with a first reset control end, a reference voltage end and the first node respectively, and is configured to write a reference voltage provided by the reference voltage end into the first node under the control of a first reset control signal provided by the first reset control end. The pixel circuit according to any one of claims 1 to 3, wherein Further comprising a third light-emitting control circuit; the third light-emitting control circuit is electrically connected with a third light-emitting control end, a power voltage end and the second node respectively, and is configured to control the power voltage end and the second node to be connected or disconnected under the control of a third light-emitting control signal provided by the third light-emitting control end. The pixel circuit according to any one of claims 1 to 3, wherein Further comprising a second initialization circuit; the second initialization circuit is electrically connected with a second reset control end and an initial voltage end respectively, and is further electrically connected with the second node or the third node, and is configured to write an initial voltage provided by the initial voltage end into the second node or the third node under the control of a second reset control signal provided by the second reset control end. The pixel circuit as claimed in claim 1, wherein the driving circuit comprises a driving transistor, the first energy storage circuit comprises a first capacitor, and the first light-emitting control circuit comprises a first transistor; a gate of the driving transistor is electrically connected with the first node, and a first electrode of the driving transistor is electrically connected with the second node. A first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with a third node. A gate of the first transistor is electrically connected with the first light-emitting control end, a first electrode of the first transistor is electrically connected with the second electrode of the driving transistor, and a second electrode of the first transistor is electrically connected with the third node. The pixel circuit as claimed in claim 2, wherein The second light-emitting control circuit includes a second transistor. A gate of the second transistor is electrically connected with the second light-emitting control end, a first electrode of the second transistor is electrically connected with the third node, and a second electrode of the second transistor is electrically connected with the first electrode of the light-emitting element. The pixel circuit as claimed in claim 4, wherein The data writing circuit includes a third transistor, and the second energy storage circuit includes a second capacitor. A gate of the third transistor is electrically connected with the scanning end, a first electrode of the third transistor is electrically connected with the data line, and a second electrode of the third transistor is electrically connected with the first node. A first end of the second capacitor is electrically connected with the third node, and a second end of the second capacitor is electrically connected with a direct-current voltage end. The pixel circuit as claimed in claim 5, wherein The first initialization circuit includes a fourth transistor. A gate of the fourth transistor is electrically connected with the first reset control end, a first electrode of the fourth transistor is electrically connected with the reference voltage end, and a second electrode of the fourth transistor is electrically connected with the first node. The pixel circuit as claimed in claim 6, wherein The third light-emitting control circuit includes a fifth transistor. A gate of the fifth transistor is electrically connected with the third light-emitting control end, a first electrode of the fifth transistor is electrically connected with the power voltage end, and a second electrode of the fifth transistor is electrically connected with the second node. The pixel circuit of claim 7, wherein, The second initialization circuit includes a sixth transistor. A gate of the sixth transistor is electrically connected with the second reset control end, a first electrode of the sixth transistor is electrically connected with the initial voltage end, and a second electrode of the sixth transistor is electrically connected with the second node or the third node. A pixel module includes a third light-emitting control circuit and N pixel circuits as claimed in any one of claims 1 to 5; N is an integer greater than 1. The third light-emitting control circuit is electrically connected with a third light-emitting control end, a power voltage end and a second node respectively, and is configured to control communication or disconnection between the power voltage end and the second node under control of a third light-emitting control signal provided by the third light-emitting control end. The pixel module of claim 14, wherein, The pixel module further includes a second initialization circuit. The second initialization circuit is electrically connected with a second reset control end, an initial voltage end and the second node respectively, and is configured to write an initial voltage provided by the initial voltage end into the second node under control of a second reset control signal provided by the second reset control end. A pixel driving method applied to the pixel circuit as claimed in any one of claims 1 to 13, wherein A display period includes a writing stage. The pixel driving method includes: In the writing stage, the first light-emitting control circuit controls disconnection between the second end of the driving circuit and the third node under control of a first light-emitting control signal. The pixel driving method as claimed in claim 16, wherein, The pixel circuit further includes a light-emitting element and a second light-emitting control circuit. The pixel driving method further includes: In the writing stage, the second light emitting control circuit controls the third node to be disconnected from the first electrode of the light emitting element under the control of a second light emitting control signal. The pixel driving method according to claim 16 or 17, wherein The pixel circuit further comprises a data writing circuit; and the pixel driving method comprises: In the writing stage, the data writing circuit writes a data voltage into the first node under the control of a scanning signal. The pixel driving method according to claim 16 or 17, wherein The pixel circuit further comprises a first initialization circuit; the display cycle further comprises a compensation stage arranged before the writing stage; and the pixel driving method comprises: In the compensation stage, the first initialization circuit writes a reference voltage into the first node under the control of a first reset control signal, and the first light emitting control circuit controls the second end of the driving circuit to be connected to the third node under the control of a first light emitting control signal. A display device comprises the pixel circuit according to any one of claims 1 to 13. A display device comprises the pixel module according to claim 14 or 15.

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