Signal transmission circuit, signal transmission system, electric control system, and vehicle

Abstract

The present application belongs to the technical field of capacitive isolation. Provided are a signal transmission circuit, a signal transmission system, an electric control system, and a vehicle. The signal transmission circuit comprises: an isolation module and a receiving module, wherein the receiving module comprises a signal receiving circuit and a signal output unit; the isolation module is configured to receive a first differential signal, electrically isolate the first differential signal, and then output a second differential signal; an input end of the signal receiving circuit is connected to an output end of the isolation module, and the signal receiving circuit is configured to process the second differential signal and then output a third differential signal; and an input end of the signal output unit is connected to an output end of the signal receiving circuit, and the signal output unit is configured to combine the third differential signal and then output a single-ended signal. The present application can improve a signal transmission effect of a capacitive isolator.

Description

Signal transmission circuit, signal transmission system, electric control system and vehicle

[0001] The present application claims priority to the Chinese patent application No. 202411038834.1, filed on July 30, 2024, and titled "Signal transmission circuit, signal transmission system, electric control system and vehicle", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of capacitive isolation, and in particular to a signal transmission circuit, a signal transmission system, an electric control system and a vehicle. BACKGROUND

[0003] The capacitive isolator is mainly used for isolating high-voltage and low-voltage domains to realize the "ground" isolation between different power domains, and is commonly used for signal transmission between chips or systems in different power domains.

[0004] The current use architecture of the capacitive isolator is that the main side input signal of the capacitive isolator is transmitted to the secondary side through the capacitive isolator, and the signal is output by the secondary side. This use architecture has the problem of poor signal transmission effect.

[0005] How to improve the signal transmission effect of the capacitive isolator is still urgent to be solved. SUMMARY

[0006] The present application aims to provide a signal transmission circuit, a signal transmission system, an electric control system and a vehicle for improving the signal transmission effect of the capacitive isolator.

[0007] In a first aspect, the present application discloses a signal transmission circuit, comprising: an isolation module and a receiving module, wherein the receiving module comprises a signal receiving circuit and a signal output device;

[0008] The isolation module is configured to receive a first differential signal, electrically isolate the first differential signal, and output a second differential signal.

[0009] The signal receiving circuit is configured to receive the second differential signal, process the second differential signal, and output a third differential signal.

[0010] The signal output device is configured to receive the third differential signal, combine the third differential signal, and output a signal.

[0011] In a second aspect, the present application discloses a signal transmission system, comprising the signal transmission circuit of the first aspect, and further comprising a controller, a driving module and a power device.

[0012] The output end of the controller is connected with the input end of the signal transmission circuit.

[0013] The input end of the driving module is connected with the output end of the signal transmission circuit.

[0014] The input end of the power device is connected with the output end of the driving module.

[0015] The driving module is used for boosting the signal output by the signal transmission circuit and outputting the signal to the power device, so as to drive the power device to operate.

[0016] In a third aspect, the application provides an electric control system of a vehicle, which comprises the signal transmission system according to the second aspect.

[0017] In a fourth aspect, the application provides a vehicle, which comprises the electric control system of the vehicle according to the third aspect.

[0018] In combination with the above technical solution, the signal transmission circuit disclosed in the application comprises an isolation module and a receiving module, the receiving module comprising a signal receiving circuit and a signal output device. The isolation module is used for receiving a first differential signal and outputting a second differential signal after electrically isolating the first differential signal. The signal receiving circuit is connected with the output end of the isolation module, and is used for outputting a third differential signal after processing the second differential signal. The signal output device is connected with the output end of the signal receiving circuit, and is used for outputting a signal after merging the third differential signal.

[0019] Compared with the traditional capacitor isolator use architecture with a large number of secondary devices and high use architecture complexity, the signal transmission circuit provided in the embodiment can realize the functions of multiple secondary devices in the traditional capacitor isolator use architecture by using one signal output device, reduce the number of secondary devices, and simplify the circuit structure of the secondary side (the receiving module) of the isolation module. The more the secondary devices are, and the more complex the circuit structure of the secondary side is, the worse the signal transmission effect is. On the contrary, the fewer the secondary devices are, and the simpler the circuit structure of the secondary side is, the fewer the factors that interfere with the signal are, and the less the signal loss is, so the signal transmission quality and transmission effect are better. Therefore, the signal transmission circuit provided in the embodiment can improve the signal transmission effect of the capacitor isolator. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0021] Figure 1 is a structural schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0022] Figure 2 is a structural schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0023] Figure 3 is a structural schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0024] Figure 4 is a structural schematic diagram of a differential amplifier circuit in a signal transmission circuit according to some embodiments of the present application;

[0025] Figure 5 is a structural schematic diagram of a circuit for generating a trigger level in a signal transmission circuit according to some embodiments of the present application;

[0026] Figure 6 is a structural schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0027] Figure 7 is a structural schematic diagram of a clamping module in a signal transmission circuit according to some embodiments of the present application;

[0028] Figure 8 is a structural schematic diagram of a clamping module in a signal transmission circuit according to some embodiments of the present application;

[0029] Figure 9 is a structural schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0030] Figure 10 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0031] Figure 11 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0032] Figure 12 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0033] Figure 13 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0034] Figure 14 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0035] Figure 15 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0036] Figure 16 is a partial structural schematic diagram of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0037] FIG. 17 is a schematic diagram of a partial structure of a front-stage differential amplifier in a signal transmission circuit according to some embodiments of the present application;

[0038] FIG. 18 is a schematic diagram of an input module in a signal transmission circuit according to some embodiments of the present application;

[0039] FIG. 19 is a schematic diagram of an input signal in a signal transmission circuit according to some embodiments of the present application;

[0040] FIG. 20 is a schematic diagram of an oscillator signal in a signal transmission circuit according to some embodiments of the present application;

[0041] FIG. 21 is a schematic diagram of a first differential signal in a signal transmission circuit according to some embodiments of the present application;

[0042] FIG. 22 is a schematic diagram of a structure in a signal transmission circuit according to some embodiments of the present application;

[0043] FIG. 23 is a schematic diagram of a filter circuit in a signal transmission circuit according to some embodiments of the present application;

[0044] FIG. 24 is a schematic diagram of a signal transmission circuit according to some embodiments of the present application;

[0045] FIG. 25 is a schematic diagram of a signal transmission system according to some embodiments of the present application;

[0046] FIG. 26 is a schematic diagram of an electric control system according to some embodiments of the present application;

[0047] FIG. 27 is a schematic diagram of a vehicle according to some embodiments of the present application.

[0048] Explanation of reference signs: 10 - signal transmission circuit; 20 - isolation module; 30 - clamping module; 31 - trigger circuit; 32 - bleeder circuit; 40 - receiving module; 41 - signal receiving circuit; 42 - signal output device; 43 - pre-stage differential amplification circuit; 44 - filter circuit; 45 - signal merging circuit; 46 - signal inverting circuit; 47 - delay circuit; 50 - input module; 51 - oscillator; 52 - logic circuit; 53 - driving circuit; 60 - signal transmission system; 61 - controller; 62 - driving module; 63 - power device; 70 - electric control system; 71 - load; 310 - first voltage dividing circuit; 320 - second voltage dividing circuit; 411 - first amplification circuit; 412 - second amplification circuit; 413 - first-stage sub-circuit; 414 - second-stage sub-circuit; 415 - third-stage sub-circuit; 416 - fourth-stage sub-circuit; 419 - preset voltage circuit; 421 - second pull-up circuit; 422 - second pull-down circuit; 423 - third pull-up circuit; 424 - third pull-down circuit; 425 - fourth pull-up circuit; 426 - fourth pull-down circuit; 427 - fifth pull-up circuit; 428 - fifth pull-down circuit; 430 - another preset voltage circuit; 440 - differential amplification circuit; 441 - first signal input circuit; 442 - second signal input circuit; 450 - merging sub-circuit; 451 - first switch circuit; 452 - second switch circuit; 453 - merging unit; 460 - inverting unit; 461 - control unit. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0050] In the description of the present application, it should be noted that unless explicitly defined and limited, the terms "mounting", "connection" and "linking" should be understood in a broad sense, for example, it can be fixed connection, or indirect connection through an intermediate medium, or internal connection of two elements or interaction relationship between two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0051] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0052] The terms "first", "second", "third" (if any) in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily have to describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0053] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or maintenance tool including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or maintenance tools.

[0054] The capacitor isolator is mainly used for isolating high-voltage and low-voltage domains to realize "ground" isolation between different power domains, and is commonly used for signal transmission between chips or systems in different power domains. The current use architecture of the capacitor isolator is that the main side input signal of the capacitor isolator is transmitted to the secondary side through the capacitor isolator, and the signal is output by the secondary side.

[0055] This use architecture has high circuit complexity, resulting in poor signal transmission effect.

[0056] Based on this, the present application provides a signal transmission circuit, a signal transmission system, an electric control system and a vehicle.

[0057] The signal transmission circuit includes an isolation module and a receiving module. The receiving module includes a signal receiving circuit and a signal output device. The isolation module is configured to receive a first differential signal, electrically isolate the first differential signal, and output a second differential signal. The signal receiving circuit is connected to the output end of the isolation module, configured to process the second differential signal, and output a third differential signal. The signal output device is connected to the output end of the signal receiving circuit, configured to combine the third differential signal, and output a signal.

[0058] Compared with the traditional capacitor isolation device usage architecture with a large number of secondary devices and high usage architecture complexity, the signal transmission circuit provided in the application can realize the function of multiple secondary devices in the traditional capacitor isolation device usage architecture with one signal output device, reduce the number of secondary devices, and simplify the circuit structure of the secondary side (the receiving module) of the isolation module. The more secondary devices and the more complex the circuit structure of the secondary side, the worse the signal transmission effect. On the contrary, the fewer secondary devices and the simpler the circuit structure of the secondary side, the fewer factors that interfere with the signal, and the less loss of the signal, so the signal transmission quality and transmission effect are better. Therefore, the signal transmission circuit provided in the application can improve the signal transmission effect of the capacitor isolation device.

[0059] Please refer to FIG. 1, one embodiment of the application provides a signal transmission circuit 10, which includes an isolation module 20 and a receiving module 40.

[0060] The description of the isolation module 20 is as follows:

[0061] The isolation module 20 is used to receive a first differential signal and output a second differential signal. Specifically, the isolation module 20 is used to output the second differential signal after electrically isolating the first differential signal.

[0062] The first differential signal is output by an input module. When the input module is connected to a chip, the pulse signal output by the chip to the input module is processed into a first differential signal. The first differential signal can also be output by other modules, which is not limited here.

[0063] As shown in FIG. 1, the first differential signal includes a first positive signal (OUT+) and a first negative signal (OUT-). The isolation module 20 outputs a second positive signal (INPUT+) after receiving the first positive signal, and outputs a second negative signal (INPUT-) after receiving the first negative signal.

[0064] In some optional embodiments, the isolation module 20 is a capacitor isolation module 20, which includes an isolation capacitor, which can be a high-voltage isolation capacitor.

[0065] For example, at least one high-voltage isolation capacitor can be provided for the first positive signal (OUT+), and two high-voltage isolation capacitors connected in series can be provided. Correspondingly, at least one high-voltage isolation capacitor can be provided for the second positive signal (OUT-), and two high-voltage isolation capacitors connected in series can be provided.

[0066] It should be noted that the number of high-voltage isolation capacitors provided for the first positive signal and the second positive signal needs to be consistent. For example, if two high-voltage isolation capacitors connected in series are provided for the first positive signal, two high-voltage isolation capacitors connected in series also need to be provided for the second positive signal.

[0067] The receiving module 40 is described as follows:

[0068] The receiving module 40 is used for outputting after demodulating the second differential signal. The demodulation processing can be amplifying the second differential signal and then fusing.

[0069] The receiving module 40 includes a signal receiving circuit 41 and a signal outputter 42.

[0070] The input end of the signal receiving circuit 41 is connected with the output end of the isolation module 20. The signal receiving circuit 41 is used for outputting a third differential signal after processing the second differential signal. The signal receiving circuit 41 can amplify, filter, etc. the second differential signal. The amplification processing can include one-stage amplification processing, multi-stage amplification processing. The filtering processing can include one-time filtering processing, multi-time filtering processing.

[0071] The input end of the signal outputter 42 is connected with the output end of the signal receiving circuit 41. The signal outputter 42 is used for outputting a signal after merging the third differential signal. The signal is almost the same as the pulse signal outputted from the chip to the input module.

[0072] The signal outputter 42 can be composed of resistors, capacitors, etc., and the circuit structure is simple.

[0073] Optionally, the signal outputter 42 can also amplify the third differential signal and then inversely merge it into a signal. It can be understood that in the actual use of the signal transmission circuit 10, the output end of the secondary device is connected with the input end of the power device, and when the power device switches, the parasitic capacitance of the isolation module 20 to the ground is large, which causes the signal outputted from the isolation module 20 to carry a common-mode level. When the common-mode level is too large, the secondary device will be damaged. When the signal outputter 42 amplifies the third differential signal, the voltage amplitude of the third differential signal is amplified differentially, which can effectively suppress the common-mode level. Further, the larger the amplification multiple of the signal outputter 42 to the third differential signal is, the stronger the anti-common-mode interference ability of the signal outputter 42 is.

[0074] In summary, the signal transmission circuit 10 provided in the embodiment includes an isolation module 20 and a receiving module 40, and the receiving module 40 includes a signal receiving circuit 41 and a signal outputter 42. The isolation module 20 is configured to receive a first differential signal, electrically isolate the first differential signal, and output a second differential signal. The signal receiving circuit 41 is connected to the output end of the isolation module 20, and is configured to process the second differential signal and output a third differential signal. The signal outputter 42 is connected to the output end of the signal receiving circuit 41, and is configured to combine the third differential signal and output a signal.

[0075] Compared with the traditional capacitor isolator architecture with a large number of secondary devices and high complexity, the signal transmission circuit 10 provided in the embodiment can realize the functions of a plurality of secondary devices in the traditional capacitor isolator architecture by using one signal outputter 42, thereby reducing the number of secondary devices and simplifying the circuit structure of the secondary side (the receiving module 40) of the isolation module 20. The more the secondary devices are and the more complex the circuit structure of the secondary side is, the worse the signal transmission effect is. On the contrary, the fewer the secondary devices are and the simpler the circuit structure of the secondary side is, the fewer the factors that interfere with the signal are, and the less the signal loss is, so the signal transmission quality and transmission effect are better. Therefore, the signal transmission circuit 10 provided in the embodiment can improve the signal transmission effect of the capacitor isolator.

[0076] Referring to FIG. 2, in some embodiments of the present application, the signal outputter 42 includes a signal combining circuit 45 and a signal inverting circuit 46.

[0077] The input end of the signal combining circuit 45 is connected to the output end of the signal receiving circuit 41, and is configured to invert and combine the third differential signal into an initial signal. Optionally, the signal combining circuit 45 can also differentially amplify the third differential signal, and then invert and combine the differentially amplified third differential signal into an initial signal.

[0078] The input end of the signal inverting circuit 46 is connected to the output end of the signal combining circuit 45, and is configured to invert the initial signal and output a signal.

[0079] It should be noted that the initial signal output by the signal combining circuit 45 is inverted with respect to the pulse signal received by the input module as described above. In order to make the finally output signal almost the same as the pulse signal received by the input module, the signal inverting circuit 46 is required to invert the initial signal output by the signal combining circuit 45 and output a signal.

[0080] The signal outputter 42 in the signal transmission circuit 10 provided by the embodiment includes a signal merging circuit 45 and a signal inverting circuit 46. The input end of the signal merging circuit 45 is connected with the output end of the signal receiving circuit 41, and is configured to inversely merge the third differential signal into an initial signal. The input end of the signal inverting circuit 46 is connected with the output end of the signal merging circuit 45, and is configured to inversely output a signal from the initial signal. The signal inverting circuit 46 outputs the signal to the power device at the next stage, and the output signal is almost the same as the pulse signal received by the input module, thereby completing the signal transmission.

[0081] Referring to FIG. 3, in some embodiments of the present application, the signal merging circuit 45 includes a differential amplification circuit 440 and a merging sub-circuit 450.

[0082] The input end of the differential amplification circuit 440 is connected with the output end of the signal receiving circuit 41, and is configured to amplify and process the third differential signal to output a fourth differential signal.

[0083] That is, the signal merging circuit 45 first performs differential amplification processing on the third differential signal based on the differential amplification circuit 440, and then performs merging on the differential signal after the differential amplification processing (i.e., the fourth differential signal).

[0084] Optionally, the differential amplification circuit 440 can be provided with a Metal-Oxide-Semiconductor (MOS) tube and the like. The MOS tube is also called a transistor. The third differential signal is amplified through the amplification of the transistor. Other devices that can amplify differential signals can also be provided in the differential amplification circuit 440, which is not limited in the embodiment.

[0085] The differential amplification circuit 440 can include a one-stage amplification circuit or a multi-stage amplification circuit, which is not limited in the embodiment.

[0086] As described above, the greater the amplification multiple of the signal outputter 42 on the third differential signal, the stronger the anti-common-mode interference ability of the signal outputter 42. That is, the greater the amplification multiple of the differential amplification circuit 440, the stronger the anti-common-mode interference ability of the signal outputter 42. Optionally, the amplification multiple of the differential amplification circuit 440 can be improved by applying a level.

[0087] The input end of the merging sub-circuit 450 is connected with the output end of the differential amplification circuit 440, for inversely merging the fourth differential signal into the one-way initial signal. The merging sub-circuit 450 can be provided with a switch periodically turned on under the control of the fourth differential signal, which can be a transistor or a type switch, as long as it can be periodically turned on under the control of the differential signal.

[0088] The signal merging circuit 45 provided by the embodiment includes a differential amplification circuit 440 and a merging sub-circuit 450. The input end of the differential amplification circuit 440 is connected with the output end of the signal receiving circuit 41, for performing differential amplification processing on the third differential signal and outputting a fourth differential signal. The input end of the merging sub-circuit 450 is connected with the output end of the differential amplification circuit 440, for inversely merging the fourth differential signal into the one-way initial signal. The greater the amplification multiple of the differential amplification circuit 440, the stronger the anti-common-mode interference capability of the signal merging circuit 45 and the signal outputter 42, and the signal transmission effect of the signal transmission circuit 10 can be further improved.

[0089] Please refer to FIG. 4, in some embodiments of the present application, the differential amplification circuit 440 includes a first signal input circuit 441 and a second signal input circuit 442. The third differential signal includes a third positive signal (OUTA+ shown in FIG. 4) and a third negative signal (OUTA- shown in FIG. 4).

[0090] The first signal input circuit 441 is used for receiving the third positive signal and a positive trigger level, outputting the fourth positive signal to the merging sub-circuit 450 according to the voltage difference between the third positive signal and the positive trigger level, and outputting the first synthesized signal of the third positive signal and the positive trigger level to the merging sub-circuit 450. The second signal input circuit 442 is used for receiving the third negative signal and a negative trigger level, outputting the fourth negative signal to the merging sub-circuit 450 according to the voltage difference between the third negative signal and the negative trigger level, and outputting the second synthesized signal of the third negative signal and the negative trigger level to the merging sub-circuit 450. The positive trigger level and the negative trigger level are common-mode levels, and the greater the absolute values of the positive trigger level and the negative trigger level, the greater the amplification multiple of the differential amplification circuit 440.

[0091] As shown in the example of FIG. 4, the first signal input circuit 441 includes a capacitor CC1, a transistor MC2, and a current source AC1. The capacitor CC1 has one end receiving the third positive signal and the other end connected to the control end of the transistor MC2. The second end of the transistor MC2 is connected to one end of the current source AC1. The other end of the current source AC1 is connected to a first power supply end (e.g., VSS as shown in FIG. 4). The first power supply end is a ground end or a low-voltage power supply end. The first end of the transistor MC2 is connected to the first end of the transistor MC1. The second end of the transistor MC1 is connected to a power supply end (e.g., VCC as shown in FIG. 4). The transistor MC1 constitutes a pull-up circuit, which can further include other devices and is not limited in the embodiment.

[0092] The capacitor CC1 is configured to transmit the voltage amplitude of the third positive signal to a positive trigger level (e.g., VB+ as shown in FIG. 4). The signal input to the control end of the transistor MC2 is a first combined signal of the third positive signal and the positive trigger level. The second end of the transistor MC2 outputs the fourth positive signal.

[0093] As shown in the example of FIG. 4, the second signal input circuit 442 includes a capacitor CC2, a transistor MC3, and a current source AC2. The capacitor CC2 has one end receiving the third negative signal and the other end connected to the control end of the transistor MC3. The second end of the transistor MC3 is connected to one end of the current source AC2. The other end of the current source AC2 is connected to the first power supply end (e.g., VSS as shown in FIG. 4). The first end of the transistor MC3 is connected to the first end of the transistor MC1. The second end of the transistor MC1 is connected to the power supply end (e.g., VCC as shown in FIG. 4). The transistor MC1 constitutes a pull-up circuit, which can further include other devices and is not limited in the embodiment.

[0094] The capacitor CC2 is configured to transmit the voltage amplitude of the third negative signal to a negative trigger level (e.g., VB- as shown in FIG. 4). The signal input to the control end of the transistor MC3 is a second combined signal of the third negative signal and the negative trigger level. The second end of the transistor MC3 outputs the fourth negative signal.

[0095] The transistor MC1 can be a PMOS transistor as shown in FIG. 4, the control end of the transistor MC1 is a gate, the first end is a drain, and the second end is a source. The transistor MC2 can be an NMOS transistor as shown in FIG. 4, the control end of the transistor MC2 is a gate, the first end is a drain, and the second end is a source. The transistor MC3 can be an NMOS transistor as shown in FIG. 4, the control end of the transistor MC3 is a gate, the first end is a drain, and the second end is a source. The transistor MC2 and the transistor MC3 need to be the same type of transistors, such as both being NMOS transistors or both being PMOS transistors.

[0096] Please refer to FIG. 5, the differential amplification circuit 440 further comprises a circuit for generating a trigger level. The circuit is used for generating a common mode level such as the positive trigger level and the negative trigger level. The circuit can comprise a transistor MC9, a resistor RC3, a resistor RC4, a resistor RC5 and a current source AC4 as shown in FIG. 5. Among them, the second end of the transistor MC9 is connected to a power supply end (such as VCC shown in FIG. 5). The control end of the transistor MC9 is connected with the first end. The first end of the transistor MC9 is connected with the first end of the resistor RC3. The second end of the resistor RC3 is connected with the first end of the resistor RC4 and the first end of the resistor RC5. The first end of the resistor RC4 and the first end of the resistor RC5 are both connected with the first end of the current source AC4. The second end of the current source AC4 is connected with the first power supply end.

[0097] The second end of the resistor RC4 outputs the positive trigger level. The second end of the resistor RC5 outputs the negative trigger level. The size of the positive trigger level and the negative trigger level can be adjusted by adjusting the size of the resistor R3. The greater the absolute value of the positive trigger level and the absolute value of the negative trigger level, the greater the amplification factor of the differential amplification circuit 440, and correspondingly, the stronger the common mode interference resistance of the signal output device 42.

[0098] In the signal transmission circuit 10 provided by the embodiment, the differential amplification circuit 440 comprises a first signal input circuit 441 and a second signal input circuit 442. The first signal input circuit 441 is used for receiving the third positive signal and the positive trigger level, outputting the fourth positive signal to the merging sub-circuit 450 according to the third positive signal and the positive trigger level, and outputting a first synthesized signal of the third positive signal and the positive trigger level to the merging sub-circuit 450. The second signal input circuit 442 is used for receiving the third negative signal and the negative trigger level, outputting the fourth negative signal to the merging sub-circuit 450 according to the third negative signal and the negative trigger level, and outputting a second synthesized signal of the third negative signal and the negative trigger level to the merging sub-circuit 450. The positive trigger level and the negative trigger level are common mode levels. The greater the absolute value of the positive trigger level and the absolute value of the negative trigger level, the greater the amplification factor of the differential amplification circuit 440.

[0099] That is, by means of the positive trigger level and the negative trigger level, the amplification factor of the differential amplification circuit 440 can be adjusted, so as to improve the common mode interference resistance of the signal output device 42, and further improve the signal transmission effect. In addition, the differential amplification circuit 440 has a simple structure, and only a few transistors are needed to realize signal amplification, which reduces the complexity of the secondary side devices in the signal transmission architecture and improves the signal transmission effect.

[0100] Please also refer to FIG. 4, in some embodiments of the present application, the merging sub-circuit 450 comprises a first switch circuit 451, a second switch circuit 452 and a merging unit 453.

[0101] The input end of the first switch circuit 451 is connected with the output end of the first signal input circuit 441, for outputting a first path to-be-merged signal based on the first synthesis signal and the fourth positive signal when conducting under the control of the first synthesis signal. The input end of the second switch is connected with the output end of the second signal input circuit 442, for outputting a second path to-be-merged signal based on the second synthesis signal and the fourth negative signal when conducting under the control of the second synthesis signal. The first switch circuit 451 and the second switch circuit 452 are not simultaneously conducting or shutting down.

[0102] The first switch circuit 451 can comprise a transistor MC5 as shown in FIG. 4, and can also comprise a resistor RC1 as shown in FIG. 4, which is equivalent to a load. The control end of the transistor MC5 receives the first synthesis signal. The first end of the resistor RC1 is connected with the second end of the transistor MC2, and the second end of the resistor RC1 is connected with the second end of the transistor MC5. The second end of the transistor MC5 is connected with the second end of the transistor MC4. The first end of the transistor MC4 is connected with a power supply end (such as VCC shown in FIG. 4). The control end of the transistor MC4 is connected with the control end of the transistor MC1.

[0103] The transistor MC4 and the transistor MC1 constitute a current mirror, for copying the current of the transistor MC1 to the transistor MC4.

[0104] The fourth positive signal output by the transistor MC2 is transmitted to the transistor MC5 through the resistor RC1. The transistor MC5 conducts or shuts down under the control of the fourth positive signal and the first synthesis signal. The transistor MC5 outputs a signal to the second end of the transistor MC4 when conducting.

[0105] The second switch circuit 452 can comprise a transistor MC6 as shown in FIG. 4, and can also comprise a resistor RC2 as shown in FIG. 4, which is equivalent to a load. The control end of the transistor MC6 receives the second synthesis signal. The first end of the resistor RC2 is connected with the second end of the transistor MC3, and the second end of the resistor RC2 is connected with the second end of the transistor MC6. The second end of the transistor MC6 is connected with the second end of the transistor MC4.

[0106] The fourth negative signal output by the transistor MC3 is transmitted to the transistor MC6 through the resistor RC2. The transistor MC6 conducts or shuts down under the control of the fourth negative signal and the second synthesis signal. The transistor MC6 outputs a signal to the second end of the transistor MC4 when conducting.

[0107] It should be noted that since the third positive signal and the third negative signal are mutually opposite periodic signals, when the transistor MC5 is turned on, the transistor MC6 is turned off, and when the transistor MC6 is turned off, the transistor MC5 is turned on.

[0108] The transistor MC5 and the transistor MC6 can be NMOS tubes as shown in FIG. 4. The control end of the transistor MC5 is the gate, the first end is the drain, and the second end is the source. The control end of the transistor MC6 is the gate, the first end is the drain, and the second end is the source. The transistor MC4 can be a PMOS tube as shown in FIG. 4, and the control end of the transistor MC4 is the gate, the first end is the source, and the second end is the drain. The transistor MC4 and the transistor MC1 constitute a current mirror.

[0109] Other switching devices and resistors can also be added to the first switching circuit 451 and the second switching circuit 452, as long as the first switching circuit 451 and the second switching circuit 452 can achieve the functions described above.

[0110] The input end of the merging unit 453 is connected with the output end of the first switching circuit 451 and the output end of the second switching circuit 452, for merging the first road to be merged signal and the second road to be merged signal into an initial signal. The merging unit 453 can include the transistor MC4 described above. The merging unit 453 can also include other devices as long as they can achieve the corresponding functions.

[0111] In the signal transmission circuit 10 provided by the embodiment, the merging sub-circuit 450 includes the first switching circuit 451, the second switching circuit 452, and the merging unit 453. The first switching circuit 451 is configured to output a first road to be merged signal based on the first synthetic signal and the fourth positive signal when the first switching circuit 451 is turned on under the control of the first synthetic signal. The second switching circuit 452 is configured to output a second road to be merged signal based on the second synthetic signal and the fourth negative signal when the second switching circuit 452 is turned on under the control of the second synthetic signal. The merging unit 453 is configured to inversely merge the first road to be merged signal and the second road to be merged signal into an initial signal. The initial signal output by the merging unit 453 is a signal that is inversely relative to the pulse signal input by the input module as described above, and after being processed by the signal inversion circuit 46, a signal that is almost the same as the pulse signal can be output, thereby completing the transmission of the signal. The merging sub-circuit 450 provided by the embodiment has a simple structure and only needs some transistors to achieve signal merging, thereby reducing the complexity of the secondary side devices in the signal transmission architecture and improving the effect of signal transmission.

[0112] Please also refer to FIG. 4, in some embodiments of the application, the signal inversion circuit 46 includes an inversion unit 460 and a control unit 461.

[0113] The input end of the inverting unit 460 is connected with the output end of the combining unit 453, for outputting a signal after inverting the initial signal under the control of the control unit 461.

[0114] The inverting unit 460 can be an inverter, or other devices with inverting function.

[0115] The inverting unit 460 can include transistors MC7 and MC8 as shown in FIG. 4. The control ends of the transistors MC7 and MC8 are connected. The first end of the transistor MC7 is connected with a power supply end (VCC as shown in FIG. 4), and the second end and the control end are connected. The second end is also connected with the second end of the transistor MC4, the first end of the transistor MC5 and the first end of the transistor MC6. The initial signal formed by the second end of the transistor MC4 is transmitted to the second end of the transistor MC7. The first end of the transistor MC8 is connected with a power supply end (VCC as shown in FIG. 4), and the second end outputs the signal.

[0116] The control unit 461 can include a current source AC3 as shown in FIG. 4. The first end of the current source AC3 is connected with the second end of the transistor MC8, and the second end is connected with a first power supply end (VSS or low voltage power supply end as shown in FIG. 4).

[0117] The transistors MC7, MC8 and the current source AC3 constitute an analog inverter, which inverts the initial signal and outputs the signal (OUTP as shown in FIG. 4). At this time, the signal is almost the same as the pulse signal as described above, and the signal transmission is completed.

[0118] The transistors MC7 and MC8 can be PMOS tubes as shown in FIG. 4. The control end of the transistor MC7 is the gate, the first end is the source, and the second end is the drain. The control end of the transistor MC8 is the gate, the first end is the source, and the second end is the drain. The transistors MC7 and MC8 can also be other types of MOS tubes, but they must meet the condition of being able to constitute a current mirror.

[0119] The signal inverting circuit 46 provided by the embodiment includes the inverting unit 460 and the control unit 461. The inverting unit 460 is used for outputting a signal after inverting the initial signal under the control of the control unit 461. The inverting unit 460 and the control unit 461 have simple structure, and only some transistors and current sources are needed to realize the inversion of the signal, which reduces the complexity of the secondary devices in the signal transmission architecture and improves the effect of signal transmission.

[0120] Please refer to FIG. 6, in some embodiments of the present application, the second differential signal includes a second positive signal and a second negative signal. The signal transmission circuit 10 further includes a clamping module 30.

[0121] The clamping module 30 is connected with the output end of the isolation module 20, and is configured to clamp the common mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal.

[0122] The reason why the common mode level needs to be clamped is that the transient interference caused by the switching of the devices on the secondary side during the secondary side of the signal transmission circuit 10 can cause the ground of the primary side to be different from the ground of the secondary side, and the different grounds can cause the absolute value of the common mode level (positive common mode level or negative common mode level) of the second differential signal output by the isolation module 20 to increase. The devices on the secondary side can be understood as power devices, and the size of the common mode level is affected by the working voltage and the switching time of the power devices. The larger the working voltage and the shorter the switching time, the larger the common mode level. The devices inside the receiving module 40 have a limited voltage resistance value. In order to prevent the common mode level from being too large to damage the devices inside the receiving module 40, the clamping module 30 clamps the common mode level below the voltage resistance value of the devices inside the receiving module 40 when the common mode level is too large.

[0123] The clamping module 30 can be provided with a circuit for discharging the common mode level, which can discharge the positive common mode level and the negative common mode level. One end of the circuit receives the second differential signal, and the other end can be connected to a power supply end with a lower voltage. When discharging the positive common mode level, the positive common mode level is discharged to the power supply end with a lower voltage, and when discharging the negative common mode level, the output end of the isolation module 20 is charged from the power supply end.

[0124] It should be noted that the clamping circuit needs to be arranged between the output end of the isolation module 20 and the input end of the receiving module 40, so as to clamp the common mode level of the second differential signal before the second differential signal enters the receiving module 40. Preventing the common mode level from damaging the devices in the receiving module 40.

[0125] The signal transmission circuit 10 provided by the present embodiment further includes a clamping module 30, which is connected with the output end of the isolation module 20 and clamps the high-frequency signal (i.e. the second positive signal and the second negative signal) transmitted by the isolation module 20. When clamping, the common mode level is adjusted based on the second positive signal and the second negative signal. The common mode level carried by the second positive signal and the common mode level carried by the second negative signal are clamped at the same time and in the same amount, which improves the clamping effect. More importantly, it prevents the signal transmitted from the primary side from causing the common mode level to be too large due to the different grounds of the primary and secondary sides, thereby damaging the devices on the secondary side. In addition, by clamping the common mode level, the risk of abnormality of the signal transmitted from the primary side to the secondary side is reduced.

[0126] In some embodiments, the clamping module 30 is configured to adjust the common mode level of the second positive signal and the second negative signal when the absolute value of the common mode level of the second positive signal and the second negative signal is greater than a preset level threshold.

[0127] The preset level threshold can be less than or equal to the voltage withstand value of the device in the receiving module 40. When there are multiple devices in the receiving module 40, the preset level threshold can be less than or equal to the voltage withstand value of the self-checking device with the worst voltage withstand performance.

[0128] Regardless of whether the common mode level is a positive common mode level or a negative common mode level, when the absolute value of the common mode level is greater than the preset level threshold, the common mode level of the second positive signal and the second negative signal is adjusted to be less than or equal to the preset level threshold. In this way, it can be ensured that the device in the receiving module 40 will not be damaged due to the common mode level, and it can also be ensured that the signal received by the receiving module 40 and the signal output by the receiving module 40 are both normal.

[0129] In some embodiments, the clamping module 30 is configured to adjust the common mode level clamping amount according to the second positive signal and the second negative signal, and adjust the common mode level of the second positive signal and the second negative signal according to the common mode level clamping amount.

[0130] That is, the clamping amount is determined according to the second positive signal and the second negative signal. When the absolute value of the common mode level carried by the second positive signal and the second negative signal is greater, the clamping amount can be greater. When the absolute value of the common mode level carried by the second positive signal and the second negative signal is smaller, the clamping amount can be smaller.

[0131] Adjusting the common mode level of the second positive signal and the second negative signal according to the clamping amount means reducing the absolute value of the common mode level according to the clamping amount. The clamping amount can be understood as a voltage value, which is negative for a positive common mode level. For a negative common mode level, the voltage value is positive.

[0132] Referring to FIG. 7, in an embodiment of the present application, the clamping module 30 includes a trigger circuit 31 and a discharge circuit 32.

[0133] The first input end of the trigger circuit 31 receives the second positive signal, and the second input end of the trigger circuit 31 receives the second negative signal. The trigger circuit 31 is configured to output a trigger signal.

[0134] The control end of the discharge circuit 32 is connected to the output end of the trigger circuit 31, the first end of the discharge circuit 32 receives the second positive signal, the second end of the discharge circuit 32 receives the second negative signal, and the third end of the discharge circuit 32 is connected to the first power supply end. The first power supply end can be a ground end (VSS shown in FIG. 7) or a low-voltage power supply end, where low voltage refers to a voltage less than the common-mode voltage when the common-mode voltage is positive.

[0135] The second positive signal can be discharged from the discharge path formed from the first end to the third end of the discharge circuit 32, or from the discharge path formed from the third end to the first end of the discharge circuit 32. The discharge circuit 32 controls the amount of charge discharged between the first end and the third end of the discharge circuit 32 according to the trigger signal.

[0136] The second negative signal can be discharged from the discharge path formed from the second end to the third end of the discharge circuit 32, or from the discharge path formed from the third end to the second end of the discharge circuit 32. The discharge circuit 32 controls the amount of charge discharged between the second end and the third end of the discharge circuit 32 according to the trigger signal.

[0137] Specifically, when the second positive signal and the second negative signal both carry positive common-mode voltages, the second positive signal is discharged from the discharge path formed from the first end to the third end of the discharge circuit 32, and the second negative signal is discharged from the discharge path formed from the second end to the third end of the discharge circuit 32.

[0138] Specifically, when the second positive signal and the second negative signal both carry negative common-mode voltages, the second positive signal is discharged from the discharge path formed from the third end to the first end of the discharge circuit 32, and the second negative signal is discharged from the discharge path formed from the third end to the second end of the discharge circuit 32.

[0139] The trigger signal is generated when the second positive signal and the second negative signal are input, and is positively related to the absolute value of the common-mode voltage carried by the second positive signal and the second negative signal. The trigger signal is used to trigger the discharge of the common-mode voltage by the discharge circuit 32. The higher the absolute value of the common-mode voltage, the higher the level of the trigger signal, the greater the amount of charge discharged between the first end and the third end of the discharge circuit 32, and the greater the amount of charge discharged between the second end and the third end of the discharge circuit 32. The smaller the absolute value of the common-mode voltage, the lower the level of the trigger signal, the smaller the amount of charge discharged between the first end and the third end of the discharge circuit 32, and the smaller the amount of charge discharged between the second end and the third end of the discharge circuit 32.

[0140] In some embodiments, the device between the first end and the third end and the device between the second end and the third end can be configured to have the same structure.

[0141] Thus, for the positive common mode level, since the devices between the first end and the third end and the devices between the second end and the third end are of the same structure, the charge discharge amount corresponding to the discharge path from the first end to the third end is the same as the charge discharge amount corresponding to the discharge path from the second end to the third end. And since the discharge paths from the first end to the third end and from the second end to the third end are formed at the same time under the control of the trigger signal, the positive common mode level carried by the second positive signal and the positive common mode level carried by the second negative signal can be clamped at the same time and in the same amount.

[0142] For the negative common mode level, since the devices between the first end and the third end and the devices between the second end and the third end are of the same structure, the charge discharge amount corresponding to the discharge path from the third end to the first end is the same as the charge discharge amount corresponding to the discharge path from the third end to the second end. And since the discharge paths from the third end to the first end and from the third end to the second end are formed at the same time under the control of the trigger signal, the negative common mode level carried by the second positive signal and the negative common mode level carried by the second negative signal can be clamped at the same time and in the same amount.

[0143] The clamping module 30 provided by the embodiment receives the second positive signal and the second negative signal through the trigger circuit 31 and outputs a trigger signal to the discharge circuit 32. The discharge circuit 32 controls the charge discharge amount according to the trigger signal and discharges the common mode levels of the second positive signal and the second negative signal based on the charge discharge amount. By discharging the common mode levels through the discharge circuit 32, the problem of the absolute value of the common mode level being too large is effectively inhibited, and the devices in the receiving circuit are prevented from being damaged. Moreover, since the same trigger signal is used to control the discharge of the common mode levels of the second positive signal and the second negative signal, the common mode level carried by the second positive signal and the common mode level carried by the second negative signal are clamped at the same time and in the same amount.

[0144] In some embodiments, when a positive common mode level is formed, that is, when the common mode levels of the second positive signal and the second negative signal are greater than the voltage of the first power terminal, the discharge circuit 32 forms a discharge path from the first end to the third end. Correspondingly, the common mode level flows from the first end to the third end. Since the third end is connected to the first power terminal, which is a low-voltage terminal (for example, a ground terminal), the common mode level can flow to the low-voltage terminal (for example, the ground terminal), thereby discharging the common mode level and achieving the effect of clamping the common mode level.

[0145] When a positive common mode level is formed, the discharge circuit 32 also forms a discharge path from the second end to the third end. Correspondingly, the common mode level flows from the second end to the third end. Since the third end is connected to the first power terminal, which is a low-voltage terminal (for example, a ground terminal), the common mode level can flow to the low-voltage terminal (for example, the ground terminal), thereby discharging the common mode level and achieving the effect of clamping the common mode level.

[0146] In some embodiments, when a negative common mode level is formed, i.e., the common mode level of the second positive signal and the second negative signal is less than the voltage of the first power terminal, the bleed circuit 32 forms a bleed path from the third terminal to the first terminal. Correspondingly, the common mode level flows from the third terminal connected to the first power terminal to the first terminal, i.e., from the low voltage terminal (such as the ground terminal) to the output terminal of the isolation module 20, thereby suppressing the negative common mode level. The common mode level is discharged into the second positive signal, achieving the effect of clamping the common mode level.

[0147] When a negative common mode level is formed, the bleed circuit 32 also forms a bleed path from the third terminal to the second terminal. Correspondingly, the common mode level flows from the third terminal connected to the first power terminal to the second terminal, i.e., from the low voltage terminal (such as the ground terminal) to the output terminal of the isolation module 20, thereby suppressing the negative common mode level. The common mode level is discharged into the second negative signal, achieving the effect of clamping the common mode level.

[0148] Please refer to FIG. 8, in an embodiment of the present application, the bleed circuit 32 includes a first transistor MA1 and a second transistor MA2. The first transistor MA1 and the second transistor MA2 can be Metal-Oxide-Semiconductor (MOS) transistors as shown in FIG. 8.

[0149] The control terminal of the first transistor MA1 is connected to the control terminal of the second transistor MA2. As shown in FIG. 8, the gate of the first transistor MA1 is connected to the gate of the second transistor MA2, and the gate is the control terminal. The first transistor MA1 and the second transistor MA2 shown in the figure are both NMOS transistors, and in actual use, they can also be replaced by PMOS transistors as long as they can achieve common mode level discharge. However, it should be emphasized that the first transistor MA1 and the second transistor MA2 are of the same size, so as to ensure that the charge discharge amount of the first transistor MA1 and the second transistor MA2 is the same.

[0150] The control terminal of the first transistor MA1 and the control terminal of the second transistor MA2 both receive the trigger signal. As shown in FIG. 8, the gate of the first transistor MA1 and the gate of the second transistor MA2 simultaneously receive the trigger signal, and the first transistor MA1 and the second transistor MA2 are simultaneously triggered to be turned on, and the common mode level carried by the second positive signal and the second negative signal is simultaneously discharged.

[0151] The first end of the first transistor MA1 is the first end of the bleed circuit 32, that is, the first end of the first transistor MA1 receives the second positive signal (INPUT+). The second end of the first transistor MA1 is connected to the first power supply end, which is VSS as shown in FIG. 8. When forming a positive common mode level, as shown in FIG. 8, the first end of the first transistor MA1 is the drain, and the second end of the first transistor MA1 is the source. When the positive common mode level is formed, the first transistor MA1 is turned on, and the positive common mode level flows into the first power supply end, achieving the effect of clamping the common mode level. When forming a negative common mode level, the first end of the first transistor MA1 is the source, and the second end of the first transistor MA1 is the drain. When the negative common mode level is formed, the first transistor MA1 is turned on, and the negative common mode level flows from the first power supply end to the output end of the isolation module 20, achieving the effect of clamping the common mode level.

[0152] The first end of the second transistor MA2 is the second end of the bleed circuit 32, that is, the second end of the second transistor MA2 receives the second negative signal (INPUT-). The second end of the second transistor MA2 is connected to the first power supply end, which is VSS as shown in FIG. 8. When forming a positive common mode level, as shown in FIG. 8, the first end of the second transistor MA2 is the drain, and the second end of the second transistor MA2 is the source. When the positive common mode level is formed, the second transistor MA2 is turned on, and the positive common mode level flows into the first power supply end, achieving the effect of clamping the common mode level. When forming a negative common mode level, the first end of the first transistor MA1 is the source, and the second end of the first transistor MA1 is the drain. When the negative common mode level is formed, the second transistor MA2 is turned on, and the negative common mode level flows from the first power supply end to the second negative signal, achieving the effect of clamping the common mode level.

[0153] It should be emphasized that the first transistor MA1 and the second transistor MA2 have the same conduction conditions, the same conduction time, and the same charge bleed amount.

[0154] The bleed circuit 32 provided in this embodiment can make the common mode level be bled by setting a transistor that can switch the source and the drain. Specifically, the trigger signal controls the first transistor MA1 and the second transistor MA2 to be turned on at the same time, and the common mode level carried by the second positive signal and the second negative signal is bled at the same time. For both positive common mode levels and negative common mode levels, the effect of clamping the common mode level can be achieved.

[0155] Please also refer to FIG. 8, in some embodiments, the first transistor MA1 and the second transistor MA2 are formed based on the same substrate. The purpose of doing so is to support that the first transistor MA1 or the second transistor MA2 can switch the source and the drain. The first transistor MA1 can switch the current source to the drain and switch the current drain to the source. Similarly, the second transistor MA2 can switch the current source to the drain and switch the current drain to the source.

[0156] In some embodiments, please refer to the example of FIG. 8, the trigger circuit 31 includes a first voltage dividing circuit 310 and a second voltage dividing circuit 320.

[0157] The first end of the first voltage dividing circuit 310 receives the second forward signal, and the second end of the first voltage dividing circuit 310 is connected to the second end of the second voltage dividing circuit 320. The second end of the first voltage dividing circuit 310 is used to output the trigger signal. The third end of the first voltage dividing circuit 310 is connected to the first power supply end.

[0158] The first end of the second voltage dividing circuit 320 receives the second reverse signal, and the third end of the second voltage dividing circuit 320 is connected to the first power supply end.

[0159] The first voltage dividing circuit 310 is used to divide the second forward signal, and the second voltage dividing circuit 320 is used to divide the second reverse signal. The trigger signal is formed when the first voltage dividing circuit 310 divides the second forward signal and the second voltage dividing circuit 320 divides the second reverse signal. The second forward signal and the second reverse signal are input at the same time, and the trigger signal is formed when the second forward signal and the second reverse signal are divided after being input.

[0160] The first voltage dividing circuit 310 and the second voltage dividing circuit 320 have the same voltage dividing capability. The first voltage dividing circuit 310 and the second voltage dividing circuit 320 can be provided with voltage dividing resistors or other voltage dividing devices. The voltage dividing resistors or other voltage dividing devices provided should meet the requirement that the first voltage dividing circuit 310 and the second voltage dividing circuit 320 have the same voltage dividing capability.

[0161] In some embodiments, please refer to FIG. 8, the first voltage dividing circuit 310 includes a first resistor RA1 and a second resistor RA2. The second voltage dividing circuit 320 includes a third resistor RA3 and a fourth resistor RA4.

[0162] The first end of the first resistor RA1 is the first end of the first voltage divider circuit 310, and the second end of the first resistor RA1 is connected to the first end of the second resistor RA2. The second end of the first resistor RA1 is the second end of the first voltage divider circuit 310. The second end of the second resistor RA2 is the third end of the first voltage divider circuit 310. As shown in FIG. 8, the first end of the first resistor RA1 receives the second positive signal, and the second end of the second resistor RA2 is connected to the first power terminal.

[0163] The first end of the third resistor RA3 is the first end of the second voltage divider circuit 320, the second end of the third resistor RA3 is connected to the first end of the fourth resistor RA4, the second end of the third resistor RA3 is the second end of the second voltage divider circuit 320, and the second end of the fourth resistor RA4 is the third end of the second voltage divider circuit 320. As shown in FIG. 8, the first end of the third resistor RA3 receives the second negative signal, and the second end of the fourth resistor RA4 is connected to the first power terminal.

[0164] The resistance values of the first resistor RA1 and the second resistor RA2 can be different. The resistance values of the third resistor RA3 and the fourth resistor RA4 can be different.

[0165] When the first transistor MA1 and the second transistor MA2 are the same, the first resistor RA1 and the third resistor RA3 should be the same, and the second resistor RA2 and the fourth resistor RA4 should be the same.

[0166] When a positive common mode level is generated, the first resistor RA1 and the second resistor RA2 divide the voltage, and the third resistor RA3 and the fourth resistor RA4 divide the voltage, so that the gate voltage of the first transistor MA1 and the gate voltage of the second transistor MA2 are both raised. At this time, the common mode current corresponding to the common mode level flows to the first power terminal (for example, the ground terminal), clamping the common mode level.

[0167] When a negative common mode level is generated, the original source of the first transistor MA1 is switched to the drain, and the original drain is switched to the source. At this time, the common mode current corresponding to the common mode level flows from the first power terminal (for example, the ground terminal) to the second positive signal. Similarly, the original source of the second transistor MA2 is switched to the drain, and the original drain is switched to the source. At this time, the common mode current corresponding to the common mode level flows from the first power terminal (for example, the ground terminal) to the second negative signal.

[0168] In some optional embodiments, the first voltage divider circuit 310 can further include additional resistors, and the second voltage divider circuit 320 can also include additional resistors. If the first voltage divider circuit 310 includes additional resistors, the second voltage divider circuit 320 also needs to include additional resistors, and the resistance values of the additional resistors included in the first voltage divider circuit 310 and the second voltage divider circuit 320 should be the same. In addition, the connection positions of the additional resistors should be corresponding.

[0169] The connection position of the added resistor is corresponding, for example, in the first voltage division circuit 310, the first end of the added resistor is connected to the first end of the first resistor RA1, and the second end of the added resistor receives the second positive signal. Then, in the second voltage division circuit 320, a resistor with the same resistance value is added, the first end of the added resistor is connected to the first end of the third resistor RA3, and the second end of the added resistor receives the second negative signal.

[0170] The voltage division circuit provided in the embodiment includes the first voltage division circuit 310 and the second voltage division circuit 320. The first voltage division circuit 310 includes the first resistor RA1 and the second resistor RA2, and the second voltage division circuit 320 includes the third circuit and the fourth resistor RA4. When a positive common mode level is generated, the common mode current corresponding to the common mode level flows to the first power supply end through the first transistor MA1 and the second transistor MA2, achieving the effect of clamping the common mode level. When a negative common mode level is generated, the common mode current flows to the output end of the isolation module 20 through the first transistor MA1 and the second transistor MA2, achieving the effect of clamping the common mode level.

[0171] In some embodiments, referring to FIG. 9, the signal receiving circuit 41 includes a front-stage differential amplification circuit 43. The input end of the front-stage differential amplification circuit 43 is connected to the output end of the isolation module 20, and is used to amplify and output a third differential signal after amplifying the second differential signal.

[0172] The reason why the signal receiving circuit 41 amplifies the first differential signal is that, due to the influence of the isolation module 20 and related parasitic parameters (such as parasitic parameters of isolation capacitors and parasitic parameters of power devices), the amplitude of the second differential signal output by the isolation module 20 after the first differential signal at the input end of the isolation module 20 is transmitted to the output end is greatly attenuated, and the second differential signal may not be able to be normally processed in the next step. Therefore, the attenuated second differential signal can be amplified first, so that subsequent devices can be recognized.

[0173] The front-stage differential amplification circuit 43 compares the voltages of differential signals, thereby reducing the interference of common mode levels on signals.

[0174] The front-stage differential amplification circuit 43 can include a transistor, and the transistor is used to amplify the second differential signal by using the amplification function of the transistor.

[0175] The signal receiving circuit 41 provided in the embodiment includes the front-stage differential amplification circuit 43, and the front-stage differential amplification circuit 43 is used to differentially amplify the second differential signal, that is, to amplify the differential signal transmitted by the isolation module 20, so that the differential signal can be recognized by subsequent circuits, and the transmission effect of the signal is further improved.

[0176] In some embodiments, referring to FIG. 10 and FIG. 14, the front-stage differential amplification circuit 43 includes a first amplification circuit 411 shown in FIG. 10 and a second amplification circuit 412 shown in FIG. 14. The first amplification circuit 411 outputs a third positive signal, and the second amplification circuit 412 outputs a third negative signal. It should be noted that IN+ shown in FIG. 10 and FIG. 14 represents the second positive signal after common-mode level clamping, and IN- represents the second negative signal after common-mode level clamping.

[0177] Specifically, the first input end of the first amplification circuit 411 receives the second negative signal (IN- shown in FIG. 10), and the second input end of the first amplification circuit 411 receives the second positive signal (IN+ shown in FIG. 10). The first amplification circuit 411 is configured to generate a third positive signal (OUTA+ shown in FIG. 10) according to the difference between the second negative signal and the second positive signal.

[0178] Specifically, the first input end of the second amplification circuit 412 receives the second positive signal (IN+ shown in FIG. 14), and the second input end of the second amplification circuit 412 receives the second negative signal (IN- shown in FIG. 14). The second amplification circuit 412 is configured to generate a third negative signal (OUTA- shown in FIG. 14) according to the difference between the second positive signal and the second negative signal.

[0179] In an example, the first amplification circuit 411 and the second amplification circuit 412 have the same structure.

[0180] The first amplification circuit 411 is described in detail below.

[0181] The first amplification circuit 411 can be provided with a one-stage amplification sub-circuit or a multi-stage amplification sub-circuit, and the second amplification circuit 412 can also be provided with a one-stage amplification sub-circuit or a multi-stage amplification sub-circuit. However, the amplification degrees of the first amplification circuit 411 and the second amplification circuit 412 need to be the same.

[0182] In some embodiments, the first amplification circuit 411 includes a first-stage sub-circuit 413. The first input end of the first-stage sub-circuit 413 receives the second positive signal, and the second input end of the first-stage sub-circuit 413 receives the second negative signal. The first-stage sub-circuit 413 generates a third positive signal according to the second positive signal and the second negative signal, specifically, according to the difference between the second positive signal and the second negative signal.

[0183] In some embodiments, the first amplification circuit 411 can also include more stages of sub-circuits, which can be set according to actual signal amplification requirements.

[0184] The second amplification circuit 412 is described in detail as follows.

[0185] The second amplification circuit 412 can be provided with one-stage or multi-stage amplification sub-circuits. However, the amplification degrees of the first amplification circuit 411 and the second amplification circuit 412 need to be the same.

[0186] In some embodiments, the second amplification circuit 412 includes a first-stage sub-circuit 413. The first input end of the first-stage sub-circuit 413 receives the second positive signal, and the second input end of the first-stage sub-circuit 413 receives the second negative signal. The first-stage sub-circuit 413 generates a third negative signal according to the second positive signal and the second negative signal, specifically, generates the third negative signal according to the voltage difference between the second positive signal and the second negative signal.

[0187] In some embodiments, the first amplification circuit 411 can further include more-stage sub-circuits, which can be set according to actual signal amplification requirements.

[0188] In the above, the front-stage differential amplification circuit 43 provided by the embodiment includes the first amplification circuit 411 and the second amplification circuit 412. The first amplification circuit 411 is used to generate a third positive signal according to the voltage difference between the second negative signal and the second positive signal. The second amplification circuit 412 is used to generate a third negative signal according to the voltage difference between the second positive signal and the second negative signal. The third differential signal output by the front-stage differential amplification circuit 43 includes the third positive signal and the third negative signal. By amplifying the second differential signal through the front-stage differential amplification circuit 43, the signal strength can be effectively improved, so that the differential signal can be recognized by the subsequent circuit.

[0189] The first amplification circuit 411 containing different numbers of sub-circuits is described in detail as follows.

[0190] The first case: the first amplification circuit 411 only contains the first-stage sub-circuit 413.

[0191] Please refer to FIG. 10. At this time, the first-stage sub-circuit 413 can include a third pull-up circuit 423 and a third pull-down circuit 424.

[0192] The first end of the third pull-up circuit 423 is connected to a power supply end (such as VCC shown in FIG. 10), and the second end of the third pull-up circuit 423 is connected to the first end of the third pull-down circuit 424.

[0193] The control end of the third pull-down circuit 424 receives the second negative signal, and the second end of the third pull-down circuit 424 receives the second positive signal. The first end of the third pull-down circuit 424 outputs the third positive signal.

[0194] The third pull-down circuit 424 adjusts the downward driving capability of the second positive signal to the first end of the third pull-down circuit 424 under the control of the second negative signal.

[0195] The third pull-up circuit 423 is used to amplify the voltage difference signal output by the third pull-down circuit 424, which is the amplified signal of the voltage difference between the second negative signal and the second positive signal.

[0196] As shown in FIG. 10, the third pull-down circuit 424 includes a first capacitor CB1 and a third transistor MB1.

[0197] The first end of the first capacitor CB1 receives the second negative signal, and the second end is connected to the control end of the third transistor MB1. The first end of the first capacitor CB1 is the first end of the third pull-down circuit 424.

[0198] The first end of the third transistor MB1 is connected to the second end of the third pull-up circuit 423. The second end of the third transistor MB1 receives the second positive signal. The control end of the third transistor MB1 is connected to the second end of the first capacitor CB1. The third transistor MB1 can be an NMOS transistor as shown in FIG. 10, the gate (control end) of which is connected to the second end of the first capacitor CB1, the source receives the second positive signal, and the drain is connected to the second end of the third pull-up circuit 423.

[0199] The third transistor MB1 outputs the difference between the second negative signal and the second positive signal when it is turned on.

[0200] Referring also to FIG. 10, the third pull-up circuit 423 includes a transistor (MB2 as shown in FIG. 10) and a capacitor (CB2 as shown in FIG. 10). The first end of the capacitor is connected to the power supply end, and the second end is connected to the control end of the transistor. The first end of the transistor is connected to the power supply end and the first end of the capacitor, and the second end of the transistor is connected to the first end of the third transistor MB1.

[0201] The transistor can be a PMOS transistor as shown in FIG. 10, the first end of which is the source, and the second end of which is the drain.

[0202] When the transistor is turned on, the third pull-up circuit 423 outputs a stable voltage signal, which is used to amplify the voltage difference signal output by the third transistor MB1.

[0203] The third pull-up circuit 423 can also be provided with a resistor RB1 as shown in FIG. 10, which acts as a load, further enhancing the amplification effect of the voltage difference signal.

[0204] Please refer to FIG. 11, in some embodiments, the third pull-down circuit 424 further includes a second capacitor CB3 and a fourth transistor MB3.

[0205] The first end of the second capacitor CB3 receives the second negative signal, and the second end is connected to the control end of the fourth transistor MB3. The first end of the fourth transistor MB3 is connected to the first end of the third transistor MB1, and the second end receives the second positive signal.

[0206] After the fourth transistor MB3 is turned on, the voltage difference signal between the second negative signal and the second positive signal is amplified by the fourth transistor MB3 and input to the first end of the third transistor MB1. After the third transistor MB1 is turned on, the voltage difference signal between the second negative signal and the voltage difference signal output by the fourth transistor MB3 is output, and the third transistor MB1 further amplifies the voltage difference signal. That is, the second capacitor CB3 and the fourth transistor MB3 provided in the embodiment can further improve the amplification effect of the voltage difference signal.

[0207] The third transistor MB1 and the fourth transistor MB3 can both be NMOS tubes. The control end of the fourth transistor MB3 is the gate, the first end is the drain, and the second end is the source.

[0208] Please refer to FIG. 12, in some embodiments, the first-stage sub-circuit 413 further includes a preset voltage circuit 419.

[0209] The first end of the preset voltage circuit 419 receives the second negative signal, and the second end of the preset voltage circuit 419 is connected to the control end of the third pull-down circuit 424. The control end of the third pull-down circuit 424 is the control end of the fourth transistor MB3.

[0210] The preset voltage circuit 419 is used to generate a preset voltage at the control end of the third pull-down circuit 424 according to the second negative signal. The preset voltage output by the preset voltage circuit 419 is input to the gate of the fourth transistor MB3, so as to further improve the amplification effect of the voltage difference signal.

[0211] The preset voltage circuit 419 can include a fifth transistor MB4 and a sixth transistor MB5 (such as the transistor MB5 shown in FIG. 12). The control end of the fifth transistor MB4 is connected to the other end of the second capacitor CB3, the first end receives the second negative signal, and the second end is connected to the first end of the sixth transistor MB5. The control end of the sixth transistor MB5 is connected to the other end of the first capacitor CB1, and the second end is connected to the control end of the fourth transistor MB3.

[0212] The fifth transistor MB4 and the sixth transistor MB5 can be NMOS transistors. The gate of the fifth transistor MB4 is connected with the second end of the second capacitor CB3, the source receives the second negative signal, and the drain is connected with the source of the sixth transistor MB5. The gate of the sixth transistor MB5 is connected with the second end of the first capacitor CB1, and the drain is connected with the gate of the fourth transistor MB3.

[0213] In some optional embodiments, the preset voltage circuit 419 can further include a resistor RB2 and a current source A1 as shown in FIG. 12, and the current source A1 provides the required power for the resistor RB2. The current source A1 takes power from the power supply end VCC. The first end of the resistor RB2 is connected with the current source A1, and the second end is connected with the control end of the fourth transistor MB3. At this time, the signal input by the fourth transistor MB3 includes the signal output by the second end of the first capacitor CB1 and the signal output by the second end of the resistor RB2.

[0214] The design of the preset voltage circuit 419 provided by the embodiment can further improve the amplification effect of the voltage difference signal.

[0215] The second case: please refer to FIG. 13. The first amplification circuit 411 includes a first-stage sub-circuit 413 and a second-stage sub-circuit 414. The specific structure of the first amplification circuit 411 can be any of the structures shown above or a variant of any of the structures, which is not limited by the embodiment. At this time, the first amplification circuit 411 is used to output an intermediate signal, and the second-stage sub-circuit 414 is used to amplify the intermediate signal and output a third positive signal.

[0216] Please refer to FIG. 13. The input end of the second-stage sub-circuit 414 is connected with the output end of the first-stage sub-circuit 413, and the second-stage sub-circuit 414 is used to amplify the signal output by the first-stage sub-circuit 413 and output the third positive signal.

[0217] The second-stage sub-circuit 414 includes a second pull-up circuit 421 and a second pull-down circuit 422. The first end of the second pull-up circuit 421 is connected with a power supply end (such as VSS shown in FIG. 13), and the second end of the second pull-up circuit 421 is connected with the first end of the third pull-down circuit 424. The second end of the second pull-down circuit 422 is connected with a second power supply end (such as A3 shown in FIG. 13).

[0218] The control end of the second pull-down circuit 422 receives the signal output by the first-stage sub-circuit 413. The first end of the second pull-down circuit 422 outputs the third positive signal.

[0219] The second pull-down circuit 422 adjusts the downward driving capability of the second power supply end to the second end of the second pull-down circuit 422 under the control of the second negative signal, and the first end of the second pull-down circuit 422 outputs the third positive signal.

[0220] In some embodiments, the second pull-down circuit 422 includes a seventh transistor MB6. The second pull-up circuit 421 includes an eighth transistor MB7 and a third capacitor CB4. The control end of the seventh transistor MB6 is the control end of the second pull-down circuit 422, which receives the signal output by the first-stage sub-circuit 413. The first end of the seventh transistor MB6 is connected to the second power supply end, and the second end is connected to the first end of the eighth transistor MB7. The control end of the eighth transistor MB7 is connected to the first end of the third capacitor CB4, and the second end is connected to the power supply end. The second end of the third capacitor CB4 is connected to the power supply end.

[0221] The seventh transistor MB6 can be an NMOS tube as shown in FIG. 13, the gate is the control end, the source is the second end, and the drain is the second end. The eighth transistor MB7 can be a PMOS tube as shown in FIG. 13, the gate is the control end, the drain is the first end, and the source is the second end.

[0222] A resistor RB3 as shown in FIG. 13 can also be provided to further improve the amplification effect of the voltage difference signal.

[0223] When the first amplification circuit 411 provided by the embodiment includes the first-stage sub-circuit 413 and the second-stage sub-circuit 414, the voltage difference signal between the second positive signal and the second negative signal is amplified once by the first-stage sub-circuit 413, and the voltage difference signal amplified by the first-stage sub-circuit 413 is amplified again by the second-stage sub-circuit 414, further improving the amplification effect of the voltage difference signal.

[0224] The following will be described in detail with respect to the case that the second amplification circuit 412 includes different numbers of sub-circuits.

[0225] The first case: please refer to FIG. 14, the second amplification circuit 412 only includes a third-stage sub-circuit 415.

[0226] Please refer to FIG. 14, at this time, the third-stage sub-circuit 415 can include a fourth pull-up circuit 425 and a fourth pull-down circuit 426.

[0227] The first end of the fourth pull-up circuit 425 is connected to the power supply end (such as VCC shown in FIG. 14), and the second end of the fourth pull-up circuit 425 is connected to the first end of the fourth pull-down circuit 426.

[0228] The control end of the fourth pull-down circuit 426 receives the second forward signal, and the second end of the fourth pull-down circuit 426 receives the second reverse signal. The first end of the fourth pull-down circuit 426 outputs the third reverse signal.

[0229] The fourth pull-down circuit 426 adjusts the downward driving capability of the second forward signal to the first end of the fourth pull-down circuit 426 under the control of the second reverse signal.

[0230] The fourth pull-up circuit 425 is used to amplify the voltage difference signal output by the fourth pull-down circuit 426, which is the voltage difference signal of the second forward signal minus the second reverse signal.

[0231] As shown in FIG. 14, the fourth pull-down circuit 426 includes a fourth capacitor CB5 and a ninth transistor MB8.

[0232] The first end of the fourth capacitor CB5 receives the second forward signal, and the second end is connected to the control end of the ninth transistor MB8. The first end of the fourth capacitor CB5 is the first end of the fourth pull-down circuit 426.

[0233] The first end of the ninth transistor MB8 is connected to the second end of the fourth pull-up circuit 425. The second end of the ninth transistor MB8 receives the second forward signal. The control end of the ninth transistor MB8 is connected to the second end of the fourth capacitor CB5. The ninth transistor MB8 can be an NMOS tube as shown in FIG. 14, the gate (control end) of which is connected to the second end of the fourth capacitor CB5, the source receives the second forward signal, and the drain is connected to the second end of the fourth pull-up circuit 425.

[0234] The ninth transistor MB8 outputs the voltage difference between the second reverse signal and the second forward signal when it is turned on.

[0235] Referring also to FIG. 14, the fourth pull-up circuit 425 includes a transistor MB9 and a capacitor CB6. The first end of the capacitor CB6 is connected to the power supply end, and the second end is connected to the control end of the transistor MB9. The first end of the transistor MB9 is connected to the power supply end and the first end of the capacitor CB6, and the second end of the transistor MB9 is connected to the first end of the third transistor MB1.

[0236] The transistor MB9 can be a PMOS tube as shown in FIG. 14, the first end of which is the source, and the second end of which is the drain.

[0237] When the transistor MB9 is turned on, the fourth pull-up circuit 425 outputs a stable voltage signal, which is used to amplify the voltage difference signal output by the ninth transistor MB8.

[0238] The fourth pull-up circuit 425 can also be provided with a resistor RB4 as shown in FIG. 14, where the RB4 functions as a load, and the effect is to further enhance the amplification of the voltage difference signal.

[0239] Referring to FIG. 15, in some embodiments, the fourth pull-down circuit 426 further includes a fifth capacitor CB7 and a tenth transistor MB10.

[0240] The first end of the fifth capacitor CB7 receives the second negative signal, and the second end is connected to the control end of the tenth transistor MB10. The first end of the tenth transistor MB10 is connected to the first end of the ninth transistor MB8, and the second end receives the second positive signal.

[0241] After the tenth transistor MB10 is turned on, the voltage difference signal between the second negative signal and the second positive signal is amplified by the tenth transistor MB10 and input to the first end of the ninth transistor MB8. After the ninth transistor MB8 is turned on, the voltage difference signal between the second negative signal and the voltage difference signal output by the tenth transistor MB10 is output, and the ninth transistor MB8 further amplifies the voltage difference signal. That is, the fifth capacitor CB7 and the tenth transistor MB10 provided in this embodiment can further enhance the amplification of the voltage difference signal.

[0242] The ninth transistor MB8 and the tenth transistor MB10 can both be NMOS transistors. The control end of the tenth transistor MB10 is the gate, the first end is the drain, and the second end is the source.

[0243] Referring to FIG. 16, in some embodiments, the third-stage sub-circuit 415 further includes another preset voltage circuit 430.

[0244] The first end of the another preset voltage circuit 430 receives the second positive signal, and the second end of the another preset voltage circuit 430 is connected to the control end of the third pull-down circuit 424. The control end of the third pull-down circuit 424 is the control end of the tenth transistor MB10.

[0245] The another preset voltage circuit 430 is configured to generate a preset voltage at the control end of the third pull-down circuit 424 according to the second positive signal. The preset voltage output by the another preset voltage circuit 430 is input to the gate of the tenth transistor MB10, so as to further enhance the amplification of the voltage difference signal.

[0246] The another preset voltage circuit 430 can include an eleventh transistor MB11 and a twelfth transistor MB12. The control end of the eleventh transistor MB11 is connected to the other end of the fifth capacitor CB7, the first end receives the second positive signal, and the second end is connected to the first end of the twelfth transistor MB12. The control end of the twelfth transistor MB12 is connected to the other end of the fourth capacitor CB5, and the second end is connected to the control end of the tenth transistor MB10.

[0247] The eleventh transistor MB11 and the twelfth transistor MB12 can both be NMOS tubes. The gate of the eleventh transistor MB11 is connected to the second end of the fifth capacitor CB7, the source receives the second negative signal, and the drain is connected to the source of the eleventh transistor MB12. The gate of the twelfth transistor MB12 is connected to the second end of the fourth capacitor CB5, and the drain is connected to the gate of the tenth transistor MB10.

[0248] In some optional embodiments, a resistor RB5 and a current source A2 as shown in FIG. 16 can also be provided. The current source A2 in the figure provides the required electrical energy for the branch where the resistor RB5 is located. The current source A2 takes electricity from the power supply end VCC. The first end of the resistor RB5 is connected to the current source A2, and the second end is connected to the control end of the tenth transistor MB10. At this time, the signal input by the tenth transistor MB10 includes the signal output by the second end of the first capacitor CB1 and the signal output by the second end of the resistor RB5. The resistor RB5 is provided to amplify the amplification multiple of the voltage difference signal.

[0249] The design of the another preset voltage circuit 430 provided in the embodiment can further improve the amplification effect of the voltage difference signal.

[0250] The second case: the second amplification circuit 412 includes a third-level sub-circuit 415 and a fourth-level sub-circuit 416. The specific structure of the second amplification circuit 412 can be any of the structures shown above or a variation of any of the structures, which is not limited in the embodiment. At this time, the signal output by the second amplification circuit 412 is not the third negative signal, and the fourth-level sub-circuit 416 outputs the third negative signal.

[0251] Please refer to FIG. 17. The input end of the fourth-level sub-circuit 416 is connected to the output end of the third-level sub-circuit 415. The fourth-level sub-circuit 416 is used to amplify the signal output by the third-level sub-circuit 415 and output the third positive signal.

[0252] The fourth-stage sub-circuit 416 includes a fifth pull-up circuit 427 and a fifth pull-down circuit 428. The first end of the fifth pull-up circuit 427 is connected to a power supply end (VSS shown in FIG. 17), and the second end of the fifth pull-up circuit 427 is connected to the first end of the fifth pull-down circuit 428. The second end of the fifth pull-down circuit 428 is connected to a second power supply end (A3 shown in FIG. 17). The second power supply end is used to make the voltage difference signal more differential.

[0253] The control end of the fifth pull-down circuit 428 receives the signal output by the third-stage sub-circuit 415. The first end of the fifth pull-down circuit 428 outputs a third positive signal.

[0254] The fifth pull-down circuit 428 adjusts the downward driving capability of the second power supply end to the second end of the fifth pull-down circuit 428 under the control of the second positive signal, and the first end of the fifth pull-down circuit 428 outputs the third negative signal.

[0255] In some embodiments, the fifth pull-down circuit 428 includes a thirteenth transistor MB13. The fifth pull-up circuit 427 includes a fourteenth transistor MB14 and a sixth capacitor CB8. The control end of the thirteenth transistor MB13 is the control end of the fifth pull-down circuit 428, and receives the signal output by the third-stage sub-circuit 415. The first end of the thirteenth transistor MB13 is connected to the second power supply end, and the second end is connected to the first end of the fourteenth transistor MB14. The control end of the fourteenth transistor MB14 is connected to the first end of the sixth capacitor CB8, and the second end is connected to the power supply end. The second end of the sixth capacitor CB8 is connected to the power supply end.

[0256] The thirteenth transistor MB13 can be an NMOS tube as shown in FIG. 17, the gate is the control end, the source is the second end, and the drain is the second end. The fourteenth transistor MB14 can be a PMOS tube as shown in FIG. 17, the gate is the control end, the drain is the first end, and the source is the second end.

[0257] A resistor RB6 as shown in FIG. 17 can also be provided to further improve the amplification effect of the voltage difference signal.

[0258] When the second amplification circuit 412 provided by the embodiment includes the third-stage sub-circuit 415 and the fourth-stage sub-circuit 416, the voltage difference signal between the second positive signal and the second negative signal is amplified once by the third-stage sub-circuit 415, and the voltage difference signal amplified by the third-stage sub-circuit 415 is amplified again by the fourth-stage sub-circuit 416, further improving the amplification effect of the voltage difference signal.

[0259] Please refer to FIG. 18. The signal transmission circuit 10 provided by one embodiment of the present application further includes an input module 50.

[0260] The input end of the input module 50 receives an input signal, and the output end of the input module 50 is connected to the isolation module 20 and outputs the first differential signal after modulating the input signal.

[0261] The input signal can be a square wave pulse signal as shown in FIG. 19. The input module 50 can include an oscillator 51 and a logic circuit 52 as shown in FIG. 18.

[0262] If the input signal is a square wave pulse signal as shown in FIG. 19, the oscillator 51 is used to output a continuous and high-frequency oscillation signal as shown in FIG. 20. The oscillator 51 can be a ring oscillator 51 or the like. The signal frequency of the oscillator 51 can be adjusted according to the internal resistance and capacitance, etc. The signal frequency of the input signal is lower than the signal frequency of the oscillator 51 signal, and the pulse width is at least 2 periods of the oscillator 51 signal or more, so as to ensure the transmission of the signal.

[0263] The logic circuit 52 includes a logic AND gate circuit and a logic NOT gate circuit. After the input signal and the oscillation signal enter the logic circuit 52, a signal is output through the logic AND gate circuit, and a signal is output through the logic NOT gate circuit. The two signals are differential signals with close pulse widths. The logic circuit 52 outputs a differential signal as shown in FIG. 21. The differential signal shown in FIG. 21 is the aforementioned first differential signal. The first differential signal is input to the isolation module 20.

[0264] In some optional embodiments, the input module 50 can further include a driving circuit 53 as shown in FIG. 18, and the driving circuit 53 outputs the first differential signal. The first differential signal output by the driving circuit 53 has a waveform similar to that of the signal output by the logic circuit 52, and the main difference is the enhanced driving capability. The driving circuit 53 is used to further enhance the strength of the differential signal output by the logic circuit 52.

[0265] It should be noted that when the high-voltage isolation capacitor is designed in the isolation module 20, the high-voltage isolation capacitor can achieve very high voltage resistance, so that the transient disturbance on the secondary side can be prevented from being transmitted to the primary side, and the circuit in the input module 50 can be protected from damage. In addition, the input module 50 processes the input signal into a differential signal, and transmits the differential signal to the isolation module 20, so as to reduce the common-mode level interference.

[0266] Please refer to FIG. 22 and FIG. 23. In some embodiments of the present application, the signal transmission circuit further includes a filter circuit 44 as shown in FIG. 22.

[0267] The filter circuit 44 is used to filter the second differential signal output by the isolation module 20.

[0268] The filter circuit 44 can be a high-pass filter. As shown in FIG. 23, the filter circuit 44 includes a resistor R1 and a resistor R2. A first end of the resistor R1 receives the second positive signal, and a second end of the resistor R1 is grounded. A first end of the resistor R2 receives the second negative signal, and a second end of the resistor R2 is grounded. The resistor R1, the resistor R2, and the isolation capacitor in the isolation module 20 form a high-pass filter, which can greatly attenuate the interference of low-frequency signals.

[0269] It should be noted that the filter circuit 44 connected to the input end of the receiving module 40 must be matched in two signal channels to prevent signal failure.

[0270] The filter circuit 44 can be arranged between the isolation module 20 and the clamping module 30, or can be arranged at other positions according to actual needs, which is not limited in the embodiment.

[0271] The filter circuit 44 provided in the embodiment can also be other filters, as long as it can attenuate the interference of low-frequency signals.

[0272] Referring to FIG. 24, in some embodiments, the receiving module 40 further includes a delay circuit 47. An input end of the delay circuit 47 is connected to an output end of the signal outputter 42.

[0273] The delay circuit 47 is used to filter out abnormal signals in one signal output by the signal outputter 42 and output one signal. The delay circuit 47 can be a transistor delay circuit, or can be other types of delay circuits, which can be selected according to actual needs, and the embodiment is not limited.

[0274] The delay circuit 47 provided in the embodiment can improve the correctness of the output signal of the signal transmission circuit, and can also improve the anti-interference ability of the signal transmission circuit to a certain extent.

[0275] Referring to FIG. 25, some embodiments of the present application further provide a signal transmission system 60.

[0276] The signal transmission system 60 includes the signal transmission circuit 10 provided in any one of the above embodiments, and further includes a controller 61, a driving module 62, and a power device 63.

[0277] An output end of the controller 61 is connected to an input end of the signal transmission circuit 10. The controller 61 can be a microcontroller unit (MCU). The output signal of the controller 61 is a square wave pulse signal.

[0278] The input end of the driving module 62 is connected with the output end of the signal transmission circuit 10, and receives the single-channel signal output by the signal transmission circuit 10. Please refer to the above description of the single-channel signal output by the receiving module 40, and the single-channel signal output by the signal transmission circuit 10 is a square wave pulse signal. The driving module 62 is used for performing voltage boosting processing on the signal output by the signal transmission circuit 10 and then outputting the signal to the power device 63, so as to drive the power device 63 to operate. That is, the driving module 62 is used for further driving the square wave pulse signal to meet the use requirements of the power device 63.

[0279] The power device 63 is, for example, a silicon carbide power device, an Insulate-Gate Bipolar Transistor (IGBT for short).

[0280] The signal transmission system 60 provided by the embodiment can clamp the transient interference generated by the switching of the power device 63 by the signal transmission circuit 10, so as not to damage the signal transmission circuit 10. Compared with the existing signal transmission system 60, the safety is higher, and the practicability is stronger.

[0281] Please refer to FIG. 26, some embodiments of the present application further provide an electric control system 70 of a vehicle, the electric control system 70 comprising the signal transmission system 60 provided by any one of the above embodiments, and further comprising a load 71. The load 71 is, for example, a motor.

[0282] As shown in FIG. 26, the power device 63 can be an IGBT as shown in FIG. 26, and the IGBT is connected with a motor on the vehicle.

[0283] Some embodiments of the present application further provide a vehicle, as shown in FIG. 27, the vehicle 100 comprising the electric control system 70 of the vehicle as described above. The vehicle can further be provided with other functions, for example, a head-up display function, an adaptive cruise function, an active brake function, etc., which are not limited by the embodiment.

[0284] According to some embodiments of the present application, referring to FIG. 27, the vehicle 100 further comprises a battery 102 and a charger 101, the electric control system 70 is connected with the charger 101 and the battery 102, and the charger 101 is connected with the battery 102. The electric control system 70 can monitor the state of the battery 102, and control the charging parameter of the charger 101 according to the state of the battery 102, and the charger 101 charges the battery 102 according to the charging parameter.

[0285] For example, the electronic control system 70 may include a battery management system (BMS) for monitoring the state of the battery 101, such as voltage, current, temperature, and charging status. The battery management system may also communicate with the charger 101 to enable the charger 101 to adjust charging parameters.

[0286] The electronic control system may also include a vehicle control unit (VCU), which is responsible for the overall management and coordination of the vehicle, including powertrain control, energy management, regenerative braking, and thermal management. It may also include a motor controller, which controls the operation of the drive motors, including regulating current and voltage to control the motor's speed and torque.

[0287] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

A signal transmission circuit, wherein The application relates to an isolation module (20) and a receiving module (40), wherein the receiving module (40) comprises a signal receiving circuit (41) and a signal output device (42); the isolation module (20) is used for receiving a first differential signal, electrically isolating the first differential signal, and outputting a second differential signal; the signal receiving circuit (41) is connected with the output end of the isolation module (20), used for processing the second differential signal, and outputting a third differential signal; the signal output device (42) is connected with the output end of the signal receiving circuit (41), used for merging the third differential signal, and outputting a signal. The signal output device (42) comprises a signal merging circuit (45) and a signal inverting circuit (46); the input end of the signal merging circuit (45) is connected with the output end of the signal receiving circuit (41), used for inverting and merging the third differential signal into an initial signal; the input end of the signal inverting circuit (46) is connected with the output end of the signal merging circuit (45), used for inverting the initial signal and outputting a signal. The signal merging circuit (45) comprises a differential amplification circuit (440) and a merging sub-circuit (450); the input end of the differential amplification circuit (440) is connected with the output end of the signal receiving circuit (41), used for differentially amplifying and processing the third differential signal, and outputting a fourth differential signal; the input end of the merging sub-circuit (450) is connected with the output end of the differential amplification circuit (440), used for inverting and merging the fourth differential signal into the initial signal. The third differential signal comprises a third positive signal and a third negative signal, the fourth differential signal comprises a fourth positive signal and a fourth negative signal, and the differential amplification circuit (440) comprises a first signal input circuit (441) and a second signal input circuit (442); the first signal input circuit (441) is used for receiving the third positive signal and a positive trigger level, outputting the fourth positive signal to the merging sub-circuit (450) according to the third positive signal and the positive trigger level, and outputting a first combined signal of the third positive signal and the positive trigger level to the merging sub-circuit (450); the second signal input circuit (442) is used for receiving the third negative signal and a negative trigger level, outputting the fourth negative signal to the merging sub-circuit (450) according to the third negative signal and the negative trigger level, and outputting a second combined signal of the third negative signal and the negative trigger level to the merging sub-circuit (450). The positive trigger level and the negative trigger level are common-mode levels. The signal transmission circuit according to claim 1, wherein The merging sub-circuit (450) comprises a first switching circuit (451), a second switching circuit (452), and a merging unit (453). ​ ​ The signal transmission circuit according to claim 2, wherein ​ ​ ​ The signal transmission circuit according to claim 3, wherein ​ ​ ​ The signal transmission circuit according to claim 4, wherein ​ The signal transmission circuit according to claim 4 or 5, wherein ​ An input terminal of the first switch circuit (451) is connected with an output terminal of the first signal input circuit (441), for outputting a first path to-be-merged signal based on the first synthesis signal and the fourth positive signal when conducting under control of the first synthesis signal; An input terminal of the second switch circuit (452) is connected with an output terminal of the second signal input circuit (442), for outputting a second path to-be-merged signal based on the second synthesis signal and the fourth negative signal when conducting under control of the second synthesis signal; An input terminal of the merging unit (453) is connected with an output terminal of the first switch circuit (451) and an output terminal of the second switch circuit (452), for inversely merging the first path to-be-merged signal and the second path to-be-merged signal into one path initial signal. The first switch circuit (451) and the second switch circuit (452) are not simultaneously conducting or turned off. The signal transmission circuit according to claim 6, wherein The signal inverting circuit (46) comprises an inverting unit (460) and a control unit (461); An input terminal of the inverting unit (460) is connected with an output terminal of the merging unit (453), for outputting one path signal after inverting the one path initial signal under control of the control unit (461). The signal transmission circuit according to any one of claims 1 to 7, wherein The second differential signal comprises a second positive signal and a second negative signal, and the signal transmission circuit (10) further comprises: A clamping module (30) connected with an output terminal of the isolation module (20), for clamping a common mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal. The signal transmission circuit according to claim 8, wherein The clamping module (30) is configured to adjust the common mode level of the second positive signal and the second negative signal when an absolute value of the common mode level of the second positive signal and the second negative signal is greater than a preset level threshold. The signal transmission circuit according to claim 8 or 9, wherein The clamping module (30) is configured to adjust a common mode clamping amount according to the second positive signal and the second negative signal, and adjust the common mode level of the second positive signal and the second negative signal according to the common mode clamping amount. The signal transmission circuit according to any one of claims 8-10, wherein The clamping module (30) comprises a trigger circuit (31) and a bleeding circuit (32); A first input terminal of the trigger circuit (31) receives the second positive signal, a second input terminal of the trigger circuit (31) receives the second negative signal, and the trigger circuit (31) is configured to output a trigger signal; A control terminal of the bleeding circuit (32) is connected with an output terminal of the trigger circuit (31), a first terminal of the bleeding circuit (32) receives the second positive signal, a second terminal of the bleeding circuit (32) receives the second negative signal, and a third terminal of the bleeding circuit (32) is connected with a first power supply terminal, the bleeding circuit (32) controls a charge bleeding amount between the first terminal and the third terminal of the bleeding circuit (32) according to the trigger signal, and controls a charge bleeding amount between the second terminal and the third terminal of the bleeding circuit (32) according to the trigger signal. The signal transmission circuit according to claim 11, wherein The bleeding circuit (32) comprises a first transistor and a second transistor; The control end of the first transistor is connected to the control end of the second transistor, the control end of the first transistor and the control end of the second transistor both receive the trigger signal, the first end of the first transistor is the first end of the bleed circuit (32), the first end of the second transistor is the second end of the bleed circuit (32), and the second end of the first transistor and the second end of the second transistor are both connected to the first power supply end. The signal transmission circuit according to claim 11 or 12, wherein The first transistor and the second transistor are formed based on the same substrate. The signal transmission circuit according to any one of claims 11 to 13, wherein The trigger circuit (31) comprises a first voltage dividing circuit (310) and a second voltage dividing circuit (320). The first end of the first voltage dividing circuit (310) receives the second positive signal, the second end of the first voltage dividing circuit (310) is connected to the second end of the second voltage dividing circuit (320), and the second end of the first voltage dividing circuit (310) is used for outputting the trigger signal; the third end of the first voltage dividing circuit (310) is connected to the first power supply end. The first end of the second voltage dividing circuit (320) receives the second negative signal, and the third end of the second voltage dividing circuit (320) is connected to the first power supply end. The signal transmission circuit according to claim 14, wherein The first voltage dividing circuit (310) comprises a first resistor and a second resistor. The first end of the first resistor is the first end of the first voltage dividing circuit (310), the second end of the first resistor is connected to the first end of the second resistor, the second end of the first resistor is the second end of the first voltage dividing circuit (310), and the second end of the second resistor is the third end of the first voltage dividing circuit (310). The signal transmission circuit according to claim 14 or 15, wherein The second voltage dividing circuit (320) comprises a third resistor and a fourth resistor. The first end of the third resistor is the first end of the second voltage dividing circuit (320), the second end of the third resistor is connected to the first end of the fourth resistor, the second end of the third resistor is the third end of the second voltage dividing circuit (320), and the second end of the fourth resistor is the third end of the second voltage dividing circuit (320). The signal transmission circuit according to any one of claims 1 to 16, wherein The signal receiving circuit (41) comprises a front-stage differential amplification circuit (43). The input end of the front-stage differential amplification circuit (43) is connected to the output end of the isolation module (20), and the front-stage differential amplification circuit (43) is used for amplifying and processing the second differential signal to output a third differential signal. The signal transmission circuit according to claim 17, wherein The third differential signal comprises a third positive signal and a third negative signal, and the front-stage differential amplification circuit (43) comprises a first amplification circuit (411) and a second amplification circuit (412). The signal transmission circuit according to claim 18, wherein The first input end of the first amplification circuit (411) receives a second negative signal, the second input end of the first amplification circuit (411) receives a second positive signal, and the first amplification circuit (411) is used for generating the third positive signal according to the difference between the second negative signal and the second positive signal; A first input end of the second amplification circuit (412) receives the second positive signal, a second input end of the second amplification circuit (412) receives the second negative signal, and the second amplification circuit (412) is configured to generate the third negative signal according to a difference between the second positive signal and the second negative signal. The signal transmission circuit according to claim 18 or 19, wherein The first amplification circuit (411) and the second amplification circuit (412) have the same structure. The signal transmission circuit according to claim 19, wherein The first amplification circuit (411) comprises a first-stage sub-circuit (413). A first input end of the first-stage sub-circuit (413) receives the second positive signal, a second input end of the first-stage sub-circuit (413) receives the second negative signal, and the first-stage sub-circuit (413) is configured to generate a third positive signal according to the second positive signal and the second negative signal. The signal transmission circuit according to claim 21, wherein The first-stage sub-circuit (413) comprises a third pull-up circuit (423) and a third pull-down circuit (424), a first end of the third pull-up circuit (423) is connected to a power supply end, a second end of the third pull-up circuit (423) is connected to a first end of the third pull-down circuit (424), a control end of the third pull-down circuit (424) receives the second negative signal, and a second end of the third pull-down circuit (424) receives the second positive signal; the third pull-down circuit (424) adjusts a downward driving capability of the second positive signal to the first end of the third pull-down circuit (424) under the control of the second negative signal, and the first end of the third pull-down circuit (424) outputs the third positive signal. The signal transmission circuit according to claim 22, wherein The first-stage sub-circuit (413) further comprises a preset voltage circuit (419), a first end of the preset voltage circuit (419) receives the second negative signal, and a second end of the preset voltage circuit (419) is connected to the control end of the third pull-down circuit (424); the preset voltage circuit (419) is configured to generate a preset voltage at the control end of the third pull-down circuit (424) according to the second negative signal. The signal transmission circuit according to any one of claims 21 to 23, wherein The first amplification circuit (411) further comprises a second-stage sub-circuit (414). An input end of the second-stage sub-circuit (414) is connected to an output end of the first-stage sub-circuit (413), and the second-stage sub-circuit (414) is configured to output the third positive signal after amplifying a signal output by the first-stage sub-circuit (413). The signal transmission circuit according to claim 24, wherein The second-stage sub-circuit (414) comprises a second pull-up circuit (421) and a second pull-down circuit (422), a first end of the second pull-up circuit (421) is connected to a power supply end, a first end of the second pull-down circuit (422) is connected to a second end of the second pull-down circuit (422), a second end of the second pull-down circuit (422) is connected to a second power supply end, and a control end of the second pull-down circuit (422) receives a signal output by the first-stage sub-circuit (413); the second pull-down circuit (422) adjusts a downward driving capability of the second power supply end to the second end of the second pull-down circuit (422) under control of the second negative signal, and a first end of the second pull-down circuit (422) outputs the third positive signal. The signal transmission circuit according to any one of claims 1 to 25, wherein The signal transmission circuit (10) further comprises an input module (50); An input end of the input module (50) receives an input signal, an output end of the input module (50) is connected to the isolation module (20), and the input module (50) outputs the first differential signal after modulating the input signal; One of the signals output by the signal outputter (42) is in phase with the input signal received by the input module (50). The signal transmission circuit according to any one of claims 1 to 26, wherein The isolation module (20) is a capacitive isolation module (20). The signal transmission circuit according to any one of claims 1 to 27, wherein The receiving module (40) further comprises: A delay circuit (47) connected to an output end of the signal outputter (42), for filtering out abnormal signals in one of the signals output by the signal outputter (42) and outputting a signal. A signal transmission system (60), wherein The signal transmission circuit, the controller (61), the drive module (62) and the power device (63) according to any one of claims 1-28; An output end of the controller (61) is connected to an input end of the signal transmission circuit (10); An input end of the drive module (62) is connected to an output end of the signal transmission circuit (10); An input end of the power device (63) is connected to an output end of the drive module (62); The drive module (62) is configured to perform voltage boosting on the signal output by the signal transmission circuit (10) and output to the power device (63) to drive the power device (63) to operate. The signal transmission system (60) according to claim 29, wherein The signal output by the controller (61) is a square wave pulse signal. An electric control system (70) of a vehicle, wherein The signal transmission system (60) according to claim 29 or 30. A vehicle (100), wherein The electric control system (70) of the vehicle according to claim 31.

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