Array substrate, display panel and manufacturing method therefor, display device and electronic device

Abstract

An array substrate, comprising: a substrate; a stack structure disposed on the substrate; and a plurality of first photo spacers (107). The array substrate further comprises a plurality of pixel opening areas and gap areas located between adjacent pixel opening areas, wherein the height of the stack structure arranged in the gap areas is larger than the height of the stack structure arranged in the pixel opening areas. The plurality of first photo spacers (107) are arranged in the gap areas, the stack structure in the gap areas comprises a metal spacer layer located above in positions where the first photo spacers (107) are arranged, and the plurality of first photo spacers (107) comprise the portion of the stack structure in an orthographic projection region of the metal spacer layer on the substrate that is higher than the stack structure located in the pixel opening areas.

Description

Array substrate, display panel and manufacturing method, display device and electronic device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate and a manufacturing method, a display panel and a manufacturing method, a display device and an electronic device. BACKGROUND

[0002] A liquid crystal display panel generally comprises an array substrate and a color film (CF) substrate which are boxed together, and liquid crystal is filled between the array substrate and the color film substrate. In order to maintain the stability of the liquid crystal display panel and the uniformity of the cell thickness, a plurality of photo spacers (PS) for supporting the array substrate and the color film substrate are generally arranged between the array substrate and the color film substrate. By arranging a plurality of photo spacers, the uniformity of the overall thickness of the liquid crystal display panel and the tolerance of the liquid crystal display panel to liquid crystal fluctuation can be improved, and thus the yield of the liquid crystal display panel is improved.

[0003] An organic layer (ORG) coating process is adopted in the manufacturing process of the liquid crystal display panel. Due to the leveling effect of the organic layer, the photo spacer occupying position in the conventional photo spacer design is relatively flat. When the display panel is pressed, the photo spacer on the color film substrate side will slide into the opening area of the thin film transistor (TFT), scratch the alignment layer in the opening area, affect the liquid crystal alignment and form light leakage, and PS Mura (photo spacer mura) occurs. In addition, in the existing scheme, the photo spacers on the array substrate side and the color film substrate side are completed by the factory that manufactures the color film substrate, which greatly affects the production capacity. SUMMARY

[0004] The present disclosure provides an array substrate and a manufacturing method, a display panel and a manufacturing method, a display device and an electronic device, to ensure that the photo spacer on the color film substrate side is not easy to slide when the display panel is pressed, so as to avoid the occurrence of PS Mura.

[0005] An array substrate is provided, including: a substrate; a stack structure disposed on the substrate; and a plurality of first substrate spacers, wherein the array substrate further includes a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, a height of the stack structure disposed in the spacing region is greater than a height of the stack structure disposed in the pixel opening region, the plurality of first substrate spacers are disposed in the spacing region, the stack structure of the spacing region includes a metal spacer layer at an upper portion at a position where the first substrate spacer is disposed, and the plurality of first substrate spacers include a portion of the stack structure that is higher than the stack structure disposed in the pixel opening region within a projection area of the metal spacer layer on the substrate.

[0006] According to embodiments of the present disclosure, the array substrate further includes: a plurality of data lines extending in a first direction; and a plurality of gate lines extending in a second direction intersecting the first direction, and a projection of each of the plurality of first substrate spacers on the substrate at least partially overlaps a projection of one of the plurality of data lines on the substrate.

[0007] According to embodiments of the present disclosure, the plurality of first substrate spacers include first spacers corresponding to main spacers on a color filter substrate and second spacers corresponding to auxiliary spacers on the color filter substrate.

[0008] According to embodiments of the present disclosure, a size of the second spacer in the first direction is smaller than a size of the first spacer in the first direction, or a size of the second spacer in the second direction is greater than a size of the first spacer in the second direction.

[0009] According to embodiments of the present disclosure, at least part of the second spacer has a size in the first direction that is smaller than a size of the first spacer in the first direction, and at least part of the second spacer has a size in the second direction that is greater than a size of the first spacer in the second direction.

[0010] According to embodiments of the present disclosure, the second spacer includes a main spacer and a sub spacer disposed on both sides of the main spacer in the first direction, and a projection of the sub spacer on the substrate at least partially overlaps a projection of one of the plurality of gate lines on the substrate.

[0011] According to embodiments of the present disclosure, the sub spacer includes a plurality of sub spacers disposed in the second direction.

[0012] According to embodiments of the present disclosure, the sub spacer is located at a higher level than the main spacer in a direction perpendicular to the substrate.

[0013] According to an embodiment of the present disclosure, the first spacers and the at least one second spacer arranged in the same row in the second direction are misaligned in the second direction.

[0014] According to an embodiment of the present disclosure, the at least one second spacer and the first spacers arranged in the same row in the second direction are misaligned in the second direction.

[0015] An embodiment of the present disclosure provides a display panel, comprising: a first substrate; and a second substrate arranged opposite to the first substrate. The first substrate comprises: a first substrate; a stack structure arranged on the first substrate and facing the second substrate; and a plurality of first substrate spacers. The second substrate comprises: a second substrate; a black matrix arranged on the second substrate and facing the first substrate; and a plurality of second substrate spacers arranged on the black matrix. The plurality of first substrate spacers correspond to the plurality of second substrate spacers one by one. The first substrate comprises a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, and the height of the stack structure arranged in the spacing region is greater than the height of the stack structure arranged in the pixel opening region. The plurality of first substrate spacers are arranged in the spacing region, the stack structure of the spacing region comprises a metal spacer layer at the upper part at the position where the first substrate spacer is arranged, and the plurality of first substrate spacers comprise a part of the stack structure which is higher than the stack structure arranged in the pixel opening region within the projection area of the metal spacer layer on the substrate.

[0016] According to an embodiment of the present disclosure, the first substrate further comprises a plurality of data lines extending in a first direction, and a plurality of gate lines extending in a second direction intersecting the first direction. The projection of each first substrate spacer on the first substrate at least partially overlaps the projection of a data line on the first substrate, and the projection of each first substrate spacer on the first substrate at least partially overlaps the projection of a corresponding second substrate spacer on the first substrate.

[0017] According to an embodiment of the present disclosure, the plurality of second substrate spacers comprises a main spacer and an auxiliary spacer, and the height of the main spacer in a third direction perpendicular to the first substrate is greater than the height of the auxiliary spacer in the third direction. The plurality of first substrate spacers comprises a first spacer corresponding to the main spacer and a second spacer corresponding to the auxiliary spacer.

[0018] According to an embodiment of the present disclosure, the second spacers have a size in the first direction that is smaller than a size of the first spacers in the first direction, or a size in the second direction that is larger than a size of the first spacers in the second direction.

[0019] According to an embodiment of the present disclosure, at least part of the second spacers have a size in the first direction that is smaller than a size of the first spacers in the first direction, and a size in the second direction that is larger than a size of the first spacers in the second direction.

[0020] According to an embodiment of the present disclosure, the second spacers include main spacers, and sub-spacers disposed on both sides of the main spacers in the first direction, a projection of the sub-spacers on the first substrate at least partially overlaps a projection of one of the plurality of gate lines on the first substrate.

[0021] According to an embodiment of the present disclosure, the sub-spacers include a plurality of sub-sub-spacers disposed in the second direction.

[0022] According to an embodiment of the present disclosure, the sub-spacers are located at a higher level than the main spacers in the third direction.

[0023] According to an embodiment of the present disclosure, the first spacers disposed in the same row in the second direction are aligned in the second direction, and the at least one second spacer and other second spacers disposed in the same row in the second direction are not aligned in the second direction.

[0024] According to an embodiment of the present disclosure, the at least one second spacer and the first spacers disposed in the same row in the second direction are not aligned in the second direction.

[0025] According to an embodiment of the present disclosure, the first substrate is an array substrate, and the second substrate is a color filter substrate.

[0026] According to an embodiment of the present disclosure, the color filter substrate further includes a plurality of color resistance layers disposed between the black matrixes.

[0027] According to an embodiment of the present disclosure, the plurality of color resistance layers include a blue color resistance layer, a green color resistance layer, and a red color resistance layer.

[0028] An embodiment of the present disclosure further provides a display device including the display panel according to an embodiment of the present disclosure.

[0029] An embodiment of the present disclosure further provides an electronic device including the display device according to an embodiment of the present disclosure.

[0030] The embodiment of the present disclosure further provides a manufacturing method of an array substrate, comprising: preparing a substrate; preparing a stack structure on the substrate; and forming a plurality of first substrate spacers through the stack structure, wherein the array substrate comprises a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, the height of the stack structure arranged in the spacing region is greater than the height of the stack structure arranged in the pixel opening region, the plurality of first substrate spacers are arranged in the spacing region, and forming the plurality of first substrate spacers through the stack structure comprises: forming a metal spacer layer on the upper part of the stack structure in the spacing region to be formed with the plurality of first substrate spacers through a metal exposure process.

[0031] The embodiment of the present disclosure further provides a manufacturing method of a display panel, comprising: preparing a first substrate; preparing a second substrate; and aligning the first substrate with the second substrate to form the display panel. Preparing the first substrate comprises: preparing a first substrate; preparing a stack structure on the first substrate; and forming a plurality of first substrate spacers through the stack structure. Preparing the second substrate comprises: preparing a second substrate; preparing a black matrix on the second substrate; and preparing a plurality of second substrate spacers on the black matrix. The plurality of first substrate spacers and the plurality of second substrate spacers correspond to each other one by one. The first substrate comprises a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, the height of the stack structure arranged in the spacing region is greater than the height of the stack structure arranged in the pixel opening region. The plurality of first substrate spacers are arranged in the spacing region, and forming the plurality of first substrate spacers through the stack structure comprises: forming a metal spacer layer on the upper part of the stack structure in the spacing region to be formed with the plurality of first substrate spacers through a metal exposure process.

[0032] The array substrate and the manufacturing method thereof, the display panel and the manufacturing method thereof, the display device and the electronic device of the embodiment of the present disclosure can increase the friction with the corresponding spacers on the color film substrate side, so as to ensure that the spacers on the color film substrate side are not easy to slide when the display panel is pressed, thereby avoiding the generation of PSMura. In addition, the high-performance exposure machine of the factory manufacturing the array substrate can be used to accurately control the various forms of the spacers, and the precision of the scheme is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, which are used together with the embodiments of the present disclosure to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed description of the specific example embodiments with reference to the attached drawings, in which:

[0034] FIG. 1A is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0035] FIG. 1B is another schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0036] FIG. 2A is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0037] FIG. 2B is another schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0038] FIG. 3 is a schematic top view of a display panel according to an embodiment of the present disclosure;

[0039] FIG. 4 is another schematic top view of a display panel according to an embodiment of the present disclosure;

[0040] FIG. 5A is another schematic top view of a display panel according to an embodiment of the present disclosure;

[0041] FIG. 5B is a schematic cross-sectional view taken along line AA in FIG. 5A;

[0042] FIG. 6 is another schematic top view of a display panel according to an embodiment of the present disclosure;

[0043] FIG. 7 is another schematic top view of a display panel according to an embodiment of the present disclosure;

[0044] FIG. 8 is another schematic top view of a display panel according to an embodiment of the present disclosure;

[0045] FIG. 9 shows a flowchart of a method of manufacturing an array substrate according to an embodiment of the present disclosure;

[0046] FIG. 10 shows a flowchart of a method of manufacturing a display panel according to an embodiment of the present disclosure.

[0047] For the sake of clarity, the attached drawings are not necessarily to scale and the same reference numbers are used to designate the same or similar elements throughout the various figures. The configuration shown in the drawings is merely an example and should not be construed in any way as limiting. DETAILED DESCRIPTION

[0048] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the display panel and the manufacturing method thereof and the display device comprising the display panel provided by the present disclosure are described in detail below with reference to the drawings.

[0049] In the following, example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments can, however, be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as example to make the disclosure fully complete and to fully convey the scope of the present disclosure to those skilled in the art.

[0050] In the manufacturing process of liquid crystal display panel, organic film layer coating process is usually adopted. Due to the leveling effect of the organic film layer, the spacer occupies a relatively flat position. When the display panel is pressed, the spacers on the color film substrate side will slide into the opening area of the thin film transistor, scratch the alignment layer in the opening area, affect the liquid crystal alignment and form light leakage, and PSMura appears.

[0051] According to the display panel of the embodiment of the present disclosure, the spacers on the array substrate side are formed by a metal layer, thereby increasing the distance between the alignment layer of the array substrate and the spacers on the color film substrate side, to ensure that the spacers on the color film substrate side are not easy to contact the alignment layer of the array substrate when the display panel is pressed, thereby avoiding the generation of PSMura; at the same time, the spacers on the array substrate side are formed by a metal layer, which can make the pattern more accurate and have less influence on the opening rate.

[0052] FIGS. 1A and 1B are cross-sectional schematic views of an array substrate according to an embodiment of the present disclosure, FIGS. 2A and 2B are cross-sectional schematic views of a display panel according to an embodiment of the present disclosure, and FIG. 3 is a top view of a display panel according to an embodiment of the present disclosure.

[0053] As shown in FIGS. 1A and 1B, the array substrate according to the embodiment of the present disclosure includes a substrate, a stack structure disposed on the substrate, and a plurality of first substrate spacers 107 formed by the stack structure. The array substrate includes a plurality of pixel opening areas and a spacing area between adjacent pixel opening areas. The height of the stack structure disposed in the spacing area is greater than the height of the stack structure disposed in the pixel opening area. The plurality of first substrate spacers 107 are disposed in the spacing area and include a metal spacer layer disposed on the upper part of a portion of the stack structure in the spacing area, and the plurality of first substrate spacers include a portion of the stack structure in the first substrate above the metal spacer layer in the first substrate.

[0054] As shown in FIGS. 2A and 2B, the display panel according to embodiments of the present disclosure includes a first substrate and a second substrate disposed opposite to the first substrate. The first substrate includes a first substrate, a stack structure disposed on the first substrate toward the second substrate, and a plurality of first substrate spacers 107 formed by the stack structure. The second substrate includes a second substrate, a black matrix disposed on the second substrate toward the first substrate, and a plurality of second substrate spacers 108 disposed on the black matrix. The plurality of first substrate spacers 107 correspond to the plurality of second substrate spacers 108 one by one. The first substrate includes a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions. The height of the stack structure disposed in the spacing region is greater than the height of the stack structure disposed in the pixel opening region. The plurality of first substrate spacers 107 are disposed in the spacing region and include a metal spacer layer disposed on a portion of the upper portion of the stack structure in the spacing region, and the plurality of first substrate spacers include a portion of the stack structure of the metal spacer layer that is higher than the stack structure located in the pixel opening region within the orthographic projection area of the metal spacer layer on the first substrate.

[0055] In the context of the present disclosure, the spacer including the metal spacer layer is referred to as a metal spacer (Metal PS, MPS).

[0056] According to embodiments of the present disclosure, as shown in FIGS. 1A and 2A, the first substrate can be a glass substrate, and the stack structure of the spacing region (or the wiring region) formed on the first substrate can include, in order, a gate layer (Gate), a gate insulating layer (GI), an active layer (IGZO), a source-drain layer (SD), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), a metal spacer layer, and a second dielectric layer (PVX2). In some embodiments, the metal oxide layer (ITO) and the metal spacer layer are in direct contact to achieve electrical connection of the metal oxide layer (ITO) and the metal spacer layer.

[0057] According to embodiments of the present disclosure, as shown in FIGS. 1B and 2B, the first substrate can be a glass substrate, and the stack structure of the spacing region (or the wiring region) formed on the first substrate can include, in order, a gate layer (Gate), a gate insulating layer (GI), an active layer (IGZO), a source-drain layer (SD), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), a second dielectric layer (PVX2), and a metal spacer layer.

[0058] Referring to FIGS. 1A-2B, the stack structure of the pixel opening region formed on the first substrate can include, in sequence, a gate insulating layer (GI), a first dielectric layer (PVX1), an organic film layer (ORG), a metal oxide layer (ITO), and a second dielectric layer (PVX2). In addition, FIGS. 1A-2B also show that the first substrate and the second substrate each include an alignment layer (PI), the alignment layer of the first substrate covers the first substrate spacers 107 and the stack structure, and the alignment layer of the second substrate covers the second substrate spacers 108 and the black matrix.

[0059] As shown in FIGS. 1A-2B, the stack structure of the pixel opening region formed on the substrate does not include a gate layer (Gate), a source-drain layer (SD), and a metal spacer layer. Since there is a height difference between the stack structure formed in the spacing region and the stack structure formed in the pixel opening region, the first substrate spacers 107 (MPS) can be formed by the stack structure of the spacing region. The height of the first substrate spacers 107 is determined by the height of the gate layer (Gate), the source-drain layer (SD), and the metal spacer layer. That is, in the case where the thicknesses of the same film layers are the same, the height difference formed by the remaining film layers constitutes the first substrate spacers 107.

[0060] In addition to the exemplary stack structure shown in FIGS. 1A-2B, the stack structure formed in the spacing region can further include other layers not shown in the figures. Similarly, the stack structure formed in the pixel opening region can also further include other layers not shown in the figures. For example, although not shown in the figures, a person skilled in the art should understand that a second metal oxide layer can also be formed in the pixel opening region, which can be formed on the first substrate or on the second substrate.

[0061] Referring to FIGS. 2A and 2B, liquid crystal (not shown) can be filled between the first substrate and the second substrate and a display panel is formed after cell alignment. In the positions corresponding to the pixel opening regions, the thickness of the liquid crystal layer (i.e., cell gap, CG) can be appropriately configured with various dimensions according to specific process requirements.

[0062] According to embodiments of the present disclosure, as shown in FIGS. 2A and 2B, the second substrate can be a glass substrate, the black matrix can be formed on the second substrate, the second substrate spacers 108 can be formed on the black matrix, and each of the second substrate spacers 108 corresponds to one of the first substrate spacers 107 on the first substrate. The orthographic projection of the black matrix on the first substrate at least partially overlaps the stack structure of the spacing region formed on the first substrate. In some embodiments, the orthographic projection of the black matrix on the first substrate completely covers the stack structure of the spacing region formed on the first substrate.

[0063] According to embodiments of the present disclosure, as shown in FIGS. 2A and 2B, the plurality of second substrate spacers 108 includes a main spacer 1081 and an auxiliary spacer 1082. The height of the main spacer 1081 in the third direction perpendicular to the first substrate is greater than the height of the auxiliary spacer 1082 in the third direction. The plurality of first substrate spacers 107 includes a first spacer 1071 corresponding to the main spacer 1081 and a second spacer 1072 corresponding to the auxiliary spacer 1082.

[0064] According to embodiments of the present disclosure, the first substrate can be an array substrate, and the second substrate can be a color filter substrate.

[0065] Referring to FIGS. 2A and 2B, the second substrate can be a color filter substrate, and in addition to the second substrate, the black matrix, and the second substrate spacers 108 shown in FIGS. 2A and 2B, the second substrate can further include a plurality of color resistance layers (not shown) disposed between the black matrix. The black matrix on the second substrate corresponds to the spacing region (or the wiring region) of the first substrate, and the plurality of color resistance layers on the second substrate correspond to the pixel opening region of the first substrate. The plurality of color resistance layers can include color resistance layers of different colors, for example, blue color resistance layers, green color resistance layers, and red color resistance layers.

[0066] According to embodiments of the present disclosure, as shown in FIG. 3, the first substrate further includes a plurality of data lines 101 extending in a first direction D1, and a plurality of gate lines 102 extending in a second direction D2 intersecting the first direction D1. The orthogonal projection of each of the plurality of first substrate spacers 107 on the first substrate at least partially overlaps the orthogonal projection of one of the plurality of data lines 101 on the first substrate, and the orthogonal projection of each of the plurality of first substrate spacers 107 on the first substrate at least partially overlaps the orthogonal projection of a corresponding one of the plurality of second substrate spacers 108 on the first substrate.

[0067] Referring to FIG. 3, the first substrate can further include a common electrode line 103 and a common via 105, the common electrode line 103 being connected to the common electrode 110 via the common via 105. In some embodiments, the common electrode 110 and the metal spacers are in direct contact to achieve electrical connection between the common electrode 110 and the metal spacers, so that the resistance of the common electrode 110 can be reduced and the metal spacers can be prevented from floating. In addition, the first substrate can further include a plurality of thin film transistors 104, the data line 101 being connected to a source of the thin film transistor 104, the gate line 102 being connected to a gate of the thin film transistor 104, a drain of the thin film transistor 104 being connected to a pixel electrode (not shown in the figure) via a drain via 106, and the thin film transistor 104 including an active layer 109. FIG. 3 shows that the first substrate includes a metal oxide layer which can be used as the common electrode 110. The material of the metal oxide layer can include a transparent oxide, for example, indium tin oxide (ITO).

[0068] As shown in FIG. 3, the width of the first substrate spacer 107 in the second direction D2 is wider than that of the data line 101. Generally, the width of the data line can be, for example, about 3 μm, and the width of the first substrate spacer 107 can be, for example, about 15 μm. The length of the first substrate spacer 107 in the first direction D1 can be, for example, about 30 μm. For example, the first substrate spacer 107 can be formed to be 14 μm x 28 μm (size in the second direction D2 x size in the first direction D1). It should be appreciated that the specific values shown are only examples, and a person skilled in the art can appropriately configure various dimensions according to specific process requirements. In some embodiments, the two ends of the first substrate spacer 107 in the first direction D1 can respectively at least partially overlap the gate line 102 and the common electrode line 103, so that the height of the two ends can be increased to block the sliding of the second substrate spacer 108. In some embodiments, the two ends of the first substrate spacer 107 in the first direction D1 can respectively extend beyond the regions of the gate line 102 and the common electrode line 103, the length of the first substrate spacer 107 in the first direction D1 is increased, the second substrate spacer 108 can be prevented from sliding out, and the aperture ratio can not be substantially reduced.

[0069] As shown in FIG. 3, the data line 101 is bent at the position of the spacer, so that the distance from the center of the data line 101 to the adjacent two drain vias 106 in the second direction D2 is substantially the same, and the distance from the center of the first substrate spacer 107 to the adjacent two drain vias 106 in the second direction D2 is also substantially the same.

[0070] According to the embodiment of the present disclosure, when the display panel is not subjected to external force, a certain mutual extrusion force exists between the convex part formed by the main spacer 1081 and the corresponding first spacer 1071, which can improve the ability of the display panel to resist external force and improve the stability of the display panel. When the display panel is subjected to external force, the main spacer 1081 is further compressed, so that the auxiliary spacer 1082 is in contact with the corresponding second spacer 1072 to further provide support to the display panel. For example, when the main spacer 1081 and the first spacer 1071 are extruded to each other, the first spacer 1071 is deformed to protrude in the direction of the first substrate under the extrusion of the main spacer 1081. Since the first spacer 1071 includes the metal spacer layer arranged at the upper portion and the topography of the metal spacer layer can be accurately controlled through the metal exposure process, the friction between the first spacer 1071 and the main spacer 1081 is increased, and it is ensured that the main spacer 1081 is not easy to slide when the display panel is subjected to external force, thereby avoiding the spacer from sliding into the opening area of the thin film transistor 104, scratching the alignment layer in the opening area, affecting the liquid crystal alignment and thus forming light leakage and PSMura. In addition, since the metal spacer layer can be formed through the metal exposure process by using the high-performance exposure machine of the factory for manufacturing the array substrate, the accurate control of various shapes of the spacer can be realized, and the precision of the scheme is improved.

[0071] According to the embodiment of the present disclosure, as shown in FIG. 3, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1 can be smaller than the size of the first spacer 1071 corresponding to the main spacer 1081 in the first direction D1.

[0072] Referring to FIG. 3, the main spacer 1081 located at the central position and the auxiliary spacer 1082 located on both sides of the main spacer 1081 are shown in the figure. For example, the first spacer 1071 corresponding to the main spacer 1081 can be formed as 14 μm × 28 μm (size in the second direction D2 × size in the first direction D1), and the second spacer 1072 corresponding to the auxiliary spacer 1082 can be formed as 14 μm × 15 μm (size in the second direction D2 × size in the first direction D1). It should be recognized that the specific numerical values shown are only examples, and a person skilled in the art can appropriately configure various sizes according to specific process requirements.

[0073] According to the embodiment of the present disclosure, by reducing the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the first direction D1, the aperture ratio (AR) can be maximized.

[0074] According to embodiments of the present disclosure, by increasing the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the first direction D1, the sliding distance of the auxiliary spacers can be increased, and the spacers can be prevented from sliding off.

[0075] As shown in FIG. 3, the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the second direction D2 can be substantially equal to the size of the first spacers 1071 corresponding to the main spacers 1081 in the second direction D2, but the present disclosure is not limited thereto. Referring to FIG. 4, according to embodiments of the present disclosure, the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the second direction D2 can be greater than or less than the size of the first spacers 1071 corresponding to the main spacers 1081 in the second direction D2. In some embodiments, the second spacers 1072 can include both the second spacers 1072 having a size in the second direction D2 greater than the size of the first spacers 1071 in the second direction D2 and the second spacers 1072 having a size in the second direction D2 less than the size of the first spacers 1071 in the second direction D2. In some embodiments, among two second spacers 1072 adjacent to both sides of the first spacer 1071, one second spacer 1072 can have a size in the second direction D2 greater than the size of the first spacer 1071 in the second direction D2, and the other second spacer 1072 can have a size in the second direction D2 less than the size of the first spacer 1071 in the second direction D2.

[0076] According to embodiments of the present disclosure, when designing the positions of the first substrate spacers 107 corresponding to the main spacers 1081 and the auxiliary spacers 1082, the via holes (including, for example, the common via hole 105 and the drain via hole 106) next to them need to be avoided to leave a gap with the via holes. Therefore, when designing the shape of the first substrate spacers 107, the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the second direction D2 can be appropriately increased while leaving sufficient gaps with the via holes on both sides, so as to increase the contact area with the auxiliary spacers 1082 and thus increase the friction. For example, the first spacers 1071 corresponding to the main spacers 1081 can be formed as 14 μm x 28 μm (size in the second direction D2 x size in the first direction D1), and the second spacers 1072 corresponding to the auxiliary spacers 1082 can be formed as 27.5 μm x 15 μm or 23.5 μm x 15 μm (size in the second direction D2 x size in the first direction D1). It should be appreciated that the specific values shown are only examples, and a person skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0077] According to embodiments of the present disclosure, the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the first direction D1 can be made smaller than the size of the first spacers 1071 corresponding to the main spacers 1081 in the first direction D1. Alternatively, the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the first direction D1 can be made larger than the size of the first spacers 1071 corresponding to the main spacers 1081 in the first direction D1. Alternatively, the size of at least one of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the first direction D1 can be made larger than the size of the first spacers 1071 corresponding to the main spacers 1081 in the first direction D1, and the size of at least one of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the first direction D1 can be made smaller than the size of the first spacers 1071 corresponding to the main spacers 1081 in the first direction D1.

[0078] According to embodiments of the present disclosure, the size of at least one of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the second direction D2 can be made larger than the size of the first spacers 1071 corresponding to the main spacers 1081 in the second direction D2. Alternatively, the size of at least one of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the second direction D2 can be made smaller than the size of the first spacers 1071 corresponding to the main spacers 1081 in the second direction D2.

[0079] According to embodiments of the present disclosure, the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the first direction D1 can be made smaller than the size of the first spacers 1071 corresponding to the main spacers 1081 in the first direction D1, and the size of the second spacers 1072 corresponding to the auxiliary spacers 1082 in the second direction D2 can be made larger than the size of the first spacers 1071 corresponding to the main spacers 1081 in the second direction D2.

[0080] FIG. 5A is another top view of a display panel according to embodiments of the present disclosure.

[0081] As shown in FIG. 5A, compared with the embodiment shown in FIG. 3, in the embodiment shown in FIG. 5A, the second spacers 1072 corresponding to the auxiliary spacers 1082 include a main spacer 10721, and a sub spacer 10722 disposed on both sides of the main spacer 10721 in the first direction D1. The orthogonal projection of the sub spacer 10722 on the first substrate at least partially overlaps with the orthogonal projection of one of the plurality of gate lines 102 on the first substrate. In FIG. 5A, the main spacer 1081 at the central position is shown, and the auxiliary spacers 1082 on both sides of the main spacer 1081 are shown.

[0082] According to the embodiments of the present disclosure, the sub-spacers 10722 can be used as a barrier to block the sliding of the auxiliary spacers 1082 in the first direction D1. As shown in FIG. 5A, the orthographic projection of the barrier formed by the sub-spacers 10722 on the first substrate can at least partially overlap with the orthographic projection of one of the plurality of gate lines 102 on the first substrate, and / or can at least partially overlap with the orthographic projection of the common electrode line 103 on the first substrate.

[0083] According to the embodiments of the present disclosure, referring to FIG. 5B, the sub-spacers 10722 can be located at a higher level than the main body spacers 10721 in the direction perpendicular to the first substrate, so as to better block the sliding of the auxiliary spacers 1082 in the first direction D1.

[0084] It should be appreciated that, for the sake of clarity, only the auxiliary spacers 1082 and the second spacers 1702 corresponding to the auxiliary spacers 1082 are schematically shown in the cross-sectional view of FIG. 5B, and the alignment layer covering the spacers is not shown, nor are the stack structure and the black matrix. In addition, the second spacers 1702 are also schematically represented by the metal spacer layer on the upper part of the second spacers 1702. It should also be appreciated by those skilled in the art that, although FIG. 5B shows that the sub-spacers 10722 can be located at a higher level than the main body spacers 10721 in the direction perpendicular to the first substrate, the present disclosure is not limited thereto. According to the embodiments of the present disclosure, the sub-spacers 10722 can be located at the same level as the main body spacers 10721 in the direction perpendicular to the first substrate.

[0085] As shown in FIG. 6, the sub-spacers 10722 can be arranged on only one side of the main body spacers 10721 in the first direction D1.

[0086] According to the embodiments of the present disclosure, as shown in FIG. 5A and FIG. 6, the width of the sub-spacers 10722 in the second direction D2 is substantially the same as the width of the main body spacers 10721 in the second direction D2. Alternatively, the width of the sub-spacers 10722 in the second direction D2 can be different from the width of the main body spacers 10721 in the second direction D2, greater than or less than the width of the main body spacers 10721 in the second direction D2. It should be appreciated that those skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0087] FIG. 7 is another top view of a display panel according to an embodiment of the present disclosure.

[0088] As shown in FIG. 7, compared with the embodiment shown in FIG. 5A, in the embodiment shown in FIG. 7, the second spacer 1072 corresponding to the auxiliary spacer 1082 includes a main spacer 10721, and a sub spacer 10722' disposed on both sides of the main spacer 10721 in the first direction D1, wherein the sub spacer 10722' includes a plurality of sub spacers disposed in the second direction D2. In FIG. 7, the main spacer 1081 located at the central position, and the auxiliary spacer 1082 located on both sides of the main spacer 1081 are shown.

[0089] According to the embodiments of the present disclosure, the sub spacer 10722' can be formed as a plurality of sub spacers, thereby facilitating the recovery of the spacer after the offset. As shown in FIG. 7, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 can be appropriately adjusted according to the specific position of the via (including, for example, the common via 105 and the drain via 106). For example, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side of the figure in the second direction D2 can be formed as large as possible to increase the contact area of the auxiliary spacer 1082 and thereby increase the friction force while meeting the avoidance of the via. For example, the distance between the two vias (two drain vias 106) shown on the left side of the figure can be 33.55 μm, therefore, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 is formed as 23.4 μm, that is, the size of the main spacer 10721 in the second direction D2 is formed as 23.4 μm, and the sub spacer 10722' can be formed as three sub spacers.

[0090] For example, the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side of the drawing in the second direction D2 can be smaller than the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side of the drawing in the second direction D2, in a case where the via is avoided. For example, the distance between the two vias (the drain via 106 and the common via 105) shown on the right side of the drawing can be 24.55 μm, and thus the size of the second spacer 1072 corresponding to the auxiliary spacer 1082 in the second direction D2 is formed to be 14.4 μm, i.e., the size of the main spacer 10721 in the second direction D2 is formed to be 14.4 μm, and the sub spacer 10722' can be formed as two sub spacers. Thus, the number of sub spacers included in the sub spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side of the drawing can be different from the number of sub spacers included in the sub spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side of the drawing. Specifically, the number of sub spacers included in the sub spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the left side of the drawing can be greater than the number of sub spacers included in the sub spacer 10722' of the second spacer 1072 corresponding to the auxiliary spacer 1082 formed on the right side of the drawing. It should be appreciated that the specific values shown are merely examples, and a person skilled in the art can appropriately configure various dimensions and the number of sub spacers according to specific process requirements.

[0091] Alternatively, the sub spacer 10722' can be provided on only one side of the main spacer 10721 in the first direction D1, and the sub spacer 10722' can be formed as a plurality of sub spacers.

[0092] Alternatively, the sub spacer 10722' can be provided on one side of the main spacer 10721 in the first direction D1, the sub spacer 10722' can be formed as a plurality of sub spacers, and the sub spacer 10722 as shown in FIGS. 5A and 6 can be provided on the other side of the main spacer 10721 in the first direction D1.

[0093] According to embodiments of the present disclosure, as shown in FIG. 7, the width of the sub spacer 10722' in the second direction D2 is substantially the same as the width of the main spacer 10721 in the second direction D2. Alternatively, the width of the sub spacer 10722' in the second direction D2 can be different from the width of the main spacer 10721 in the second direction D2, greater or smaller than the width of the main spacer 10721 in the second direction D2. It should be appreciated that a person skilled in the art can appropriately configure various dimensions according to specific process requirements.

[0094] According to the embodiment of the present disclosure, the first substrate spacers 107 are formed as metal spacers including a metal spacer layer, so that the metal spacer layer can be formed by a metal exposure process using a high-performance exposure machine of a factory manufacturing an array substrate, to realize accurate control of various shapes of the spacers and improve the accuracy of the scheme.

[0095] FIG. 8 is another top view of a display panel according to an embodiment of the present disclosure.

[0096] As shown in FIG. 8, compared with the embodiment shown in FIG. 3, in the embodiment shown in FIG. 8, each first substrate spacer 107 (including the first spacer 1071 and the second spacer 1072) disposed in the same row is misaligned in the second direction D2.

[0097] Specifically, referring to FIG. 8, in the same row, each first spacer 1071 corresponding to the main spacer 1081 can be aligned in the second direction D2, at least one second spacer 1072 corresponding to the auxiliary spacer 1082 and other second spacers 1072 corresponding to the auxiliary spacer 1082 can be misaligned in the second direction D2, and at least one second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 can be misaligned in the second direction D2. In FIG. 8, the main spacer 1081 located at the central position and the auxiliary spacers 1082 located on both sides of the main spacer 1081 are shown. It should be appreciated that the "alignment" described herein specifically refers to the center alignment of the components.

[0098] Although it is shown in FIG. 8 that the second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 have different sizes in the first direction D1, the present disclosure is not limited thereto, and the second spacer 1072 corresponding to the auxiliary spacer 1082 and the first spacer 1071 corresponding to the main spacer 1081 can have the same size in the first direction D1. Although it is shown in FIG. 8 that the second spacer 1072 corresponding to the auxiliary spacer 1082 does not include a main spacer and a sub spacer, the present disclosure is not limited thereto, and the second spacer 1072 corresponding to the auxiliary spacer 1072 can include a main spacer 10721 and a sub spacer 10722 as shown in FIGS. 5A and 6 and / or a main spacer 10721 and a sub spacer 10722' as shown in FIG. 7.

[0099] By setting the second spacers 1072 corresponding to the auxiliary spacers 1082 to be misaligned in the second direction D2 and the first spacers 1071 corresponding to the main spacers 1081 to include different offset directions, it can be ensured that at least part of the second spacers 1072 can be supported when the auxiliary spacers 1082 are offset in a certain direction, and the total area of the second spacers 1072 can be reduced to improve the aperture ratio.

[0100] According to the embodiments of the present disclosure, a display device is also provided, which includes the display panel according to the embodiments of the present disclosure.

[0101] According to the embodiments of the present disclosure, an electronic device is also provided, which includes the display device according to the embodiments of the present disclosure, and the display device includes the display panel according to the embodiments of the present disclosure.

[0102] Since the display panel according to the embodiments of the present disclosure is adopted, when the display panel is not extruded by external force, a certain mutual extrusion force exists between the convex part formed by the main spacer and the corresponding first spacer, which can improve the ability of the display panel to resist external force and improve the stability of the display panel. When the display panel is extruded by external force, the main spacer is further compressed, so that the auxiliary spacer is in contact with the corresponding second spacer to further provide support to the display panel. Since the first substrate spacer includes the metal spacer layer arranged on the upper part, the friction between the first substrate spacer and the corresponding second substrate spacer is increased, which ensures that the second substrate spacer is not easy to slide when the display panel is extruded by external force, thereby avoiding the spacer from sliding into the opening area of the thin film transistor, scratching the alignment layer in the opening area, affecting the liquid crystal alignment and thus causing light leakage and PSMura. In addition, since the metal spacer layer can be formed by the metal exposure process by using the high-performance exposure machine of the factory for manufacturing the array substrate, the precise control of various forms of the spacer can be realized, and the precision of the scheme is improved.

[0103] FIG. 9 shows a flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure.

[0104] As shown in FIG. 9, the manufacturing method of the array substrate according to the embodiments of the present disclosure includes the following steps S11-S13.

[0105] In step S11, a substrate is prepared.

[0106] In step S12, a stack structure is prepared on the substrate.

[0107] In step S13, a plurality of first substrate spacers are formed through the stack structure.

[0108] According to the embodiment of the present disclosure, the array substrate comprises a plurality of pixel opening regions and a plurality of interval regions between adjacent pixel opening regions, a height of the stack structure arranged in the interval region is greater than a height of the stack structure arranged in the pixel opening region, a plurality of first substrate spacers are arranged in the interval region, and the forming of the plurality of first substrate spacers through the stack structure (i.e., step S13) comprises: forming a metal spacer layer on the upper portion of the stack structure in the interval region where the plurality of first substrate spacers are to be formed through a metal exposure process.

[0109] According to the method for manufacturing the array substrate of the embodiment of the present disclosure, since the metal spacer layer is formed on the upper portion of the stack structure in the interval region where the plurality of first substrate spacers are to be formed through the metal exposure process, the friction between the first substrate spacer and the corresponding second substrate spacer is increased, and it is ensured that the second substrate spacer is not easy to slide when the display panel is pressed by external force, so as to avoid the spacer from sliding into the opening region of the thin film transistor, scratch the alignment layer in the opening region, affect the liquid crystal alignment and thus form light leakage and PSMura. In addition, since the metal spacer layer can be formed through the metal exposure process by using the high-performance exposure machine of the factory manufacturing the array substrate, the precise control of various forms of the spacer can be realized, and the precision of the scheme is improved.

[0110] FIG. 10 shows a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0111] As shown in FIG. 10, the method for manufacturing a display panel according to the embodiment of the present disclosure comprises the following steps S100-S300.

[0112] In step S100, a first substrate is prepared.

[0113] In step S200, a second substrate is prepared.

[0114] In step S300, the first substrate is aligned with the second substrate to form a display panel.

[0115] The preparation of the first substrate (i.e., step S100) comprises the following steps S110-S130.

[0116] In step S110, a first substrate is prepared.

[0117] In step S120, a stack structure is prepared on the first substrate.

[0118] In step S130, a plurality of first substrate spacers are formed through the stack structure.

[0119] The preparation of the second substrate (i.e., step S200) comprises the following steps S210-S230.

[0120] In step S210, a second substrate is prepared.

[0121] In step S220, a black matrix is prepared on the second substrate.

[0122] In step S230, a plurality of second substrate spacers are prepared on the black matrix.

[0123] According to the embodiment of the present disclosure, the plurality of first substrate spacers and the plurality of second substrate spacers are in one-to-one correspondence, the first substrate includes a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, the height of the stack structure arranged in the spacing region is greater than the height of the stack structure arranged in the pixel opening region, the plurality of first substrate spacers are arranged in the spacing region, and the plurality of first substrate spacers are formed by the stack structure (i.e., step S130) includes: forming a metal spacer layer on the upper part of the stack structure in the spacing region where the plurality of first substrate spacers are to be formed by a metal exposure process.

[0124] According to the manufacturing method of the display panel of the embodiment of the present disclosure, when the cell is formed, there is a certain mutual extrusion force between the second substrate spacer and the convex part formed by the corresponding first substrate spacer, which can improve the ability of the display panel to resist external force and improve the stability of the display panel. Since the metal spacer layer is formed on the upper part of the stack structure in the spacing region where the plurality of first substrate spacers are to be formed by a metal exposure process, the friction between the first substrate spacer and the corresponding second substrate spacer is increased, so that the second substrate spacer is not easy to slide when the display panel is extruded by external force, thereby avoiding the spacer from sliding into the opening region of the thin film transistor, scratching the alignment layer in the opening region, affecting the liquid crystal alignment and causing light leakage, and PSMura. In addition, since the high-performance exposure machine of the factory manufacturing the array substrate can be used to form the metal spacer layer by the metal exposure process, the precise control of various forms of the spacer can be realized, and the precision of the scheme is improved.

[0125] For the convenience of description, spatial relative terms such as "below", "above", "left", "right" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. It should be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the drawing is turned over, the element described as "below" the other element or feature will be oriented "above" the other element or feature accordingly. In this way, the exemplary term "below" can cover both "below" and "above" orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0126] For ease of description, ordinal numbers such as "first," "second," "third," etc. can be used herein. These ordinal numbers are used only to distinguish one element or feature from another element or feature, and not for limiting the order of the elements or features.

[0127] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0128] Exemplary embodiments have been disclosed herein and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. In some embodiments, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment can be used in conjunction with other embodiments unless otherwise explicitly stated. Accordingly, it will be understood that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. An array substrate, comprising: a substrate; a stack structure disposed on the substrate; and a plurality of first substrate spacers, wherein the array substrate further comprises a plurality of pixel opening regions and a plurality of spacing regions between adjacent pixel opening regions, a height of the stack structure disposed in the spacing regions is greater than a height of the stack structure disposed in the pixel opening regions, the plurality of first substrate spacers are disposed in the spacing regions, the stack structure in the spacing regions comprises a metal spacer layer on an upper portion at a position where the first substrate spacers are disposed, and the plurality of first substrate spacers comprise a portion of the stack structure that is higher than the stack structure disposed in the pixel opening regions within a projection area of the metal spacer layer on the substrate. The stack structure comprises a metal oxide layer, and the metal spacer layer is directly on the metal oxide layer.

2. The array substrate according to claim 1, wherein, 3.The array substrate of claim 1, further comprising: a plurality of data lines extending in a first direction; and a plurality of gate lines extending in a second direction intersecting the first direction, a projection of each of the plurality of first substrate spacers on the substrate at least partially overlaps a projection of one of the plurality of data lines on the substrate. The plurality of first substrate spacers comprise first spacers corresponding to main spacers on a color filter substrate and second spacers corresponding to auxiliary spacers on the color filter substrate. A dimension of the second spacers in the first direction is smaller than a dimension of the first spacers in the first direction, or 4. The array substrate according to claim 3, wherein, A dimension of the second spacers in the second direction is greater than a dimension of the first spacers in the second direction.

5. The array substrate according to claim 4, wherein, At least part of the second spacers has a dimension in the first direction that is smaller than a dimension of the first spacers in the first direction, and At least part of the second spacers has a dimension in the second direction that is greater than a dimension of the first spacers in the second direction.

6. The array substrate according to claim 4, wherein, 7.The array substrate of claim 4, wherein the second spacers comprise main spacers and sub spacers disposed on both sides of the main spacers in the first direction, a projection of the sub spacers on the substrate at least partially overlaps a projection of one of the plurality of gate lines on the substrate. The sub spacers comprise a plurality of sub spacers disposed in the second direction. The sub spacers are located at a higher level than the main spacers in a direction perpendicular to the substrate.

8. The array substrate according to claim 7, wherein, 10.The array substrate of claim 4, wherein 9. The array substrate according to claim 7 or 8, wherein, each of the first spacers disposed in a same row in the second direction are aligned in the second direction, at least one of the second spacers disposed in a same row in the second direction and other second spacers are not aligned in the second direction. 11.A display panel, comprising: a first substrate; and a second substrate disposed opposite the first substrate, the first substrate comprising: a first substrate; a stack structure disposed on the first substrate toward the second substrate; and a plurality of first substrate spacers, the second substrate comprising: a second substrate; and a stack structure disposed on the second substrate toward the first substrate. ​ ​ a black matrix disposed on the second substrate and facing the first substrate; and a plurality of second substrate spacers disposed on the black matrix, wherein the plurality of first substrate spacers and the plurality of second substrate spacers correspond to each other one by one, the first substrate includes a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, a height of a stack structure disposed in the spacing region is greater than a height of a stack structure disposed in the pixel opening region, the plurality of first substrate spacers are disposed in the spacing region, the stack structure of the spacing region includes a metal spacer layer at an upper portion at a position where the first substrate spacer is disposed, and the plurality of first substrate spacers include a portion of the stack structure of the metal spacer layer that is higher than the stack structure disposed in the pixel opening region within a projection area of the metal spacer layer on the substrate.

12. The display panel of claim 11, wherein, The stack structure includes a metal oxide layer, and the metal spacer layer is directly located on the metal oxide layer.

13. The display panel of claim 12, wherein the first substrate further includes a plurality of data lines extending in a first direction, and a plurality of gate lines extending in a second direction intersecting the first direction, a projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps a projection of one of the plurality of data lines on the first substrate, and a projection of each of the plurality of first substrate spacers on the first substrate at least partially overlaps a projection of a corresponding second substrate spacer of the plurality of second substrate spacers on the first substrate.

14. The display panel of claim 13, wherein the plurality of second substrate spacers includes a main spacer and an auxiliary spacer, a height of the main spacer in a third direction perpendicular to the first substrate is greater than a height of the auxiliary spacer in the third direction, the plurality of first substrate spacers includes a first spacer corresponding to the main spacer and a second spacer corresponding to the auxiliary spacer.

15. The display panel of claim 14, wherein, a size of the second spacer in the first direction is less than a size of the first spacer in the first direction, or a size of the second spacer in the second direction is greater than a size of the first spacer in the second direction.

16. The display panel of claim 14, wherein, at least part of the size of the second spacer in the first direction is less than the size of the first spacer in the first direction, and at least part of the size of the second spacer in the second direction is greater than the size of the first spacer in the second direction.

17. The display panel of claim 14, wherein the second spacer includes a main spacer, and a sub spacer disposed on both sides of the main spacer in the first direction, a projection of the sub spacer on the first substrate at least partially overlaps a projection of one of the plurality of gate lines on the first substrate.

18. The display panel of claim 17, wherein, the sub spacer includes a plurality of sub-spacers disposed in the second direction.

19. The display panel of claim 17 or 18, wherein, The sub-spacers are located at a higher level than the main-spacers in the third direction.

20. The display panel of claim 14, wherein, Each of the first spacers arranged in the same row in the second direction is aligned in the second direction, At least one second spacer and other second spacers arranged in the same row in the second direction are misaligned in the second direction.

21. A display device comprising the display panel according to any one of claims 11 to 20.

22. An electronic device comprising the display device according to claim 21.

23. A method for manufacturing an array substrate, comprising: preparing a substrate; preparing a stack structure on the substrate; and forming a plurality of first substrate spacers through the stack structure, wherein the array substrate comprises a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, a height of the stack structure arranged in the spacing region is greater than a height of the stack structure arranged in the pixel opening region, the plurality of first substrate spacers are arranged in the spacing region, and forming a plurality of first substrate spacers through the stack structure comprises forming a metal spacer layer on an upper portion of the stack structure in the spacing region where the plurality of first substrate spacers are to be formed by a metal exposure process.

24. A method for manufacturing a display panel, comprising: preparing a first substrate, comprising: preparing a first substrate; preparing a stack structure on the first substrate; and forming a plurality of first substrate spacers through the stack structure, preparing a second substrate, comprising: preparing a second substrate; preparing a black matrix on the second substrate; and preparing a plurality of second substrate spacers on the black matrix, aligning the first substrate and the second substrate to form the display panel, wherein the plurality of first substrate spacers correspond one-to-one to the plurality of second substrate spacers, the first substrate comprises a plurality of pixel opening regions and a spacing region between adjacent pixel opening regions, a height of the stack structure arranged in the spacing region is greater than a height of the stack structure arranged in the pixel opening region, the plurality of first substrate spacers are arranged in the spacing region, and forming a plurality of first substrate spacers through the stack structure comprises forming a metal spacer layer on an upper portion of the stack structure in the spacing region where the plurality of first substrate spacers are to be formed by a metal exposure process.

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