Display control method, apparatus, and system

Abstract

Provided in the embodiments of the present application are a display control method, an apparatus, and a system. The method comprises: a Sink end controlling, on the basis of a synchronization signal, a Source end to transmit a new image frame or a self-refresh signal to the Sink end, wherein the self-refresh signal is used for indicating that the new image frame is a repeated image frame. The Sink end can receive the new image frame or the self-refresh signal, and can display the new image frame or an old image frame received last time. In this way, when an image frame is repeated, the Source end can control, by means of the self-refresh signal, the Sink end to execute a self-refresh operation, thereby effectively reducing transmission overheads of the Source end and the Sink end, and reducing system power consumption.

Description

Display control method, device and system

[0001] The present application claims priority to the Chinese patent application No. 202411038766.9, filed on July 30, 2024, and entitled "Display control method, device and system", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of media technology, in particular to a display control method, device and system. BACKGROUND

[0003] Organic light emitting diode (OLED) display screens are widely used in terminal devices in the display field, such as mobile phones, televisions and navigation devices, etc. When the OLED display screen is idle, the prior art usually adopts the method of reducing the display frame rate to reduce the power consumption of the OLED display screen. SUMMARY

[0004] The present application provides a display control method, device and system. In the method, through the synchronization signal and the self-refresh signal, the self-refresh of the display screen can be realized, and the power consumption of the device is reduced.

[0005] In a first aspect, the present application provides a display control method. The method comprises: a sink end sending a first synchronization signal, the first synchronization signal being used to indicate that a source end starts to transmit a new image frame; the sink end receiving a first image frame transmitted by the source end in response to the first synchronization signal, caching the first image frame into a frame buffer, and displaying the first image frame in the frame buffer; the sink end sending a second synchronization signal to the source end, the second synchronization signal being used to indicate that the source end starts to transmit a new image frame or a self-refresh signal; if a self-refresh signal transmitted by the source end is received, the first image frame cached in the frame buffer is displayed based on the self-refresh signal, the self-refresh signal being used to indicate that the new image frame is the same as the first image frame; if the self-refresh signal transmitted by the source end is not received and a second image frame transmitted by the source end is received, the second image frame is cached into the frame buffer, and the second image frame cached in the frame buffer is displayed; the second image frame is different from the first image frame. In this way, in the case that the new image frame is the same as the image frame cached by the sink end, the source end can make the sink end realize self-refresh of the image frame based on the self-refresh signal, i.e., the sink end displays the old image frame cached in the cache. The source end and the sink end do not need to interact with the new image frame again, thereby avoiding repeated transmission of the repeated image frame, effectively reducing transmission overhead and interface overhead. Moreover, in the case that the sink end does not receive the new image frame again, the sink end displays the old image frame cached last time, does not need to perform image refreshing operation on the frame buffer, and can reduce processing overhead of the sink end, thereby reducing power consumption of the sink end and further reducing overall power consumption of the system.

[0006] Exemplarily, the sink end can be a TCON, a chip where the TCON is located, a display driving board or a display screen. The sink end can also be referred to as a receiving end or a display end.

[0007] Exemplarily, the source end can be a processor, a chip where the processor is located, a mainboard or a host. The source end can also be referred to as a transmitting end or an image generating end.

[0008] Exemplarily, the first image frame and the second image frame can be continuous image frames or non-continuous image frames.

[0009] In a possible implementation, the method for displaying the first image frame cached in the Frame Buffer comprises: displaying the first image frame cached in the Frame Buffer based on the self-refresh signal, which comprises: displaying the first image frame at a first time. The method for sending the second synchronization signal to the Source end comprises: sending the second synchronization signal to the Source end at a second time before the first time; the first time is separated from the second time by a specified time length. In this way, in the case of dynamic transformation of the display frame rate, the Sink end sends the synchronization signal at the time corresponding to the specified time length before the display time of each image frame, so that the sending frequency of the synchronization signal is consistent with the display frame rate, and thus the Source end can also transmit image frames or self-refresh signals to the Sink end according to the display frame rate (which can be equal or approximately equal) through the synchronization signal, so as to avoid sending repeated data and further reduce power consumption while gradually reducing the display frame rate.

[0010] For example, the first time can be understood as the display time of the new image frame. The display time of the image frame corresponds to the occurrence time of the anode reset pulse signal. For example, the first time can be the T7 time in FIG. 7.

[0011] For example, the display frame rate can also be referred to as the frame rate of the display frame or the frame frequency of the display frame. The display frame is the displayed image frame. The display frame rate can be understood as the screen refresh frequency of the display screen. The higher the display frame rate, the better the visual effect and the higher the power consumption. Conversely, the lower the display frame rate, the lower the power consumption.

[0012] In a possible implementation, if the self-refresh signal sent by the Source end is received, the first image frame cached in the Frame Buffer is displayed based on the self-refresh signal, which comprises: receiving the self-refresh signal sent by the Source end at a third time, and the third time is between the second time and the first time. In this way, through the synchronization signal, the Source end can timely send image frames or self-refresh signals, so that the Sink end can timely display the image frames corresponding to the display time of the image frames (which can be the first image frame or the second image frame), and avoid the problem of frame freezing.

[0013] In a possible implementation, the second synchronization signal is sent to the Source end, comprising: sending the second synchronization signal to the Source end based on the display frame rate. Illustratively, the display frame rate is switched in a descending trend, thereby realizing switching from a high frame rate to a low frame rate to avoid the problem of picture flicker caused by direct switching. The display time of each image frame is aligned with the anode reset pulse occurrence time. The display frame rate of each image frame is Nth of the anode reset frequency. In the process of gradually decreasing the display frame rate, the display frame rate maintains the descending trend and is still Nth of the anode reset frequency. The sending frequency of the synchronization signal is the same as the display frame rate, thereby enabling the Source end to also transmit image frames or self-refresh signals based on the display frame rate, and realizing frequency synchronization between the Sink end and the Source end.

[0014] In a possible implementation, the second synchronization signal is sent to the Source end, comprising: sending the second synchronization signal to the Source end based on the display frame rate. Illustratively, the display frame rate is switched in a descending trend, thereby realizing switching from a high frame rate to a low frame rate to avoid the problem of picture flicker caused by direct switching. The display time of each image frame is aligned with the anode reset pulse occurrence time. The display frame rate of each image frame is Nth of the anode reset frequency. In the process of gradually decreasing the display frame rate, the display frame rate maintains the descending trend and is still Nth of the anode reset frequency. The sending frequency of the synchronization signal is the same as the display frame rate, thereby enabling the Source end to also transmit image frames or self-refresh signals based on the display frame rate, and realizing frequency synchronization between the Sink end and the Source end.

[0015] In a possible implementation, the second synchronization signal is sent to the Source end, comprising: sending the second synchronization signal to the Source end based on the display frame rate. Illustratively, the display frame rate is switched in a descending trend, thereby realizing switching from a high frame rate to a low frame rate to avoid the problem of picture flicker caused by direct switching. The display time of each image frame is aligned with the anode reset pulse occurrence time. The display frame rate of each image frame is Nth of the anode reset frequency. In the process of gradually decreasing the display frame rate, the display frame rate maintains the descending trend and is still Nth of the anode reset frequency. The sending frequency of the synchronization signal is the same as the display frame rate, thereby enabling the Source end to also transmit image frames or self-refresh signals based on the display frame rate, and realizing frequency synchronization between the Sink end and the Source end.

[0016] In a possible implementation, the second synchronization signal is sent to the Source end, comprising: sending the second synchronization signal to the Source end based on the display frame rate. Illustratively, the display frame rate is switched in a descending trend, thereby realizing switching from a high frame rate to a low frame rate to avoid the problem of picture flicker caused by direct switching. The display time of each image frame is aligned with the anode reset pulse occurrence time. The display frame rate of each image frame is Nth of the anode reset frequency. In the process of gradually decreasing the display frame rate, the display frame rate maintains the descending trend and is still Nth of the anode reset frequency. The sending frequency of the synchronization signal is the same as the display frame rate, thereby enabling the Source end to also transmit image frames or self-refresh signals based on the display frame rate, and realizing frequency synchronization between the Sink end and the Source end.

[0017] In a possible implementation, if the second image frame is the same as the first image frame, the Sink end sends a self-refresh signal to the Source end, including: at a third time, the Sink end sends the self-refresh signal to the Source end, the third time being between the second time and the first time.

[0018] In a third aspect, the present application provides a display control method. The method includes: a target Sink end sending a first synchronization signal to a Source end, the first synchronization signal being used to instruct the Source end to start transmitting a new image frame; the Source end sending a first image frame to the Sink end in response to the received first synchronization signal; the Sink end receiving the first image frame, caching the first image frame into a frame buffer, and displaying the first image frame in the frame buffer; the Sink end sending a second synchronization signal to the Source end, the second synchronization signal being used to instruct the Source end to start transmitting a new image frame or a self-refresh signal; the Source end sending a self-refresh signal to the Sink end in response to the second synchronization signal, the self-refresh signal being used to instruct that the second image frame is the same as the first image frame, if the second image frame is the same as the first image frame; the Sink end displaying the cached first image frame in the frame buffer in response to the received self-refresh signal; and the Source end sending a second image frame to the Sink end, if the second image frame is not the same as the first image frame; the Sink end receiving the second image frame, caching the second image frame into the frame buffer, and displaying the cached second image frame in the frame buffer.

[0019] In a possible implementation, the Sink end sends the second synchronization signal to the Source end, including: the Sink end sending the second synchronization signal to the Source end based on a display frame rate.

[0020] In a possible implementation, the Sink end sends the second synchronization signal to the Source end, including: the Sink end sending the second synchronization signal to the Source end based on an anode reset frequency; and the Source end responding to the second synchronization signal, including: the Source end judging whether the current time is a time for sending the second image frame or the self-refresh signal based on the display frame rate; the Source end sending the self-refresh signal to the Sink end, if the second image frame is the same as the first image frame, including: the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is the same as the first image frame, the Source end sends the self-refresh signal to the Sink end; and the Source end sending the second image frame to the Sink end, if the second image frame is not the same as the first image frame, including: the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is not the same as the first image frame, the Source end sends the second image frame to the Sink end.

[0021] In a fourth aspect, the present application provides a display control device, characterized in that the device is applied to a target sink end and comprises one or more processors, a memory, and one or more computer programs, wherein the one or more computer programs are stored in the memory and, when the computer programs are executed by the one or more processors, cause the device to perform the following steps: sending a first synchronization signal to a source end, the first synchronization signal being used to instruct the source end to start transmitting a new image frame; receiving a first image frame sent by the source end in response to the first synchronization signal, caching the first image frame in a frame buffer, and displaying the first image frame in the frame buffer; sending a second synchronization signal to the source end, the second synchronization signal being used to instruct the source end to start transmitting a new image frame or a self-refresh signal; if a self-refresh signal sent by the source end is received, displaying the first image frame cached in the frame buffer based on the self-refresh signal, the self-refresh signal being used to instruct that the new image frame is the same as the first image frame; and if no self-refresh signal sent by the source end is received and a second image frame sent by the source end is received, caching the second image frame in the frame buffer, and displaying the second image frame cached in the frame buffer, the second image frame being different from the first image frame.

[0022] In a possible implementation, when the computer programs are executed by the one or more processors, the device is caused to perform the following steps: at a first time, displaying a first image frame; at a second time before the first time, sending a synchronization signal to the source end; and the first time is separated from the second time by a specified time length.

[0023] In a possible implementation, when the computer programs are executed by the one or more processors, the device is caused to perform the following steps: at a third time, receiving a self-refresh signal sent by the source end, the third time being between the second time and the first time.

[0024] In a possible implementation, when the computer programs are executed by the one or more processors, the device is caused to perform the following steps: sending the second synchronization signal to the source end based on a display frame rate.

[0025] In a fifth aspect, the present application provides a display control device, characterized in that the device is applied to a source end and comprises one or more processors, a memory, and one or more computer programs, wherein the one or more computer programs are stored in the memory and, when the computer programs are executed by the one or more processors, cause the device to perform the following steps: receiving a first synchronization signal sent by a target sink end, the first synchronization signal being used to instruct the source end to start transmitting a new image frame; in response to the first synchronization signal, sending a first image frame to the sink end, so that the sink end displays the first image frame; receiving a second synchronization signal sent by the sink end, the second synchronization signal being used to instruct the source end to start transmitting a new image frame or a self-refresh signal; in response to the second synchronization signal, if a second image frame is the same as the first image frame, sending a self-refresh signal to the sink end, the self-refresh signal being used to instruct that the second image frame is the same as the first image frame, so that the sink end displays the first image frame; if the second image frame is different from the first image frame, sending the second image frame to the sink end, so that the sink end displays the second image frame.

[0026] In a possible implementation, when the computer programs are executed by the one or more processors, the device is caused to perform the following steps: determining, based on a display frame rate, whether a current time is a time for sending a second image frame or a self-refresh signal; if the current time is the time for sending the second image frame or the self-refresh signal and the second image frame is the same as the first image frame, sending the self-refresh signal to the sink end; if the current time is the time for sending the second image frame or the self-refresh signal and the second image frame is different from the first image frame, sending the second image frame to the sink end.

[0027] In a possible implementation, when the computer programs are executed by the one or more processors, the device is caused to perform the following steps: at a second time before a first time, receiving a second synchronization signal; the first time is a time for the sink end to display the first image frame or the second image frame, and the first time is separated from the second time by a specified time length.

[0028] In a possible implementation, when the computer programs are executed by the one or more processors, the device is caused to perform the following steps: at a third time, sending a self-refresh signal to the sink end, the third time being between the second time and the first time.

[0029] In a sixth aspect, the present application provides a display control system, characterized in that comprising: a target Sink end, configured to send a first synchronization signal to a source Source end, the first synchronization signal being used to instruct the Source end to start transmitting a new image frame; the Source end, configured to send a first image frame to the Sink end in response to the received first synchronization signal; the Sink end, configured to receive the first image frame, cache the first image frame into a frame buffer Frame Buffer, and display the first image frame in the Frame Buffer; the Sink end, configured to send a second synchronization signal to the Source end, the second synchronization signal being used to instruct the Source end to start transmitting a new image frame or a self-refresh signal; the Source end, configured to send a self-refresh signal to the Sink end in response to the second synchronization signal, the self-refresh signal being used to instruct that the second image frame is the same as the first image frame; the Sink end, configured to display the cached first image frame in the Frame Buffer in response to the received self-refresh signal; the Source end, configured to send a second image frame to the Sink end if the second image frame is not the same as the first image frame; and the Sink end, configured to receive the second image frame, cache the second image frame into the Frame Buffer, and display the cached second image frame in the Frame Buffer.

[0030] In a possible implementation, the Sink end is configured to send the second synchronization signal to the Source end based on a display frame rate.

[0031] In a possible implementation, the Sink end is configured to: send the second synchronization signal to the Source end based on an anode reset frequency; and the Source end is configured to respond to the second synchronization signal by: determining, by the Source end based on the display frame rate, whether the current time is a time for sending the second image frame or the self-refresh signal; sending the self-refresh signal to the Sink end if the second image frame is the same as the first image frame, including: if the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is the same as the first image frame, sending the self-refresh signal to the Sink end; and sending the second image frame to the Sink end if the second image frame is not the same as the first image frame, including: if the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is not the same as the first image frame, sending the second image frame to the Sink end.

[0032] In a seventh aspect, the present application provides an electronic device, comprising a timing controller TCON and a processor, the TCON being configured to execute instructions of the method in the first aspect or any possible implementation manner of the first aspect, and the processor being configured to execute instructions of the method in the second aspect or any possible implementation manner of the second aspect.

[0033] In an eighth aspect, an embodiment of the present application provides a computer readable medium for storing a computer program, the computer program comprising instructions for executing the method in the first aspect or any possible implementation manner of the first aspect.

[0034] In a ninth aspect, an embodiment of the present application provides a computer readable medium for storing a computer program, the computer program comprising instructions for executing the method in the second aspect or any possible implementation manner of the second aspect.

[0035] In a tenth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation manner of the first aspect.

[0036] In an eleventh aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the second aspect or any possible implementation manner of the second aspect.

[0037] In a twelfth aspect, an embodiment of the present application provides a chip comprising a processing circuit and a transceiving pin. The transceiving pin and the processing circuit communicate with each other through an internal connection path. The processing circuit executes the method in the first aspect or any possible implementation manner of the first aspect to control the receiving pin to receive a signal and control the sending pin to send a signal.

[0038] In a thirteenth aspect, an embodiment of the present application provides a chip comprising a processing circuit and a transceiving pin. The transceiving pin and the processing circuit communicate with each other through an internal connection path. The processing circuit executes the method in the first aspect or any possible implementation manner of the first aspect to control the receiving pin to receive a signal and control the sending pin to send a signal. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is a schematic diagram of an electronic device;

[0040] FIG. 2 is a schematic diagram of a hardware structure of an electronic device;

[0041] FIG. 3 is a schematic diagram of a structure of an electronic device;

[0042] FIG. 4 is a schematic diagram of an interface;

[0043] FIG. 5 is a schematic diagram of a processing of Frame dimming;

[0044] FIG. 6 is a schematic diagram of a flow of a display control method according to an embodiment of the present application;

[0045] FIG. 7 is a timing diagram of a display control method.

[0046] FIG. 8 is a timing diagram of an example of a display control method;

[0047] FIG. 9 is a structural schematic diagram of an example of a display control device. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application.

[0049] The present application provides a display control method. The method can be applied to an electronic device, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial electronic device product, etc. The consumer electronic product is, for example, a mobile phone, a pad, a notebook computer, an e-book, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a drone, etc. The home electronic product is, for example, a smart door lock, a television, a remote controller, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), etc. The vehicle-mounted electronic product is, for example, a vehicle-mounted navigation device, a vehicle-mounted high-density digital video disc (DVD), etc. The financial electronic device product is, for example, an automated teller machine (ATM), a self-service electronic device, etc. The present application does not specially limit the specific form of the above-mentioned electronic device.

[0050] FIG. 1 is a schematic diagram of an example of an electronic device. Referring to FIG. 1, the electronic device includes but is not limited to a display module 10, a housing 11, a camera module, etc.

[0051] For example, the housing 11 can be configured with a mainboard, which can include but is not limited to a printed circuit board (PCB) or a flexible printed circuit (FPC). The display module 10 can be mounted on the housing 11 and coupled with the PCB or the FPC.

[0052] The display module 11 can include, but is not limited to, a display driving board (also referred to as a display driver or a display driving chip) and at least one display screen. In some embodiments, the display screen is optionally an organic light emitting diode (OLED) display screen, a micro OLED display screen, a quantum dot light emitting diode (QLED) display screen, or the like, which can realize self-luminous display.

[0053] FIG. 2 is a schematic diagram of a hardware structure of an electronic device, which is shown as an example. Referring to FIG. 2, the electronic device includes, but is not limited to, a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a loudspeaker 170A, a receiver 170B, a microphone 170C, a headset interface 170D, a sensor module 180, a camera 193, a display screen 194, and the like. It should be understood that the electronic device shown in FIG. 2 is only an example of the electronic device, and the electronic device can have more or fewer components than those shown in the figure, two or more components can be combined, or can have a different component configuration. The various components shown in FIG. 2 can be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application-specific integrated circuits.

[0054] The electronic device can include, but is not limited to, a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a loudspeaker 170A, a receiver 170B, a microphone 170C, a headset interface 170D, a sensor module 180, a camera 193, a display screen 194, and the like.

[0055] The processor 110 can include one or more processing units. For example, the processor 110 can include, but is not limited to, a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), and the like. Different processing units can be independent devices or integrated into one or more processors.

[0056] The processor 110 can also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory can hold instructions or data that the processor 110 has just used or is using repeatedly. If the processor 110 needs to use the instructions or data again, it can call them directly from the memory. This avoids repeated access and reduces the latency of the processor 110, thus improving the efficiency of the system.

[0057] In some embodiments, the processor 110 can include one or more interfaces. The interfaces can include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0058] The charging management module 140 is configured to receive charging input from a charger. The charger can be a wireless charger or a wired charger. In some embodiments of wired charging, the charging management module 140 can receive charging input from a wired charger through the USB interface 130. In some embodiments of wireless charging, the charging management module 140 can receive wireless charging input through a wireless charging coil of the electronic device 100. The charging management module 140 can charge the battery 142 while also supplying power to the electronic device through the power management module 141.

[0059] The power management module 141 is configured to connect the battery 142 and the charging management module 140 to the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 110, the internal memory 121, the external memory, the display 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 can also be configured to monitor parameters such as the battery capacity, the number of battery cycles, the battery health status (leakage, impedance), and the like. In some embodiments, the power management module 141 can also be disposed in the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 can also be disposed in the same device.

[0060] The wireless communication function of the electronic device 100 can be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor, and the baseband processor, and the like.

[0061] The antenna 1 and the antenna 2 are configured to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 can be configured to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example, the antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in combination with a tuning switch.

[0062] The mobile communication module 150 can provide a solution for wireless communication including 2G / 3G / 4G / 5G and the like applied to the electronic device 100. The mobile communication module 150 can include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), and the like. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, filter, amplify, and the like the received electromagnetic waves, and transmit the processed signals to the modem processor for demodulation. The mobile communication module 150 can also amplify signals modulated by the modem processor and radiate the signals as electromagnetic waves through the antenna 1. In some embodiments, at least part of the functional modules of the mobile communication module 150 can be disposed in the processor 110. In some embodiments, at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 can be disposed in the same device.

[0063] The modem processor can include a modulator and a demodulator. The modulator is configured to modulate a low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is configured to demodulate a received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. The low-frequency baseband signal, after being processed by the baseband processor, is transmitted to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a microphone 170B, etc.), or displays an image or a video through the display screen 194. In some embodiments, the modem processor can be a separate device. In other embodiments, the modem processor can be independent of the processor 110 and be disposed in the same device as the mobile communication module 150 or other functional modules.

[0064] The wireless communication module 160 can provide a wireless communication solution including a wireless local area network (WLAN) (such as a wireless fidelity (Wi-Fi) network), Bluetooth (BT), a global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, and the like, which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives an electromagnetic wave via the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signal, and transmits the processed signal to the processor 110. The wireless communication module 160 can also receive a signal to be transmitted from the processor 110, perform frequency modulation and amplification thereon, and convert the signal into electromagnetic wave radiation via the antenna 2.

[0065] The electronic device implements a display function through a GPU, the display screen 194, and an application processor, etc. The GPU is a microprocessor for image processing, which is connected to the display screen 194 and the application processor. The GPU is configured to perform mathematical and geometric calculations for graphics rendering. The processor 110 can include one or more GPUs, which execute program instructions to generate or change display information.

[0066] The display screen 194 is configured to display images, videos, and the like. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flex light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light emitting diodes (QLED), or the like.

[0067] In some embodiments, the electronic device can include one or N display screens 194, where N is a positive integer greater than 1.

[0068] The electronic device 100 can implement the photographing function through the ISP, the camera 193, the video codec, the GPU, the display screen 194, and the application processor, and the like.

[0069] The ISP is configured to process the data fed back by the camera 193. For example, when taking a photo, the shutter is opened, the light is transmitted to the camera photosensitive element through the lens, the light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing to convert it into an image visible to the naked eye. The ISP can also optimize the noise, brightness, and skin color of the image. The ISP can also optimize the exposure, color temperature, and other parameters of the shooting scene. In some embodiments, the ISP can be disposed in the camera 193.

[0070] The camera 193 is configured to capture still images or videos. An object generates an optical image through a lens and projects it onto a photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into a standard RGB, YUV, or the like format image signal. In some embodiments, the electronic device 100 can include one or N cameras 193, where N is a positive integer greater than 1.

[0071] The digital signal processor is used to process digital signals, in addition to being able to process digital image signals, it can also process other digital signals. For example, when the electronic device selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy, etc.

[0072] The video codec is used to compress or decompress digital video. The electronic device 100 can support one or more video codecs. In this way, the electronic device 100 can play or record videos in multiple encoding formats, such as: moving picture experts group (MPEG) 1, MPEG 2, MPEG 3, MPEG 4, etc.

[0073] The NPU is a neural-network (NN) calculation processor, which can quickly process input information by drawing on the structure of a biological neural network, such as drawing on the transmission mode between human brain neurons, and can also continuously self-learn. Through the NPU, the electronic device 100 can realize intelligent cognition applications such as image recognition, face recognition, voice recognition, text understanding, etc.

[0074] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to realize data storage functions. For example, music, video, etc. Files are saved in the external memory card.

[0075] The internal memory 121 can be used to store computer executable program codes, which include instructions. The processor 110 executes various function applications and data processing of the electronic device 100 by running the instructions stored in the internal memory 121. The internal memory 121 can include a program storage area and a data storage area. The program storage area can store an operating system, at least one application program required by a function (such as a sound playing function, an image playing function, etc.), etc. The data storage area can store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (UFS), etc.

[0076] The electronic device 100 can realize audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor, etc. For example, music playing, recording, etc.

[0077] In the embodiments of the present application, the OLED display screen supports adaptive multi-grade frame rate dynamic switching technology. The frame rate can be referred to as frame frequency, that is, frame rate. The display frame rate involved in the embodiments of the present application is the frame rate (or frame frequency) corresponding to the display frame. The display frame can also be referred to as a display image frame, that is, the image frame displayed by the display screen. In some examples, the display frame rate can also be understood as the refresh frequency of the image of the display screen, that is, the screen refresh rate. The screen refresh rate refers to the number of times the display screen updates the image per second. Correspondingly, the display frame rate is the number of images displayed by the display screen per second. For example, a display frame rate of 120 Hz means that the display screen can refresh the screen image 120 times per second, that is, 120 image frames (or can be understood as image data or image content corresponding to the image frame) per second. It should be noted that in the embodiments of the present application, the display time of each image frame is the same, that is, the display time of each image frame remains unchanged during the dynamic switching of the display frame rate of the display screen.

[0078] In an electronic device, the frame rate greatly affects the style and viewing experience of a video. Different frame rates will bring different viewing experiences. For example, in the fields of games, movies, computer graphics, etc., high display frame rate means smoother motion and better visual experience. For real-time interactive content such as games, higher display frame rate can reduce the sense of delay and improve operation response speed.

[0079] In the embodiments of the present application, the electronic device can dynamically switch the display frame rate based on the display scenario. For example, in some examples, when the user uses a scenario that does not require a high display frame rate (such as desktop mode or reading mode, etc.), the electronic device can reduce the display frame rate of the display screen to reduce the power consumption of the electronic device. The reduction of the display frame rate of the display screen also reduces the rendering frame rate of the processor of the electronic device. Alternatively, the rendering frame rate of the processor can also be referred to as the rate of rendering image frames, or can be understood as the frequency at which the processor generates image frames, or can also be understood as the frequency at which the processor transmits image frames to the display screen. Alternatively, the rendering frame rate of the processor is the same as the display frame rate of the display screen to avoid screen freezing and other problems.

[0080] In other examples, when the user uses a scenario that requires a high display frame rate (such as game mode or video mode), the electronic device can increase the display frame rate of the display screen to improve the visual effect.

[0081] However, when the display screen of the electronic device is directly switched from a higher display frame rate to a lower display frame rate, flicker of the display screen will occur. For example, the highest display frame rate of an OLED display screen is 240Hz, and the lowest display frame rate is 1Hz. When the electronic device directly switches the display screen from the highest frame rate 240Hz to 1Hz, flicker of the picture will occur, affecting the user's viewing experience.

[0082] It should be noted that the various frequency values and time length values involved in the embodiments of the present application are exemplary examples, which can be set according to actual needs, and the present application is not limited, which will not be repeated hereinafter.

[0083] To solve the above problems, the existing display screen usually adopts a frame transition (also known as gradual transition) technology, which gradually switches from a high display frame rate to a low display frame rate by gradually decreasing (or also known as gradually decreasing) the gear.

[0084] The display control method provided in the embodiments of the present application can realize the image frame self-refreshing mode of the display screen through the synchronization signal and the self-refreshing signal, so as to avoid repeatedly interacting with the same image frame, thereby further reducing the power consumption (including image processing power consumption and image frame transmission power consumption between the mainboard and the display screen) of the electronic device in the case that the display screen is in a low display frame rate (which can also be understood as a low refresh rate or a low image refresh rate).

[0085] FIG. 3 is a structural schematic diagram of an electronic device, which is exemplarily shown. Please refer to FIG. 3, which includes but is not limited to a display screen 310, a display driving board 320, and a mainboard 330.

[0086] The mainboard 330 includes but is not limited to a processor 331 and the like. The related description of the processor can be referred to the above, which will not be repeated here.

[0087] The display driving board 320 includes but is not limited to a timing controller (TCON) 332, a power module (or a power chip, not shown in the figure) and the like.

[0088] Exemplarily, the processor 331 is electrically connected with the TCON 332, and the TCON is electrically connected with the display screen. The display driving board 320 can optionally provide at least one of a power signal, a control signal, an initialization signal and a data signal required for the pixel circuit in the display screen to emit light. The display driving board 320 can optionally be a display driver integrated circuit (DDIC).

[0089] In some examples, the main board and the display screen can be integrated together, i.e., an all-in-one display screen such as a tablet, a smart screen, etc. In other examples, the main board and the display screen can be independent, such as a notebook computer, a vehicle-mounted device, etc.

[0090] In some examples, the main board and the display driving board are optionally a main chip and a display driving chip, respectively, which can be integrated on one circuit board. They can also be on different circuit boards and electrically connected.

[0091] Optionally, the processor described in the present application can refer to one or more processor units (such as a central processing unit (CPU), an application processor (AP), etc.) on the main board, or can refer to a processor including the TCON and one or more processor units (such as a central processing unit (CPU), an application processor (AP), etc.) on the main board, and the present application does not make any limitation.

[0092] FIG. 4 is an exemplary interface schematic diagram. Referring to FIG. 4, in the embodiment of the present application, the processor 331 and the TCON 332 can be connected through at least one interface. For example, the interface 1-1 of the processor 331 is connected to the interface 2-2 of the TCON 332, the interface 1-2 of the processor 331 is connected to the interface 2-2 of the TCON 332, and the interface 1-3 of the processor 331 is connected to the interface 2-3 of the TCON 332.

[0093] In one example, the interface 1-1 and the interface 2-1 are an embedded display interface (Embedded DisplayPort, eDP). The eDP interface is a fully digital interface based on the DisplayPort architecture and protocol, which can be applied to the communication interface of the display screen of a notebook computer, a tablet computer, a computer, etc., and has the characteristics of large bandwidth and low power consumption. High-resolution and high-frame-rate display screens mostly use the eDP interface for image data transmission between the processor 331 of the main board and the display driving board of the display screen.

[0094] In the embodiment of the present application, the processor 331 can send an image frame (which can also be referred to as an image, image data, etc., and the present application does not make any limitation) to the TCON 332 through the interface 1-1. The TCON 332 receives the image frame through the interface 2-1. In some examples, the processor 331 and the TCON 332 can also interact some control signals based on the interface 1-1 and the interface 2-1, and the present application does not make any limitation.

[0095] For example, the TCON 332 can send a synchronization signal to the processor 331 through the interface 2-2, which is used to indicate that a new image frame starts to be transmitted, and can also be understood as that the TCON 332 can receive a new image frame. The processor 331 receives the synchronization signal through the interface 1-2.

[0096] For example, the processor 331 can send a self-refresh signal to the TCON 332 through the interface 1-3, which is used to indicate that a new image frame is the same as a previously transmitted image frame, and can also be understood as that the new image frame is a repeated image frame. The self-refresh signal can also be understood as being used to instruct the TCON 332 to perform a self-refresh operation. In the embodiment of the present application, the self-refresh refers to that the display screen displays an image frame that is cached most recently in the Frame Buffer. The TCON 332 receives the self-refresh signal through the interface 2-3 and performs the self-refresh operation. The specific process can be referred to the following embodiments.

[0097] Optionally, in some instances, the processor 331 can also send the self-refresh signal to the interface 2-1 of the TCON 332 through an existing interface (for example, the interface 1-1), and / or the TCON 332 can send the synchronization signal to the processor 331 through an existing interface, which is not limited in the present application. That is, the processor 331 and the TCON 332 in the electronic device can multiplex the eDP interface to transmit the self-defined synchronization signal and the self-refresh signal. For example, the processor 331 and the TCON 332 can transmit the synchronization signal and the self-refresh signal through a reserved field (or a reserved code word) defined in the eDP interface protocol, which can be set according to actual needs, which is not limited in the present application.

[0098] In the embodiment of the present application, the TCON 332 includes but is not limited to a Frame Buffer (frame cache or frame buffer) for caching an image frame. Optionally, one image frame is cached in the Frame Buffer. When the TCON 332 caches a newly received image frame in the Frame Buffer, the TCON 332 covers the image frame previously cached in the Frame Buffer. This step can be referred to as Frame Buffer refreshing, or image frame refreshing.

[0099] In order for those skilled in the art to better understand the scheme in the embodiment of the present application, first, the Frame dimming technology is briefly described:

[0100] Fig. 5 is a schematic diagram of frame dimming, as shown in Fig. 5, when a user uses a desktop or reads, the sink (target) end switches to an idle state. It can be understood that in the desktop mode, the plurality of image frames displayed by the display screen are all the same. In the case of displaying the same image frames, the power consumption of the source (source) end and the sink end can be reduced by reducing the display frame rate. In the embodiment of the present application, the sink end, which can also be referred to as the receiving end or the image receiving end, can be a display screen, a TCON or a chip where the TCON is located. The source end, which can also be referred to as the sending end or the image generating end, can be a host, a motherboard, a processor or a chip where the processor is located.

[0101] Referring to Fig. 5, the anode reset frequency of the electronic device is f (denoted as sub_frm_cnt), for example, 240 Hz (may also be 360 Hz, etc., which is only an illustrative example, and can be set according to actual needs, and the present application is not limited). As shown in Fig. 5, the anode reset frequency is 240 Hz, that is, the electronic device generates 240 anode reset pulse signals (denoted as r_SGL) per second.

[0102] In the embodiment of the present application, the display frame rate (i.e. the refresh rate of the display screen) is associated with the anode reset frequency. Alternatively, the display frame rate of the display screen is equal to the anode reset frequency, or is N times of the anode reset frequency, N is a positive integer. For example, in the case of an anode reset frequency of 240 Hz, the display frame rate of the display screen can be 240 Hz, 120 Hz, 80 Hz, 60 Hz, 30 Hz, 1 Hz, etc., and the present application is not limited. That is, the display screen can display 240 image frames per second, or 120 image frames, etc., and the present application is not limited.

[0103] For example, as shown in Fig. 5, the display frame rate can also be understood as the inverse ratio of the time length (i.e. the total time length) between the left edge (i.e. the starting time) of the image frame of the sink end and the left edge of the next image frame. For example, the starting time (i.e. the left edge of each image frame in Fig. 5) of each image frame is aligned with an anode pulse reset signal. Therefore, it can also be understood that the time length between the anode pulse signal corresponding to the starting time of the image frame and the anode pulse signal corresponding to the starting time of the next image frame is the total time length of the image frame, and the inverse ratio is the display frame rate of the image frame.

[0104] In the embodiments of the present application, the total duration of the image frame is equal to the display duration of the image frame. For example, the duration of the screen displaying the image frame F0 is the total duration corresponding to the image frame F0, which is inversely proportional to the display frame rate. For example, the display time of each image frame corresponds to the start time of each image frame described above, and is aligned with the anode reset pulse signal.

[0105] Optionally, the total duration of each image frame includes but is not limited to the frame length and the blank duration. For example, the frame length of each image frame is equal, that is, the frame length of each image frame remains unchanged regardless of the change of the display frame rate.

[0106] In the embodiments of the present application, the characteristics of the display screen include a large amplitude difference between the high display frame rate and the low display frame rate. For example, the highest display frame rate of the OLED display screen is optionally 240Hz, and the lowest display frame rate is 1Hz. As described above, if the display frame rate of the display screen is directly switched from 240Hz to 1Hz, the screen flickering problem will occur. In the Frame dimming technology, a gradual decrease, also known as a step-by-step decrease, is used to gradually reduce the display frame rate, and the screen flickering problem caused by high and low frequency switching is overcome by slowly reducing the display frame rate. During the gradual decrease of the display frame rate, the display frame rate is always associated with the anode reset frequency, that is, the display frame rate after each decrease is optionally one Nth of the anode reset frequency. Optionally, in the Frame Dimming technology, the gradual decrease of the display frame rate can be continuous or gentle. For example, the display frame rate can be decreased according to the rule of 120Hz, 80Hz, 60Hz, and 30Hz. In some examples, the display frame rate can also be decreased according to the rule of 120Hz, 80Hz, 60Hz, 60Hz, and 30Hz, which can be set according to actual needs, and the present application is not limited. In addition, the amplitude of the gradual decrease can be set according to actual needs, and the present application is not limited.

[0107] Still referring to FIG. 5, the Source transmits the image frame to be displayed (i.e., the display image frame, referred to as the display frame for short) to the Sink before the display time corresponding to each display frame, so that the Sink can display the corresponding image frame when the display time arrives (i.e., the time corresponding to the anode reset pulse). For example, T2 is the display time of the image frame F0 (the first image frame F0 in the figure), and accordingly, the Source transmits the image frame F0 to the Sink before T2, for example, at T1.

[0108] The Sink receives the image frame F0 and caches the image frame F0 into a Frame Buffer. At T2, the Sink outputs the image frame F0 in the Frame Buffer to a display screen. The display screen displays the image frame F0. The current display frame rate of the Sink is 120 Hz, that is, the display frame rate corresponding to the image frame F0 is 120 Hz, which can also be understood as the rendering frame rate (i.e., the rate of rendering image frames) of the Source is 120 Hz.

[0109] Optionally, in the scenario of gradually decreasing display frame rate, the display frame rate gradually decreases according to the rule of 120 Hz, 80 Hz, 60 Hz, 60 Hz, and so on.

[0110] In this example, taking the desktop scenario as an example, the image frames generated by the Source are all repeated image frames, for example, all are the image frame F0. In the embodiments of the present application, the repeated image frames are optionally the same in image data (or image content). Taking the second image frame F0 as an example, the display frame rate decreases to 80 Hz, that is, the display frame rate corresponding to the second image frame F0 is 80 Hz, that is, the total time length corresponding to the second image frame is greater than the total time length of the first image frame F0, and in the case of constant frame length, the BLANK time length of the second image frame is enlarged. The other descriptions are similar to those of the first image frame F0, which will not be described here.

[0111] As shown in FIG. 5, the display frame rates of the subsequent image frames decrease or remain unchanged and then decrease in turn. Optionally, the display frame rate can decrease to the lowest display frame rate, for example, 1 Hz, or decrease to any value before the lowest display frame rate, for example, 30 Hz. The actual requirements can be set, and the present application is not limited. Moreover, the specific decreasing gradient and amplitude can be set according to actual requirements, and the present application is not limited.

[0112] FIG. 6 is a flow diagram of a display control method provided in the embodiments of the present application, which is shown as an example. Please refer to FIG. 6, which specifically includes but is not limited to the following steps:

[0113] S601, the Sink sends a synchronization signal to the Source.

[0114] For example, the Sink sends a synchronization signal to the Source, which is optionally denoted as a Req_Sync signal. The synchronization signal is used to instruct the Source to start transmitting a new image frame or a self-refresh signal, which can also be understood as instructing to start transmitting the next image frame, and can also be understood as being used to instruct the Sink to start receiving a new image frame (or the next image frame).

[0115] Specifically, the Sink end sends a synchronization signal to the Source end at a second time point before a display time point (denoted as a first time point) corresponding to the next image frame. The first time point and the second time point are separated by a preset time length t1. The preset time length is a result of negotiation between the Source end and the Sink end, and can be set according to actual needs, which is not limited in the present application.

[0116] In a possible implementation, the Sink end sends the synchronization signal at a display frame rate, that is, the transmission frequency of the synchronization signal is equal to the display frame rate, and both are associated with the anode reset frequency (that is, one Nth of the anode reset frequency). In an example, the display frame rate gradually decreases at idle time, and therefore, the transmission interval of the synchronization signal satisfies the gradual decrease rule of the display frame. It can be understood that, in the embodiments of the present application, the display frame rate and the transmission interval of the synchronization signal are both associated with the anode reset frequency. The display frame rate decreases according to a gradually decreasing trend, and the display frame rate after each decrease is one Nth of the anode reset frequency. Correspondingly, the transmission interval of the synchronization signal remains consistent with the display frame rate. That is, in the process of dynamic switching of the display frame rate, the transmission interval of the synchronization signal is switched at the same frequency. The Sink end can enable the Source end to transmit image frames (or self-refresh signals) according to the dynamic switching frequency of the display frame rate (that is, the gradual decrease rule) through the synchronization signal. The transmission frequency of the image frames or the self-refresh signals of the Source end (referring to the frequency corresponding to the combination of the image frames and the self-refresh signals) is synchronized with the frame rate of the display frame (that is, the screen refresh rate), so as to avoid the problem of frame freezing.

[0117] Optionally, in this example, when the Source end detects that the display screen switches to an idle state (for example, including but not limited to a desktop state or a reading state), the Source end sends idle state indication information to the Sink end, to indicate that the display screen switches to the idle state. Correspondingly, the Sink end gradually switches the current high display frame rate to a low display frame rate in response to the received idle state indication information.

[0118] In another possible implementation, the Sink end sends the synchronization signal at the anode reset frequency, that is, the transmission frequency of the synchronization signal is equal to the anode reset frequency. In this scenario, the Source end can control the Sink end to gradually switch from a high display frame rate to a low display frame rate through the self-refresh signal. The specific description can be referred to below.

[0119] S602, the Source end identifies whether the new image frame is a repeated image frame.

[0120] For example, the Source end receives the synchronization signal. The Source end determines that the Sink end can receive the next image frame, or determines that the next image frame can be sent to the Sink end in response to the synchronization signal.

[0121] In the idle mode such as the desktop mode or the reading mode, a plurality of continuous image frames can be repeated image frames, i.e., the image data (which can also be understood as image content) of the image frames is the same, in the embodiment of the present application. The Source end can identify whether the image frames are repeated image frames. Specifically, after the Source end generates (i.e., renders) an image frame, the image frame to be sent is placed in the cache (for example, a cache queue) of the Source end. When the Source end receives a synchronization signal and is ready to send a new image frame, i.e., the next image frame, which can also be understood as the image frame at the head of the cache queue, the Source end can identify whether the new image frame (i.e., the image frame to be sent) is the same image frame as the image frame that is sent last time.

[0122] Optionally, the image frame that is sent last time can be sent based on the last synchronization signal or can be sent at an interval of at least one synchronization signal, which is not limited in the present application.

[0123] In the embodiment of the present application, the image frame that is sent last time by the Source end can also be understood as the image frame (for example, the first image frame involved in the embodiment of the present application) currently cached by the Frame Buffer of the Sink end. That is, before the Frame Buffer is refreshed, the image frame cached by the Frame Buffer is the image frame that is sent last time by the Source end to the Sink end (i.e., the image frame that is received last time by the Sink end). The identification manner of the image frame can be the pixel-by-pixel identification manner, which is not limited in the present application.

[0124] In one example, if the Source end identifies that the new image frame is a repeated image frame, i.e., the new image frame is the same as the image frame that is sent last time (which can also be understood as the first image frame currently cached by the Frame Buffer or the image frame that is received last time by the Sink end), S605 is performed.

[0125] In another example, if the Source end identifies that the new image frame is not a repeated image frame, S603 is performed.

[0126] In a possible implementation manner, if the synchronization signal is sent according to the display frame rate, the Source end can identify whether the image frame is a repeated image frame after receiving the synchronization signal, to determine whether to send the next image frame or the self-refresh signal to the Sink end.

[0127] In another possible implementation, as described above, if the sink end sends the synchronization signal according to the anode reset frequency, that is, the sending frequency of the synchronization signal is equal to the anode reset frequency. In this scenario, after the source end receives the synchronization signal, it can determine whether the current time is the time for sending the next image frame or the self-refresh signal based on the display frame rate. In one example, if the current time is not the time for sending the next image frame or the self-refresh signal, the source end does not perform processing, and accordingly, the sink end does not receive the next image frame or the self-refresh signal, and the sink end maintains the current processing state (for example, it can display the image frame obtained at the last time). In another example, if the current time is the time for sending the next image frame or the self-refresh signal, the source end determines whether the next image frame is a repeated image frame, and performs subsequent steps based on the determination result to send the next image frame or the self-refresh signal. That is, in this example, the source end can control the sink end to gradually switch from a high display frame rate to a low display frame rate through the self-refresh signal.

[0128] S603, the source end sends a self-refresh signal to the sink end.

[0129] For example, the source end sends a self-refresh signal to the sink end, which can be denoted as a self_refresh signal. The self-refresh signal is used to indicate that the new image frame is the same as the image frame that is sent last time (which can also be understood as the first image frame that is currently cached in the frame buffer and that is received by the sink end last time), or it can also be understood as being used to instruct the sink end to perform a self-refresh operation. In the embodiments of the present application, the self-refresh operation can be referred to S604.

[0130] S604, the sink end displays the first image frame cached in the frame buffer.

[0131] For example, the sink end displays the first image frame cached in the frame buffer in response to the received self-refresh signal, that is, the image frame received last time.

[0132] S606, the source end sends a second image frame to the sink end.

[0133] For example, if the source end identifies that the new image frame (for example, the second image frame) is not a repeated image frame, that is, the first image frame is different from the second image frame, the source end sends the second image frame to the sink end.

[0134] S606, the sink end displays the second image frame cached in the frame buffer.

[0135] For example, when the Sink end does not receive the self-refresh signal and receives the second image frame, the Sink end stores the second image frame in the Frame Buffer and replaces the previously stored image frame, and displays the second image frame currently stored in the Frame Buffer.

[0136] FIG. 7 is a timing diagram of an exemplary display control method. The display control method shown in FIG. 6 is described in detail below in combination with FIG. 7. Referring to FIG. 7, in this example, the Sink end sends the synchronization signal (denoted as req_sync) at a display frame rate, i.e., the interval of sending the synchronization signal is associated with (or equal to) the display frame rate.

[0137] Specifically, after the display screen switches to the idle state (e.g., the desktop mode), the Source end sends the idle state indication information to the Sink end, and the Sink end gradually reduces the display frame rate according to a preset descending gradient (or gear) in response to the idle state indication information. In this example, the idle state is taken as an example of descending at gears of 120 Hz, 80 Hz, 60 Hz, 60 Hz, 30 Hz, and 1 Hz, with the highest display frame rate being 120 Hz (i.e., one-half of the anode reset frequency). Among them, 30 Hz and 1 Hz are not shown in FIG. 7.

[0138] Still referring to FIG. 7, at time T1, the Source end sends the req_sync signal to the Sink end, indicating that the Sink end can start transmitting the next image frame (i.e., the new image frame in the embodiments of the present application) or the self-refresh signal. The time of sending the req_sync signal and the time of the anode reset pulse signal corresponding to the start time of the new image frame are separated by a preset time t, which can be set according to actual needs, and is not limited in the present application. For example, the interval between time T1 and time T3 is t, time T1 is the time of sending the req_sync signal, and time T3 is the time of the anode reset pulse signal corresponding to the start time of the new image frame. In this way, as described above, the reciprocal of the time interval between the start time of the image frame and the start time of the next image frame is the display frame rate of the image frame, and the time interval between each req_sync signal and the next req_sync signal is fixed, and the reciprocal of the time interval between the req_sync signal and the next req_sync signal is equal to the display frame rate.

[0139] Alternatively, as shown in FIG. 4, the TCON can output a high level to the processor through the interface 2-2, and the processor receives the high level through the interface 1-2 to determine that the synchronization signal is received.

[0140] Please continue to refer to FIG. 7, the Source end judges whether the new image frame (for example, image frame F0) is a repeated image frame in response to the received req sync signal. In this example, the image frame F0 is the first image frame involved in the embodiments of the present application. Alternatively, if the image frame F0 is the first image frame sent by the Source end to the Sink end, it can be directly sent to the Sink end without judging whether it is a repeated frame.

[0141] For example, the Source end sends the image frame F0 to the Sink end. The Sink end receives the image frame F0 and caches the image frame F0 into the Frame Buffer. At T3, the Sink end displays the image frame F0. Between T3 and T7, the display frame rate corresponding to the image frame F0 (referred to as the first image frame F0 for the sake of distinction from subsequent image frames F0) is 120 Hz. That is, between T3 and T7, the Sink end displays the image frame data corresponding to the image frame F0. The total time length of the processing of the first image frame F0 between T3 and T7 includes the frame length of the first image frame F0 and the blank time length.

[0142] For example, the Source end gradually reduces the display frame rate according to the gear described above, for example, the display frame rate corresponding to the current image frame (i.e., the first image frame described in the embodiments of the present application) is 120 Hz.

[0143] Specifically, the Source end sends the req sync signal to the Sink end at T4. The Source end judges whether the new image frame (i.e., the second image frame) is the same as the image frame F0 (which can also be understood as the image frame sent last time) in response to the received req sync signal, i.e., whether the new image frame is a repeated image frame. The transmission frequency corresponding to T4 and T8 is the display frame rate corresponding to the second image frame F0, for example, 80 Hz.

[0144] If they are the same, the self refresh signal (denoted as self refresh) is sent.

[0145] If they are different, the new image frame (i.e., the second image frame) is sent. In the case that the Sink end does not receive the self refresh signal and receives the new image frame, the Sink end caches the received image frame into the Frame Buffer and displays the new image frame (i.e., the second image frame) currently cached in the Frame Buffer, for example, the image frame F1, which is not shown in the figure. The processing manner of the Sink end can refer to the image frame F0, which is not described herein again.

[0146] In this example, the new image frame is the same as the image frame F0, and at the T5 moment, the Source end sends a self-refresh signal to the Sink end, indicating that the new image frame is the same as the image frame F0, which can also be understood as the image data or image content corresponding to the two image frames being the same.

[0147] For example, the Sink end receives the self-refresh signal self_refresh. At the T7 moment, the Sink end displays the image frame F0 cached in the Frame Buffer. Specifically, the TCON outputs the first image frame cached in the Frame Buffer to the display screen for display, i.e., the display screen displays the image frame F0 at the T7 moment.

[0148] In this example, the new image frame is the same as the image frame F0, and at the T5 moment, the Source end sends a self-refresh signal to the Sink end, indicating that the new image frame is the same as the image frame F0, which can also be understood as the image data or image content corresponding to the two image frames being the same.

[0149] In the scenario shown in FIG. 7, the T7 moment is the first moment described in the embodiments of the present application, the T4 moment is the second moment described in the embodiments of the present application, and the T5 moment is the third moment described in the embodiments of the present application. The T5 moment is any moment between the T4 and T6 moments, which is not limited in the present application.

[0150] For example, as shown in FIG. 4, the processor can output a high level to the TCON through the interface 1-3, and the TCON receives the high level through the interface 2-3 to determine that the self_refresh signal is received.

[0151] That is, as shown in FIG. 7, after the Source end receives the req_sync signal and identifies that the new image frame is a repeated image frame, the Source does not send the image frame, but instructs the Sink end to perform the self-refresh operation through the self-refresh signal. That is, the self-refresh operation of the Sink end can be understood as that the Sink end displays based on the old image frame cached by itself, without receiving the new image frame or refreshing the Frame Buffer based on the new image frame.

[0152] Optionally, there can be a certain time delay between the rising edge of the self_refresh signal and the falling edge of the req_sync. The moments, time lengths, and frequencies in FIG. 7 are only illustrative examples, which are not limited in the present application.

[0153] Please continue to refer to FIG. 7, for example, the display frame rate corresponding to the current image frame (i.e., the second image frame in the embodiments of the present application) is 60 Hz.

[0154] Specifically, the Source end sends a req sync signal to the Sink end at T8. The Source end judges whether the new image frame (i.e., the second image frame) is the same as the image frame F0 (which can also be understood as the image frame sent last) in response to the received req sync signal, i.e., whether the new image frame is a repeated image frame. The transmission frequency corresponding to the time period between T8 and T10 is the display frame rate corresponding to the third image frame F0, for example, 60 Hz.

[0155] If the same, a self refresh signal (denoted as self refresh) is sent.

[0156] If different, the new image frame (i.e., the second image frame) is sent. In the case that the Sink end does not receive the self refresh signal and receives the new image frame, the Sink end caches the received image frame into the Frame Buffer, and displays the new image frame (i.e., the second image frame) currently cached in the Frame Buffer, for example, the image frame F1, which is not shown in the figure. The processing manner of the Sink end can refer to the image frame F0, which will not be described here. It can be understood that the second image frame in the embodiments of the present application can refer to the second image frame F0, or the third image frame F0, etc., which is not limited in the present application.

[0157] In this example, the new image frame is the same as the image frame F0, and the Source end sends a self refresh signal to the Sink end, which is used to indicate that the new image frame is the same as the image frame F0, which can also be understood as that the image data or image content corresponding to the two image frames is the same.

[0158] For example, the Sink end receives the self refresh signal self refresh. At T9, the Sink end displays the image frame F0 cached in the Frame Buffer. The display frame rate corresponding to the image frame F0 (which is referred to as the third image frame F0 for the sake of distinction from the subsequent image frame F0) between T9 and T11 is 60 Hz. That is, between T9 and T11, the Sink end displays the image frame data corresponding to the image frame F0. The total time length of the third image frame F0 between T9 and T11 includes the frame length of the third image frame F0 and the blank time length.

[0159] In the scenario shown in FIG. 7, the time corresponding to the third image frame F0 and any subsequent image frame can also correspond to the first time, the second time, the third time, etc. described in the embodiments of the present application, which are not limited in the present application.

[0160] For example, as shown in FIG. 4, the processor can output a high level to the TCON through the interface 1-3, and the TCON receives the high level through the interface 2-3 and determines that the self refresh signal is received.

[0161] That is, as shown in FIG. 7, after the Source receives the req sync signal and identifies that the new image frame is a repeated image frame, the Source does not send the image frame, but instructs the Sink to perform the self refresh operation through the self refresh signal. It can be understood that in the process of reducing the display frame rate, the TCON receives the image frame F0 only once, and the image frame displayed by the TCON for each screen refresh is the image frame F0 received last time. That is, the self refresh operation of the Sink can be understood as that the Sink displays based on the old image frame cached by itself, without receiving a new image frame and refreshing the Frame Buffer based on the new image frame. The processing of other image frames can refer to the first image frame F0 and the second image frame F0, which are not limited in the present application.

[0162] In a possible implementation, when in the non-idle state, for example, the Sink switches from the desktop mode to the video mode, i.e. in the case of a high display frame rate, the Sink and the Source can still interact through the synchronization signal. In this example, the transmission interval corresponding to the synchronization signal is still associated with the display frame rate, i.e. the synchronization signal is sent at the time corresponding to the preset time length before the display time corresponding to each display frame rate. The processing manner is the same as the transmission and display manner of the image frame F0, which is not described herein again. Alternatively, in the case of a high display frame rate, the Source can still instruct the operations of S602-S606. That is, in the case of a high frame rate, if there are consecutive repeated image frames, the Sink can also be instructed to perform the self refresh operation through the self refresh signal. Of course, in some examples, in the case of a low frame rate (i.e. the display frame rate is kept at a low frame rate and remains unchanged), the operations of S602-S606 can also be performed. It can be understood that in the case of non-dynamic switching of the display frame rate, the present application is still applicable.

[0163] Fig. 8 is a timing diagram of an example of the display control method. Referring to Fig. 8, in this example, the sink can send a sync signal based on the frequency of the anode pulse signal. After receiving the sync signal, the source can determine whether the current time is the time for sending a new image frame (e.g., the second image frame) or a self-refresh signal based on the display frequency. In one example, if yes, the source sends a new image frame or a self-refresh signal. If no, the source does not send an image frame or a self-refresh signal. Referring to Fig. 8, the sink sends a sync signal req sync at T1 according to the anode reset pulse frequency (e.g., 240 Hz). Specifically, the sink sends the sync signal req sync to the source at T1. The specific description can be referred to Fig. 7, which will not be repeated here. After detecting that the display screen switches to the idle state, the source can determine the reduction gear of the display frame rate and control the sink to reduce the display frame rate based on the sending interval of the self-refresh signal or the image frame. The processing of the image frame F0 can be referred to the above, which will not be repeated here. Alternatively, if the image frame F0 is the first displayed image frame, the source can send the image frame F0 to the sink directly after receiving the sync signal without performing the judgment process. Of course, the source can also perform the judgment process. The judgment process can be referred to below, which will not be repeated here.

[0164] Still referring to Fig. 8, in an example, at T12, the sync signal trigger time arrives. That is, the time length between T1 and T12 is inversely proportional to 240 Hz, which can also be understood as the sending frequency of each sync signal being 240 Hz. The source sends the req sync signal to the sink.

[0165] The source receives the req sync signal. Based on the display frame rate, the source determines whether the current time is the time for sending an image frame or a self-refresh signal. Specifically, based on the current display frame rate (i.e., 120 Hz), the source determines that the time for sending the next image frame or a self-refresh signal has not arrived, and the source does not send an image frame or a self-refresh signal. The sink does not receive a self-refresh signal or an image frame, and continues to process the image frame F0 as described in Fig. 7.

[0166] At T4, the sync signal trigger time arrives. The sink sends the req sync signal. The source receives the req sync signal and determines whether the current time is the time for sending an image frame or a self-refresh signal. Based on the current display frame rate (i.e., 120 Hz), the source determines that the current time is the time for sending an image frame or a self-refresh signal. That is, the time length between the sending time of the previous image frame (or a self-refresh signal) (i.e., T1) and the current time (i.e., T4) is inversely proportional to 120 Hz.

[0167] The Source further judges whether the new image frame (i.e., the second image frame) is a repeated image frame, and based on the judgment result, transmits the second image frame or the self-refresh signal. Details can be referred to FIG. 7, which will not be repeated here. For example, as described above, the Source transmits the image frame or the self-refresh signal at a preset time length before each image frame display time point. Correspondingly, after the Sink receives the image frame or the self-refresh signal, the Sink can display the new image frame or the old image frame at a time point corresponding to the most recently arrived anode reset pulse signal. In this way, the Source can further control the display frame rate of the Sink by controlling the transmission frequency of the image frame or the self-refresh signal.

[0168] At T13 and T14, the Source transmits the synchronization signals respectively. After receiving the two synchronization signals, the Sink judges the transmission time point of the non-image frame or the self-refresh signal based on the current display frame rate (for example, 80 Hz), and the Sink does not respond. The Source does not receive the image frame or the self-refresh signal, and continues to perform the current processing.

[0169] At T8, the synchronization signal triggering time point arrives. The Sink transmits the req sync signal. The Source receives the req sync signal, and judges whether the current time point is the transmission time point of the image frame or the self-refresh signal. Based on the current display frame rate (i.e., 80 Hz), the Source judges that the current time point is the transmission time point of the image frame or the self-refresh signal. That is, the reciprocal of the time length between the transmission time point of the last image frame (or the self-refresh signal) (i.e., T4) and the current time point (i.e., T8) is 80 Hz.

[0170] The Source further judges whether the new image frame (i.e., the second image frame) is a repeated image frame, and based on the judgment result, transmits the second image frame or the self-refresh signal. Details can be referred to FIG. 7, which will not be repeated here.

[0171] FIG. 9 shows a schematic block diagram of a display control device 900 according to an embodiment of the present application. The display control device can include a processor 901 and a transceiver / transceiver pin 902, and optionally further include a memory 903. The processor 901 can be configured to perform the steps performed by the mainboard or the display driving board in the methods of the foregoing embodiments, and control the receiving pin to receive signals and the transmitting pin to transmit signals.

[0172] The various components of the display control device 900 are coupled together by a bus system 904, which can include a data bus, a power bus, a control bus, and a state signal bus. For the sake of clarity, the various buses are illustrated in FIG. 9 as the bus system 904.

[0173] Optionally, the memory 903 can be used for storing instructions in the foregoing method embodiments.

[0174] It should be understood that the display control apparatus 900 according to the embodiments of the present application can correspond to the processor or TCON in each method of the foregoing embodiments, and can also correspond to the mainboard or display driving board, and can also correspond to the host or display screen, and the foregoing and other management operations and / or functions of each element in the display control apparatus 900 are respectively for realizing the corresponding steps of the foregoing each method, and for the sake of brevity, will not be repeated here.

[0175] Wherein, all the related contents of each step involved in the foregoing method embodiments can be cited to the function description of the corresponding function module, and will not be repeated here.

[0176] Based on the same technical concept, the embodiments of the present application further provide a computer readable storage medium, which stores a computer program, the computer program contains at least one code, the at least one code can be executed by a display control apparatus to control the display control apparatus to realize the foregoing method embodiments. The display control apparatus can be a processor, a chip where the processor is located or a host. The display control apparatus can also be a TCON, a display driving board or a display screen.

[0177] Based on the same technical concept, the embodiments of the present application further provide a computer program, when the computer program is executed by a display control apparatus, to realize the foregoing method embodiments. The display control apparatus can be a processor, a chip where the processor is located or a host. The display control apparatus can also be a TCON, a display driving board or a display screen.

[0178] The program can be stored in whole or in part on a storage medium packaged together with the processor, or in part or in whole on a storage medium not packaged together with the processor.

[0179] Based on the same technical concept, the embodiments of the present application further provide a processor, which is used to realize the foregoing method embodiments. The foregoing processor can be a chip.

[0180] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable media, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. Alternatively, the processor and the storage medium can be located in a remote terminal. The processor and the storage medium can also be located in a server that is in communication with a remote terminal. The processor and the storage medium can comprise one or more components of exemplary computer system 800.

[0181] Those skilled in the art can readily recognize that the functions described in one or more examples above can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a general purpose or special purpose computer.

[0182] The steps of methods or algorithms described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. Alternatively, the processor and the storage medium can be located in a remote terminal. The processor and the storage medium can also be located in a server that is in communication with a remote terminal. The processor can execute software modules stored in a storage medium that can reside in the remote terminal, an ASIC or a server. Those of skill in the art will further appreciate that the mechanisms described herein, while possibly characterized as software, can be implemented in hardware.

[0183] Those skilled in the art will recognize that the functions described in one or more examples above can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a general purpose or special purpose computer.

[0184] The term "and / or", merely describes association relationship of associated objects, and indicates that three relationships can exist, for example, A and / or B can indicate that A exists alone, A and B exist together, and B exists alone.

[0185] The terms "first" and "second" and the like in the specification and claims of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.

[0186] In the embodiments of the present application, the word "exemplary" or "for example" is used to mean serving as an example, instance, or illustration. Any implementation or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being preferred or advantageous over other implementations or design solutions. Rather, the use of "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0187] In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more unless otherwise specified. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0188] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative, but are not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope of protection of the claims, and all belong to the protection of the present application.

Claims

1. A display control method characterized by comprising: The method comprises: sending a first synchronization signal to a source end, the first synchronization signal being used to instruct the source end to start transmitting a new image frame; receiving a first image frame sent by the source end in response to the first synchronization signal, caching the first image frame into a frame buffer, and displaying the first image frame in the frame buffer; sending a second synchronization signal to the source end, the second synchronization signal being used to instruct the source end to start transmitting a new image frame or a self-refresh signal; if a self-refresh signal sent by the source end is received, displaying the first image frame cached in the frame buffer based on the self-refresh signal, the self-refresh signal being used to instruct that the new image frame is the same as the first image frame; if the self-refresh signal sent by the source end is not received, and a second image frame sent by the source end is received, caching the second image frame into the frame buffer, and displaying the second image frame cached in the frame buffer, the second image frame being different from the first image frame.

2. The method of claim 1, wherein, The displaying of the first image frame cached in the frame buffer based on the self-refresh signal comprises: displaying the first image frame at a first time point; The sending of the second synchronization signal to the source end comprises: sending the second synchronization signal to the source end at a second time point before the first time point, the first time point being separated from the second time point by a specified time length.

3. The method of claim 2, wherein, The displaying of the first image frame cached in the frame buffer based on the self-refresh signal comprises: receiving the self-refresh signal sent by the source end at a third time point, the third time point being between the second time point and the first time point.

4. The method according to any one of claims 1 to 3, characterized in that, The sending of the second synchronization signal to the source end comprises: sending the second synchronization signal to the source end based on a display frame rate.

5. A display control method characterized by comprising: The method comprises: receiving a first synchronization signal sent by a target sink end, the first synchronization signal being used to instruct a source end to start transmitting a new image frame; sending the first image frame to the sink end in response to the first synchronization signal, so that the sink end displays the first image frame; receiving a second synchronization signal sent by the sink end, the second synchronization signal being used to instruct the source end to start transmitting a new image frame or a self-refresh signal; sending a self-refresh signal to the sink end in response to the second synchronization signal, if a second image frame is the same as the first image frame, the self-refresh signal being used to instruct that the second image frame is the same as the first image frame, so that the sink end displays the first image frame; If the second image frame is different from the first image frame, the second image frame is sent to the Sink end, so that the Sink end displays the second image frame.

6. The method of claim 5, wherein, The response to the second synchronization signal includes: Based on the display frame rate, it is determined whether the current time is the time for sending the second image frame or the self-refresh signal; If the second image frame is the same as the first image frame, a self-refresh signal is sent to the Sink end, including: If the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is the same as the first image frame, a self-refresh signal is sent to the Sink end; If the second image frame is different from the first image frame, the second image frame is sent to the Sink end, including: If the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is different from the first image frame, the second image frame is sent to the Sink end.

7. The method of claim 5, wherein, The second synchronization signal sent by the Sink end is received, including: At a second time point before a first time point, the second synchronization signal is received; the first time point is the time point at which the Sink end displays the first image frame or the second image frame, and the first time point is separated from the second time point by a specified time length.

8. The method of claim 7, wherein, If the second image frame is the same as the first image frame, a self-refresh signal is sent to the Sink end, including: At a third time point, the self-refresh signal is sent to the Sink end, and the third time point is between the second time point and the first time point.

9. A display control method characterized by comprising: Including: The target Sink end sends a first synchronization signal to the source Source end, and the first synchronization signal is used to instruct the Source end to start transmitting a new image frame; The Source end sends the first image frame to the Sink end in response to the received first synchronization signal; The Sink end receives the first image frame, caches the first image frame into a frame buffer Frame Buffer, and displays the first image frame in the Frame Buffer; The Sink end sends a second synchronization signal to the Source end, and the second synchronization signal is used to instruct the Source end to start transmitting a new image frame or a self-refresh signal; The Source end sends a self-refresh signal to the Sink end in response to the second synchronization signal if the second image frame is the same as the first image frame, and the self-refresh signal is used to indicate that the second image frame is the same as the first image frame; The Sink end displays the first image frame cached in the Frame Buffer in response to the received self-refresh signal; If the second image frame is different from the first image frame, the Source end sends the second image frame to the Sink end; The Sink end receives the second image frame, caches the second image frame into the Frame Buffer, and displays the second image frame cached in the Frame Buffer.

10. The method of claim 9, wherein, The Sink end sends a second synchronization signal to the Source end, including: The Sink end sends a second synchronization signal to the Source end based on the display frame rate.

11. The method of claim 9, wherein, The Sink end sends a second synchronization signal to the Source end, including: The Sink end sends a second synchronization signal to the Source end based on the anode reset frequency. The Source end responds to the second synchronization signal, including: The Source end determines whether the current time is the time for sending the second image frame or the self-refresh signal based on the display frame rate. If the second image frame is the same as the first image frame, the Sink end is sent a self-refresh signal, including: If the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is the same as the first image frame, the Sink end is sent a self-refresh signal. If the second image frame is not the same as the first image frame, the Sink end is sent the second image frame, including: If the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is not the same as the first image frame, the Sink end is sent the second image frame.

12. A display control device characterized by comprising: Applied to a target Sink end, including: One or more processors; Memory; And one or more computer programs, wherein the one or more computer programs are stored on the memory, when the computer programs are executed by the one or more processors, the device performs the following steps: Send a first synchronization signal to the Source end, the first synchronization signal is used to indicate that the Source end starts to transmit a new image frame; Receive the first image frame sent by the Source end in response to the first synchronization signal, cache the first image frame into a frame buffer, and display the first image frame in the frame buffer; Send a second synchronization signal to the Source end, the second synchronization signal is used to indicate that the Source end starts to transmit a new image frame or a self-refresh signal; If the self-refresh signal sent by the Source end is received, display the first image frame cached in the frame buffer based on the self-refresh signal; the self-refresh signal is used to indicate that the new image frame is the same as the first image frame; If the self-refresh signal sent by the Source end is not received, and the second image frame sent by the Source end is received, cache the second image frame into the frame buffer, and display the second image frame cached in the frame buffer; the second image frame is not the same as the first image frame.

13. The apparatus of claim 12, wherein, When the computer programs are executed by the one or more processors, the device performs the following steps: At a first time, display the first image frame; At a second time before the first time, send the synchronization signal to the Source end; the first time and the second time are separated by a specified time length.

14. The apparatus of claim 13, wherein, When the computer program is executed by the one or more processors, the apparatus performs the following steps: At a third time, receiving the self-refresh signal sent by the Source end, the third time being between the second time and the first time.

15. The apparatus of any one of claims 12 to 14, wherein, When the computer program is executed by the one or more processors, the apparatus performs the following steps: Based on the display frame rate, sending a second synchronization signal to the Source end.

16. A display control device, characterized by comprising: Applied to a Source end, comprising: One or more processors; Memory; And one or more computer programs, wherein the one or more computer programs are stored on the memory, when the computer program is executed by the one or more processors, the apparatus performs the following steps: Receiving a first synchronization signal sent by a target Sink end, the first synchronization signal being used to instruct the Source end to start transmitting a new image frame; In response to the first synchronization signal, sending the first image frame to the Sink end, so that the Sink end displays the first image frame; Receiving a second synchronization signal sent by the Sink end, the second synchronization signal being used to instruct the Source end to start transmitting a new image frame or a self-refresh signal; In response to the second synchronization signal, if a second image frame is the same as the first image frame, sending a self-refresh signal to the Sink end, the self-refresh signal being used to instruct that the second image frame is the same as the first image frame, so that the Sink end displays the first image frame; If the second image frame is not the same as the first image frame, sending the second image frame to the Sink end, so that the Sink end displays the second image frame.

17. The apparatus of claim 16, wherein, When the computer program is executed by the one or more processors, the apparatus performs the following steps: Based on the display frame rate, judging whether the current time is the time for sending the second image frame or the self-refresh signal; If the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is the same as the first image frame, sending a self-refresh signal to the Sink end; If the current time is the time for sending the second image frame or the self-refresh signal, and the second image frame is not the same as the first image frame, sending the second image frame to the Sink end.

18. The apparatus of claim 16, wherein, When the computer program is executed by the one or more processors, the apparatus performs the following steps: At a second time before a first time, receiving the second synchronization signal; the first time being the time for the Sink end to display the first image frame or the second image frame, the first time being spaced apart from the second time by a specified time length.

19. The apparatus of claim 18, wherein, When the computer program is executed by the one or more processors, the apparatus performs the following steps: At a third time, sending the self-refresh signal to the Sink end, the third time being between the second time and the first time.

20. A display control system characterized by comprising: Comprising: a target Sink end configured to send a first synchronization signal to a source Source end, the first synchronization signal being used to indicate the Source end to start transmitting a new image frame; the Source end configured to send the first image frame to the Sink end in response to the received first synchronization signal; the Sink end configured to receive the first image frame, cache the first image frame into a frame buffer, and display the first image frame in the frame buffer; the Sink end configured to send a second synchronization signal to the Source end, the second synchronization signal being used to indicate the Source end to start transmitting a new image frame or a self-refresh signal; the Source end configured to send a self-refresh signal to the Sink end in response to the second synchronization signal, the self-refresh signal being used to indicate that the second image frame is the same as the first image frame, if the second image frame is the same as the first image frame; the Sink end configured to display the first image frame cached in the frame buffer in response to the received self-refresh signal; the Source end configured to send the second image frame to the Sink end, if the second image frame is not the same as the first image frame; the Sink end configured to receive the second image frame, cache the second image frame into the frame buffer, and display the second image frame cached in the frame buffer.

21. A computer storage medium, comprising, computer instructions that, when executed on an electronic device, cause the electronic device to perform the method of any one of claims 1-4, or perform the method of any one of claims 5-8.

22. A computer program product, characterised in that, a computer program product that, when executed on a computer, causes the computer to perform the method of any one of claims 1-4, or perform the method of any one of claims 5-8.

23. A chip, characterized by one or more interface circuits and one or more processors; the interface circuits configured to receive signals from a memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processors execute the computer instructions, cause the electronic device to perform the method of any one of claims 1-4, or perform the method of any one of claims 5-8.

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