Method for generating a task-specific adapted topology for quantum electrodynamics (CQED)-based hardware and fabrication system implementing such a method

Abstract

The invention relates to a method for generating a task-specific adapted topology for hardware based on quantum electrodynamics (cQED), characterized in that it comprises the iterative steps of: - determining an error committed by a circuit initially obtained by transpilation of an M agnostic qubit generated using a client task; - comparing the transpiled circuit error with an error threshold corresponding to the circuit of M agnostic qubits; - if the transpiled circuit error is greater than the error threshold, modifying some of the hardware specifications to be processed in the transpilation step; - if the transpiled circuit error is less than the error threshold, supplying the transpiled circuit as a task-specific adapted topology to a chip design and nanofabrication unit.

Description

a process for generating a task-specific adapted topology for a quantum electrodynamics (cQED) based hardware and a manufacturing system implementing such a process FIELD OF INVENTION

[0001] The present invention relates to a method for generating a task-specific adapted topology for circuit and cavity quantum electrodynamics (cQED) hardware. It also relates to a cQED hardware fabrication system implementing such a method.

[0002] DEFINITIONS

[0003] Agnostic circuit: A quantum circuit is said to be agnostic when it is written as a circuit model that ignores any hardware specifics or requirements. It focuses solely on manipulating quantum information.

[0004] All-to-all connectivity (ATA): the connectivity of a processor that is represented using a complete graph is said to be all-to-all.

[0005] Connectivity: By representing a processor as a graph in which nodes represent qubits and edges represent a physical link between qubits, the connectivity of a quantum processor refers to the connectivity (in graph theory) of the graph.

[0006] Coupling map: A coupling map refers to the graphical representation of a quantum processor.

[0007] cQED material: Quantum electrodynamics-based material for circuits (or cavities) (cQED).

[0008] cQED hardware with long-range interaction: Quantum electrodynamics-based circuit (or cavity) (cQED) hardware implementing two-qubit gates with long-range interaction, e.g. mediated by a resonator.

[0009] Crosstalk: the effect of residual physical coupling between qubits when they are not supposed to undergo an operation together.

[0010] Crosstalk and routing trade-off: Trade-off between crosstalk errors occurring in cQED hardware cavity-mediated two-qubit gates and intermediate gate errors for routing information around the processor.

[0011] Fidelity: In quantum computing, fidelity quantifies how well the actual state or operation aligns with the predicted or ideal state or operation.

[0012] Gate set: The set of gates that a processor can implement is called its quantum gate set.

[0013] Inactive qubit: A qubit is said to be inactive when it is not undergoing an operation.

[0014] iSWAP: An iSWAP gate is a two-qubit gate that swaps information between two different qubits with the addition of a purely complex phase when they are in two different states. The gate does not affect the qubits if they are in the same state.

[0015] Quantum circuit: A quantum circuit refers to a model of quantum computing in which operations are broken down into quantum logic gates and an algorithm, which are represented as a sequence of such gates applied to a qubit register.

[0016] Quantum gate: In digital quantum computing, a quantum gate, or quantum logic gate, refers to an elementary quantum operation on the processor.

[0017] Routing permutations: refers to permutations that are used only to bring information to a required position in the processor, but are not part of a quantum-agnostic algorithm.

[0018] Single-qubit gate: A gate operating on a single qubit is called a single-qubit gate.

[0019] Permutations: refers to a permutation of the state of two qubits.

[0020] Topology: by representing a processor as a graph in which nodes represent qubits and edges represent the physical link between qubits, the topology of a quantum processor refers to the connectivity (in graph theory) of the graph.

[0021] Two-qubit gate: A gate operating two qubits is called a two-qubit gate.

[0022] Transpilation: Transpilation refers to the process of transforming a quantum circuit into an equivalent circuit, optimized to work on a specific quantum hardware architecture. TECHNICAL BACKGROUND

[0023] Quantum algorithms are mostly written in a hardware-agnostic way. For this reason, before execution on hardware, an algorithm must be transpiled [1]. In this step, the algorithm is first translated into the hardware's native gate set, then logical qubits from the algorithm are associated with physical qubits in the hardware, and, depending on the actual physical connections between the physical qubits, intermediate SWAP gates are added to receive any missing direct connections.

[0024] This step is routing [2, 3] which allows the processor topology to be received. Consequently, transpilation should depend on the hardware's natural logic gate set and its topology [4, 5] (and specific strategies have even been designed based on particular hardware [6]), the choice of which can strongly affect hardware performance when running the algorithm, and considering the limitations of quantum computing today, having hardware tuned to be efficient in performing a specific task is quite sensible.

[0025] cQED hardware with long-range interaction has the very interesting property of theoretically being able to interconnect distant qubits, theoretically enabling all-to-all connectivity. In other words, the qubit array can be represented as a fully connected graph. In practice, however, such all-to-all connectivity, due to residual couplings among the qubits, introduces flaws in hardware operations known as crosstalk errors.

[0026] To moderate the amount of crosstalk errors, some connections in the processor can always be removed, moving away from the all-connected processor at the cost of more complex routing. Consequently, this type of processor offers considerable freedom in how the processor topology is constructed. Although several groups [7-9], such as that of Lieven Vandersypen at Delft University of Technology

[0010] , have investigated crosstalk errors, and even more so, that of Guido Burkard at the University of Konstanz [11, 12], has conducted a similar study on crosstalk errors resulting from residual couplings, until now there has been no tool available to model and predict such errors in such a simple and accurate way.

[0027] Similarly, while routing algorithms have been proposed and are widely used during the transpilation process, for example on IBM's Qiskit platform [13, 14], and noise-adaptive or optimized-mapping compilation algorithms have also been presented [13-17], so far no one has taken advantage of an adaptable topology.

[0028] The problem to be solved can be expressed as:

[0029] Given an algorithm, a circuit-agnostic implementation (CA), an error threshold Ethr, and the set of allowed connected graphs G = {G(V,E)}, with sets of vertices and edges (V, E) for each graph, representing all allowed hardware topologies, find a graph G*(V,E) that allows the execution of CA within the limits of the error threshold Ethr, i.e., such that:

[0030] (1)

[0031] where Ecirc G(V,E) is defined as the total error rate of a circuit executed on V hardware qubits with connectivity represented by the graph G(V,E). Such a total circuit error is a function of the total circuit gate and crosstalk errors, a trade-off of which guides the choice of G*(V,E) within the limits of G. Indeed, the total circuit gate error increases with the number of routing permutations, while the crosstalk error increases with the processor connectivity.

[0032] For example, a high-connectivity graph reduces the required number of routing SWAP gates because, from any qubit, the distance to reach any other qubit is relatively small. However, a high-connectivity processor is then also affected by a greater amount of crosstalk errors.

[0033] On the other hand, a low-connectivity processor has few crosstalk errors since all the qubits are more isolated, but it is also likely to require a large number of routing SWAP gates for the same reason. The routing cost is easily quantified by the number of additional intermediate SWAP gates needed to connect distant qubits.

[0034] Among the cQED architectures to which the procedure can be applied are semiconductor spin qubits connected by an on-chip resonator, or Rydberg atoms linked by a macroscopic cavity. Spin qubits can, for example, be hosted in carbon nanotubes, such as in a double quantum dot structure.

[0035] A resonator-on-a-chip can, for example, be a coplanar waveguide, a ribbon line, or a microstrip. It can be made of a high-impedance material such as niobium nitride.

[0036] The document XP91792411AI (Ali Javadi-Abhari et al.) discloses the Qiskit® software development kit for quantum computing and a complete workflow for solving a condensed matter physics problem on a quantum computer.

[0037] The document XP34650181AI (Orenstein Aaron et al.) discloses a quantum circuit mapping using binary integer linear programming (BINLP).

[0038] US document 2019 / 018721 A1 discloses systems and methods for performing a multi-gate quantum computation on a quantum information processor.

[0039] Paper XP91463021AI (Paul D. Nation et al.) discloses a quantum circuit optimization technique that accounts for the variability in error rates inherent in current noisy quantum computing platforms. This paper addresses a different problem, does not use cost metrics or functions, and its optimization is based on the collection of calibration data.

[0040] However, none of these documents solves the aforementioned problem of finding a graph that allows the execution of an agnostic circuit within the limits of a total error threshold including crosstalk and gate errors.

[0041] This objective is achieved with a process that generates a task-specific topology, particularly for a customer task, for hardware based on the quantum electrodynamics of circuits or cavities (cQED), characterized in that it also includes iterative steps consisting of:

[0042] - determine an error committed, preferably by a circuit initially obtained by transpiling a magnostic qubit M generated from a client task, or by said transpiled circuit,

[0043] - compare said transpiled circuit error, preferably to an error threshold corresponding to said circuit of M agnostic qubits, or to said error threshold,

[0044] - if said transpiled circuit error is greater than said error threshold, modify some of said hardware specifications to be processed in the transpilation step,

[0045] - if said transpiled circuit error is less than said error threshold, provide said transpiled circuit as a task-specific, unit-specific adapted topology for chip design and nanofabrication.

[0046] The method according to the invention may further include a transpilation step of the circuit of M agnostic qubits, preferably initially generated from a client task, to generate a transpiled circuit, said transpilation step implementing hardware specifications.

[0047] The method according to the invention may further include an initial step of generating, from a client task, a circuit of M agnostic qubits and a corresponding error threshold.

[0048] The hardware specifications preferably include a set of native gates and gate errors, and / or a set of allowed technologies, and / or a coupling on / off ratio.

[0049] Preferably, the process may provide for the introduction of input data comprising a circuit of agnostic M qubits implementing an algorithm chosen from one or more, for example two or three, sets of client task adaptive topology algorithms.

[0050] In an advantageous embodiment of the invention, the generation process further comprises the steps of:

[0051] - input input data containing a C-agnostic circuit A implementing an algorithm chosen from one or more sets of task-adaptive topology algorithms (Q-Algo, AQ-Algo, RWC-algo), an algorithm error threshold Ethr, a on / off coupling ratio, and an idle qubit fidelity F I ,

[0052] - initialize, from the aforementioned input data, a translation Co of the agnostic circuit C Ain a set of hardware gates, a number N of qubits in said agnostic circuit Co and a gate fidelity FG,

[0053] - if said gate fidelity FG is greater than an algorithm fidelity threshold Fthr, iteratively calculate a new number n of qubits and a circuit fidelity Fcirc for a circuit to be transpiled, until said circuit fidelity Fcirc is greater than said algorithm fidelity threshold Fthr.

[0054] In a first algorithmic embodiment, in which the input data further include a length C A of the agnostic circuit, the initialization step further includes the initialization of the length Lo of the translated circuit material, and the calculation step further includes the calculation of a length L of the circuit to be transpiled.

[0055] In a second algorithmic embodiment, optionally compatible with the preceding algorithmic embodiment or compatible with one or more subsequent algorithmic embodiments, wherein the input data further include a predetermined optimal variation of fidelity Δ opt The process also includes the iterative steps of:

[0056] - transpile the circuit, so as to map said circuit to hardware qubits with a coupling board and to extract a new circuit length L i ,

[0057] - estimate total circuit fidelities including circuit crosstalk fidelity and calculate a variation Δ of circuit fidelity and a decoherence Δ D ,

[0058] - provided that the circuit fidelity Fcirc is greater than or equal to the calculated new circuit fidelity Fcircnew, increment / decrement the number n of qubits, until said circuit fidelity variation Δ and said decoherence Δ D are approximately equal.

[0059] In a third algorithmic embodiment optionally compatible with one of the two preceding algorithmic embodiments or compatible with one or more of the following algorithmic embodiments, wherein the input data further include a predetermined optimal variation of fidelity Δ opt The process also includes the iterative steps of:

[0060] - transpile the circuit, so as to map said circuit to hardware qubits with a wmapet coupling map to extract a new circuit length L i ,

[0061] - estimate a circuit crosstalk fidelity Fcirc,ct [G(V,E)] and a total circuit fidelity Fcirc [G(V,E)],

[0062] - if said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has decreased since the previous step, slow down the iteration and return to the wmap coupling map,

[0063] - if said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has increased since said previous step, trim edges to maximum weight and obtain a new wmapi coupling map,

[0064] - provided that the total circuit fidelity Fcirc[G(V,E)] is less than the algorithm threshold fidelity Fthr, continue the iteration on the steps above,

[0065] - if the fidelity Fcirc [G(V,E)] is greater than or equal to the algorithm threshold fidelity Fthr and the optimal variation in fidelity Δ opt is approximately equal to 0, break the iteration and choose the wmapi coupling map,

[0066] - if the optimal variation Δ opt is not equal to 0, continue the iteration until the iterative variation Δ I is greater than the optimal variation in fidelity Δ opt.

[0067] The iterative steps for each algorithmic embodiment above can be implemented as a task-adaptive topology algorithm.

[0068] The process, preferably the task-adaptive topology, can be executed on cQED hardware with long-range interaction.

[0069] The method according to the invention can be implemented to provide task-appropriate topology optimized instructions for hardware nanofabrication or for quantum simulations on hardware emulators.

[0070] According to another aspect, in particular alternative to or at least partly complementary to the first aspect, the invention proposes a method for generating a task-specific adapted topology, in particular a client task, for hardware based on the quantum electrodynamics of circuits or cavities (cQED), comprising an initial step for generating, from said task, in particular said client task, a circuit of agnostic M qubits and a corresponding error threshold, and iterative steps consisting of:

[0071] - transpile said initially generated agnostic M qubit circuit, to generate a transpiled circuit, said transpilation step implementing hardware specifications including a set of native gates and gate errors,

[0072] - to determine an error committed by said transpiled circuit,

[0073] - compare said error thus committed to an error threshold corresponding to said circuit of M agnostic qubits,

[0074] - if said transpiled circuit error is greater than said error threshold, modify some of said hardware specifications to be processed in the transpilation step,

[0075] - if said transpiled circuit error is less than said error threshold, provide said transpiled circuit as a suitable topology specific to said customer task to a chip design and nanofabrication unit.

[0076] Preferably, the process may provide for the introduction of input data comprising a circuit of agnostic M qubits implementing an algorithm chosen from one or more, for example two or three, sets of client task adaptive topology algorithms.

[0077] Preferably, the initial generation step can include the following steps:

[0078] - to input data comprising an agnostic M qubit circuit (CA), an adaptive topology algorithm chosen from one or more sets of adaptive topology algorithms for the client task (Q-Algo, AQ-Algo, RWC-algo), an algorithm error threshold (Ethr), a on / off coupling ratio, an idle qubit fidelity (FI) and a length (LA) of the agnostic circuit,

[0079] - initialize from said input data, a translation (Co) of the circuit of M agnostic qubits (CA) into a set of hardware gates, a number (N) of qubits in said circuit of M agnostic qubits (Co), a gate fidelity (FG) and the length (Lo) of the circuit to be transpiled.

[0080] In addition or as an alternative, the process may also include the steps of:

[0081] - introduce input data comprising a circuit of agnostic M qubits (CA) implementing an algorithm chosen from one or more sets of client task adaptive topology algorithms (Q-Algo, AQ-Algo, RWC-algo), an algorithm error threshold (Ethr), a on / off coupling ratio and an idle qubit fidelity (FI),

[0082] - initialize from said input data, a translation (Co) of the circuit of M agnostic qubits (CA) into a set of hardware gates, a number (N) of qubits in said circuit of M agnostic qubits (Co) and a gate fidelity (FG),

[0083] - if said gate fidelity (FG) is greater than an algorithm fidelity threshold (Fthr), iteratively calculate a new number n of qubits and a circuit fidelity (Fcirc) for a circuit to be transpiled, until said circuit fidelity (Fcirc) is greater than said algorithm fidelity threshold (Fthr).

[0084] Preferably or alternatively to the previous embodiment, the iterative steps may further include a step to iteratively calculate a new number n of qubits, a length (L) of the circuit to be transpiled and a circuit fidelity (Fcirc) for a circuit to be transpiled if said gate fidelity (FG) is greater than an algorithm fidelity threshold (Fthr), until said circuit fidelity (Fcirc) is greater than said algorithm fidelity threshold (Fthr),

[0085] these computational steps leading to a selection of a cQED topology represented by a connected graph {G(V,E)} from among allowed topologies represented by connected graphs G = {G(V,E)} allowed with sets of vertices and edges (V, E) for each graph, and to a transpilation of the hardware-agnostic circuit with these hardware specifications.

[0086] According to an algorithmic embodiment, the input data may further include a length (L A ) of the agnostic circuit, the initialization step further includes the initialization of the length (Lo) of the translated circuit material, and the calculation step further includes the calculation of a length (L) of the circuit to be transpiled.

[0087] According to a second algorithmic embodiment, optionally compatible with the preceding algorithmic embodiment or compatible with one or more of the following algorithmic embodiments, the input data may further include a predetermined optimal variation of fidelity Δopt, characterized in that it further includes the iterative steps of:

[0088] - transpile the circuit, so as to map said circuit to hardware qubits with a coupling card and to extract a new circuit length (Li,)

[0089] - estimate total circuit fidelities including circuit crosstalk fidelity and calculate a variation Δ of circuit fidelity and a decoherence (ΔD),

[0090] provided that the circuit fidelity (Fcirc) is greater than or equal to the new calculated circuit fidelity (Fcircnew), increment / decrement the number (n) of qubits, until said variation of circuit fidelity (Δ) and said decoherence (ΔD) are substantially equal.

[0091] According to a third algorithmic embodiment, optionally compatible with one of the two preceding algorithmic embodiments or compatible with one or more of the following algorithmic embodiments, the input data may further include a predetermined optimal variation of fidelity (Δopt), characterized in that it further includes the iterative steps of:

[0092] - transpile the circuit, so as to map said circuit to hardware qubits with a coupling map (wmap) and to extract a new length of circuit Li,

[0093] - estimate a circuit crosstalk fidelity Fcirc,ct [G(V,E)] and a total circuit fidelity Fcirc [G(V,E)],

[0094] - if said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has decreased since the previous step, break the iteration and return to the coupling map (wmap),

[0095] - if said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has increased since said previous step, trim the edges to maximum weight and obtain a new coupling map (wmapi),

[0096] - provided that the total circuit fidelity Fcirc[G(V,E)] is less than the algorithm threshold fidelity (Fthr), maintain the iteration during the steps above,

[0097] - if the fidelity Fcirc [G(V,E)] is greater than or equal to the algorithm threshold fidelity (Fthr) and the optimal variation in fidelity (Δopt) is approximately equal to 0, break the iteration and choose the coupling map (wmapi),

[0098] - if the optimal variation (Δopt) is not equal to 0, keep the iteration until an iterative variation (ΔI) is greater than the optimal fidelity variation (Δopt).

[0099] Preferably, the process can be performed on cQED hardware with long-range interaction.

[0100] In particular, the process can be implemented to provide task-optimized topology instructions for the nanofabrication of cQED material.

[0101] According to one variant, the method can be implemented to provide task-appropriate optimized topology instructions for quantum simulations on emulators of cQED hardware.

[0102] According to yet another aspect of the invention, a system is proposed for the manufacture of cQED material, implementing the process according to one of the preceding aspects of the invention.

[0103] According to one variant, the invention proposes a system for the nanofabrication of a material based on the quantum electrodynamics of circuits or cavities (cQED), intended to receive and process optimized instructions of topology adapted to a customer task, these instructions resulting from the execution of the topology generation process according to any of the preceding characteristics of one of the preceding aspects of the invention.

[0104] The present invention thus provides three task-adaptive topology (TAT) algorithms to adjust the topology of cQED hardware with long-range interaction to a given task, optimizing crosstalk errors, instead of considering a topology fixed a priori.

[0105] Regarding crosstalk errors, an algorithmic approach has been developed to predict the amount of crosstalk based on the connectivity of a processor in a cQED hardware environment. With such tools, each TAT algorithm chooses a topology from the set of allowed topologies in its own way, as described below.

[0106] The agnostic circuit is then transpiled to the native hardware set of gates with the chosen candidate topology. Based on the number of routing gates and our crosstalk metric, the transpiled circuit error is compared to the error threshold given by the client: if the circuit fidelity is below a threshold (or optimized, if requested), the algorithm stops; otherwise, the procedure is repeated.

[0107] TAT algorithms can then provide task-appropriate topology optimized instructions for cQED hardware fabrication, quantum simulations on hardware emulators.

[0108] Regardless of the preceding aspects, the algorithm provides a hardware topology—that is, the connectivity of the qubits—optimized for a specific task, which can be used by a cQED hardware manufacturer to build cQED hardware, particularly one specific to a particular use case. This hardware topology will then be mapped onto a circuit.

[0109] Adjustable-coupling CQED devices theoretically allow "everything-to-everything" connectivity. While this connectivity is generally a sound architectural choice (as it reduces the number of routing gates required), it introduces additional cavity-related errors (crosstalk) when using two-qubit gates.

[0110] The algorithm proposed within the framework of the invention makes it possible to identify the architecture that optimizes the trade-off between routing errors (low connectivity) and crosstalk errors (high connectivity).

[0111] Given a task, translated into an independent hardware circuit, the algorithm iteratively transpiles this circuit into a set of native (fixed) gates and a hardware topology (i.e., a qubit architecture). Once the transpilation is complete, the algorithm uses internal metrics to evaluate whether the chosen topology falls below a client-defined error threshold. If the error exceeds this threshold, the loop is repeated; if it falls below, the algorithm stops and the optimized hardware topology is provided.

[0112] The algorithm allows for circuit transpilation, independent of the transpilation tool. It provides an example of some of the standard transpilers provided by "QISKIT®" software or software suites familiar to those in the trade.

[0113] Regardless of the above, alternatively or at least partially in addition, one or more of the following steps may be envisaged:

[0114] - Mapping of logical qubits to physical qubits based on hardware constraints (e.g., connectivity / topology),

[0115] - Replacing abstract gate operations with the hardware's native set of gates,

[0116] - Insertion of SWAP gates if the qubits that need to interact are not physically connected.

[0117] - Optimize the circuit to reduce error rates and execution time (e.g., number of gates, circuit depth).

[0118] Thus, the algorithm allows:

[0119] - 1) Depending on the choice of algorithm (Q, AQ, RWC), the process provides a procedure for choosing the initial connectivity and updating it at each time step. This step is important because the transpiler must be connected to the hardware;

[0120] - 2) After transpilation, the algorithm(s) provide a method for evaluating whether the output circuit has a total error below the error threshold provided with the task. This is done by combining two error metrics that take into account the routing / crosstalk trade-off:

[0121] i) Routing metric: To calculate total gate errors, it can be assumed that each gate error accumulates independently, so the total gate error is equal to the single gate error multiplied by the number of gates executed. The number of gates executed increases with the number of routing gates required due to low connectivity;

[0122] ii) Crosstalk metric: This metric calculates the error due to the chosen connectivity. It calculates the crosstalk error. This metric is particularly advantageous for evaluating this type of crosstalk error (two-qubit cavity-mediated gate in cQED hardware). BRIEF DESCRIPTION OF THE FIGURES

[0123] This is a schematic functional representation of the main stages of interaction between the customer and the hardware company in resolving a given task;

[0124] Laillustre un premier algorithm Q-algo qui peut être implemented dans la process selon l'invention;

[0125] Laillustre illustrates a second AQ-algo algorithm that can be implemented in the process according to the invention; and

[0126] Laillustre un troisième algorithm RWC-algo qui peut être implemented dans le process selon l'invention. DETAILED DESCRIPTION OF THE INVENTION

[0127] With reference to the [reference to a specific document], a schematic functional representation of the main stages of interaction between the customer and the hardware company in resolving a given task illustrates:

[0128] - In its left-hand side, a standardized process, in which the client assigns a task to a quantum developer who translates it into an algorithm implemented on a hardware-agnostic M qubit circuit within the limits of an error threshold provided by the client. The agnostic circuit is transpiled to the native hardware set of gates and the pre-defined topology provided by the hardware company.

[0129] - In its right part, an adaptive topology algorithm (TAT) process, in which the client assigns a task to a quantum developer who translates it into an algorithm implemented on a hardware M-agnostic qubit circuit within the limits of an error threshold given by the client.

[0130] The agnostic circuit enters the TAT algorithm: depending on the chosen algorithm, a cQED topology is selected from among the allowed topologies with a corresponding number of qubits and on / off coupling ratio, and the hardware-agnostic circuit is transpiled with such hardware specifications. This procedure is repeated until the error of the transpiled circuit is smaller than the customer error threshold (and optimized if necessary). TAT algorithms provide task-appropriate topology-optimized instructions for cQED hardware fabrication or quantum simulations on hardware emulators.

[0131] A technical solution to the problem defined above implements a mathematical formula to predict the amount of crosstalk error based on the connectivity of a processor in a cQED hardware environment. Various architectures based on different qubit connectivity are presented in turn. The choice of connectivity defines the hardware topology, which can be varied and fed into a quantum transpiler that translates a quantum-agnostic algorithm into the best hardware-specific algorithm.

[0132] Incorporated into an optimization algorithm that compares the ideal circuit to the transpiled one based on their operational fidelity, it is possible to deduce, from among all the proposed topologies, the one best suited to the desired algorithm. This tool can then lead to the production of the best available cQED hardware for a given task.

[0133] Connectivity options considered:

[0134] The different connectivity options that are explored are separated into three categories: ii) Maximum connectivity: All-to-all (ATA) ii) Medium connectivity: islands of n qubits connected with a variable number of "bridges" (links). The number of qubits per island, the connectivity among them, and the number of bridges per island do not necessarily have to be equal;

[0135] iii) Minimum connectivity: islands of two qubits connected by a single bridge.

[0136] Crosstalk errors

[0137] Crosstalk errors can generally be defined as errors occurring during computation due to unwanted many-body interactions within the material

[0018] .

[0138] The method according to the invention can address crosstalk errors occurring within microwave cavity-mediated entanglement gates (e.g., iSWAP), due to residual couplings between inactive and active qubits. Such an error is quantified using the metric:

[0139]

[0140] where n is the number of idle qubits,

[0141]

[0142] is the dimension of the system, Fe the entanglement fidelity, m the on / off coupling ratio between qubits integrated in the same microwave cavity, and x and the fidelity depend solely on the gate time tg (for example, for the gate time of an iSWAP,

[0143]

[0144] , we find

[0145]

[0146] And

[0147]

[0148] It is worth noting that, in cases where active qubits are coupled with different inactive qubits, the formula, thanks to the linearity of the operators involved in the fidelity calculation, can be easily modified to F′ct(n1, n2,m), where {n1, n2} are the number of inactive qubits for the first and second qubits involved in the two-qubit gate, respectively. Alternatively, the error can simply be approximated as that given by the qubit coupled to the maximum number of qubits.

[0149] Crosstalk error calculation

[0150] The following describes how to calculate the crosstalk error during the execution of a circuit for a given coupling map. Consider a circuit to be executed on N hardware qubits with a coupling map of fixed weights, i.e., a graph G(V,E) describing the connectivity among the qubits, such that each node is assigned a crosstalk weight based on the number of edges via Eq. (2). Let L be the number of two-qubit gates in the circuit, m the on / off coupling ratio, and assume that the errors stack independently among the different gates.

[0151] In the case of all-to-all (ATA) connectivity, the total crosstalk circuit fidelity is given by

[0152]

[0153] Since any pair of qubits shares the same weight, meaning they will be bound to the same N-2 qubits and therefore share exactly the same crosstalk error, in the case of an arbitrary coupling board, however, there will be both pairs of qubits with identical and different weights. In this case, the total circuit fidelity can be calculated in two ways:

[0154] i) with the modified F′ct(n1, n2,m), that is

[0155]

[0156] where {n1(l), n2(l)} are the number of inactive qubits respectively for the first and second qubits involved in the two-qubit gate 1;

[0157] ii) approximate the crosstalk error of the pair as the maximum error of the qubits in the pair, i.e.

[0158]

[0159] Description of task adaptive topology (TAT) algorithms implemented in the invention

[0160] Three algorithms, namely Q-algo, AQ-algo and RWC-algo, are now described.

[0161] Q-algorithm

[0162] With reference to LA, we assume that an algorithm fidelity threshold Fthr and a CA-agnostic circuit are provided. LA is defined as the length of CA after transpilation (translation and optimization) into the set of hardware gates, defined as the number of two-qubit gates in C0. From a prediction of L0, a per-gate fidelity budget is calculated.

[0163]

[0164] is predicted. It should be noted that, given that a circuit C to be implemented on a processor represented by a graph G(V,E), while the number of two-qubit gates depends on both C and G, i.e. L = L(C,G), for the sake of brevity the length will just be indicated by L.

[0165] The maximum number of qubits per cavity n corresponding to FG is calculated.

[0166] Let N be the total number of qubits in the processor and G(V=N,E) the graph representing the processor's connectivity. Let Fct(n) be the crosstalk fidelity of the two-qubit gate in an arrangement of n qubits per cavity and FD the gate fidelity that can be experimentally determined or theoretically predicted.

[0167] The Sabre algorithmic tool [8] and an optimizer are used to route the qubits according to the algorithm, then remove redundant or unnecessary gates and parallelize them if possible. The application of these two steps will be referred to as the route.

[0168] From n, the processor layout is deduced and the route is applied to extract a new circuit length L and estimate the total circuit fidelity as.

[0169]

[0170] where Fcirc,D [G(V,E)] and Fcirc,ct [G(V,E)] are respectively the total gate and crosstalk fidelities and are approximated to be independent:

[0171] [Math 12]

[0172] (3)

[0173] with vk being the number of two-qubit gates at stage k, FG the gate fidelity and FI the idle qubit fidelity, and

[0174] [Math 13]

[0175] (4)

[0176] where nk is the number of qubit islands in the processor and Fct(n) is the estimated crosstalk fidelity for n qubits per island. If Fcirc(n) < Fthr, there is a halt and the n layout is chosen; otherwise, there is an estimate from L of the new error budget per gate and the corresponding new n, assuming that to decrease n, L increases and iterates.

[0177] AQ-algo

[0178] With reference to the, a second algorithm is provided to be implemented on quantum hardware with a fidelity threshold F thr given and agnostic circuitC A By translating and optimizing C A Towards the set of hardware gates, the circuit C0 is obtained and L0 is defined as the length of C0, defined as the number of two-qubit gates in C0. Let N be the total number of qubits in C0. D andF I respectively the gate and idle qubit fidelities which can be determined experimentally or predicted theoretically.

[0179] It should be noted that, given that a circuit C to be implemented on a processor represented by a graph G(V,E), while the number of two-qubit gates depends on both C and G, i.e. L=L(C, G), for the sake of brevity, it is simply identified by L.

[0180] From L0, a loyalty budget per door is predicted

[0181]

[0182] which must be lower than F D If not, the fidelity threshold is set too high for the given hardware. Alternatively, one can proceed by mapping the circuit to the hardware qubits with the SABRE algorithm [8] and adjusting the connectivity with the formula in Eq. (2), which provides the suggested number of qubits per cavity corresponding to F0.

[0183] Sinest close to N (for example, Nn < nn). min n,n min (= 2 the minimum connectivity) we start from all-to-all connectivity, whereas if it is not, we start from den. Let cmap=island cmap(N, n) be the coupling map, that is, a graph G(V=N,E) representing the processor's connectivity; for simplicity, island cmap(N, n) is constructed such that it starts by dividing N by N isl islands of equal size orN islOne island of equal size and one smaller island, all connected by a single connection (i.e., the nearest neighbor), for example, for N = 6, `island cmap(6,2)` returns three nearest neighbor islands of size two, while for `island cmap(6,4)` returns two nearest neighbor islands of size four and one of size two. It should be noted that such a function could potentially be applied recursively as a subroutine within islands to obtain a more complex matching map. At each step, the total circuit fidelity is calculated as

[0184]

[0185] Or

[0186]

[0187] is the total gate fidelity, vk is the number of two-qubit gates at step k, and Fcirc,ct [G(V,E)] is the total circuit crosstalk fidelity calculated in the manner described above.

[0188] It should be noted that decoherence and crosstalk errors are approximated to be independent.

[0189] The following steps are iterated:

[0190] 1. Transpile the circuit using the SABRE algorithm to map a circuit to hardware qubits with a cmap coupling board i (n) and extract a new circuit length L i ;

[0191] 2. Estimate the total errors F circ , D G(V, E), F circ , ct G(V, E) and F circ G(V, E). SiF circ , ct G(V, E) has decreased since the last step, we break the iteration and return cmap i (n), whereas if it has improved we define the following:

[0192] [Math 17]

[0193] (5)

[0194] and as a function of ∆ i,D and ∆ i,ct we define ∆ i :

[0195] [Math 18]

[0196] (6)

[0197] If ∆ i is equal to the decoherence ∆ Di we increase the number of qubits per cavity, whereas if ∆ i is equal to the crosstalk ∆ cti we reduce it:

[0198] [Math 19]

[0199] (7)

[0200] 3. SiF circ G(V, E) < F thr We continue iterating over the steps above. If circ G(V, E) > F thr and ∆ opt = 0 we stop and choose cmap i (n i ), otherwise if ∆ opt / = 0 we keep iterating until ∆ i > opt = 0.

[0201] RWC-algo

[0202] With reference to the previous example, consider a third algorithm to be implemented on quantum hardware with a given fidelity threshold Fthr implemented on a CA-agnostic circuit. By translating and optimizing CA to the hardware gate set, we obtain the circuit C0 and define L0 as the length of C0, defined as the number of two-qubit gates in C0. Let N be the total number of qubits in C0, and FD and FI, respectively, the gate and idle qubit fidelities that can be determined experimentally or predicted theoretically.

[0203] It should be noted that, given that a circuit C to be implemented on a processor is represented by a graph G(V,E), while the number of two-qubit gates depends on both C and G, i.e., L = L(C, G), for the sake of brevity, we will simply identify it as L. From L0, we predict a fidelity budget per gate

[0204]

[0205] which must be lower than FD; otherwise, the fidelity threshold is set too high for the given hardware. Alternatively, we can map a circuit to hardware qubits using the SABRE algorithm [8] and set the connectivity to all-to-all.

[0206] From this, we construct a weighted wmap coupling map, that is, a graph G(V=N,E) describing the connectivity among the qubits, such that each node is assigned a crosstalk weight based on the number of edges via Eq. (2). The idea of ​​RWC is then to cut the edge associated with the maximum-weight nodes at each step. This operation is performed by a function `cut max edge(wmap)` which orders the edges associated with maximum-weight nodes, identifies

[0207] The function recursively cuts edges associated with nodes of equal weight until the total circuit fidelity Fcirc G(V,E) improves. Clearly, if an edge is cut and Fcirc G(V,E) decreases, that edge is restored, and the function transitions to trying to cut another edge. Similarly, we allow any type of connectivity possible within the hardware qubits.

[0208] At each step, the total circuit fidelity is calculated as Fcirc G(V,E) = Fcirc,DG(V,E) * Fcirc,ct G(V,E), where Fcirc,DG(V,E) = QL k=1 Fvk. D FN−2vkI is the total gate fidelity, vk is the number of two-qubit gates at step k, and Fcirc,ct G(V,E) is the total circuit crosstalk fidelity, calculated as described in Section III A.

[0209] It should be noted that the gate and crosstalk fidelities are approximated to be independent. Therefore, we iterate through the following steps:

[0210] 1. Transpile the circuit using the SABRE algorithm to map a circuit to hardware qubits with a wmapi coupling map and extract a new circuit length Li;

[0211] 2. Estimate the total errors Fcirc,DG(V,E), Fcirc,ct G(V,E) and Fcirc G(V,E). If Fcirc,ct G(V,E) has decreased since the last step, we break the iteration and return wmapi, whereas if it has improved we continue to cut the edges at maximum weight and obtain a new wmapi = cut max edge(wmapi);

[0212] 3. If Fcirc G(V, E) < Fthr we continue the iteration on the steps above. If Fcirc G(V,E) ≥ Fthr and Δopt = 0 we stop and choose wmapi, otherwise if Δopt = 0 we continue the iteration until Δi > Δopt.

[0213] Of course, the invention is not limited to the embodiments described above and can be applied to many types of qubit technologies, including carbon nanotube qubits, superconducting qubits, silicon qubits, trapped ion qubits or photonic qubits.

[0214] Among the cQED architectures to which the method of the invention can be applied are semiconductor spin qubits connected by an on-chip resonator, or Rydberg atoms linked by a macroscopic cavity. Spin qubits can, for example, be hosted in carbon nanotubes, such as in a double quantum dot structure. Photonic qubits can implement microwave cavity photons. An on-chip resonator can, for example, be a coplanar waveguide, a ribbon line, or a microstrip. It can be made of a high-impedance material such as niobium nitride.

[0215] Legend for variables used in the algorithms:

[0216] Problem variables

[0217] 1. CA: Agnostic circuit implementing a chosen algorithm

[0218] 2. LA: Agnostic circuit length

[0219] 3. Eth: Algorithm error threshold

[0220] 4. Fth = 1 − Eth: Algorithm fidelity threshold

[0221] Hardware specifications

[0222] 1. C0: Translation (and optimization) of CA in the hardware gate set

[0223] 2. L0: Length of C0

[0224] 3. N: number of qubits in C0

[0225] 4. m: on / off coupling ratio

[0226] 5. FD: Door Loyalty

[0227] 6. FI: Idle Qubit Fidelity

[0228] 7. G(V,E) graph with fixed sets of vertices and edges (V, E) representing the processor connectivity

[0229] 8. G = {G(V,E)} allowed set of graphs with fixed sets of vertices and edges (V, E), representing all allowed material topologies

[0230] 9. G*(V,E): graph ∈ G allowing the execution of CA within the limits of the error threshold Ethr

[0231] Algorithm variables

[0232] 1. Nstep: Number of algorithm steps before convergence

[0233] 2. i: algorithm step

[0234] 3. circi: circuit at step i

[0235] 4. vki: number of two-qubit gates at circuit step ki of algorithm step i

[0236] 5. Li: circuit length at step i (it is better to specify whether it is its size or its depth)

[0237] 6. Nisli: number of islets at stage i

[0238] 7. nji: number of qubits per island ji at step i

[0239] 8. cmapi: graph G(V,E) describing connectivity among qubits

[0240] 9. wmapi graph G(V,E) describing the connectivity among the qubits and such that each node is assigned a crosstalk weight as a function of the number of edges via Eq. (2).

[0241] 10.

[0242]

[0243] Budget fidelity per door at stage i

[0244] 11.

[0245]

[0246] total circuit gate fidelity at step i

[0247] 12.

[0248]

[0249] : Δ between two stages of total circuit gate fidelity

[0250] 13. Fct(nji) = Fct(nji,m): crosstalk fidelity at step i of Eq. (2)

[0251] 14. Fcirc,cti G(V,E): Crosstalk circuit fidelity for a given coupling card, see section (III A)

[0252] 15.

[0253]

[0254] Δ total crosstalk fidelity between two stages

[0255] 16.

[0256] total circuit fidelity approximated at step i (assuming that the two errors are independent, which is not true)

[0257] 17. Δi = Fcirci − Fcirci−1 Δ total circuit fidelity between two steps REFERENCES

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Claims

A method for generating a task-specific adapted topology for circuit or cavity quantum electrodynamics (cQED)-based hardware, comprising an initial step for generating, from said customer task, a circuit of agnostic M qubits and a corresponding error threshold, characterized in that the method comprises iterative steps of: transpiling said initially generated circuit of agnostic M qubits to generate a transpiled circuit, said transpilation step implementing hardware specifications including a set of native gates and gate errors; determining an error committed by said transpiled circuit; comparing said error thus committed to an error threshold corresponding to said circuit of agnostic M qubits; if said error of the transpiled circuit is greater than said error threshold, modifying some of said hardware specifications to be addressed in the transpilation step.If the said transpiled circuit error is less than the said error threshold, provide said transpiled circuit as a task-specific, task-appropriate topology to a chip design and nanofabrication unit. A method according to the preceding claim, further comprising the steps of: introducing input data comprising a circuit of M agnostic qubits (C A ) implementing an algorithm chosen from one or more sets of client-task adaptive topology algorithms (Q-Algo, AQ-Algo, RWC-algo), an algorithm error threshold (Ethr), an on / off coupling ratio, and an idle qubit fidelity (F I ), initialize, from the aforementioned input data, a translation (Co) of the circuit of agnostic M qubits (C A) in a set of hardware gates, a number (N) of qubits in said circuit of M agnostic qubits (Co) and a gate fidelity (FG), if said gate fidelity (FG) is greater than an algorithm fidelity threshold (Fthr), iteratively compute a new number n of qubits and a circuit fidelity (Fcirc) for a circuit to be transpiled, until said circuit fidelity (Fcirc) is greater than said algorithm fidelity threshold (Fthr). A method according to the preceding claim, wherein the input data further comprise a length (L A ) of the agnostic circuit, the initialization step further includes the initialization of the length (Lo) of the translated circuit material, and the calculation step further includes the calculation of a length (L) of the circuit to be transpiled. A method (AQ-algo) according to the preceding claim 2 or 3, wherein the input data further include a predetermined optimal variation of fidelity Δ opt characterized in that it further comprises the iterative steps of: transpiling the circuit, so as to map said circuit to hardware qubits with a coupling card and to extract a new circuit length (L i ) estimate total circuit fidelities including circuit crosstalk fidelity and calculate a variation Δ of circuit fidelity and a decoherence (Δ D ), provided that the circuit fidelity (Fcirc) is greater than or equal to the new calculated circuit fidelity (Fcircnew), increment / decrement the number (n) of qubits, until said circuit fidelity variation (Δ) and said decoherence (Δ D ) are approximately equal. A method (RCW-algo) according to any one of claims 2 to 4, wherein the input data further comprise a predetermined optimal variation of fidelity (Δ opt ), characterized in that it further comprises the iterative steps of: transpiling the circuit, so as to map said circuit to hardware qubits with a coupling map (wmap) and to extract a new circuit length L iEstimate a circuit crosstalk fidelity Fcirc,ct [G(V,E)] and a total circuit fidelity Fcirc [G(V,E)]. If said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has decreased since the previous step, break the iteration and return to the coupling map (wmap). If said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has increased since said previous step, clip the maximum weight edges and obtain a new coupling map (wmapi). Provided that said total circuit fidelity Fcirc [G(V,E)] is less than the algorithm threshold fidelity (Fthr), continue the iteration through the above steps. If the fidelity Fcirc [G(V,E)] is greater than or equal to the algorithm threshold fidelity (Fthr) and the optimal fidelity variation (Δ opt ) is approximately equal to 0, break the iteration and choose the coupling map (wmapi), if the optimal variation (Δ opt ) is not equal to 0, keep iterating until an iterative variation (Δ I) is greater than the optimal variation in fidelity (Δ opt ) . A method according to any one of the preceding claims, characterized in that it is carried out on cQED material with long-range interaction. A method according to any one of the preceding claims, implemented to provide task-adapted, optimized topology instructions for the nanofabrication of cQED material. A method according to any one of claims 1 to 6, implemented to provide task-appropriate optimized topology instructions for quantum simulations on emulators of cQED hardware. System for the nanofabrication of a material based on the quantum electrodynamics of circuits or cavities (cQED), intended to receive and process optimized instructions of topology adapted to a customer task, these instructions resulting from the execution of the topology generation process according to any one of the preceding claims.

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