Storage device

Abstract

The present invention provides a highly reliable storage device having a long data retention time. This storage device has a peripheral circuit and a plurality of memory cells. Each of the memory cells has a first transistor and a capacitive element. The peripheral circuit has a second transistor and a third transistor. A first terminal of the first transistor is electrically connected to a first terminal of the capacitive element, and a second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor. Respective semiconductor layers of the first transistor, the second transistor, and the third transistor have mutually different compositions.

Description

storage device

[0001] One aspect of the present invention relates to a memory device, and more particularly to a memory device that can function by utilizing semiconductor properties.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Dynamic random access memories (DRAMs) are widely used as storage devices (also referred to as memories) built into various electronic devices. Examples of applying transistors (also referred to as "OS transistors") that use an oxide semiconductor for a semiconductor layer in which a channel is formed to memory cells of DRAMs have been proposed (see, for example, Patent Document 1 and Non-Patent Document 1).

[0004] Since an OS transistor has an extremely small leakage current (off-state current) in an off state, by applying an OS transistor to a memory cell of a DRAM, a memory with low refresh frequency and low power consumption can be manufactured.

[0005] In this specification and the like, a DRAM in which an OS transistor is used as a memory cell is referred to as an "oxide semiconductor DRAM" or a "Dynamic Oxide Semiconductor Random Access Memory (DOSRAM)" (registered trademark).

[0006] The oxide semiconductors described above have recently attracted attention as semiconductor materials applicable to transistors. Known oxide semiconductors include not only oxides containing one metal element as a main component, such as In oxide (also called indium oxide or indium oxide) and zinc oxide (also called zinc oxide), but also oxides containing multiple metal elements as main components. In particular, research on In oxide and In—Ga—Zn oxide (also called indium-gallium-zinc oxide, IGZO) has been actively conducted.

[0007] JP 2012-256820 A

[0008] T. Onuki et al. ,”DRAM with Storage Capacitance of 3.9fF using CAAC-OS Transistor with L of 60nm and having More Than 1-h Retention “Characteristics”, Ext. Abstr. SSDM, 2014, pp. 430-431. Takashi Koita, “High Mobility Transparent Conductive Film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Research Results Report Meeting 2019, Internet <URL: https: / / unit. aist. go. jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0009] When a negative potential is applied to the back gate of an OS transistor, the threshold voltage of the OS transistor shifts to the positive side, and a current (also referred to as a cutoff current) that flows between the source and drain when the potential difference between the source and gate is 0 V can be reduced. That is, data retention time can be extended in a DRAM (DOSRAM) in which an OS transistor is used as a memory cell.

[0010] However, a relatively large potential is sometimes required to be applied to the back gate of a transistor so as to affect the electrical characteristics of the transistor, and a large potential applied to the back gate of a transistor can reduce the reliability of the transistor.

[0011] An object of one embodiment of the present invention is to provide a highly reliable storage device with a long data retention time, a novel storage device, or an electronic device including the novel storage device.

[0012] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these can be found by a person skilled in the art from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0013] One embodiment of the present invention is a memory device including a memory cell and a peripheral circuit, the memory cell including a first transistor and a capacitor, the peripheral circuit including a second transistor and a third transistor, a first terminal of the first transistor being electrically connected to a first terminal of the capacitor, a second terminal of the first transistor being electrically connected to a first terminal of the second transistor and a first terminal of the third transistor, and semiconductor layers of the first transistor, the second transistor, and the third transistor having different compositions.

[0014] The first transistor preferably has a first gate and a second gate, the first gate and the second gate having a region overlapping each other via a channel formation region, and the peripheral circuit preferably has a function of supplying a first potential to the first gate that is lower than a potential supplied to the second terminal of the first transistor and a function of supplying a second potential to the second gate that is lower than the first potential during a period in which the memory cell retains data.

[0015] The semiconductor layer of the first transistor preferably contains indium, gallium, zinc, and oxygen. The semiconductor layer of the second transistor preferably contains indium and oxygen. The semiconductor layer of the third transistor preferably contains silicon. The semiconductor layer of the second transistor is preferably a polycrystalline or single-crystalline semiconductor layer. The first transistor and the second transistor are preferably n-type transistors. The third transistor is preferably, for example, a p-type transistor.

[0016] According to one embodiment of the present invention, a highly reliable storage device having a long data retention time can be provided. Alternatively, according to one embodiment of the present invention, a novel storage device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the novel storage device can be provided.

[0017] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be found by a person skilled in the art from the description in the specification, claims, drawings, etc., and other effects can be extracted from the description in the specification, claims, drawings, etc.

[0018] FIG. 1 is a block diagram illustrating an example of a memory configuration. FIG. 2A is a diagram illustrating a memory cell array. FIG. 2B is a circuit diagram illustrating an example of a memory cell configuration. FIGS. 3A, 3B, and 3C are circuit diagrams illustrating examples of memory cell configurations. FIG. 4A is a block diagram illustrating an example of a word line driver circuit. FIG. 4B is a circuit diagram illustrating an example of a circuit LVB. FIGS. 5A and 5B are diagrams illustrating examples of inputs and outputs of the word line driver circuit. FIGS. 6A and 6B are circuit diagrams illustrating an example of a potential generation circuit. FIG. 7 is a diagram illustrating an example of a memory cell array and a bit line driver circuit. FIG. 8 is a diagram illustrating an example of a circuit configuration. FIG. 9 is a timing chart illustrating an example of the operation of a memory device. FIG. 10 is a timing chart illustrating an example of the operation of a memory device. FIG. 11 is a timing chart illustrating an example of the operation of a memory device. FIGS. 12A and 12B are diagrams illustrating an example of a memory device configuration. FIGS. 13A and 13B are diagrams illustrating an example of a memory device configuration. FIGS. 14A, 14B, and 14C are diagrams illustrating examples of transistor configurations. 15A, 15B, and 15C are diagrams illustrating a configuration example of a transistor. FIG. 16 is a cross-sectional view illustrating a configuration example of a memory device. FIGS. 17A and 17B are diagrams illustrating the carrier concentration dependence of hole mobility. FIG. 17C is a cross-sectional view illustrating an indium oxide film. FIGS. 18A and 18B are configuration examples of electronic components. FIGS. 19A, 19B, 19C, 19D, 19E1, and 19E2 are diagrams illustrating configuration examples of electronic devices.

[0019] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0020] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0021] In addition, the following multiple embodiments can be combined as appropriate. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0022] In the drawings related to this specification, components may be classified by function and shown as independent blocks. However, in actuality, it may be difficult to completely separate components by function. Therefore, one component may be involved in multiple functions.

[0023] In addition, in the drawings and the like relating to this specification, sizes, layer thicknesses, regions, and the like may be exaggerated for clarity. Therefore, they are not necessarily limited to the scale. The drawings are shown schematically to aid in understanding the inventions disclosed in this specification, and are not necessarily limited to the shapes, values, and the like shown in the drawings.

[0024] In addition, in drawings, etc., identical elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same symbol, and repeated explanations may be omitted.

[0025] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film" in some cases. Or, for example, the term "insulating film" can be changed to the term "insulating layer" in some cases.

[0026] Furthermore, in this specification and the like, terms indicating arrangement such as "above" or "below" do not limit the positional relationship of components to "directly above" or "directly below." For example, the expression "gate electrode on a gate insulating layer" does not exclude other components between the gate insulating layer and the gate electrode.

[0027] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0028] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0029] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0030] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0031] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0032] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0033] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0034] Furthermore, in this specification and the like, the term "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential difference can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be used interchangeably.

[0035] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel formation region in a semiconductor layer between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and can pass a current between the source and the drain through the channel formation region.

[0036] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0037] In this specification and the like, unless otherwise specified, off-state current refers to a current (also referred to as a "drain current") that flows between the source and the drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the potential difference between the source and the gate (also referred to as a "gate voltage" or "gate voltage Vg") with respect to the source is lower than the threshold voltage Vth for an n-channel transistor, and a state in which the gate voltage is higher than the threshold voltage Vth for a p-channel transistor. In other words, the off-state current of an n-channel transistor may be referred to as the drain current when the gate voltage is lower than the threshold voltage Vth.

[0038] In the above description of the off-state current, the drain may be read as the source. That is, the off-state current may refer to the source current when the transistor is in the off state. The off-state current may also be referred to as leakage current, which has the same meaning as the off-state current.

[0039] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors), and the like.

[0040] In addition, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and no distinction is made between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0041] In this specification, one of the source and the drain of a transistor may be referred to as a "first terminal of the transistor." The other of the source and the drain of the transistor may be referred to as a "second terminal of the transistor."

[0042] Generally, "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator. In addition, in this specification, one electrode of a capacitance element may be referred to as a "first terminal of the capacitance element." In addition, the other electrode of the capacitance element may be referred to as a "second terminal of the capacitance element."

[0043] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0044] Note that one embodiment of the present invention is all or part of the circuit configuration described in this specification, etc. Therefore, one embodiment of the present invention satisfies the support requirement and the clarity requirement even if it does not include all or part of the operations described in this specification, etc.

[0045] Embodiment 1 In this embodiment, a configuration example of a memory device 100 according to one embodiment of the present invention will be described. The memory device 100 according to one embodiment of the present invention is a memory device that can function by utilizing semiconductor characteristics. Note that in the drawings, the flow of main signals may be indicated by arrows or lines. Furthermore, for ease of understanding, some illustrations, such as power lines, may be omitted in the drawings.

[0046] 1 is a block diagram illustrating a configuration example of a memory device 100 according to one embodiment of the present invention. The memory device 100 includes a peripheral circuit 111 and a memory cell array 201. The memory cell array 201 includes a plurality of memory cells 211. The peripheral circuit 111 includes a row decoder 121, a word line driver circuit 122, an output circuit 140, a negative potential generation circuit 150, a negative potential generation circuit 151, and a control logic circuit 160.

[0047] The word line driver circuit 122 is connected to a plurality of wirings WL and a plurality of wirings WLB. The bit line driver circuit 130 is connected to a plurality of wirings BL. Each of the plurality of memory cells 211 is connected to one of the plurality of wirings WL, one of the plurality of wirings WLB, and one of the plurality of wirings BL.

[0048] The bit line driver circuit 130 includes a column decoder 131, a precharge circuit 132, a sense amplifier circuit 133, and an input / output circuit 134. The precharge circuit 132 has a function of precharging the wiring BL. The sense amplifier circuit 133 has a function of amplifying a data signal read from the memory cell 211. The input / output circuit 134 has a function of writing a data signal to the wiring BL and a function of outputting the data signal read from the wiring BL to the output circuit 140.

[0049] The data signal amplified by the sense amplifier circuit 133 is outputted to the outside of the memory device 100 via the output circuit 140 as a data signal RDATA.

[0050] The memory device 100 is supplied with a low power supply potential VSS from the outside, a high power supply potential VDD for the peripheral circuit 111, and a high power supply potential VIH for the memory cell array 201. Here, the high power supply potential VDD is a potential higher than the low power supply potential VSS. Also, for example, the high power supply potential VIH can be a potential higher than the high power supply potential VDD or the same potential as the high power supply potential VDD.

[0051] The negative potential generation circuit 150 has a function of generating a low power supply potential VLL. The negative potential generation circuit 151 has a function of generating a low power supply potential VBL. The low power supply potential VLL and the low power supply potential VBL are lower than the low power supply potential VSS. Note that the memory device 100 may be configured without the negative potential generation circuit 150 and the negative potential generation circuit 151, and the low power supply potential VLL and the low power supply potential VBL may be supplied from outside the memory device 100.

[0052] Control signals (signal CE, signal WE, signal RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 100. The address signal ADDR is input to a row decoder 121 and a column decoder 131, and the data signal WDATA is input to an input / output circuit 134.

[0053] The control logic circuit 160 has a function of generating control signals for the row decoder 121 and the column decoder 131 in response to signals CE, WE, and RE. The signal CE is a chip enable signal, the signal WE is a write enable signal, and the signal RE is a read enable signal. The signals processed by the control logic circuit 160 are not limited to these, and other control signals can be processed as needed.

[0054] It should be noted that the above-described circuits, signals, and potentials may be appropriately selected or omitted as necessary in the storage device 100. Alternatively, other circuits, other signals, or other potentials may be added.

[0055] Here, an OS transistor can be used as the transistor forming the memory cell 211. Since the off-state current of an OS transistor is extremely small, data written to the memory cell 211 can be held for a long time. Therefore, the memory cell 211 can be refreshed less frequently, and the memory device 100 can be a memory device with low power consumption.

[0056] Furthermore, the OS transistor is a thin film transistor and can be stacked on a semiconductor substrate. For example, the peripheral circuit 111 can be formed on a silicon substrate, and the memory cell 211 including the OS transistor can be provided on the silicon substrate. By forming the peripheral circuit 111 on a silicon substrate, it becomes easy to configure the peripheral circuit 111 using a transistor using silicon (also referred to as a Si transistor) for a semiconductor layer in which a channel is formed. The peripheral circuit 111 including the Si transistor can operate at high speed.

[0057] FIG. 2A shows details of the memory cell array 201. The memory cell array 201 has m×n memory cells 211 arranged in a matrix of m rows (m is an integer equal to or greater than 1) and n columns (n ​​is an integer equal to or greater than 1). In FIG. 2A, the memory cell 211 arranged in the first row and first column is indicated as 211[1,1], and the memory cell 211 arranged in the mth row and first column is indicated as 211[m,1]. The memory cell 211 arranged in the first row and nth column is indicated as 211[1,n], and the memory cell 211 arranged in the mth row and nth column is indicated as 211[m,n]. The memory cell 211 arranged in the ith row and jth column is indicated as 211[i,j] (i is an integer equal to or greater than 1 and m, and j is an integer equal to or greater than 1 and n). Note that [m,1], [i,j], [1,n], and [m,n] can also be referred to as addresses of the memory cells 211.

[0058] Furthermore, each memory cell 211 is connected to any one of m wirings WL (WL[1] to WL[m]), any one of m wirings WLB (WLB[1] to WLB[m]), and any one of n wirings BL (BL[1] to BL[n]). As shown in FIG. 2A , a memory cell 211[i,j] is connected to a wiring WL[i], a wiring WLB[i], and a wiring BL[j]. The memory cell 211 is connected to the word line driver circuit 122 via a wiring WL, to the word line driver circuit 122 via a wiring WLB, and to the bit line driver circuit 130 via a wiring BL.

[0059] <Configuration Example 1 of Memory Cell> FIG. 2B is a circuit diagram showing a configuration example of the memory cell 211. As shown in FIG.

[0060] The memory cell 211 includes a transistor M11 and a capacitor CA. The transistor M11 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0061] One of the source and drain of the transistor M11 is connected to a first terminal of the capacitor CA, and the other of the source and drain of the transistor M11 is connected to a wiring BL. The gate of the transistor M11 is connected to a wiring WL, and the back gate of the transistor M11 is connected to a wiring WLB. The second terminal of the capacitor CA is connected to a wiring CAL.

[0062] The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential (e.g., a low-level potential, a GND potential, a common potential, etc.) to the second terminal of the capacitor CA. The wiring WLB functions as a wiring for applying a potential to the back gate of the transistor M11. The threshold voltage of the transistor M11 can be controlled by applying an arbitrary potential to the wiring WLB.

[0063] The transistor M11 functions as a switch that brings the first terminal of the capacitor CA and the wiring BL into electrical continuity or non-conduction. Data is written or read by applying a high-level potential to the wiring WL to bring the first terminal of the capacitor CA and the wiring BL into electrical continuity (a state in which current can flow). The memory cell 211 has a function of retaining data by accumulating charge in the capacitor CA. Data retained in the memory cell 211 is written or read via the wiring BL and the transistor M11.

[0064] Note that an OS transistor is preferably used for the transistor M11. For example, a metal oxide containing indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc can be used for a semiconductor layer in which a channel of the transistor M11 is formed. In particular, a metal oxide containing indium, gallium, and zinc (also referred to as "In-Ga-Zn oxide" or "IGZO") is preferable. An OS transistor using In-Ga-Zn oxide for a semiconductor layer can easily be realized as an enhancement-type (normally-off) transistor.

[0065] Since an OS transistor has a very low off-state current, using an OS transistor for the transistor M11 allows data written to the memory cell 211 to be held for a long time. Therefore, the refresh frequency of the memory cell 211 can be reduced, and the memory device 100 can be a memory with low power consumption. Alternatively, using an OS transistor for the transistor M11 can substantially eliminate the need for a refresh operation of the memory cell 211. Furthermore, using an OS transistor for the transistor M11 allows multilevel data or analog data to be held in the memory cell 211. Furthermore, by using a normally-off transistor as the transistor M11, the transistor M11 can be reliably turned off even when the gate voltage is 0 V. Therefore, data written to the memory cell 211 can be held for a long time even when power supply to the memory cell 211 is stopped.

[0066] The above-described DOSRAM can be configured by using an OS transistor as the transistor M11. Depending on the material of an oxide semiconductor used for a semiconductor layer of the OS transistor, the operating frequency of the DOSRAM may increase as the temperature increases.

[0067] <Configuration Example 2 of Memory Cell> Note that, as memory cells that configure the memory cell array 201, memory cells having a circuit configuration other than that of the memory cell 211 can also be used. An example of a memory cell having a circuit configuration other than that of the memory cell 211 is shown in FIGS. 3A to 3C .

[0068] 3A includes a transistor M12, a transistor M13, and a capacitance element CB. The transistor M12 has a front gate and a back gate. The transistor M12 corresponds to the transistor M11 of the memory cell 211, and the capacitance element CB corresponds to the capacitance element CA.

[0069] One of the source or drain of the transistor M12 is connected to the first terminal of the capacitor CB and the gate of the transistor M13, and the other of the source or drain of the transistor M12 is connected to the wiring WBL. The gate of the transistor M12 is connected to the wiring WL, and the back gate of the transistor M12 is connected to the wiring WLB. The second terminal of the capacitor CB is connected to the wiring CAL. One of the source or drain of the transistor M13 is connected to the wiring SL, and the other of the source or drain of the transistor M13 is connected to the wiring RBL.

[0070] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. The wiring WLB functions as a wiring for applying a potential to the back gate of the transistor M12. The threshold voltage of the transistor M12 can be controlled by applying an arbitrary potential to the wiring WLB.

[0071] The transistor M12 functions as a switch that brings the first terminal of the capacitor CB and the wiring WBL into electrical conduction or non-conduction.

[0072] Data can be written in the same manner as in the memory cell 211. Data can be read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M13 is determined by the potential of the gate of the transistor M13 and the potential of one of the source and drain of the transistor M13 (the wiring SL). The current also determines the potential of the other of the source and drain of the transistor M13. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M13) can be read by reading the potential of the wiring RBL connected to the other of the source and drain of the transistor M13. In other words, data written in the memory cell 212 can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M13).

[0073] Note that an OS transistor is preferably used as the transistor M12. As described above, an OS transistor has an extremely low off-state current and can therefore retain data written to the memory cell 212 for a long time. In particular, an n-channel OS transistor used as the transistor M12 is preferably an OS transistor using an In—Ga—Zn oxide for its semiconductor layer, similar to the transistor M11. As described above, an OS transistor using an In—Ga—Zn oxide for its semiconductor layer is suitable for the transistor M12 because it can easily be realized as an enhancement-type (normally-off) transistor.

[0074] The transistor used for the transistor M13 is not particularly limited. For example, an OS transistor or a Si transistor can be used for the transistor M13. Since a Si transistor has higher field-effect mobility than an OS transistor, high-speed data reading is possible. On the other hand, since a Si transistor has a larger off-state current than an OS transistor, the power consumption of the storage device tends to be high. Furthermore, charge leakage from memory cells that are not the read target is likely to occur, which may reduce the accuracy of data reading.

[0075] By using an OS transistor as the transistor M13, the power consumption of the storage device can be reduced and the accuracy of data reading can be improved. Furthermore, when an OS transistor is used as the transistor M13, it is preferable to use an OS transistor using indium oxide (In oxide) for its semiconductor layer. For example, an OS transistor using an In oxide for its semiconductor layer can achieve higher field-effect mobility than an OS transistor using an In—Ga—Zn oxide, thereby increasing the data reading speed.

[0076] The memory cell 212 is a gain cell memory cell with two transistors and one capacitor. A gain cell memory cell can operate as a memory even when the capacitance of the capacitor is small by amplifying the accumulated charge using the nearest transistor. Furthermore, by using an OS transistor with very low off-state current as the transistor M12, the accumulated charge can be held for a long time even when the power supply is stopped.

[0077] In this specification, a memory configured with gain cell memory cells using OS transistors is referred to as a "Nonvolatile Oxide Semiconductor Random Access Memory (NOSRAM)." Note that, since NOSRAM rewrites data by charging and discharging a capacitive element, there is no theoretical limit to the number of times data can be rewritten.

[0078] The memory cell 212 can have a configuration in which the wirings WBL and RBL are combined into a single wiring BL. An example of a configuration in which the wirings WBL and RBL are combined into a single wiring BL is shown in FIG.

[0079] 3B, the other of the source and drain of the transistor M12 and the other of the source and drain of the transistor M13 are connected to the wiring BL. That is, the memory cell 213 has a configuration in which a single wiring BL is used as both a write bit line and a read bit line. In the memory cell 213, when data is written, the transistor M13 may be unintentionally turned on, bringing the wiring SL and the wiring BL into electrical continuity. Therefore, when data is written, it is preferable to keep the wiring SL in an electrically floating state (floating).

[0080] <Configuration Example 3 of Memory Cell> It is also possible to configure the memory cell 212 as a gain cell type memory cell with three transistors and one capacitor element. A configuration example in which the memory cell 212 is a gain cell type memory cell with three transistors and one capacitor element is shown in FIG.

[0081] 3C includes transistors M14 to M16 and a capacitor CC. The transistor M14 has a front gate and a back gate. The transistor M14 corresponds to the transistor M12 in the memory cells 212 and 213. The transistor M15 corresponds to the transistor M13 in the memory cells 212 and 213. The capacitor CC corresponds to the capacitor CB in the memory cells 212 and 213.

[0082] Therefore, the transistor M14 can be a transistor similar to the transistor M12, and the transistors M15 and M16 can be a transistor similar to the transistor M13.

[0083] One of the source and drain of the transistor M14 is connected to a first terminal of the capacitor CC and the gate of the transistor M15, and the other of the source and drain of the transistor M14 is connected to the wiring BL. The gate of the transistor M14 is connected to the wiring WL, and the back gate of the transistor M14 is connected to the wiring WLB. The second terminal of the capacitor CC is connected to the wiring CAL and the one of the source and drain of the transistor M15, and the other of the source and drain of the transistor M15 is connected to the one of the source and drain of the transistor M16. The other of the source and drain of the transistor M16 is connected to the wiring BL, and the gate of the transistor M16 is connected to the wiring RWL.

[0084] The wiring BL functions as a bit line, the wiring WL functions as a write word line, and the wiring RWL functions as a read word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CC. The wiring WLB functions as a wiring for applying a potential to the back gate of the transistor M14. The threshold voltage of the transistor M14 can be controlled by applying an arbitrary potential to the wiring WLB.

[0085] The transistor M14 functions as a switch that connects or disconnects the first terminal of the capacitor CC and the wiring BL, and the transistor M16 functions as a switch that connects or disconnects the other of the source or drain of the transistor M15 and the wiring BL.

[0086] Data can be written in the same way as in the memory cells 211 to 213. Data can be read by applying a predetermined potential to the wiring BL (precharging) and then electrically floating the wiring BL and applying a high-level potential to the wiring RWL. Applying a high-level potential to the wiring RWL turns on the transistor M16, and the other of the source and drain of the transistor M15 is connected to the wiring BL. At this time, a voltage corresponding to the potential difference between the wiring BL and the wiring CAL is applied between the source and drain of the transistor M15, and the current flowing between the source and drain of the transistor M15 is determined by the gate potential of the transistor M15 and the voltage applied between the source and drain.

[0087] Here, the potential of the wiring BL changes depending on the current flowing between the source and drain of the transistor M15, so that the potential held in the first terminal of the capacitor CC (or the gate of the transistor M15) can be read by reading the potential of the wiring BL. In other words, data written in the memory cell 214 can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M15).

[0088] Although other configuration examples of the memory cell 211 have been described using FIGS. 3A to 3C, the configuration examples of the memory cell 211 are not limited to these, and the circuit configuration can be changed as appropriate.

[0089] <Configuration Example of Word Line Driver Circuit> FIG. 4A is a block diagram showing a configuration example of the word line driver circuit 122. As shown in FIG.

[0090] The word line driver circuit 122 has a function of driving the wiring WL that functions as a word line. The word line driver circuit 122 receives signals WI and WIB for driving the wiring WL and wiring WLB from the row decoder 121. Here, the signals WI and WIB are digital signals expressed as high or low levels, and the signal WIB is an inverted signal obtained by inverting the logic of the signal WI.

[0091] Since there are m wirings WL and m wirings WLB, the number of signals WI and WIB is also m. In FIG. 4A, these signals are represented as signals WI[1] to WI[m] and signals WIB[1] to WIB[m].

[0092] Since the row decoder 121 is supplied with a low power supply potential VSS and a high power supply potential VDD, the potential corresponding to the high level of the signals WI and WIB is the high power supply potential VDD, and the potential corresponding to the low level of the signals WI and WIB is the low power supply potential VSS.

[0093] On the other hand, in the memory cell array 201, a high power supply potential VIH is used as a potential corresponding to a high level of the wiring WL, and a low power supply potential VLL is used as a potential corresponding to a low level of the wiring WL. Also, a low power supply potential VBL is supplied to the wiring WLB.

[0094] Therefore, the word line driver circuit 122 has a function of adjusting the high level or low level, or both the high level and the low level, of an input signal (also referred to as a level adjustment function), and a function of adding the ability to drive wirings WL (represented as WL[1] to WL[m] in FIG. 4A) to the input signal (also referred to as a buffer function). The word line driver circuit 122 has m circuits LVB, which are represented as LVB[1] to LVB[m] in FIG. 4A.

[0095] A low power supply potential VBL is input to the word line driver circuit 122, and the low power supply potential VBL is output to the wirings WLB (represented as WLB[1] to WLB[m] in FIG. 4A).

[0096] <Configuration Example of Circuit LVB> FIG. 4B is a circuit diagram showing a configuration example of the circuit LVB.

[0097] The circuit LVB includes n-channel transistors 13 to 21 and p-channel transistors 33 to 41. The circuit LVB also includes an input terminal WI_IN, an input terminal WIB_IN, a wiring VIH_IN, a wiring VSS_IN, a wiring VLL_IN, and an output terminal WL_OUT.

[0098] The circuit LVB receives a signal WI at its input terminal WI_IN, a signal WIB at its input terminal WIB_IN, a high power supply potential VIH at its wiring VIH_IN, a low power supply potential VSS at its wiring VSS_IN, and a low power supply potential VLL at its wiring VLL_IN. The circuit LVB outputs a signal for driving the wiring WL from its output terminal WL_OUT.

[0099] In the circuit LVB, one of the source and the drain of the transistor 13 is connected to the wiring VSS_IN, the other of the source and the drain of the transistor 13 is connected to one of the source and the drain of the transistor 34 and the gate of the transistor 35, and the gate of the transistor 13 is connected to the input terminal WI_IN and the gate of the transistor 34. The other of the source and the drain of the transistor 34 is connected to one of the source and the drain of the transistor 33, and the other of the source and the drain of the transistor 33 is connected to the wiring VIH_IN.

[0100] One of the source and the drain of the transistor 14 is connected to the wiring VSS_IN, the other of the source and the drain of the transistor 14 is connected to one of the source and the drain of the transistor 36 and the gate of the transistor 33, and the gate of the transistor 14 is connected to the input terminal WIB_IN and the gate of the transistor 36. The other of the source and the drain of the transistor 36 is connected to one of the source and the drain of the transistor 35, and the other of the source and the drain of the transistor 35 is connected to the wiring VIH_IN. Here, the connection between the other of the source and the drain of the transistor 36 and the one of the source and the drain of the transistor 35 is referred to as a node N11, and other elements connected to the node N11 will be described later.

[0101] The transistors 13, 14, and 33 to 36 have a level adjustment function of converting a potential corresponding to a high level of the input signals WI and WIB from a high power supply potential VDD to a high power supply potential VIH.

[0102] In the circuit LVB, one of the source and the drain of the transistor 15 is connected to the wiring VSS_IN, the other of the source and the drain of the transistor 15 is connected to one of the source and the drain of the transistor 37, the gate of the transistor 16, and the gate of the transistor 38, and the gate of the transistor 15 is connected to the node N11 and the gate of the transistor 37. The other of the source and the drain of the transistor 37 is connected to the wiring VIH_IN. Here, a connection between the other of the source and the drain of the transistor 15 and the one of the source and the drain of the transistor 37, the gate of the transistor 16, and the gate of the transistor 38 is referred to as a node N12, and other elements connected to the node N12 will be described later.

[0103] One of the source and the drain of the transistor 16 is connected to the wiring VSS_IN, the other of the source and the drain of the transistor 16 is connected to the one of the source and the drain of the transistor 38, and the other of the source and the drain of the transistor 38 is connected to the wiring VIH_IN. Here, the connection portion between the other of the source and the drain of the transistor 16 and the one of the source and the drain of the transistor 38 is referred to as a node N13, and other elements connected to the node N13 will be described later.

[0104] The transistor 15 and the transistor 37 have a function of generating an inverted signal of the signal at the node N11.

[0105] In the circuit LVB, one of the source and the drain of the transistor 18 is connected to the wiring VLL_IN, the other of the source and the drain of the transistor 18 is connected to one of the source and the drain of the transistor 17, the other of the source and the drain of the transistor 17 is connected to one of the source and the drain of the transistor 39 and the gate of the transistor 20, and the other of the source and the drain of the transistor 39 is connected to the wiring VIH_IN. The gate of the transistor 17 is connected to the node N12 and the gate of the transistor 39.

[0106] One of the source and the drain of the transistor 20 is connected to the wiring VLL_IN, the other of the source and the drain of the transistor 20 is connected to one of the source and the drain of the transistor 19, the other of the source and the drain of the transistor 19 is connected to one of the source and the drain of the transistor 40 and the gate of the transistor 18, and the other of the source and the drain of the transistor 40 is connected to the wiring VIH_IN. The gate of the transistor 19 is connected to the node N13 and the gate of the transistor 40. Here, the connection between the other of the source and the drain of the transistor 20 and the one of the source and the drain of the transistor 19 is referred to as a node N14, and other elements connected to the node N14 will be described later.

[0107] The transistors 17 to 20, the transistor 39, and the transistor 40 have a level adjustment function of converting potentials corresponding to low levels of the signals at the nodes N12 and N13 from the low power supply potential VSS to the low power supply potential VLL.

[0108] In the circuit LVB, one of the source and the drain of the transistor 21 is connected to the wiring VLL_IN, the other of the source and the drain of the transistor 21 is connected to one of the source and the drain of the transistor 41 and the output terminal WL_OUT, and the gate of the transistor 21 is connected to the node N14 and the gate of the transistor 41. The other of the source and the drain of the transistor 41 is connected to the wiring VIH_IN.

[0109] The transistor 21 and the transistor 41 function as a buffer that outputs the signal at the node N14 from the output terminal WL_OUT.

[0110] <Example of Input / Output of Word Line Driver Circuit> FIG. 5A is a diagram showing an example of input / output of the word line driver circuit 122. As shown in FIG.

[0111] 5A , the relationship between the potentials of the signals WI and WIB input to the word line driver circuit 122 and the potentials of the wirings WL and WLB driven by the word line driver circuit 122 will be described. There are m signals WI, m signals WIB, m wirings WL, and m wirings WLB, and one of them (signal WI[i], WIB[i], wiring WL[i], and WLB[i]) will be described as an example (i is an integer from 1 to m).

[0112] The vertical axis in FIG. 5A represents potential, and the potentials are, from highest to lowest, high power supply potential VIH, high power supply potential VDD, low power supply potential VSS, low power supply potential VLL, and low power supply potential VBL.

[0113] In Figure 5A, T1 and T2 indicate time, and show how the wiring WL[i] is driven at approximately the same time as the signals WI[i] and WIB[i]. In reality, there is a delay between the input signals WI[i] and WIB[i] and the driving of the wiring WL[i], and the signals may contain distortion, noise, etc. Figure 5A shows waveforms in an ideal case.

[0114] 5A, the signal WI[i] and the signal WIB[i] are digital signals that are at a high level or a low level at a high power supply potential VDD or a low power supply potential VSS. The signal WI[i] becomes a high level when data is written to or read from the memory cell 211 connected to the wiring WL[i] and the wiring WLB[i] (the signal WIB is an inverted signal of the signal WI and therefore becomes a low level).

[0115] When the signal WI[i] is at a low level, the word line driver circuit 122 outputs a low power supply potential VLL to the wiring WL[i], and when the signal WI[i] is at a high level, the word line driver circuit 122 outputs a high power supply potential VIH to the wiring WL[i]. The word line driver circuit 122 also outputs a low power supply potential VBL to the wiring WLB[i].

[0116] Alternatively, the word line driver circuit 122 can drive the wiring WLB in addition to the wiring WL. When the word line driver circuit 122 drives the wiring WLB, for example, a circuit LVB is added to the word line driver circuit 122.

[0117] 5A, Fig. 5B is a diagram illustrating an example of input / output of the word line driver circuit 122. As illustrated in Fig. 5B, for example, when the signal WI[i] is at a low level, the word line driver circuit 122 can output a low power supply potential VBL to the wiring WLB[i], and when the signal WI[i] is at a high level, the word line driver circuit 122 can output a potential between the high power supply potential VDD and the low power supply potential VSS to the wiring WLB[i].

[0118] In this way, the word line driver circuit 122 changes the high level or low level, or the high level and low level, of the signal WI[i] and the signal WIB[i] to drive the wiring WL[i], or the wiring WL[i] and the wiring WLB[i].

[0119] <Negative Potential Generation Circuit> Next, configuration examples of the circuit 54 and the circuit 55 that can be used for the negative potential generation circuit 150 and the negative potential generation circuit 151 are shown in FIGS. 6A and 6B. FIG.

[0120] The circuit 54 and the circuit 55 are step-down charge pumps, and a low power supply potential VSS is input to an input terminal IN, and a low power supply potential VLL or a low power supply potential VBL is output from an output terminal OUT. Here, as an example, the number of stages in the basic circuit of the charge pump circuit is five, but the number of stages is not limited to five, and the charge pump circuit can be configured with any number of stages.

[0121] 6A includes transistors M21 to M25 and capacitors C21 to C25. Note that the transistors M21 to M25 can be configured using n-channel transistors.

[0122] The transistors M21 to M25 are connected in series between the input terminal IN and the output terminal OUT. The gate of each of the transistors M21 to M25 is connected to one of the source and the drain, and each of the transistors M21 to M25 functions as a diode. In each of the transistors M21 to M25, one of the source and the drain functions as the anode of the diode, and the other of the source and the drain functions as the cathode.

[0123] 6A, one of the source or drain of transistor M25 is connected to the output terminal OUT, and the other is connected to one of the source or drain of transistor M24. The other of the source or drain of transistor M24 is connected to one of the source or drain of transistor M23. The other of the source or drain of transistor M23 is connected to one of the source or drain of transistor M22. The other of the source or drain of transistor M22 is connected to one of the source or drain of transistor M21. The other of the source or drain of transistor M21 is connected to the input terminal IN.

[0124] Furthermore, one electrode of a capacitance element C21 is connected to the gate of transistor M21. One electrode of a capacitance element C22 is connected to the gate of transistor M22. One electrode of a capacitance element C23 is connected to the gate of transistor M23. One electrode of a capacitance element C24 is connected to the gate of transistor M24. One electrode of a capacitance element C25 is connected to the gate of transistor M25.

[0125] A clock signal CLK is input to the other electrodes of the capacitive elements C21 and C23 via a terminal CL, and an inverted clock signal CLKB is input to the other electrodes of the capacitive elements C22 and C24 via a terminal CLB. The signal CLKB is an inverted clock signal obtained by inverting the phase of the signal CLK. A fixed potential such as VSS or GND is supplied to the other electrode of the capacitive element C25.

[0126] The circuit 54 has a function of stepping down the low power supply potential VSS input to the input terminal IN to generate the low power supply potential VLL or the low power supply potential VBL. The circuit 54 can generate the low power supply potential VLL or the low power supply potential VBL by stepping down the low power supply potential VSS only by supplying the signal CLK and the signal CLKB.

[0127] 6B is composed of p-channel transistors M31 to M34. The transistors M31 to M35 are connected in series between the input terminal IN and the output terminal OUT. The gate of each of the transistors M31 to M35 is connected to one of the source and the drain, and each of the transistors M31 to M35 functions as a diode. In each of the transistors M31 to M35, one of the source and the drain functions as the cathode of the diode, and the other of the source and the drain functions as the anode.

[0128] 6B, the other of the source or drain of transistor M35 is connected to the output terminal OUT, and the other of the source or drain is connected to the other of the source or drain of transistor M34. Also, one of the source or drain of transistor M34 is connected to the other of the source or drain of transistor M33. Also, one of the source or drain of transistor M33 is connected to the other of the source or drain of transistor M32. Also, one of the source or drain of transistor M32 is connected to the other of the source or drain of transistor M31. One of the source or drain of transistor M31 is connected to the input terminal IN.

[0129] In addition, one electrode of a capacitance element C21 is connected to the other of the source or drain of transistor M31. One electrode of a capacitance element C22 is connected to the other of the source or drain of transistor M32. One electrode of a capacitance element C23 is connected to the other of the source or drain of transistor M33. One electrode of a capacitance element C24 is connected to the other of the source or drain of transistor M34. One electrode of a capacitance element C25 is connected to the other of the source or drain of transistor M35. The description of circuit 54 can be used for the other components.

[0130] <Transistor M11> As described above, the transistor M11, the transistor M12, and the transistor M14 can be OS transistors having a back gate. The threshold voltage of an OS transistor can be controlled by applying a potential to the back gate. Specifically, the threshold voltage of an OS transistor is shifted negatively by increasing the potential applied to the back gate, and the threshold voltage is shifted positively by decreasing the potential applied to the back gate.

[0131] That is, by lowering the potential applied to the back gate (low power supply potential VBL in this specification and the like), it is possible to reduce the current (also referred to as cutoff current) that flows between the source and drain when the gate voltage is 0 V. By reducing the cutoff current, it is possible to lengthen the retention time of data written to the memory cell 211.

[0132] Furthermore, by setting the potential applied to the front gate when the transistor is not conducting (off state) to a potential lower than the low power supply potential VSS (low power supply potential VLL in this specification, etc.), the current flowing between the source and drain of the transistor can be reduced. In other words, by applying the low power supply potential VLL to the front gate when the transistor is not conducting, the current flowing between the source and drain of the transistor can be reduced even if the potential difference between the low power supply potential VBL and the low power supply potential VSS is reduced.

[0133] By reducing the potential difference between the low power supply potential VBL and the low power supply potential VSS, the electric field strength applied to an insulating film (also referred to as a gate insulating film or a gate insulating layer) between the back gate and the channel formation region of the transistor can be reduced, thereby improving the reliability of the transistor. That is, the electric field stress applied to the transistor can be reduced, thereby improving the reliability of the transistor. The memory device 100 can be a highly reliable memory device with a long data retention time.

[0134] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0135] Embodiment 2 In this embodiment, a configuration example of a memory cell array 201 included in a memory device 100 and an operation example thereof will be described.

[0136] 7 shows an example of a memory cell array 201 different from that shown in FIG. 2A. FIG. 7 shows a memory cell array of a folded bit line system. Note that the memory cell 221 can also be used in a memory cell array of an open bit line system. Also, in FIG. 7, the wiring WLB is omitted.

[0137] The memory cell array 201 shown in Fig. 7 has a total of m x n memory cells 221 arranged in a matrix of m rows and n columns. Fig. 7 also shows the addresses of the memory cells 221. For example, [i, j] indicates the memory cell 221 in the ith row and jth column.

[0138] 7 has m wirings WL connected to the word line driver circuit 122. A wiring WL[1] is connected to the memory cell 221 in the first row. Similarly, a wiring WL[i] is connected to the memory cell 221 in the i-th row.

[0139] 7 has two wirings BIL (wirings BILa and BILb) in one column. In FIG. 7 and other figures, the wiring BILa in the first column is indicated as wiring BILa[1], and the wiring BILb in the j-th column is indicated as wiring BILb[j].

[0140] The memory cells 221 arranged in odd-numbered rows are connected to one of the wirings BILa and BILb, and the memory cells 221 arranged in even-numbered rows are connected to the other of the wirings BILa and BILb.

[0141] The wirings BILa and BILb are connected to a precharge circuit 132, a sense amplifier circuit 133, and an input / output circuit 134, which are provided for each column. The input / output circuit 134 is connected to the wirings SALa and SALb for each column. In FIG. 7 and other figures, the precharge circuit 132 for the first column is indicated as a precharge circuit 132[1], and the precharge circuit 132 for the jth column is indicated as a precharge circuit 132[j]. The sense amplifier circuit 133 and the input / output circuit 134 are also indicated in the same way. The bit line driver circuit 130 includes a column decoder 131 (see FIG. 1).

[0142] <Circuit Configuration Example> FIG. 8 shows a circuit configuration example of the memory cell 221 in the J-th column, the precharge circuit 132, the sense amplifier circuit 133, and the input / output circuit 134.

[0143] <Precharge Circuit 132> The precharge circuit 132[j] includes n-channel transistors Tr21 to Tr23. Note that the transistors Tr21 to Tr23 may be p-channel transistors. One of the source or drain of the transistor Tr21 is connected to the wiring BILa[j], and the other is connected to the wiring PRE. One of the source or drain of the transistor Tr22 is connected to the wiring BILb[j], and the other is connected to the wiring PRE. One of the source or drain of the transistor Tr23 is connected to the wiring BILa[j], and the other is connected to the wiring BILb[j]. The gates of the transistors Tr21, Tr22, and Tr23 are connected to the wiring PL. The precharge circuit 132 has a function of initializing the potentials of the wirings BILa[j] and BILb[j].

[0144] <Sense amplifier circuit 133> The sense amplifier circuit 133[j] includes p-channel transistors Tr31 and Tr32, and n-channel transistors Tr33 and Tr34. One of the source or drain of the transistor Tr31 is connected to a wiring SP, and the other of the source or drain is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BILa[j]. One of the source or drain of the transistor Tr33 is connected to the gate of the transistor Tr32, the gate of the transistor Tr34, and the wiring BLa[j], and the other of the source or drain is connected to a wiring SN. One of the source or drain of the transistor Tr32 is connected to the wiring SP, and the other of the source or drain is connected to the gate of the transistor Tr31, the gate of the transistor Tr33, and the wiring BLb[j]. One of the source and drain of the transistor Tr34 is connected to the gate of the transistor Tr31, the gate of the transistor Tr33, and the wiring BLb[j], and the other is connected to the wiring SN. The sense amplifier circuit 133[j] has a function of amplifying the potentials of the wirings BLa[j] and BILb[j]. Note that the sense amplifier circuit 133[j] functions as a latch-type sense amplifier circuit.

[0145] <Input / Output Circuit 134> The input / output circuit 134[j] includes n-channel transistors Tr41 and Tr42. Note that the transistors Tr41 and Tr42 may be p-channel transistors. One of the source or the drain of the transistor Tr41 is connected to the wiring BILa[j], and the other is connected to the wiring SALa[j]. One of the source or the drain of the transistor Tr42 is connected to the wiring BILb[j], and the other is connected to the wiring SALb[j]. The gates of the transistors Tr41 and Tr42 are connected to the wiring CSEL.

[0146] The input / output circuit 134[j] has a function of controlling the conduction state between the wiring BILa[j] and the wiring SALa[j] and the conduction state between the wiring BILb[j] and the wiring SALb[j] based on a potential supplied to the wiring CSEL. That is, the input / output circuit 134[j] can select whether to output a potential to the wiring SALa[j] and the wiring SALb[j].

[0147] The wirings SP, SN, CSEL, PRE, and PL have a function of transmitting signals for controlling the operations of the precharge circuit 132, the sense amplifier circuit 133, and the input / output circuit 134. The wirings SP, SN, CSEL, PRE, and PL are connected to the control logic circuit 160 shown in FIG. 1. The control logic circuit 160 has a function of supplying control signals to the wirings SP, SN, CSEL, PRE, and PL.

[0148] An operation mode of the memory device 100 will be described using the memory cell 221[i,j], the precharge circuit 132[j], the sense amplifier circuit 133[j], and the input / output circuit 134[j] shown in Figure 8. It is also assumed that -3 V is supplied to the wiring BGL[i].

[0149] <Read Mode> First, an example of the operation of the sense amplifier circuit 133[j] when reading data from the memory cell 221[i,j] will be described with reference to the timing chart shown in FIG.

[0150] [Period T11] In the period T11, the precharge circuit 132[j] is operated to initialize the potentials of the wiring BILa[j] and the wiring BILb[j]. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the potential Vpre of the wiring PRE is supplied to the wiring BILa[j] and the wiring BILb[j]. Note that the potential Vpre can be, for example, (VH_SP+VL_SN) / 2. VH_SP is a high-level potential supplied to the wiring SP, and VL_SN is a low-level potential supplied to the wiring SN.

[0151] Note that during the period T11, the potential of the wiring CSEL is low (VL_CSEL), and the transistors Tr41 and Tr42 in the input / output circuit 134[j] are off. The potential of the wiring WL[i] is low (VL_WL), and the transistor M11 included in the memory cell 221[i,j] is off. Similarly, although not shown in FIG. 8 , the potential of the wiring WL[i+1] is low (VL_WL), and the transistor M11 included in the memory cell 221[i+1,j] is off. The potentials of the wiring SP and the wiring SN are Vpre, and the sense amplifier circuit 133[j] is in a stopped state.

[0152] Note that VL_WL is preferably a potential lower than VL_SN. Also, VL_WL is preferably a potential lower than the potential obtained by subtracting the Vth of the transistor M11 from VL_SN. In other words, when VL_SN is the reference potential (0 V), VL_WL is preferably a negative potential (also referred to as a "negative potential" or a "negative bias").

[0153] By supplying a negative bias to the wiring WL[i], the transistor M11 can be turned off more reliably. In particular, a memory device that retains data for a long time even under high-temperature operation can be provided.

[0154] The transistor M11 can also be turned off by supplying a negative bias to the wiring BGL[i]. In particular, by supplying a negative bias to both the wiring WL[i] and the wiring BGL[i], the same effect can be achieved with a smaller bias than when a negative bias is supplied to only one of them. Furthermore, the electric field stress applied to the transistor M11 can be reduced, thereby improving the reliability of the transistor M11. Furthermore, the power consumption of the transistor M11 can be reduced. That is, the reliability of the memory device 100 can be improved and the power consumption can be reduced.

[0155] [Period T12] During the period T12, the potential of the wiring PL is set to a low level (VL_PL) to turn off the transistors Tr21 to Tr23. The wiring WL[i] is also selected. Specifically, the potential of the wiring WL[i] is set to a high level (VH_WL) to turn on the transistor M11 included in the memory cell 221[i,j]. This brings the wiring BILa[j] and the capacitor CA in the memory cell 221[i,j] into electrical continuity through the transistor M11, and the potential of the wiring BILa[j] changes depending on the amount of charge stored in the capacitor CA.

[0156] Here, VH_WL is preferably a potential higher than VH_SP. Specifically, VH_WL is preferably a potential higher than the potential obtained by adding Vth of the transistor M11 to VH_SP.

[0157] 9 illustrates a case where data "1" is stored in memory cell 221[i,j] and a large amount of charge is stored in capacitance element CA. Specifically, when a large amount of charge is stored in capacitance element CA, charge is released from capacitance element CA to wiring BILa[j], causing the potential of wiring BILa[j] to rise by ΔV1 from potential Vpre. On the other hand, when data "0" is stored in memory cell 221[i,j] and a small amount of charge is stored in capacitance element CA, charge flows from wiring BILa[j] to capacitance element CA, causing the potential of wiring BILa[j] to fall by ΔV2 (not shown).

[0158] In the period T12, the potential of the wiring CSEL is at a low level (VL_CSEL), the transistors Tr41 and Tr42 are off in the input / output circuit 134[j], the potentials of the wiring SP and the wiring SN are at the potential Vpre, and the sense amplifier circuit 133[j] remains in a stopped state.

[0159] [Period T13] During the period T13, the potential of the wiring SP is changed to a high level (VH_SP), and the potential of the wiring SN is changed to a low level (VL_SN). This causes the sense amplifier circuit 133[j] to enter an active state. The sense amplifier circuit 133[j] has a function of amplifying the potential difference (ΔV1 in FIG. 9 ) between the wiring BILa[j] and the wiring BILb[j]. When the sense amplifier circuit 133[j] enters an active state, the potential of the wiring BILa[j] approaches the potential of the wiring SP (VH_SP) from Vpre+ΔV1. Furthermore, the potential of the wiring BILb[j] approaches the potential of the wiring SN (VL_SN) from Vpre.

[0160] Note that at the beginning of the period T13, when the potential of the wiring BILa[j] is Vpre-ΔV2, the sense amplifier circuit 133[j] becomes active, so that the potential of the wiring BILa[j] approaches the potential of the wiring SN (VL_SN) from Vpre-ΔV2. Also, the potential of the wiring BILb[j] approaches the potential of the wiring SP (VH_SP) from the potential Vpre.

[0161] During the period T13, the potential of the wiring PL is low (VL_PL), and the transistors Tr21 to Tr23 are off in the precharge circuit 132[j]. The potential of the wiring CSEL is low (VL_CSEL), and the transistors Tr41 and Tr42 are off in the input / output circuit 134[j]. The potential of the wiring WL[i] is high (VH_WL), and the transistor M11 in the memory cell 221[i,j] is on. Therefore, in the memory cell 221[i,j], an amount of charge corresponding to the potential (VH_SP) of the wiring BILa[j] is stored in the capacitor CA.

[0162] [Period T14] In the period T14, the potential of the wiring CSEL is controlled to turn on the input / output circuit 134[j]. Specifically, the potential of the wiring CSEL is set to a high level (VH_CSEL) to turn on the transistors Tr41 and Tr42. As a result, the potential of the wiring BILa[j] is supplied to the wiring SALa[j], and the potential of the wiring BILb[j] is supplied to the wiring SALb[j].

[0163] Note that during the period T14, the potential of the wiring PL is low (VL_PL), and the transistors Tr21 to Tr23 in the precharge circuit 132[j] are off. The potential of the wiring WL[i] is high (VH_WL), and the transistor M11 included in the memory cell 221[i,j] is on. The potential of the wiring SP is high (VH_SP), the potential of the wiring SN is low (VL_SN), and the sense amplifier circuit 133[j] is in an active state. Therefore, in the memory cell 221[i,j], charge corresponding to the potential (VH_SP) of the wiring BILa[j] is stored in the capacitor CA.

[0164] [Period T15] In the period T15, the potential of the wiring CSEL is controlled to turn off the input / output circuit 134[j]. Specifically, the potential of the wiring CSEL is set to a low level (VL_CSEL), thereby turning off the transistors Tr41 and Tr42.

[0165] Furthermore, in the period T15, VL_WL is supplied to the wiring WL[i] to deselect the wiring WL[i]. Specifically, the potential of the wiring WL[i] is set to a low level (VL_WL). Then, the transistor included in the memory cell 221[i,j] is turned off. As a result, an amount of charge corresponding to the potential (VH_SP) of the wiring BLa is held in the capacitor CA included in the memory cell 221[i,j]. Therefore, even after the data is read, the data is held in the memory cell 221[i,j].

[0166] By setting the potential VL_WL supplied to the wiring WL[i] to a negative potential, the transistor M11 can be turned off more reliably. In particular, a memory device that retains data for a long time even under high-temperature operation can be provided.

[0167] Note that even if the input / output circuit 134[j] is turned off in the period T15, the potentials of the wirings BILa[j] and BILb[j] are held by the sense amplifier circuit 133[j] as long as the sense amplifier circuit 133[j] is in an operating state. Therefore, the sense amplifier circuit 133[j] has a function of temporarily holding data read from the memory cell 221[i,j].

[0168] By the above operation, data can be read from the memory cell 221[i,j]. The read data is supplied to the output circuit 140 (see FIG. 1) via the wiring SALa[j] or the wiring SALb[j]. Note that data can also be read from the memory cell 221[i+1,j] in the same manner as the memory cell 221[i,j].

[0169] <Write Mode> Next, an example of the operation of the sense amplifier circuit 133[j] when writing data to the memory cell 221[i,j] will be described using the timing chart shown in Fig. 10. Writing data to the memory cell 221[i+1,j] can be performed using the same principle as above.

[0170] [Period T21] During the period T21, the transistors Tr21 to Tr23 included in the precharge circuit 132[j] are turned on to initialize the potentials of the wirings BILa[j] and BILb[j]. Specifically, the potential of the wiring PL is set to a high level (VH_PL), and the transistors Tr21 to Tr23 are turned on. As a result, the potential Vpre of the wiring PRE is supplied to the wirings BILa[j] and BILb[j]. Note that the potential Vpre can be, for example, (VH_SP+VL_SN) / 2.

[0171] [Period T22] After that, during the period T22, the potential of the wiring PL is set to a low level (VL_PL) to turn off the transistors Tr21 to Tr23. Furthermore, the wiring WL[i] connected to the memory cell 221[i,j] to which data is written is selected. Specifically, the potential of the wiring WL[i] is set to a high level (VH_WL) to turn on the transistor M11 included in the memory cell 221[i,j]. As a result, electrical continuity is established between the wiring BILa[j] and the capacitor CA in the memory cell 221[i,j] through the transistor M11.

[0172] Although a negative bias can be continuously supplied to the wiring BGL[i] during the write mode operation, it is preferable to increase the potential of the wiring BGL[i] in accordance with the potential of the wiring WL[i] becoming VH_WL. In FIG. 10, the potential of the wiring BGL[i] is set to an L potential (for example, 0 V) ​​in the period T22.

[0173] By increasing the potential of the wiring BGL[i] in accordance with the increase in the potential of the wiring WL[i], the threshold voltage Vth of the transistor M11 is reduced, and the operating speed can be increased. Therefore, the time required for a write operation can be shortened. Therefore, the operating speed of the memory device 100 can be increased.

[0174] Furthermore, by increasing the potential of both the wiring WL[i] and the wiring BGL[i], the same write speed can be achieved with a smaller increase in potential than when increasing the potential of only one of them. Therefore, the electric field stress applied to the transistor M11 can be reduced, thereby improving the reliability of the transistor M11. Furthermore, the power consumption of the transistor M11 can be reduced. That is, the reliability of the memory device 100 can be improved and the power consumption can be reduced.

[0175] At this time, if data "1" is already stored in memory cell 221[i,j], charge is released from capacitive element CA to wiring BILa[j], causing the potential of wiring BILa[j] to rise by ΔV1 from potential Vpre.

[0176] [Period T23] In the period T23, the potential of the wiring SP is set to a high level (VH_SP), the potential of the wiring SN is set to a low level (VL_SN), and the sense amplifier circuit 133[j] is put into an operating state.

[0177] [Period T24] In the period T24, the potential of the wiring CSEL is controlled to turn on the input / output circuit 134[j]. As a result, the wiring BILa[j] and the wiring SALa[j] are brought into electrical continuity, and the wiring BILb[j] and the wiring SALb[j] are brought into electrical continuity.

[0178] The data signal WDATA is supplied to the input / output circuit 134[j] through the wiring SALa[j] and the wiring SALb[j]. By supplying a write potential corresponding to the data signal WDATA to the wiring SALa[j] and the wiring SALb[j], a write potential is applied to the wiring BILa[j] and the wiring BILb[j] through the input / output circuit 134[j]. For example, when data "0" is stored in the memory cell 221[i,j], a low level (VL_SN) is supplied to the wiring SALa[j] and a high level (VH_SP) is supplied to the wiring SALb[j].

[0179] As a result, the on / off states of the transistors Tr31 to Tr34 included in the sense amplifier circuit 133[j] are inverted, the potential (VL_SN) of the wiring SN is supplied to the wiring BILa[j], and the potential (VH_SP) of the wiring SP is supplied to the wiring BILb[j]. Thus, an amount of charge corresponding to the potential (VL_SN) representing data "0" is accumulated in the capacitor CA. By this operation, data can be written to the memory cell 221[i,j].

[0180] [Period T25] During the period T25, VL_WL is supplied to the wiring WL[i] to deselect the wiring WL[i]. This allows the charge written to the memory cell 221[i,j] to be retained. If the potential of the wiring BGL[i] is also increased in accordance with the increase in the potential of the wiring WL[i], the potential of the wiring BGL[i] is lowered in accordance with the potential of the wiring WL[i] becoming VL_WL. For example, −3 V is supplied to the wiring BGL[i].

[0181] In addition, the potential of the wiring CSEL is set to a low level (VL_CSEL), thereby turning off the transistors Tr41 and Tr42.

[0182] After the potential of the wiring SALa[j] is supplied to the wiring BILa[j], even if the transistors Tr41 and Tr42 are turned off in the input / output circuit 134[j], the potentials of the wiring BILa[j] and the wiring BILb[j] are held by the sense amplifier circuit 133[j] as long as the sense amplifier circuit 133[j] is in an operating state. Therefore, the timing at which the transistors Tr41 and Tr42 are changed from an on state to an off state may be before or after the wiring WL[i] is selected.

[0183] By the above operation, data can be written to the memory cell 221[i,j]. Note that data can be written to the memory cell 221[i+1,j] in the same manner as the memory cell 221[i,j].

[0184] By setting the potential VL_WL supplied to the wiring WL[i] to a negative potential, the transistor M11 can be turned off more reliably. In particular, a memory device that retains data for a long time even under high-temperature operation can be provided.

[0185] <Refresh mode> In order to maintain the data written in the memory cell 221[i,j], a refresh operation (rewrite operation) is performed at regular intervals. An example of the operation of the sense amplifier circuit 133[j] during the refresh operation will be described using the timing chart shown in FIG. 11. The refresh operation can also be performed according to the same principle as above.

[0186] [Period T31] In the period T31, the transistors Tr21 to Tr23 included in the precharge circuit 132[j] are turned on to initialize the potentials of the wirings BILa[j] and BILb[j]. Specifically, the potential of the wiring PL is set to a high level (VH_PL) to turn on the transistors Tr21 to Tr23. As a result, the potential Vpre of the wiring PRE is supplied to the wirings BILa[j] and BILb[j].

[0187] [Period T32] During the period T32, the potential of the wiring PL is set to a low level (VL_PL) to turn off the transistors Tr21 to Tr23. Furthermore, the wiring WL[i] connected to the memory cell 221[i,j] to which data is written is selected. Specifically, the potential of the wiring WL[i] is set to a high level (VH_WL) to turn on the transistor M11 included in the memory cell 221[i,j]. As a result, electrical continuity is established between the wiring BILa[j] and the capacitor CA in the memory cell 221[i,j] through the transistor M11.

[0188] While the device is operating in the refresh mode, it is possible to keep supplying a negative bias to the wiring BGL[i]. However, it is preferable to increase the potential of the wiring BGL[i] in accordance with the potential of the wiring WL[i] becoming VH_WL. In FIG. 11, the potential of the wiring BGL[i] is set to an L potential (for example, 0 V) ​​in the period T32.

[0189] By increasing the potential of the wiring BGL[i] in accordance with the increase in the potential of the wiring WL[i], the operation speed of the transistor M11 can be increased. Therefore, the time required for refresh can be shortened. Therefore, the operation speed of the memory device 100 can be increased.

[0190] Furthermore, by increasing the potential of both the wiring WL[i] and the wiring BGL[i], the same write speed can be achieved with a smaller increase in potential than when increasing the potential of only one of them. Therefore, the electric field stress applied to the transistor M11 can be reduced, thereby improving the reliability of the transistor M11. Furthermore, the power consumption of the transistor M11 can be reduced.

[0191] At this time, if data "1" is already stored in memory cell 221[i,j], charge is released from capacitive element CA to wiring BILa[j], causing the potential of wiring BILa[j] to rise by ΔV1 from potential Vpre.

[0192] [Period T33] During the period T33, the potential of the wiring SP is set to a high level (VH_SP), the potential of the wiring SN is set to a low level (VL_SN), and the sense amplifier circuit 133[j] is put into an operating state. When the sense amplifier circuit 133[j] is put into an operating state, the potential of the wiring BILa[j] approaches the potential of the wiring SP (VH_SP) from Vpre+ΔV1. Furthermore, the potential of the wiring BILb[j] approaches the potential of the wiring SN (VL_SN) from Vpre. Note that in this specification and elsewhere, the time required for the period T33 is referred to as a "write time."

[0193] [Period T34] During the period T34, VL_WL is supplied to the wiring WL[i] to deselect the wiring WL[i]. Specifically, the potential of the wiring WL[i] is set to a low level (VL_WL), thereby turning off the transistor included in the memory cell 221[i,j]. As a result, an amount of charge corresponding to the potential (VH_SP) of the wiring BLa is held in the capacitor CA included in the memory cell 221[i,j].

[0194] Furthermore, by setting VL_WL to a negative potential, the transistor M11 can be turned off more reliably. In particular, a memory device that retains data for a long time even under high temperature operation can be provided.

[0195] In addition, the potential of the wiring BGL[i] is lowered in response to the potential of the wiring WL[i] becoming VL_WL. For example, −3 V is supplied to the wiring BGL[i].

[0196] In the refresh mode, since no data is read or written, the input / output circuit 134[j] can remain in the off state. Therefore, the refresh mode can be performed in a shorter time than the read mode and the write mode. Note that the refresh mode for the memory cell 221[i+1,j] can be performed in the same way as for the memory cell 221[i,j].

[0197] <Stacked Configuration Example> The circuits, transistors, and the like that constitute the memory device 100 can be provided on the same plane, but it is preferable to provide them with at least a partial overlap. For example, by providing the peripheral circuit 111 and the memory cell array 201 so that they overlap, the area occupied by the memory device 100 can be reduced. This allows for an increased degree of integration of the memory device 100. Furthermore, since the signal propagation distance between the peripheral circuit 111 and the memory cell array 201 is shortened, the parasitic resistance and parasitic capacitance between the peripheral circuit 111 and the memory cell array 201 are reduced, thereby realizing reduced power consumption and signal delay. This allows for improved operating speed and reduced power consumption.

[0198] 12A and 12B show a configuration example in which p-type transistors constituting the peripheral circuit 111 are formed in an element layer 60 including Si transistors, n-type transistors constituting the peripheral circuit 111 are formed in an element layer 70 including OS transistors on the element layer 60, and memory cells 221 are formed in an element layer 80 including OS transistors on the element layer 70. FIG. 12A is a schematic perspective view showing an example of a stacked configuration of the memory device 100. FIG. 12B is a schematic perspective view showing a part of the memory device 100 with circuit symbols. FIG. 12B shows a bit line driver circuit 130 as an example of the peripheral circuit 111.

[0199] By not providing an n-channel transistor in the element layer 60 including a Si transistor, the process for forming an n-channel Si transistor can be reduced. Furthermore, an OS transistor formed in the element layer 70 over the element layer 60 and functioning as an n-channel transistor in the peripheral circuit 111 preferably uses an In oxide for the semiconductor layer in which a channel is formed. For example, it is more preferable to use a single-crystal or polycrystalline In oxide for the semiconductor layer. An OS transistor using an In oxide for the semiconductor layer has higher field-effect mobility than an OS transistor using an In—Ga—Zn oxide for the semiconductor layer. On the other hand, its off-state current tends to be slightly higher than that of an OS transistor using an In—Ga—Zn oxide for the semiconductor layer, but is still sufficiently lower than that of a Si transistor. Furthermore, because hydrogen is less likely to become an impurity element in an OS transistor using an In oxide for the semiconductor layer, it can be provided adjacent to a Si transistor using hydrogen for stabilizing its characteristics. Furthermore, the characteristics of an OS transistor are less likely to fluctuate even in a high-temperature environment, allowing stable operation. Therefore, even when an OS transistor is provided overlapping a Si transistor, it is less susceptible to heat generation from the Si transistor. An n-channel OS transistor using an In oxide for a semiconductor layer is suitable for an area-saving CMOS circuit in combination with a p-channel Si transistor.

[0200] 12B , OS transistors using an In oxide in their semiconductor layers are preferably used for at least some or all of the transistors Tr21, Tr22, Tr23, Tr33, Tr34, Tr41, and Tr42. In particular, OS transistors using an In oxide in their semiconductor layers are preferably used for the transistors Tr33 and Tr34 that constitute the sense amplifier circuit 133. Furthermore, OS transistors using an In oxide in their semiconductor layers are preferably used for the transistors Tr21, Tr22, and Tr23 that constitute the precharge circuit 132. Using OS transistors using an In oxide in their semiconductor layers for the transistors Tr33 and Tr34 can increase the amplification speed of read data signals. Using OS transistors using an In oxide in their semiconductor layers for the transistors Tr21, Tr22, and Tr23 can increase the precharge speed of the wirings BILa and BILb.

[0201] Furthermore, by using OS transistors with an In oxide semiconductor layer for each of the transistors Tr41 and Tr42, the speed of data input / output with the outside can be increased. Note that OS transistors with an In—Ga—Zn oxide semiconductor layer can also be used for the transistors Tr41 and Tr42. By using OS transistors with an In—Ga—Zn oxide semiconductor layer for each of the transistors Tr41 and Tr42, connection with the outside can be more reliably cut off. Therefore, intrusion of noise from the outside can be prevented, and the reliability of the memory device 100 can be improved.

[0202] Furthermore, it is preferable to use an OS transistor using In—Ga—Zn oxide for its semiconductor layer as the transistor M11 included in the memory cell 221. It is more preferable to use an In—Ga—Zn oxide with crystallinity, such as c-axis-aligned crystalline line (CAAC), for its semiconductor layer. As described above, an OS transistor using In—Ga—Zn oxide for its semiconductor layer has lower field-effect mobility than an OS transistor using In oxide for its semiconductor layer, but has a smaller off-state current. Furthermore, an OS transistor using In—Ga—Zn oxide for its semiconductor layer can easily be realized as a normally-off transistor. Therefore, it is suitable for the transistor M11, which is required to retain data for a long time.

[0203] 13A and 13B , it is also possible to stack a plurality of element layers 80 including OS transistors and provide a memory cell 221 in each of the element layers 80. Fig. 13A is a schematic perspective view showing an example of a stacked structure of the memory device 100. Fig. 13B is a schematic perspective view showing a part of the memory device 100 with circuit symbols.

[0204] 13A and 13B show an example in which a memory cell 221[i,j] is formed in an element layer 80[i] that is the ith element layer 80, and a memory cell 221[i+1,j] is formed in an element layer 80[i+1] that is the (i+1)th element layer 80. By stacking multiple memory cells 221 connected to one bit line driver circuit 130 in the Z direction, the area occupied by the memory device 100 can be further reduced.

[0205] In this way, by changing the composition of the material constituting the semiconductor layer depending on the characteristics required of the transistor, it is possible to realize a memory device that is small in area, low in power consumption, operates at high speed, and can retain data for a long time.

[0206] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0207] Embodiment 3 In this embodiment, a transistor that can be used for a semiconductor device such as a memory device according to one embodiment of the present invention will be described.

[0208] <Transistor Configuration Example 1> Figure 14A is a plan view of a transistor 300A that can be used for a semiconductor device such as a memory device according to one embodiment of the present invention. Figure 14B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Figure 14A. Figure 14C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Figure 14A. Note that Figure 14A is a cross-sectional view of the transistor 300A in the channel length direction, and Figure 14C is a cross-sectional view of the transistor 300A in the channel width direction.

[0209] 14A to 14C , the transistor 300A includes a semiconductor layer 520a disposed on a substrate 501, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, the insulating layer 580, and the insulating layer 550.

[0210] 14B and 14C , the top surface of the conductive layer 560 is substantially flush with the top surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may be collectively referred to as the semiconductor layer 520.

[0211] The conductive layer 542a functions as one of a source electrode and a drain electrode of the transistor 300A. The conductive layer 542b functions as the other of the source electrode and the drain electrode of the transistor 300A. In this specification, the conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0212] 14A to 14C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. The insulating layer 554 is in contact with the side surface of the semiconductor layer 520c, the top surface and side surface of the conductive layer 542a, the top surface and side surface of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0213] The channel of the transistor 300A is formed in a region of the semiconductor layer 520 that overlaps with the conductive layer 560. Therefore, the channel length L of the transistor 300A can be expressed as the length of the conductive layer 560 in the X direction in the region that overlaps with the semiconductor layer 520. The channel length L of the transistor 300A is formed between a region that functions as a source and a region that functions as a drain of the semiconductor layer 520. Therefore, the channel length L of the transistor 300A can be expressed as the distance from the end of the conductive layer 542a to the end of the conductive layer 542b that face each other.

[0214] The channel width W of the transistor 300A can be expressed as the length of the semiconductor layer 520 in the Y direction in a region where the semiconductor layer 520 overlaps with the conductive layer 560 .

[0215] Although the transistor 300A has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be used. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may also have a stacked structure of two or more layers.

[0216] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the semiconductor layer 520b, and the second metal oxide has a composition similar to that of the semiconductor layer 520a.

[0217] Here, the conductive layer 560 functions as a gate electrode of the transistor, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 560 is formed so as to fill the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 300A, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 300A. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0218] 14A to 14C , the conductive layer 560 includes a conductive layer 560a provided over the insulating layer 550 and a conductive layer 560b provided over the conductive layer 560a, both of which are located inside the opening of the insulating layer 580. The insulating layer 550 and the conductive layer 560 are provided so as to be embedded in the opening of the insulating layer 580. Although the conductive layer 560 in the transistor 300A has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 can have a single-layer structure or a stacked structure of three or more layers.

[0219] The transistor 300A includes an insulating layer 502 disposed on a substrate 501, an insulating layer 514 disposed on the insulating layer 502, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0220] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 300A. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0221] When an oxide semiconductor is used for the semiconductor layer 520, an insulating layer having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0222] Furthermore, an insulating layer having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) is preferably used for the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522 and the insulating layer 554. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0223] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are sandwiched between the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from diffusing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0224] 14B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) that is connected to the transistor 300A and functions as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 that functions as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 14B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0225] Here, the height of the top surface of the conductive layer 545 can be made approximately the same as the height of the top surface of the insulating layer 581. Note that although the transistor 300A has a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can also have a single layer structure or a stacked structure of three or more layers.

[0226] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b that is located between the conductive layer 542a and the conductive layer 542b in a plan view, it is possible to prevent a channel from being formed in that region.

[0227] Next, the detailed configuration of the transistor 300A will be described.

[0228] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0229] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom and sidewall of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The top surface of the conductive layer 505b is lower than the top end (the highest position as viewed from the substrate surface) of the conductive layer 505a and the top surface of the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is equal to or approximately equal to the height of the top end of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0230] In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c can be formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, or a conductive material that has a function of suppressing the diffusion of oxygen.

[0231] By using a conductive material that can reduce hydrogen diffusion for the conductive layers 505a and 505c, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0232] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0233] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 14C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0234] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0235] The conductive layer 505 can be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, without being limited thereto, a conductive layer that functions as a wiring can also be provided under the conductive layer 505.

[0236] The insulating layer 514 may be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from diffusing from the substrate side to the transistor 300A. Therefore, the insulating layer 514 may be formed using an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, the insulating layer 514 may be formed using an insulating material that has a function of preventing the diffusion of oxygen (i.e., through which the oxygen is less likely to permeate).

[0237] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 300A side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing to the substrate side of the insulating layer 514.

[0238] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0239] When the conductive layer 505 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0240] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 300A is improved.

[0241] 14C , the insulating layer 524 may have a thinner film thickness in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b than in other regions. The insulating layer 524 preferably has a film thickness in the region that does not overlap with the insulating layer 554 and the semiconductor layer 520b that allows sufficient diffusion of the oxygen.

[0242] The insulating layer 522 is made of a material that functions as a barrier insulating film that suppresses diffusion of impurities such as water or hydrogen from the substrate side into the transistor 300A, similar to the insulating layer 514. For example, the insulating layer 522 is made of a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be suppressed from entering the transistor 300A from the outside.

[0243] Furthermore, a material having a function of suppressing oxygen diffusion (the above-mentioned oxygen is less likely to permeate) is preferably used for the insulating layer 522. For example, a material having lower oxygen permeability than the insulating layer 524 is used for the insulating layer 522. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, so that oxygen diffusing from the semiconductor layer 520 toward the substrate can be reduced. Furthermore, reaction of the conductive layer 505 with oxygen contained in the insulating layer 524 or the semiconductor layer 520 can be suppressed.

[0244] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses release of oxygen from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 300A.

[0245] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulating layer 522. Alternatively, the insulating layer 522 can be subjected to nitriding treatment. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be stacked on the insulating layer 522. For example, the insulating layer 522 can have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0246] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３An insulating layer containing a so-called high-k material such as BST can be used as a single layer or a laminate. As transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulating layers. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0247] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0248] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0249] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a is made higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In is made higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c can use the metal oxide used for the semiconductor layer 520a or the semiconductor layer 520b.

[0250] The energy of the conduction band minimum of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c is preferably higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In is preferably higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0251] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, it is preferable that the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c is low.

[0252] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. For example, when the semiconductor layer 520b is an In—Ga—Zn oxide, the semiconductor layers 520a and 520c can be made of In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide, or the like. The semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of In—Ga—Zn oxide and gallium oxide on the In—Ga—Zn oxide can be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0253] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:1 [atomic ratio] or the vicinity thereof, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:5 [atomic ratio] or the vicinity thereof, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and gallium oxide.

[0254] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect level density at the interface between the semiconductor layers 520a and 520b and at the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 300A to achieve high on-state current and high frequency characteristics. Note that if the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect level density at the interface between the semiconductor layers 520b and 520c, it is expected that the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, since the semiconductor layer 520c has a stacked structure and an oxide not containing In is located above the stacked structure, it is possible to suppress In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating layer, and diffusion of In can cause poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, a highly reliable semiconductor device can be provided.

[0255] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably formed using a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0256] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 300A. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0257] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0258] The insulating layer 550 is formed using an insulating material in which the concentration of impurities such as water or hydrogen is reduced, similarly to the insulating layer 524. The thickness of the insulating layer 550 is greater than or equal to 1 nm and less than or equal to 20 nm.

[0259] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0260] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 14A to 14C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0261] The conductive layer 560a may be made of any of the above-mentioned conductive layers having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or may be made of a conductive material having a function of suppressing diffusion of oxygen.

[0262] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0263] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure. For example, the conductive layer 560b may have a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0264] 14B and 14C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 300A, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 300A and improves its frequency characteristics.

[0265] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from diffusing from the insulating layer 580 side to the transistor 300A. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 14B and 14C , the insulating layer 554 is provided in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. This structure can prevent hydrogen contained in the insulating layer 580 from penetrating into the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0266] Furthermore, an insulating material that has a function of suppressing oxygen diffusion (is less permeable to oxygen) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0267] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, and suppresses the transistor from becoming normally on.

[0268] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium, or the like can be used.

[0269] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0270] The insulating layer 574, like the insulating layer 514, is formed using an insulating material that functions as a barrier insulating film that suppresses diffusion of impurities such as water or hydrogen from above into the insulating layer 580. The insulating layer 574 is formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0271] 14A to 14C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524.

[0272] Conductive layers 545a and 545b are disposed in openings formed in insulating layers 581, 574, 580, and 554. The conductive layers 545a and 545b are provided opposite each other with the conductive layer 560 interposed therebetween. When viewed from a direction perpendicular to the Z direction, it is preferable that the positions of the upper surfaces of the conductive layers 545a and 545b coincide or substantially coincide with the position of the upper surface of the insulating layer 581.

[0273] Note that an insulating layer 541a is provided in contact with the inner wall of one of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner wall of the other of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0274] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b can also have a stacked structure of two or more layers.

[0275] When the conductive layer 545 has a stacked structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used for the conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen can be prevented from diffusing from above the insulating layer 581 into the semiconductor layer 520 through the conductive layers 545a and 545b.

[0276] The insulating layer 541a and the insulating layer 541b may be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layer 541a and the insulating layer 541b are provided in contact with the insulating layer 554, and thus can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from diffusing into the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0277] <Transistor Configuration Example 2> A modification of the transistor 300A shown in FIG. 14 is shown in FIG. 15. FIG. 15A is a plan view of a transistor 300B which is a modification of the transistor 300A. FIG. 15B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 15A. FIG. 15C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 15A. Because the transistor 300B is a modification of the transistor 300A, differences between the transistor 300B and the transistor 300A will be mainly described.

[0278] The transistor 300B has a structure in which the semiconductor layer 520c and the conductive layer 505c are removed from the structure of the transistor 300A. Reducing the number of components of the transistor can reduce production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, thereby improving manufacturing yield.

[0279] Furthermore, the transistor 300B has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0280] Note that an insulating layer is preferably provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550 side, excessive supply of oxygen from the insulating layer 550 side to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0281] <Constituent Materials of Transistor> Next, constituent materials that can be used for the transistor 300 (transistor 300A and transistor 300B) will be described.

[0282] [Substrate] When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light transparency, heat resistance sufficient to withstand heat treatment, and the like. For example, an insulating layer substrate, a semiconductor substrate, or a conductive layer substrate can be used as the substrate. Examples of insulating layer substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0283] Examples of semiconductor substrates include semiconductor substrates made of silicon, germanium, or the like, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having an insulating layer region inside the aforementioned semiconductor substrate, such as SOI (Silicon On Insulator) substrates. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0284] Conductive layer substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Also, there are substrates having metal nitrides, substrates having metal oxides, etc. Furthermore, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating layer substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive layer substrate.

[0285] Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0286] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, it is also possible to use a substrate on which elements are provided. Elements that can be provided on the substrate include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0287] [Insulating Layer] An inorganic insulating film is used for each of the insulating layers (insulating layer 502, insulating layer 516, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film can also be used for an insulating layer included in a semiconductor device.

[0288] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0289] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the insulating layer that functions as the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0290] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0291] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0292] [Conductive Layer] For the conductive layers (conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 300, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements, is preferably used. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0293] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, and ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include materials containing tungsten oxide and indium oxide, materials containing titanium oxide and indium oxide, materials containing indium oxide and tin oxide (ITO: Indium Tin Oxide), materials containing titanium oxide and indium tin oxide, materials containing silicon and indium tin oxide (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and materials containing tungsten oxide and indium zinc oxide. In this specification and the like, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0294] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0295] It is also possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. Also, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. Also, a stacked structure can be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0296] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 520, the conductive layers 542a and 542b are conductive layers in contact with the semiconductor layer 520. Therefore, the conductive layers 542a and 542b may be formed using a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductive layer), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b.

[0297] By using a conductive material containing oxygen for the conductive layers 542a and 542b, the conductive layers 542a and 542b can maintain their conductivity even when they absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 542a and 542b, this is preferable because the conductive layers 542a and 542b can maintain their conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like can be used for the conductive layers 542a and 542b.

[0298] [Semiconductor Layer] As the semiconductor layer, single crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, and the like can be used alone or in combination. Using a single crystal semiconductor or a crystalline semiconductor for the semiconductor layer in which a channel is formed is preferable because it can suppress deterioration of transistor characteristics. As the semiconductor material, for example, a semiconductor made of an element such as silicon or germanium can be used. Alternatively, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can be used. As the compound semiconductor, an organic material having semiconducting properties (also referred to as an "organic semiconductor"), a metal nitride having semiconducting properties (also referred to as a "nitride semiconductor"), or a metal oxide having semiconducting properties (also referred to as an "oxide semiconductor") can be used. Note that these semiconductor materials can contain impurities as dopants.

[0299] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon.

[0300] Two-dimensional materials that function as semiconductors can also be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0301] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0302] [Metal Oxide Layer] The transistor 300 preferably includes an oxide semiconductor, which is a type of metal oxide, in the semiconductor layer 520 including a channel formation region. That is, the transistor 300 is preferably an OS transistor.

[0303] An OS transistor is a transistor that has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0304] On the other hand, the source and drain regions in a metal oxide that functions as a semiconductor of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, and have a high carrier concentration and low resistance due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0305] The band gap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide functioning as a semiconductor and having a wide band gap for the semiconductor layer 520, the off-state current of the transistor 300 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0306] A metal oxide that can be used for a semiconductor layer of an OS transistor preferably contains at least indium (In). The metal oxide preferably contains at least one of indium (In) and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0307] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0308] For example, indium oxide (In oxide) can be used as a metal oxide for a semiconductor layer of an OS transistor. Examples of the metal oxide include zinc oxide (Zn oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”), and indium aluminum. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0309] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0310] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0311] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0312] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0313] <Example of Cross-Sectional Structure of Memory Device> Figure 16 shows an example of the cross-sectional structure of a portion of the memory device 100 shown in Figures 12A and 12B. In Figure 16, one transistor 400 is illustrated as an example of the plurality of transistors included in the element layer 60. The transistor 400 in the element layer 60 corresponds to, for example, transistor Tr31. Also in Figure 16, one transistor 300B is illustrated as an example of the plurality of transistors included in the element layer 70. The transistor 300B in the element layer 70 corresponds to, for example, transistor Tr33. Also in Figure 16, one transistor 300B is illustrated as an example of the plurality of transistors included in the element layer 80. The transistor 300B in the element layer 80 corresponds to, for example, transistor M11.

[0314] The transistor 400 is provided over a substrate 371 and includes a conductive layer 376 functioning as a gate electrode, an insulating layer 375 functioning as a gate insulating layer, a semiconductor region 373 formed of part of the substrate 371, and low-resistance regions 374a and 374b formed of part of the substrate 371 and functioning as source and drain regions. The substrate 371 can be, for example, a single crystal silicon substrate.

[0315] In the transistor 400, a semiconductor region 373 (a part of the substrate 371) where a channel is formed has a convex shape. A conductive layer 376 is provided to cover the side and top surfaces of the semiconductor region 373 with an insulating layer 375 interposed therebetween. A material for adjusting the work function can also be used for the conductive layer 376. Such a transistor is also called a Fin-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulating layer that functions as a mask for forming the convex portion can also be provided in contact with the top of the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape can also be formed by processing an SOI substrate.

[0316] The peripheral circuit 111 is configured to include a plurality of transistors 400. The transistors 400 can be used not only as transistors included in the bit line driver circuit 130 but also as transistors included in other circuits (not shown) formed in the element layer 60. The transistor 400 shown in FIG. 16 is an example, and the structure is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration or driving method.

[0317] The element layer 60 may be provided with a wiring layer including an interlayer film, wiring, plugs, and the like. A plurality of wiring layers may be provided as needed. In this specification, the wiring and the plug may be integrated. That is, a portion of the conductive layer may function as the wiring, and a portion of the conductive layer may function as the plug.

[0318] For example, an insulating layer 390, an insulating layer 391, an insulating layer 393, and an insulating layer 394 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 392 and the like are formed to be embedded in the insulating layer 390 and the insulating layer 391. A conductive layer 395, a conductive layer 397, and the like are formed to be embedded in the insulating layer 393 and the insulating layer 394. The conductive layer 392, the conductive layer 395, the conductive layer 397, and the like function as contact plugs or wirings.

[0319] In addition, the insulating layer functioning as an interlayer film preferably functions as a planarizing film that covers the uneven shape below it. By providing the planarizing film, the coverage of conductive layers, insulating layers, and the like formed in subsequent steps can be improved. For example, the top surface of the insulating layer 391 may be subjected to CMP treatment or the like to improve the planarity.

[0320] 16, an insulating layer 396, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 394 and the conductive layer 395. A conductive layer 385, a conductive layer 386, and the like are formed on the insulating layer 396, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 385, the conductive layer 386, and the like function as contact plugs or wirings.

[0321] 16, the insulating layer 502 of the element layer 70 is provided over the insulating layer 384. In the element layer 70 shown in FIG. 16, a conductive layer 583 and an insulating layer 582 are provided over the insulating layer 581. The conductive layer 583 is formed so as to be embedded in the insulating layer 582. The conductive layer 583 is connected to the conductive layer 545a. An insulating layer 584 is provided over the conductive layer 583 and the insulating layer 582, and an insulating layer 585 is provided over the insulating layer 584. The insulating layer 502 of the element layer 80 is provided over the insulating layer 585 of the element layer 70.

[0322] As described above, the transistor 300B in the element layer 70 corresponds to the transistor Tr33. Therefore, it is preferable to use an In oxide for the semiconductor layer 520 of the transistor 300B in the element layer 70. In particular, it is more preferable to use a single-crystal or polycrystalline In oxide.

[0323] In the element layer 80, an insulating layer 586 is provided over the conductive layer 583 and the insulating layer 582. A conductive layer 588 and an insulating layer 587 are provided over the insulating layer 586. The conductive layer 588 is formed so as to be embedded in the insulating layer 587. A region where the conductive layer 583 and the conductive layer 588 overlap with each other with the insulating layer 586 interposed therebetween functions as a capacitor CA. In the element layer 80, an insulating layer 584 is provided over the conductive layer 588 and the insulating layer 587, and an insulating layer 585 is provided over the insulating layer 584.

[0324] As described above, the transistor 300B in the element layer 80 corresponds to the transistor M11. Therefore, it is preferable to use an In—Ga—Zn oxide as the semiconductor layer 520 of the transistor 300B in the element layer 80. In particular, it is more preferable to use an In—Ga—Zn oxide having crystallinity, such as CAAC.

[0325] By stacking the element layer 60, the element layer 70, and the element layer 80, it is possible to reduce the area occupied by the memory device 100. Furthermore, when the area occupied is the same, it is possible to increase the storage capacity per unit area.

[0326] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0327] Embodiment 4 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a memory device of one embodiment of the present invention will be described.

[0328] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0329] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0330] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 17A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 17B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0331] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 17B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 17A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 17A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 17A.

[0332] 17A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0333] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0334] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0335] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0336] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 17A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0337] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0338] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0339] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0340] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0341] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0342] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0343] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0344] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0345] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0346] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 17C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0347] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0348] 17C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0349] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0350] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0351]

[0352] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0353] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0354] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0355] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0356] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0357] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0358] Embodiment 5 In this embodiment, examples of electronic components and electronic devices in which the memory device described in the above embodiment can be used will be described.

[0359] <Electronic Component> FIG. 18A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 18A has memory device 710 in mold 711. Memory device 100 described in the above embodiment can be used as memory device 710. FIG. 18A omits some details in order to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to memory device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0360] The memory device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking multiple memory cell arrays. The drive circuit layer 715 corresponds to the aforementioned element layer 60 and element layer 70, and the memory layer 716 corresponds to the element layer 80. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0361] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0362] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0363] The memory device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0364] 18B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 710 provided on the interposer 731.

[0365] The electronic component 730 shows an example in which the memory device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0366] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0367] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, a TSV can also be used as the through electrode.

[0368] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0369] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0370] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space corresponding to the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure can be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0371] It is also preferable to provide a heat sink (heat dissipation plate) overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 710 and the height of the semiconductor device 735.

[0372] In order to mount the electronic component 730 on another substrate, it is preferable to provide electrodes 733 on the bottom of the package substrate 732. Fig. 18B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 can also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0373] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0374] <Electronic Device> A storage device according to one embodiment of the present invention can be installed in various electronic devices. In particular, the storage device according to one embodiment of the present invention can be used as a built-in memory in an electronic device. Examples of the electronic device include electronic devices with relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound players.

[0375] The electronic device of one embodiment of the present invention preferably includes an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can also be used for contactless power transmission.

[0376] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0377] An electronic device of one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 19A , 19B , 19C , 19D , (E1), and (E2).

[0378] 19A illustrates a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0379] 19B shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0380] 19A and 19B, a smartphone and a desktop information terminal are shown as examples of electronic devices, but information terminals other than smartphones and desktop information terminals can also be used. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0381] 19C shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0382] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0383] 19D shows a portable game machine 5200, which is an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0384] 19D illustrates a portable game machine as an example of a game machine, but the game machine to which the storage device according to one embodiment of the present invention can be applied is not limited to this. Examples of game machines to which the storage device according to one embodiment of the present invention can be applied include home-use stationary game machines, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0385] Fig. 19E1 shows an automobile 5700 as an example of a moving body, and Fig. 19E2 shows the area around the windshield inside the automobile. Fig. 19E2 shows display panels 5701, 5702, and 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0386] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. In addition, the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0387] The display panel 5704 can display an image from an imaging device (not shown) provided in the automobile 5700 to complement a view (blind spot) blocked by a pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, the blind spot can be complemented and safety can be improved. Furthermore, by displaying an image that complements an invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0388] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and a storage device according to one embodiment of the present invention can be applied to these moving objects.

[0389] A storage device according to one embodiment of the present invention can retain data for a long time even in a high-temperature environment and can operate at high speed even in a low-temperature environment. By using a storage device according to one embodiment of the present invention in the various electronic devices described above, highly reliable electronic devices that can operate reliably in both high-temperature and low-temperature environments can be provided. Furthermore, the power consumption of the electronic devices can be reduced. Therefore, according to one embodiment of the present invention, a storage device suitable for IoT (Internet of Things), AI edge computing, and the like can be realized.

[0390] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0391] 13: Transistor, 14: Transistor, 15: Transistor, 16: Transistor, 17: Transistor, 18: Transistor, 19: Transistor, 20: Transistor, 21: Transistor, 33: Transistor, 34: Transistor, 35: Transistor, 36: Transistor, 37: Transistor, 38: Transistor, 39: Transistor, 40: Transistor, 41: Transistor, 54: Circuit, 55: Circuit, 60: Element layer, 70: Element layer, 80: Element layer, 100: Memory device, 111: Peripheral circuit, 121: Row decoder, 122: Word bit line driver circuit, 130: bit line driver circuit, 131: column decoder, 132: precharge circuit, 133: sense amplifier circuit, 134: input / output circuit, 140: output circuit, 150: negative potential generation circuit, 151: negative potential generation circuit, 160: control logic circuit, 201: memory cell array, 211: memory cell, 212: memory cell, 213: memory cell, 214: memory cell, 221: memory cell, 300: transistor, 371: substrate, 373: semiconductor region, 375: insulating layer, 376: conductive layer, 382: insulating layer, 384: insulating layer, 385 : conductive layer, 386: conductive layer, 390: insulating layer, 391: insulating layer, 392: conductive layer, 393: insulating layer, 394: insulating layer, 395: conductive layer, 396: insulating layer, 397: conductive layer, 400: transistor, 501: substrate, 502: insulating layer, 505: conductive layer, 514: insulating layer, 516: insulating layer, 520: semiconductor layer, 522: insulating layer, 524: insulating layer, 541: insulating layer, 542: conductive layer, 545: conductive layer, 550: insulating layer, 554: insulating layer, 560: conductive layer, 574: insulating layer, 580: insulating layer, 581: insulating layer, 582: insulating layer, 583: conductive layer, 584: insulating layer, 585: insulating layer, 586: insulating layer, 587: insulating layer, 588: conductive layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: memory device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display,5303: keyboard, 5500: information terminal, 5510: housing, 5511: display unit, 5700: automobile, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator compartment door, 5803: freezer compartment door, 132[1]: precharge circuit, 132[j]: precharge circuit, 133[j]: sense amplifier circuit, 134[j]: input / output circuit, 211[i,j]: memory cell, 221[i,j]: memory cell, 221[i+1,j]: memory cell, 300A: transistor transistor, 300B: transistor, 374a: low resistance region, 374b: low resistance region, 505a: conductive layer, 505b: conductive layer, 505c: conductive layer, 520a: semiconductor layer, 520b: semiconductor layer, 520c: semiconductor layer, 541a: insulating layer, 541b: insulating layer, 542a: conductive layer, 542b: conductive layer, 545a: conductive layer, 545b: conductive layer, 560a: conductive layer, 560b: conductive layer, 80[i]: element layer, 80[i+1]: element layer, ADDR: address signal, BGL[i]: wiring, BIL: wiring, BILa: wiring, BILa[1]: wiring, BILa[j]: wiring, B ILb: wiring, BILb[j]: wiring, BL: wiring, BL[j]: wiring, BLa: wiring, BLa[j]: wiring, BLb[j]: wiring, C21: capacitance element, C22: capacitance element, C23: capacitance element, C24: capacitance element, CA: capacitance element, CAL: wiring, CB: capacitance element, CC: capacitance element, CE: signal, CLK: signal, CLKB: signal, CSEL: wiring, IN: input terminal, LVB: circuit, M11: transistor, M12: transistor, M13: transistor, M14: transistor, M15: transistor, M16: transistor, M21: transistor, M2 4: transistor, M31: transistor, M34: transistor, N11: node, N12: node, N13: node, N14: node, OUT: output terminal, PL: wiring, PRE: wiring, RBL: wiring, RDATA: data signal, RE: signal, RWL: wiring, SALa: wiring, SALa[j]: wiring, SALb: wiring, SALb[j]: wiring, SL: wiring, SN: wiring, SP: wiring, T11: period, T12: period, T13: period, T14: period, T15: period, T21: period, T22: period, T23: period, T24: period, T25: period, T31: period,T32: period, T33: period, T34: period, Tr21: transistor, Tr22: transistor, Tr23: transistor, Tr31: transistor, Tr32: transistor, Tr33: transistor, Tr34: transistor, Tr41: transistor, Tr42: transistor, VBL: low power supply potential, VDD: high power supply potential, Vg: gate voltage, VIH: high power supply potential, VIH_IN: wiring, VLL: low power supply potential, VL L_IN: wiring, Vpre: potential, VSS: low power supply potential, VSS_IN: wiring, Vth: threshold voltage, WBL: wiring, WDATA: data signal, WE: signal, WI: signal, WI[i]: signal, WI_IN: input terminal, WIB: signal, WIB[i]: signal, WIB_IN: input terminal, WL: wiring, WL[1]: wiring, WL[i]: wiring, WL[i+1]: wiring, WL_OUT: output terminal, WLB: wiring, WLB[i]: wiring,

Claims

1. A memory device comprising a memory cell and a peripheral circuit, wherein the memory cell comprises a first transistor and a capacitance element, and the peripheral circuit comprises a second transistor and a third transistor, wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitance element, and a second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor, and wherein semiconductor layers of the first transistor, the second transistor, and the third transistor have compositions different from one another.

2. A memory device according to claim 1, wherein the first transistor has a first gate and a second gate, the first gate and the second gate having an overlapping region with a channel formation region interposed therebetween, and the peripheral circuit has the function of supplying a first potential to the first gate that is lower than a potential supplied to a second terminal of the first transistor, and the function of supplying a second potential to the second gate that is lower than the first potential, during a period in which the memory cell retains data.

3. A memory device according to claim 1 or claim 2, wherein the semiconductor layer of the first transistor contains indium, gallium, zinc, and oxygen, the semiconductor layer of the second transistor contains indium and oxygen, and the semiconductor layer of the third transistor contains silicon.

4. A memory device according to claim 3, wherein the semiconductor layer of the second transistor is a polycrystalline or single-crystalline semiconductor layer.

5. The memory device according to claim 3, wherein the first transistor and the second transistor are n-type transistors, and the third transistor is a p-type transistor.

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