Drive circuit and semiconductor relay comprising same

Abstract

A drive circuit 100 comprises: an oscillation circuit 20 that is connected to a first and a second input terminal 11, 12 into which an input signal is input, and that outputs, in response to the input signal, a first and a second signal which have opposite phases from one another; and an isolated drive circuit 40 that is electrically connected to the oscillation circuit 20. The isolated drive circuit 40 includes a first input end 41 into which the first signal is input, a second input end 42 into which the second signal is input, an isolated circuit 44 which has a first and a second capacitor C1, C2, a diode bridge DB which rectifies a signal input thereto by the isolated circuit 44, a control circuit 44 which is connected to the diode bridge DB, and a first and a second output end 45, 46 which are each connected to the control circuit 44.

Description

Drive circuit and semiconductor relay equipped with the same

[0001] The present disclosure relates to a drive circuit and a semiconductor relay including the same.

[0002] Various semiconductor relays are known that output an output signal in response to an input signal while maintaining isolation between the input and output. Several isolation methods have been proposed for semiconductor relays. For example, in an optical isolation method, an input signal drives a light-emitting element to output an optical signal, a light-receiving element disposed apart from the light-emitting element receives the optical signal, and an output MOSFET is turned on and off based on the received light signal output from the light-receiving element.

[0003] In the capacitive isolation method, a capacitor is connected in series between the input terminal and the output terminal, and a time-varying signal is input to a control circuit via the capacitor, which then turns the output on and off (see, for example, Patent Documents 1 to 3). The capacitive isolation method allows for smaller size and lower power consumption than the optical isolation method. It can also be used at high temperatures.

[0004] Japanese Patent Application Laid-Open No. 2012-124806 U.S. Patent No. 11,984,802 U.S. Patent No. 09,531,376

[0005] However, in the conventional configuration described in Patent Document 1, transient voltage fluctuations that occur between the primary side where the input signal is input and the secondary side where the input signal is rectified, in other words, common mode noise, can cause voltage to be generated on the secondary side, which can lead to malfunction of the semiconductor relay.

[0006] In the conventional configuration disclosed in Patent Document 2, a transmission circuit, a rectifier circuit, an isolation circuit, a detection circuit, and a drive circuit are connected to each input terminal, and the drive circuit drives a MOSFET connected to the output terminal. However, this configuration results in a large circuit scale.

[0007] The present disclosure has been made in consideration of the above points, and its purpose is to provide a drive circuit that can prevent malfunctions caused by transient voltage fluctuations such as common-mode noise, and a semiconductor relay including the same.

[0008] To achieve the above object, a drive circuit according to the present disclosure includes a first input terminal and a second input terminal to which an input signal is input, an oscillation circuit connected to the first input terminal and the second input terminal and outputting a first signal and a second signal having an opposite phase to the first signal in response to the input signal, and an isolated drive circuit connected to the oscillation circuit. The isolated drive circuit has a first input terminal to which the first signal is input, a second input terminal to which the second signal is input, and an isolated circuit having a first capacitor connected to the first input terminal and a second capacitor connected to the second input terminal. The isolated drive circuit further includes a diode bridge that rectifies the signal input from the isolated circuit, a control circuit connected to the diode bridge, and first and second output terminals connected to the control circuit, respectively. When the first signal is input to the first input terminal and the second signal is input to the second input terminal, the control circuit rectifies the first signal and the second signal and controls so that the potential difference between the first output terminal and the second output terminal becomes a first value. When the first signal is not input to the first input terminal and the second signal is not input to the second input terminal, the control circuit does not rectify the first signal and the second signal, and controls the potential difference between the first output terminal and the second output terminal to be a second value different from the first value.

[0009] The semiconductor relay according to the present disclosure includes the drive circuit, a switching circuit controlled by the control circuit, and first and second output terminals. The switching circuit has a first FET including a fifth drain connected to the first output terminal. The switching circuit controls the conduction state between the first and second output terminals in response to an output voltage of the control circuit.

[0010] According to the present disclosure, in a capacitively isolated semiconductor relay, it is possible to prevent malfunction when a transient voltage fluctuation such as common mode noise occurs on the output side.

[0011] FIG. 1 is a functional block diagram of a semiconductor relay according to a first embodiment. FIG. 2 is a circuit diagram of a main part of the semiconductor relay according to the first embodiment. FIG. 3A is a diagram showing a signal flow and a time change in an output signal in a capacitively coupled drive circuit. FIG. 3B is a diagram showing a signal flow and a time change in an output signal in another capacitively coupled drive circuit. FIG. 4A is a diagram showing a signal flow and a time change in an output signal in a capacitively coupled drive circuit when common mode noise is present. FIG. 4B is a diagram showing a signal flow and a time change in an output signal in another capacitively coupled drive circuit when common mode noise is present. FIG. 5 is a circuit diagram comparing a main part of a conventional semiconductor relay with a main part of the semiconductor relay according to this embodiment. FIG. 6 is a diagram showing a signal flow within the insulating drive circuit when a first signal and a second signal are not input. FIG. 7 is a diagram showing a time change in potential of each part of the insulating drive circuit when the insulating drive circuit is operating. FIG. 8 is a diagram showing a signal flow within the insulating drive circuit when the insulating drive circuit is operating. FIG. 9 is a circuit diagram of an insulating drive circuit according to a first modification. Fig. 10 is a diagram showing the flow of signals inside the insulation drive circuit when the semiconductor relay is on. Fig. 11A is a diagram showing the flow of signals inside the insulation drive circuit when the semiconductor relay is off and the source potential of the discharge element is dropping. Fig. 11B is a diagram showing the flow of signals inside the insulation drive circuit when the semiconductor relay is off and the source potential of the discharge element is rising. Fig. 12 is a functional block diagram of a semiconductor relay according to a second embodiment. Fig. 13 is a functional block diagram of a semiconductor relay according to a third embodiment. Fig. 14 is a circuit diagram of the semiconductor relay according to the third embodiment. Fig. 15 is a diagram showing the flow of signals on the input side of the semiconductor relay when the charge pump circuit is operating. Fig. 16 is a circuit diagram of a charge pump circuit according to a second modification.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following description of the preferred embodiments is merely exemplary in nature and is not intended to limit the present disclosure, its applications, or its uses.

[0013] (Embodiment 1) [Configuration of semiconductor relay and drive circuit] Fig. 1 is a functional block diagram of a semiconductor relay according to embodiment 1. Fig. 2 is a circuit diagram of a main part of the semiconductor relay according to embodiment 1.

[0014] As shown in FIG. 1, the semiconductor relay 200 has first and second input terminals 11, 12, an oscillation circuit 20, an insulating boost circuit 30, an insulating drive circuit 40, a discharge circuit 50, a switching circuit 60, and first and second output terminals 71, 72.

[0015] The second input terminal 12 is a GND terminal, and an input signal is input to the first input terminal 11. The oscillator circuit 20 outputs a first signal and a second signal having a predetermined frequency in response to the input signal. Of the two signal lines connecting the oscillator circuit 20 and the isolated boost circuit 30, a signal flowing through one signal line is the first signal, and a signal flowing through the other signal line is the second signal. The first signal and the second signal are 180° out of phase with each other. In other words, the second signal is a signal of opposite phase to the first signal. The first signal and the second signal are square waves with a duty ratio of approximately 50%. The configuration of the oscillator circuit 20 is not particularly limited; for example, the oscillator circuit 20 may be an RC oscillator circuit. In this case, the frequencies of the first signal and the second signal are determined by the resistance and capacitance values ​​within the circuit.

[0016] 2, the isolated boost circuit 30 includes a fourth capacitor (fourth capacitance) C4, a fifth capacitor (fifth capacitance) C5, and a boost rectifier circuit 31 that is configured with one or more diodes. The boost rectifier circuit 31 is, for example, a voltage doubler rectifier circuit.

[0017] When the first signal passes through the fourth capacitor C4, the DC component of the first signal is blocked, and only the AC component is boosted by the boost circuit and input to one of the two signal lines connecting the isolation boost circuit 30 and the discharge element 51. When the second signal passes through the fifth capacitor C5, the DC component of the second signal is blocked, and only the AC component is boosted and rectified by the boost rectifier circuit 31 and input to the other of the two signal lines connecting the isolation boost circuit 30 and the discharge element 51. The signal boosted by the boost rectifier circuit 31 is input to the gate (G) and source (S) of the switching circuit 60. More specifically, the signal boosted by the boost rectifier circuit 31 is input to the gate (G) and source (S) of the first output element 61 and the second output element 62, respectively. The signal boosted by the boost rectifier circuit 31 is also input to the drain and source (S) of the discharge element 51, respectively. This generates a predetermined potential difference between the drain and source (S) of the discharge element 51 .

[0018] In the semiconductor relay 200, the fourth capacitor C4 and the fifth capacitor C5 provide insulation between the input and output. In other words, the semiconductor relay 200 is a capacitively isolated semiconductor relay.

[0019] The discharge circuit 50 includes an isolation drive circuit 40 and a discharge element 51. The isolation drive circuit 40 includes a first input terminal 41 to which a first signal is input, a second input terminal 42 to which a second signal is input, an isolation circuit 43, a diode bridge DB, a control circuit 44, a first output terminal 45, and a second output terminal 46. The detailed configuration and function of the isolation drive circuit 40 will be described later.

[0020] 2, the discharge element 51 is a depletion-type metal oxide semiconductor field effect transistor (MOSFET). The gate (DG) of the discharge element 51 is connected to the second output terminal 46 of the isolation drive circuit 40, and the source (S) is connected to the first output terminal 45 of the isolation drive circuit 40.

[0021] As shown in FIG. 2 , the switching circuit 60 has a first output element 61 and a second output element 62. The first output element 61 and the second output element 62 are each an enhancement-type MOSFET, and their sources are connected to each other. That is, the first output element 61 and the second output element 62 are common-source connected. The drain of the first output element 61 is connected to a first output terminal 71, and the drain of the second output element 62 is connected to a second output terminal 72. Also, as shown in FIG. 2 , the drain of the discharge element 51 is connected to the gates (G) of the first output element 61 and the second output element 62, and the source (S) of the discharge element 51 is connected to the sources (S) of the first output element 61 and the second output element 62. Note that the first output element 61 and the second output element 62 are not limited to MOSFETs and may be FETs.

[0022] In this embodiment, the voltage between the gate (G) and source (S) of the switching circuit 60 is approximately 8 V to 12 V, and the threshold voltages of the first output element 61 and the second output element 62 are approximately 1 V to 3 V. However, these values ​​can be changed as appropriate depending on the design specifications of the semiconductor relay 200.

[0023] In the following description, the circuit of the semiconductor relay 200 excluding the switching circuit 60 , the first output terminal 71 , and the second output terminal 72 will be referred to as the drive circuit 100 .

[0024] In the drive circuit 100, the output terminal connected to the source (S) of the switching circuit 60 may be referred to as a first drive output terminal 52. In the drive circuit 100, the output terminal connected to the gate (G) of the switching circuit 60 may be referred to as a second drive output terminal 53.

[0025] The gate, source, and drain of the first output element 61 may be referred to as a fifth gate, a fifth source, and a fifth drain, respectively. The gate, source, and drain of the second output element 62 may be referred to as a sixth gate, a sixth source, and a sixth drain, respectively.

[0026] Next, the configuration of the insulating drive circuit 40 will be described in detail.

[0027] As shown in FIG. 2 , the isolation circuit 43 of the isolation drive circuit 40 has a first capacitor (first capacitance) C1 and a second capacitor (second capacitance) C2. The diode bridge DB is a bridge circuit composed of first to fourth diodes D1 to D4. Note that the number of diodes constituting the diode bridge DB is not limited to four. The control circuit 44 is a circuit in which a first MOSFET M1 and a second MOSFET M2, each of which is a p-channel MOSFET, are cascade-connected. Note that a first source of the first MOSFET M1 and a second drain of the second MOSFET M2 are connected to a second resistor R2. From another perspective, the second resistor R2 is connected in parallel to the cascade-connected circuit of the first MOSFET M1 and the second MOSFET M2.

[0028] In the following description, the anodes of the first to fourth diodes D1 to D4 may be referred to as the first to fourth anodes, and the cathodes may be referred to as the first to fourth cathodes. Also, the gates of the first MOSFET M1 and the second MOSFET M2 may be referred to as the first gate and the second gate, the sources thereof may be referred to as the first source and the second source, and the drains thereof may be referred to as the first drain and the second drain.

[0029] One end of the first capacitor C1 is connected to the first input terminal 41, and the other end is connected to a junction point between the first anode of the first diode D1 and the second cathode of the second diode D2 of the diode bridge DB. The first gate of the first MOSFET M1 is also connected to this junction point. In this case, when an AC current flows through the diode bridge DB, a first voltage corresponding to the potential at the junction point between the first anode of the first diode D1 and the second cathode of the second diode D2 is input to the first gate of the first MOSFET M1. The first voltage is a voltage generated when the first signal that has passed through the first capacitor C1 is input to the diode bridge DB.

[0030] One end of the second capacitor C2 is connected to the second input port 42, and the other end is connected to the junction point between the third anode of the third diode D3 and the fourth cathode of the fourth diode D4 of the diode bridge DB. The second gate of the second MOSFET M2 is also connected to this junction point. In this case, when an AC current flows through the diode bridge DB, a second voltage corresponding to the potential at the junction point between the third anode of the third diode D3 and the fourth cathode of the fourth diode D4 is input to the gate of the second MOSFET M2. The second voltage is a voltage generated when the second signal, which has passed through the second capacitor C2, is input to the diode bridge DB.

[0031] A first source of the first MOSFET M1 is connected to a cathode terminal N1, which is a connection point between the first cathode of the first diode D1 and the third cathode of the third diode D3. One end of the second resistor R2 and the source (S) of the discharge element 51 are also connected to this connection point.

[0032] The second drain of the second MOSFET M2 is connected via the first resistor R1 to an anode terminal N2, which is the connection point between the second anode of the second diode D2 and the fourth anode of the fourth diode D4. The connection point between the first resistor R1 and the second drain of the second MOSFET M2 is connected to the other end of the second resistor R2 and, via the second output terminal 46, to the gate (DG) of the discharge element 51.

[0033] As will be described in detail later, when a first signal is input to the first input terminal 41 and a second signal is input to the second input terminal 42, the control circuit 44 controls the potential difference between the first output terminal 45 and the second output terminal 46 to a predetermined value. When the first signal is not input to the first input terminal 41 and the second signal is not input to the second input terminal 42, the control circuit 44 controls the potential difference between the first output terminal 45 and the second output terminal 46 to be zero.

[0034] [Operation of the Semiconductor Relay] Next, the operation of the semiconductor relay 200 will be described.

[0035] When an input signal is input to the first input terminal 11 , the oscillation circuit 20 generates a first signal and a second signal and outputs them to the isolated boost circuit 30 .

[0036] The isolated boost circuit 30 generates the aforementioned signal, which is input to the gate (G) and source (S) of the switching circuit 60 via the discharge element 51 .

[0037] Meanwhile, the first signal and the second signal output from the oscillator circuit 20 are also input to the isolation drive circuit 40. The first signal that has passed through the first capacitor C1 and the second signal that has passed through the second capacitor C2 are each input to the diode bridge DB and rectified. The cathode terminal N1 has a higher potential than the anode terminal N2. In the discharge element 51, the gate (DG) and source (S) are connected via the diode bridge DB and the second resistor R2. While an AC current is flowing through the diode bridge DB, the gate (DG) of the discharge element 51 has a negative potential relative to the source (S).

[0038] For example, if the threshold voltage of the discharge element 51 is -2V, a voltage is generated that is the amplitude of the first signal and the second signal minus two of the forward voltages of the diodes used in the diode bridge DB, and when this voltage exceeds the threshold voltage, the discharge element 51 turns off. At this time, when one of the first gate of the first MOSFET M1 and the second gate of the second MOSFET M2 becomes a high voltage, the other becomes a low voltage, so no current flows through the control circuit 44. In other words, the gate (DG) and source (S) of the discharge element 51 are maintained in a non-conductive state, and the discharge element 51 is also maintained in an off state.

[0039] When the discharge element 51 is turned off, a signal output from the isolation boost circuit 30 is applied between the gate (G) and source (S) of the switching circuit 60, charging the first gate of the first output element 61 and the second gate of the second output element 62. This increases the potential of the gate (G) of the switching circuit 60. When the potential difference between the gate (G) and source (S) becomes higher than the threshold voltages of the first output element 61 and the second output element 62, the first output element 61 and the second output element 62 are turned on. As a result, conduction is established between the first output terminal 71 and the second output terminal 72, and the semiconductor relay 200 is turned on. In other words, signals can be transmitted between the first output terminal 71 and the second output terminal 72.

[0040] On the other hand, when the input signal is no longer input to the first input terminal 11, the oscillation circuit 20 does not operate, and the first signal and the second signal are no longer input to the isolated boost circuit 30 and the isolated drive circuit 40, respectively.

[0041] When the first signal and the second signal are not input to the isolation drive circuit 40, a current flows from the source (S) to the gate (DG) of the discharge element 51 via the second resistor R2, and the potential difference between the source (S) and the gate (DG) approaches zero. As a result, the discharge element 51 is turned on, and the charges stored in the first gate of the first output element 61 and the second gate of the second output element 62 are extracted and discharged. As a result, the gate (G) and source (S) of the switching circuit 60 are shorted by the discharge element 51.

[0042] As a result, the drain-source of each of the first output element 61 and the second output element 62 is not electrically connected, the first output terminal 71 is disconnected from the second output terminal 72, and the semiconductor relay 200 is turned off. In other words, a state is reached in which signals cannot be transmitted between the first output terminal 71 and the second output terminal 72.

[0043] [Effects, etc.] As described above, the drive circuit 100 according to this embodiment includes at least the first input terminal 11 , the second input terminal 12 , the oscillation circuit 20 , and the isolated drive circuit 40 .

[0044] An input signal is input to the first input terminal 11 and the second input terminal 12. The oscillation circuit 20 is connected to the first input terminal 11 and the second input terminal 12, and outputs a first signal and a second signal that is in opposite phase to the first signal in response to the input signal. The isolation drive circuit 40 is connected to the oscillation circuit 20.

[0045] The isolation drive circuit 40 includes at least a first input terminal 41 , a second input terminal 42 , an isolation circuit 43 , a diode bridge DB, a control circuit 44 , a first output terminal 45 , and a second output terminal 46 .

[0046] A first signal is input to the first input terminal 41 from the oscillator circuit 20, and a second signal, which is a signal having an opposite phase to the first signal, is input to the second input terminal 42 from the oscillator circuit 20.

[0047] The isolation circuit 43 includes a first capacitor C1 and a second capacitor C2. One end of the first capacitor C1 is connected to the first input terminal 41, and one end of the second capacitor C2 is connected to the second input terminal 42.

[0048] The diode bridge DB rectifies the signal input from the isolation circuit 43, i.e., the signal input from the other end of the first capacitor C1 and the other end of the second capacitor C2. The control circuit 44 is connected to the diode bridge DB, and the first output terminal 45 and the second output terminal 46 are connected to the control circuit 44.

[0049] When a first signal is input to the first input terminal 41 and a second signal is input to the second input terminal 42, the control circuit 44 rectifies the first signal and the second signal and controls the potential difference between the first output terminal 45 and the second output terminal 46 to be a predetermined value, which in this embodiment is equal to or less than the threshold voltage of the discharge element 51. When the first signal is not input to the first input terminal 41 and the second signal is not input to the second input terminal 42, the control circuit 44 controls the potential difference between the first output terminal 45 and the second output terminal 46 to be zero.

[0050] The control circuit 44 has at least a first MOSFET M1 and a second MOSFET M2. The first MOSFET M1 and the second MOSFET M2 are P-channel MOSFETs. The first MOSFET M1 has a first gate connected to a first capacitor C1 via a diode bridge DB, and a first source connected to a first output terminal 45. The second MOSFET M2 has a second gate connected to a second capacitor C2 via a diode bridge DB, and a second drain connected to a second output terminal 46. The first drain of the first MOSFET M1 is connected to a second source of the second MOSFET M2.

[0051] A first voltage is input to the first gate of the first MOSFET M1, and a second voltage is input to the gate of the second MOSFET M2. The first voltage is generated by inputting a first signal that has passed through the first capacitor C1 to the diode bridge DB. The second voltage is generated by inputting a second signal that has passed through the second capacitor C2 to the diode bridge DB.

[0052] The diode bridge DB is a bridge circuit composed of first to fourth diodes D1 to D4. The first anode of the first diode D1 is connected to a first capacitor C1. The second cathode of the second diode D2 is connected to the first anode of the first diode D1. The third anode of the third diode D3 is connected to the second capacitor C2. The fourth cathode of the fourth diode D4 is connected to the third anode of the third diode D3. The first cathode of the first diode D1 and the third cathode of the third diode D3 are connected at a cathode terminal N1. The second anode of the second diode D2 and the fourth anode of the fourth diode D4 are connected at an anode terminal N2. The cathode terminal N1 is connected to a first output terminal 45, and the anode terminal N2 is connected to a second output terminal 46. With the potential of the first output terminal 45 as a reference, while a first voltage is input to the first gate and a second voltage is input to the second gate, the potential of the second output terminal 46 as seen from the first output terminal 45 is negative.

[0053] By configuring the insulating drive circuit 40 in this way, it is possible to prevent malfunctions due to transient voltage fluctuations such as common mode noise in the capacitively insulating semiconductor relay 200. This will be described in further detail below.

[0054] Fig. 3A is a diagram showing signal flow and time changes in output signals in a capacitively coupled drive circuit. Fig. 3B is a diagram showing signal flow and time changes in output signals in another capacitively coupled drive circuit. Fig. 4A is a diagram showing signal flow and time changes in output signals in a capacitively coupled drive circuit when common mode noise is present. Fig. 4B is a diagram showing signal flow and time changes in output signals in another capacitively coupled drive circuit when common mode noise is present. Note that Fig. 4 also shows signal flow and time changes in output signals when the potential of node Na fluctuates with respect to the GND potential in another capacitively coupled drive circuit.

[0055] 3A to 4B correspond to the isolated boost circuit 30 shown in Fig. 1. Nodes Na and Nb, which are both ends of Cout in the rectifier circuits 30A and 30B, correspond to the source (S) and gate (G), respectively, of the switching circuit 60 in Fig. 2. Cout is not an actual element, but corresponds to the capacitance between the source (S) and gate (G) of the switching circuit 60.

[0056] As shown in FIG. 3A , an AC signal input to the input terminal Vin1 of the rectifier circuit 30A passes through a capacitor Cc1 connected to the input terminal Vin1 and is input to the junction between the cathode of diode Da and the anode of diode Dc. When the signal rises, diode Dc is forward biased, so the AC signal flows through diode Dc and charges Cout. On the other hand, when the signal falls, diode Da is forward biased, so the AC signal flows from Cout through diode Da and charges Cc1. The AC signal is rectified by capacitor Cc1 and diodes Da and Dc. The potential Vmid at the junction between the cathode of diode Da and the anode of diode Dc rises over time, repeatedly rising and falling according to the signal flow path. Furthermore, the potential Vout across Cout rises stepwise in response to changes in potential Vmid. Since capacitor Cc1 has a high withstand voltage, even if a potential difference occurs between input terminal Vin1 and the connection point between the cathode of diode Da and the anode of diode Dc, the operation of rectifier circuit 30A does not change within the withstand voltage range of capacitor Cc1.

[0057] 3B, an input terminal Vin2 is added, and a capacitor Cc2 is connected to the input terminal Vin2. A diode Db is connected in series between the diodes Da and Dc. The other end of the capacitor Cc1 is connected to the connection point between the cathode of the diode Da and the anode of the diode Db. The other end of the capacitor Cc2 is connected to the connection point between the cathode of the diode Db and the anode of the diode Dc.

[0058] In the rectifier circuit 30B, the AC signal input to the input terminal Vin2 is in opposite phase to the AC signal input to the input terminal Vin1. The basic operation of the rectifier circuit 30B is the same as that described with reference to FIG. 3A. The potential Vmid1 at the junction between the cathode of diode Da and the anode of diode Db rises over time, repeatedly rising and falling in accordance with the signal flow path. The potential Vmid2 at the junction between the cathode of diode Db and the anode of diode Dc also rises over time, repeatedly rising and falling in accordance with the signal flow path. However, the time changes of the potential Vmid1 and the time changes of the potential Vmid2 are in opposite phase, and the two amplitudes are superimposed to obtain the output voltage. Therefore, the potential Vout across Cout increases compared to the case shown in FIG. 3A. This is the same principle as a Dickson-type charge pump, and the output voltage can be increased by increasing the capacitance and diode configuration in cascade. In the rectifier circuit 30B, the number of diode connection stages is not limited to three.

[0059] Consider the case where a transient voltage fluctuation such as common mode noise occurs between the nodes Na and Nb on the input and output sides. Looking at the equivalent circuit, the potential of the node Na fluctuates in an AC manner, as shown in Figures 4A and 4B.

[0060] In this case, as shown in Fig. 4A, even if no AC signal is input to the input terminal Vin1, charging and discharging of the capacitors Ccp and Cout are repeated in response to fluctuations in the potential of the node Na, causing Vout to increase over time. As shown in Fig. 4B, this tendency is the same in the rectifier circuit 30B. In other words, the voltage on the output side rises even when no input signal is input to the input terminal.

[0061] FIG. 5 is a circuit diagram comparing the main parts of a conventional drive circuit with the main parts of the drive circuit according to this embodiment.

[0062] In the conventional drive circuit 110, a configuration is adopted in which a rectifier circuit 30A or 30B, or a diode connected in series to the rectifier circuit 30B, is further added as the isolated boost circuit 30. On the other hand, as shown in Fig. 5, the isolated drive circuit 40 is omitted.

[0063] In the conventional drive circuit 110, even if the input signal is stopped and an attempt is made to turn off the switching circuit 60, common mode noise may generate a voltage between the gate (G) and source (S) of the switching circuit 60, as described above, causing the switching circuit 60 to unintentionally turn on.

[0064] When the input signal is stopped, the discharge element 51 must remain on to suppress a rise in the potential at the gate (G) of the switching circuit 60. However, in the conventional drive circuit 110, even a small current flowing between the input terminals of the isolated boost circuit 30 turns off the discharge element 51, making it prone to malfunction. Specifically, when current flows through the series-connected diodes Da to Dc, only a current limited by the resistance value of the third resistor R3 flows through the discharge element 51 of the discharge circuit 50A, so the discharge element 51 is essentially in an off state, and the potential at the gate (G) of the switching circuit 60 rises. As a result, the drive circuit 110 turns on.

[0065] Therefore, in the drive circuit 100 of this embodiment, this problem is solved by using the insulating drive circuit 40 to directly drive the gate of the discharge element 51 .

[0066] 6 is a diagram showing the flow of signals inside the isolated drive circuit when the first signal and the second signal are not input. Note that Cout1 shown in FIG. 6 is not an actual element, but the capacitance between the gate (DG) and source (S) of the discharge element 51.

[0067] As already mentioned, when no input signal is input to the first input terminal 11, neither the first signal nor the second signal is input from the oscillation circuit 20 to the isolated drive circuit 40. Consider a case where, at this time, the source potentials of the switching circuit 60 and the discharge element 51 fluctuate, causing common mode noise to occur in the isolated drive circuit 40.

[0068] When the first signal is not input to the first input terminal 41 and the second signal is not input to the second input terminal 42, if the source potential of the discharge element 51 fluctuates by repeatedly rising and falling due to the generation of common mode noise, etc., a voltage may be generated at the gate (DG) of the discharge element 51.

[0069] As shown in Figure 6, when the source potential is rising, a voltage is generated across Cout1. Meanwhile, the same voltage is also applied to the cascade-connected circuit of the first MOSFET M1 and the second MOSFET M2, causing a through current to flow through this cascade-connected circuit. As a result, the gate (DG)-source (S) voltage of the discharge element 51 approaches zero, and the discharge element 51 enters the ON state. In other words, the OFF state of the semiconductor relay 200 is maintained. Meanwhile, when the source potential is falling, no through current flows through the cascade-connected circuit, so the gate (DG)-source (S) voltage of the discharge element 51 is maintained at zero.

[0070] According to this embodiment, the control circuit 44 is provided with a cascade-connected circuit of a first MOSFET M1 and a second MOSFET M2, each of which is a p-channel MOSFET, and the cascade-connected circuit is connected in parallel to the gate (DG) and source (S) of the discharge element 51. In this way, the gate (DG)-source (S) voltage of the discharge element 51 is controlled to be zero or close to zero, and the on state of the discharge element 51 is maintained. As a result, the off state of the semiconductor relay 200 is maintained.

[0071] Furthermore, by providing the insulating drive circuit 40 according to this embodiment, it is possible to prevent malfunction when the semiconductor relay 200 is in the ON state. This will be further explained below.

[0072] 7 is a diagram showing the time change of the potential of each part of the isolation drive circuit when the isolation drive circuit is operating. Note that the threshold voltage Vth shown in FIG. 7 is the threshold voltage of the first MOSFET M1 and the second MOSFET M2.

[0073] Consider a case where the semiconductor relay 200 is in the on state and there is no gradient in the source potential of the discharge element 51 with respect to time. In this case, as shown in the upper part of Fig. 7, the gate potential of the first MOSFET M1, i.e., the first voltage, and the gate potential of the second MOSFET M2, i.e., the second voltage, are square waves of opposite phase with respect to time.

[0074] Next, consider the case where the source potential of the discharge element 51 is inclined with respect to time. In this case, during the period when the source potential is rising, a through current flows through the cascade-connected circuit of the first MOSFET M1 and the second MOSFET M2. On the other hand, during the period when the source potential is falling, the change in the source potential acts in a direction that actively turns off the first MOSFET M1 and the second MOSFET M2, which are both p-channel MOSFETs.

[0075] 7, if the gradient of the source potential of the discharge element 51 with respect to time is equal to or less than a predetermined value, the through current flowing through the cascade-connected circuit of the first MOSFET M1 and the second MOSFET M2 when the source potential rises is small, and therefore the drop in the potential of the gate (DG) of the discharge element 51 is also small, and the discharge element 51 is maintained in the off state.

[0076] On the other hand, as shown in the lower part of Figure 7, if the slope of the source potential of the discharge element 51 with respect to time is steep, when the source potential rises, the through current flowing in the cascade connection circuit of the first MOSFET M1 and the second MOSFET M2 becomes large enough to be ignored.

[0077] Furthermore, when the semiconductor relay 200 is in the on state, the discharge element 51 is off, and the gate (DG)-source (S) voltage is determined by the negative voltage generated when the first signal and the second signal are input. However, if common-mode noise is present, the negative voltage caused by the common-mode noise is also added. On the other hand, when a through-current flows through the cascade-connected circuit of the first MOSFET M1 and the second MOSFET M2, a voltage caused by the amount of through-current is induced between the gate (DG) and source (S), which acts to reduce the absolute value of the negative voltage.

[0078] Therefore, when the through current increases, the gate (DG)-source (S) voltage shifts in the positive direction, and when it exceeds the threshold voltage Vth, the discharge element 51 turns on. As a result, the gate (G)-source (S) of the switching circuit 60 is short-circuited by the discharge element 51, and the semiconductor relay 200 cannot maintain the on state.

[0079] FIG. 8 is a diagram showing the flow of signals inside the isolated drive circuit when the isolated drive circuit is operating.

[0080] When the semiconductor relay 200 is in the on state, the isolation drive circuit 40 also operates by receiving the first and second signals, which are square waves of opposite phases. As described above, the first signal that has passed through the first capacitor C1 and the second signal that has passed through the second capacitor C2 are rectified by being input to the diode bridge DB. While the first and second signals are flowing through the diode bridge DB, the gate (DG) of the discharge element 51 has a negative potential relative to the source (S).

[0081] As shown in Figure 8, the phases of the first signal and the second signal change periodically, so that the signal inside the isolation drive circuit 40, specifically the flow of current flowing inside the isolation drive circuit 40, also changes periodically.

[0082] However, during a period in which the current changes, either the first MOSFET M1 or the second MOSFET M2 is off. For example, when the first signal is high and the second signal is low, the connection point between the anode of the first diode D1 and the cathode of the second diode D2 is at high potential, while the connection point between the anode of the third diode D3 and the cathode of the fourth diode D4 is at low potential. As a result, the second MOSFET M2 is on, but the first MOSFET M1 is off.

[0083] When the first signal is at a low potential and the second signal is at a high potential, the connection point between the anode of the first diode D1 and the cathode of the second diode D2 is at a low potential, while the connection point between the anode of the third diode D3 and the cathode of the fourth diode D4 is at a high potential, so that the first MOSFET M1 is turned on but the second MOSFET M2 is turned off.

[0084] In this way, while the first signal and the second signal are input and the isolation drive circuit 40 is operating, either the first MOSFET M1 or the second MOSFET M2 is always off, so no through current flows through the cascade-connected circuit. This prevents the gate (DG)-source (S) voltage of the discharge element 51 from shifting in the positive direction, and the off state of the discharge element 51 can be stably maintained. As a result, the on state of the semiconductor relay 200 can be stably maintained.

[0085] The first resistor R1 has the effect of strengthening the suppression of malfunctions caused by common-mode noise when the semiconductor relay 200 is off. When common-mode noise causes a through-current to flow through the first MOSFET M1 and the second MOSFET M2 while the semiconductor relay 200 is off, a voltage drop occurs due to the through-current and the resistance value of the first resistor R1, thereby reducing the potential difference between DG and S, i.e., the potential difference between the first output terminal 45 and the second output terminal 46. Without the first resistor R1, even if a through-current flows, power is supplied to the second output terminal 46 due to rectification of the diode bridge DB by common-mode noise. Therefore, when at least one of the first MOSFET M1 and the second MOSFET M2 is in a saturated state, the reduction in the aforementioned potential difference is small, and the semiconductor relay 200 may not be able to maintain its off state sufficiently.

[0086] The control circuit 44 further comprises a first resistor R1 connected in series with the first MOSFET M1 and the second MOSFET M2, and connected to the first output terminal 45 and the diode bridge DB.

[0087] The drive circuit 100 further includes an insulating boost circuit 30 , a discharge circuit 50 , a first drive output terminal 52 , and a second drive output terminal 53 .

[0088] The discharge circuit 50 is connected to a first drive output terminal 52 and a second drive output terminal 53, and has a discharge element 51 controlled by the isolation drive circuit 40. The discharge element 51 is a depletion-type MOSFET.

[0089] The isolated boost circuit 30 is connected to the discharge circuit 50 and the second drive output terminal 53, and applies a predetermined voltage to the discharge element 51 and the second drive output terminal 53 in response to an input signal. The isolated drive circuit 40 controls the potential difference between the first drive output terminal 52 and the second drive output terminal 53 based on the first signal and the second signal.

[0090] By configuring the drive circuit 100 in this manner, the potential difference between the first drive output terminal 52 and the second drive output terminal 53, which correspond to the input terminals of the switching circuit 60, can be controlled to turn the switching circuit 60 on and off.

[0091] The isolated boost circuit 30 also has a fourth capacitor C4, a fifth capacitor C5, and a boost rectifier circuit 31. The first signal that has passed through the fourth capacitor C4 and the second signal that has passed through the fifth capacitor C5 are input to the boost rectifier circuit 31, which generates a predetermined voltage. By configuring the isolated boost circuit 30 in this manner, the drive circuit 100 can transmit a signal from the input side to the output side while isolating the first input terminal 11, the second input terminal 12, and the oscillator circuit 20 on the input side from the discharge circuit 50, the first drive output terminal 52, and the second drive output terminal 53 on the output side.

[0092] The semiconductor relay 200 according to this embodiment includes a drive circuit 100, a switching circuit 60, a first output terminal 71, and a second output terminal 72.

[0093] The switching circuit 60 has a common-source-connected first output element (first FET) 61 and a second output element (second FET) 62. A fifth drain of the first output element 61 is connected to a first output terminal 71, and a sixth drain of the second output element 62 is connected to a second output terminal 72.

[0094] The switching circuit 60 controls the conduction state between the first output terminal 71 and the second output terminal 72 via the first output element 61 and the second output element 62 in accordance with the output voltage of the control circuit 44. Specifically, the switching circuit 60 brings the first output terminal 71 and the second output terminal 72 into conduction or non-conduction in accordance with the output voltage of the control circuit 44.

[0095] According to this embodiment, it is possible to prevent malfunction due to transient voltage fluctuations such as common mode noise in the capacitively isolated semiconductor relay 200. Furthermore, it is possible to prevent malfunction of the semiconductor relay 200 whether the semiconductor relay 200 is in the on state or the off state.

[0096] In this embodiment, an input signal is input to the first input terminal 11 and the second input terminal 12 is fixed to the GND potential, but an input signal may be input to the second input terminal 12 and the first input terminal 11 may be fixed to the GND potential. In that case, however, the arrangement and connection relationship of the elements inside the oscillation circuit 20, the isolated boost circuit 30, and the discharge circuit 50 may be changed from the configuration shown in FIG.

[0097] <Modification 1> Fig. 9 is a circuit diagram of an isolated drive circuit according to Modification 1. For ease of explanation, in Fig. 9 and the following drawings, the same parts as those in embodiment 1 are denoted by the same reference numerals, and detailed explanations thereof will be omitted.

[0098] The circuit configuration of the isolated drive circuit 40 mounted on the drive circuit 100 is not particularly limited to the configuration shown in Fig. 2. For example, as shown in Fig. 9, the isolated drive circuit 40 shown in Fig. 2 may be configured such that a third MOSFET M3 and a fourth MOSFET M4, each of which is a p-channel MOSFET, and a third capacitor (third capacitance) C3 are added to the control circuit 44. In the following description, the gates of the third MOSFET M3 and the fourth MOSFET M4 may be referred to as the third gate and the fourth gate, the sources of the third MOSFET M3 and the fourth MOSFET M4 may be referred to as the third source and the fourth source, and the drains of the fourth MOSFET M4 may be referred to as the third drain and the fourth drain.

[0099] In the control circuit 44 shown in FIG. 9, the third capacitor C3 is connected in parallel to the first MOSFET M1 and the second MOSFET M2.

[0100] The third MOSFET M3 is connected in parallel to the first MOSFET M1 and the second MOSFET M2. The third source of the third MOSFET M3 is connected to the cathode terminal N1. The fourth MOSFET M4 is also connected in parallel to the first MOSFET M1 and the second MOSFET M2. The fourth drain of the fourth MOSFET M3 is connected to the anode terminal N2 via the first resistor R1. The third drain of the third MOSFET M3 is connected to the fourth source of the fourth MOSFET M4. In other words, the control circuit 44 has two cascade-connected circuits in which p-channel MOSFETs are connected in series, and the two cascade-connected circuits are connected in parallel. The second voltage is input to the third gate of the third MOSFET M3, and the first voltage is input to the fourth gate of the fourth MOSFET M4.

[0101] 9, it is possible to stabilize the time fluctuation of the gate (DG)-source (S) voltage of the discharge element 51. This will be further explained.

[0102] Fig. 10 is a diagram showing the flow of signals inside the isolation drive circuit when the semiconductor relay is on. Fig. 11A is a diagram showing the flow of signals inside the isolation drive circuit when the semiconductor relay is off and the source potential of the discharge element is dropping. Fig. 11B is a diagram showing the flow of signals inside the isolation drive circuit when the semiconductor relay is off and the source potential of the discharge element is rising.

[0103] In addition, in Figures 10 to 11B, the oscillator circuit 20 connected to the first capacitor C1 and the second capacitor C2 and the oscillator circuit 20 connected to the fourth capacitor C4 and the fifth capacitor C5 are the same and are not separate.

[0104] As shown in FIG. 10 , when the semiconductor relay 200 is on and the first signal is high and the second signal is low, the first MOSFET M1 and the fourth MOSFET M4 are both turned on. Meanwhile, the second MOSFET M2 and the third MOSFET M3 are both turned off. Therefore, no through-current flows through either the cascade-connected circuit formed by the first MOSFET M1 and the second MOSFET M2 or the cascade-connected circuit formed by the third MOSFET M3 and the fourth MOSFET M4. Therefore, the gate (DG)-source (S) voltage of the discharge element 51 is maintained. Although not shown, when the first signal is low and the second signal is high, no through-current flows through either of the two cascade-connected circuits, and the gate (DG)-source (S) voltage of the discharge element 51 is maintained. However, at the timing when the potentials of the first signal and the second signal switch, a through current flows through the two cascade-connected circuits, but the amount of current is small, and the gate (DG)-source (S) voltage of the discharge element 51 is maintained.

[0105] 11A, when the semiconductor relay 200 is off and the source potential of the discharge element 51 is dropping, the first to fourth MOSFETs M1 to M4 are each turned off, as shown in Fig. 6. In other words, no through current flows through either of the two cascade-connected circuits, and the gate (DG)-source (S) voltage of the discharge element 51 is maintained at zero.

[0106] On the other hand, as shown in Fig. 11B, when the semiconductor relay 200 is off and the source potential of the discharge element 51 is rising, the first to fourth MOSFETs M1 to M4 are each turned on, as shown in Fig. 6. In other words, a through current flows through each of the two cascade-connected circuits. As a result, the gate (DG)-source (S) voltage of the discharge element 51 approaches zero, and the discharge element 51 is turned on. In other words, the semiconductor relay 200 is maintained in the off state.

[0107] According to this modification, in the control circuit 44, two cascade-connected circuits are connected in parallel, and the diode bridge DB is cross-connected to the gates of the first to fourth MOSFETs M1 to M4. When the cascade-connected circuits are in a single row, the current when the first signal and the second signal switch is different at the rising and falling edges of the first signal, resulting in a large difference in waveform fluctuation. On the other hand, by using two rows of cascade-connected circuits and cross-connecting the diode bridge DB to the first to fourth gates as shown in this modification, the total amount of current becomes uniform, making it easier to suppress voltage fluctuations.

[0108] The first resistor R1 and the third capacitor C3 form a kind of low-pass filter, which can stabilize the time fluctuation of the gate (DG)-source (S) voltage of the discharge element 51.

[0109] Second Embodiment FIG. 12 is a functional block diagram of a semiconductor relay according to a second embodiment.

[0110] The semiconductor relay 200 and the drive circuit 100 shown in FIG. 12 differ from the semiconductor relay 200 and the drive circuit 100 of the first embodiment shown in FIGS. 1 and 2 in that the insulating boost circuit 30 and the discharge element 51 are omitted.

[0111] For example, when a signal corresponding to the first signal is input to the first input terminal 11 and a signal corresponding to the second signal is input to the second input terminal 12 from an external circuit (not shown), the semiconductor relay 200 may be configured as shown in Fig. 12. In this configuration, the first capacitor C1 and the second capacitor C2 also function to provide insulation between the input and output. Furthermore, the cascade connection circuit and the second resistor R2 of the control circuit 44 discharge the fifth gate of the first output element 61 and the sixth gate of the second output element 62, respectively, and the diode bridge DB charges them.

[0112] According to this embodiment, it is possible to achieve the same effects as the configuration shown in the first embodiment. That is, it is possible to prevent malfunctions of the semiconductor relay 200 due to transient voltage fluctuations such as common-mode noise in the capacitively isolated semiconductor relay 200. Furthermore, it is possible to prevent malfunctions of the semiconductor relay 200 whether the semiconductor relay 200 is in the on state or the off state.

[0113] Furthermore, the semiconductor relay 200 of this embodiment is suitable for use as a relay for transmitting and interrupting signal levels, and the number of circuits to be mounted can be reduced, allowing the semiconductor relay 200 to be made smaller.

[0114] (Embodiment 3) Fig. 13 is a functional block diagram of a semiconductor relay according to embodiment 3. Fig. 14 is a circuit diagram of the semiconductor relay according to embodiment 3.

[0115] The semiconductor relay 200 of this embodiment shown in FIGS. 13 and 14 differs from the semiconductor relay 200 of the first embodiment shown in FIGS. 1 and 2 in that a charge pump circuit 80 and a signal generating circuit 90 are added.

[0116] In the semiconductor relay 200 of the present embodiment, similarly to the semiconductor relay 200 of the first embodiment, an input signal is input to at least one of the first input terminal 11 and the second input terminal 12. The oscillator circuit 20 is connected to the first input terminal 11 and the second input terminal 12, and outputs an oscillation signal in response to the input signal.

[0117] The charge pump circuit 80 is connected to the first input terminal 11, receives an input signal, and outputs a third voltage. When an input signal is input to the second input terminal 12, the charge pump circuit 80 is connected to the second input terminal 12. The signal generation circuit 90 outputs a third signal and a fourth signal based on the oscillation signal input from the oscillation circuit 20 and the third voltage input from the charge pump circuit 80.

[0118] The isolation boost circuit 30 outputs a fourth voltage based on the third and fourth signals input from the signal generation circuit 90, and the isolation drive circuit 40 controls the on / off of the discharge element 51 based on the third and fourth signals input from the signal generation circuit 90. The switching circuit 60 controls the conduction state between the first output terminal 71 and the second output terminal 72 depending on whether the discharge element 51 is in the on state or the off state.

[0119] The circuit configuration of the isolated boost circuit 30 is similar to that shown in FIG. 2 and includes at least a fourth capacitor C4, a fifth capacitor C5, and a boost rectifier circuit 31. The boost rectifier circuit 31 outputs a fourth voltage based on a third signal input to the fourth capacitor C4 and a fourth signal input to the fifth capacitor C5. In this embodiment, a capacitor C4A is connected in parallel to the fourth capacitor C4, and a capacitor C5A is connected in parallel to the fifth capacitor C5. The boost rectifier circuit 31 is a series-connected circuit of fifth to ninth diodes D5 to D9, and one end of each of the fourth capacitor C4, the fifth capacitor C5, and the capacitors C4A and C5A is connected to the connection point between the anode and cathode of each diode. By configuring the boost rectifier circuit 31 in this manner, the input signal can be boosted to a higher voltage than the boost rectifier circuit 31 of the first embodiment.

[0120] The charge pump circuit 80 includes first to fourth switches S1 to S4, sixth to eighth capacitors (sixth to eighth capacitances) C6 to C8, and first to third inverters IN1 to IN3. The sixth capacitor C6 and the seventh capacitor C7 have lower breakdown voltages than the fourth capacitor C4 and the fifth capacitor C5. The signal generation circuit 90 includes a level shift circuit 91 and fourth to sixth inverters IN4 to IN6.

[0121] The operations of the charge pump circuit 80 and the signal generating circuit 90 will now be described.

[0122] 15 is a diagram showing the signal flow on the input side of the semiconductor relay when the charge pump circuit is operating. In the example shown in Fig. 15, VDD is input as an input signal to the first input terminal 11, and the second input terminal 12 is fixed to the GND potential.

[0123] As shown in FIG. 15, the first to fourth switches S1 to S4 are periodically switched on and off during operation of the charge pump circuit 80. As shown in the upper part of FIG. 15, when the first switch S1 and the fourth switch S4 are on, the second switch S2 and the third switch S3 are off. In this case, the input signal VDD charges the eighth capacitor C8 via the first switch S1. Meanwhile, the oscillator circuit 20 outputs an oscillation signal, which is a clock signal that falls to a low potential, based on the input signal VDD. This oscillation signal is input to the first to third inverters IN1 to IN3, respectively.

[0124] The oscillation signal input to the first inverter IN1 is inverted and becomes a signal that rises to a high potential, causing the potential at the other end of the sixth capacitor C6 connected to the output terminal of the first inverter IN1 to rise and charge the seventh capacitor C7 via the fourth switch S4. Also, the second inverter IN2 and the third inverter IN3 are connected in series, and a low-potential signal is output from the output terminal of the third inverter IN3. Therefore, the eighth capacitor C8 connected to the output terminal of the third inverter IN3 remains charged.

[0125] The charging voltage of the sixth capacitor C6 is superimposed on the input signal VDD and input to the signal generating circuit 90. In other words, the third voltage VDDH described above is boosted higher than the input signal VDD. Furthermore, a seventh capacitor C7 is connected in parallel to the input terminal of the signal generating circuit 90. In other words, the third voltage VDDH, which is boosted higher than the input signal VDD, is applied to the terminal at both ends of the seventh capacitor C7 other than the terminal fixed to GND potential, i.e., the terminal at a higher potential.

[0126] Meanwhile, the charge pump circuit 80 periodically switches from the state shown in the upper part of Fig. 15 to the state shown in the lower part. In the state shown in the lower part of Fig. 15, when the second switch S2 and the third switch S3 are both on, the first switch S1 and the fourth switch S4 are both off. The oscillator circuit 20 outputs an oscillation signal, which is a clock signal that rises to a high potential, based on the input signal VDD that has been input. This oscillation signal is input to the first to third inverters IN1 to IN3, respectively.

[0127] The oscillation signal input to the first inverter IN1 is inverted and becomes a signal that falls to a low potential, and the terminal of the sixth capacitor C6 connected to the output terminal of the first inverter IN1 also becomes a low potential. Meanwhile, the input signal VDD is input to the sixth capacitor C6 via the third switch S3 and charges the sixth capacitor C6. A high-potential signal is output from the output terminal of the third inverter IN3. As a result, the potential at the other end of the eighth capacitor C8 connected to the output terminal of the third inverter IN3 rises, and the seventh capacitor C7 is charged via the second switch S2.

[0128] A third voltage VDDH obtained by superimposing the charging voltage of the eighth capacitor C8 on the input signal VDD is input to the signal generating circuit 90. The third voltage VDDH is also applied to the terminal at the higher potential of both ends of the seventh capacitor C7.

[0129] No steady current flows through the sixth capacitor C6 to which the output signal of the first inverter IN1 is input. The current consumption generated when the charge pump circuit 80 operates consists of the current consumed by the first to third inverters IN1 to IN3 when the phase of the oscillation signal switches, and the charge / discharge current generated in the sixth to eighth capacitors C6 to C8 immediately after the switch.

[0130] In this embodiment, as shown in FIG. 15, the first to fourth switches S1 to S4 in the charge pump circuit 80 are operated exclusively, and the sixth to eighth capacitors C6 to C8 are charged and discharged using an oscillation signal that drives the charge pump circuit 80.

[0131] In the signal generating circuit 90, the third voltage VDDH is input to the high potential power supply terminals of the fourth to sixth inverters IN4 to IN6 and to the input terminal of the level shift circuit 91. The fifth inverter IN5 and the sixth inverter IN6 are connected in series, and the fourth inverter IN4 and the series connection circuit of the fifth inverter IN5 and the sixth inverter IN6 are connected in parallel.

[0132] The third voltage VDDH input to the input terminal of the level shift circuit 91 is boosted by the level shift circuit 91 and input as a logic signal at the same level as VDDH to the fourth inverter IN4 and the series-connected circuit of the fifth inverter IN5 and the sixth inverter IN6. The output signal of the fourth inverter IN4 and the output signal of the series-connected circuit of the fifth inverter IN5 and the sixth inverter IN6 are in opposite phase to each other.

[0133] The output signal of the fourth inverter IN4 is input to the fourth capacitor C4 and capacitor C4A of the isolation boost circuit 30, and the output signal of the series connection circuit of the fifth inverter IN5 and sixth inverter IN6 is input to the fifth capacitor C5 and capacitor C5A of the isolation boost circuit 30. These output signals are boosted and rectified by the boost rectifier circuit 31 and input between the gate (DG) and source (S) of the discharge element 51 of the discharge circuit 50.

[0134] In addition, the output signal of the fourth inverter IN4 is input to the first capacitor C1 via the first input terminal 41 of the isolation drive circuit 40. The output signal of the series-connected circuit of the fifth inverter IN5 and the sixth inverter IN6 is input to the second capacitor C2 via the second input terminal 42 of the isolation drive circuit 40. That is, in the example shown in Fig. 14, the output signal of the fourth inverter IN4 is the above-mentioned first signal, and the output signal of the series-connected circuit of the fifth inverter IN5 and the sixth inverter IN6 is the above-mentioned second signal.

[0135] As described above, in the charge pump circuit 80, the first to fourth switches S1 to S4 are opened and closed exclusively, and the sixth to eighth capacitors C6 to C8 are charged and discharged using the same signal as the oscillation signal that drives the charge pump circuit 80. By doing so, the charge pump circuit 80 consumes the most power immediately after the potential of the oscillation signal switches. Similarly, the power consumption and supply are well balanced with the signal generation circuit 90, through which the most current flows immediately after the potential of the oscillation signal switches. This allows the capacitance of the eighth capacitor C8 to be reduced, for example, to a few pF, and therefore suppresses ripple in the output of the charge pump circuit 80, making it easier to incorporate the eighth capacitor C8 into the charge pump circuit 80.

[0136] The charge pump circuit 80 requires the MOSFETs and diodes to operate at a voltage higher than the power supply voltage of the circuit. However, this is often difficult to achieve with a typical CMOS (Complementary Metal Oxide Semiconductor) process due to issues with withstand voltage and isolation. The use of an SOI (Silicon-On-Insulator) process easily solves these issues. The same applies to the secondary-side isolated boost circuit 30 and the isolated drive circuit 40 that generates the negative potential. Furthermore, the SOI process insulates the back surface of the wafer from the front surface of the wafer on which the circuits are formed, and the input and output sides are isolated using deep trench isolation (DTI), ensuring a voltage difference between the circuits of 100 V or more. This allows the drive circuit 100 described in embodiment 3 to be easily configured on a single die. For example, a drive circuit 100 can be realized in which the oscillation circuit 20 and the isolated drive circuit 40 are formed on the same die. The charge pump circuit 80, signal generation circuit 90, discharge circuit 50, and isolated boost circuit 30 may also be formed on the same die.

[0137] When forming the drive circuit 100 using a CMOS process, in addition to the problems of withstand voltage and isolation, the back surface of one die is set to a single potential, so even if the withstand voltage of the insulating capacitance is sufficient, it is not possible to separate the ground potential between the input and output. For this reason, it is preferable to configure at least the input side circuit and the output side circuit as separate dies, with the insulating capacitance, for example, the fourth capacitor C4 and the fifth capacitor C5 as the boundary.

[0138] According to this embodiment, it is possible to achieve the same effects as the configuration shown in the first embodiment. That is, it is possible to prevent malfunctions of the semiconductor relay 200 due to transient voltage fluctuations such as common-mode noise in the capacitively isolated semiconductor relay 200. Furthermore, it is possible to prevent malfunctions of the semiconductor relay 200 whether the semiconductor relay 200 is in the on state or the off state.

[0139] Furthermore, in recent years, in the field of measuring instruments, there has been a demand for the semiconductor relay 200 to be more compact and have a lower operating voltage, i.e., to be more power-efficient and be usable in high-temperature environments. This embodiment can achieve these demands. This will be further explained below.

[0140] In order to reduce the through current that flows through the control circuit 44 when the potential of the source (S) of the discharge element 51 changes, it is preferable to drive the control circuit 44 with a signal having a higher frequency and a higher amplitude.

[0141] Although it is easy to increase the frequencies of the first and second signals input to the isolated drive circuit 40, in other words, the oscillation frequency of the oscillator circuit 20, there is a limit to the value of the frequency because the circuit configuration becomes complicated. Therefore, it is necessary to increase the output voltage of the signal generation circuit 90 on the input side to increase the signal amplitude, and as shown in this embodiment, a charge pump circuit 80 is provided on the input side, and the output voltage of the charge pump circuit 80 is made higher than the voltage of the input signal VDD.

[0142] However, because semiconductor relay 200 is typically required to operate independently, it is not possible to externally attach a flying capacitor or a decoupling capacitor to suppress output voltage ripple, as is the case with general charge pump circuits. Furthermore, if elements equivalent to these capacitors are built into charge pump circuit 80, the problem of insufficient capacitance arises. Generally, when charge pump circuit 80 is configured on a semiconductor chip, the capacitance of the capacitor can only be secured at a few pF to several tens of pF due to area limitations.

[0143] Therefore, as shown in this embodiment, by synchronizing the charging and discharging timing of the internal capacitor with the driving timing of the output, a charge pump circuit 80 incorporating a capacitor with a low capacitance of about a few pF can be applied to the semiconductor relay 200. Furthermore, by providing an internal boost function, the voltage of the input signal VDD can be reduced, i.e., the operating voltage can be reduced. Furthermore, by incorporating the charge pump circuit 80 into the semiconductor relay 200, an increase in chip area can be prevented, which in turn allows the semiconductor relay 200 to be made smaller and achieve power savings.

[0144] <Modification 2> FIG. 16 is a circuit diagram of a charge pump circuit according to Modification 2. In FIG.

[0145] In the semiconductor relay 200 shown in the third embodiment, the charge pump circuit 80 may have the configuration shown in Fig. 16. The charge pump circuit 80 shown in Fig. 16 differs from the charge pump circuit 80 shown in Fig. 14 in that a fifth switch S5 connected in series to the first switch S1 and the second switch S2 is inserted between them. In addition, the charge pump circuit 80 shown in Fig. 16 has a sixth switch S6 connected in series to the third switch S3 and the fourth switch S4 inserted between them.

[0146] The eighth capacitor C8 is connected between the output terminal of the third inverter IN3 and the connection point between the first switch S1 and the fifth switch S5. The ninth capacitor C9 is connected between the output terminal of the first inverter IN1 and the connection point between the sixth switch S6 and the fourth switch S4. The tenth capacitor C10 is connected between the output terminal of the third inverter IN3 and the connection point between the fifth switch S5 and the second switch S2.

[0147] 16, when a clock signal is input from the oscillator circuit 20 to the input terminal of the first inverter IN1, an opposite-phase signal is output from the first inverter IN1, and this signal charges the sixth capacitor C6 and the ninth capacitor C9. Also, a signal in phase with the clock signal output from the oscillator circuit 20 is output from the third inverter IN3, and this signal charges the eighth capacitor C8 and the tenth capacitor C10.

[0148] This modification can achieve the same effects as the configuration shown in embodiment 2. That is, it is possible to prevent malfunction of the semiconductor relay 200 due to transient voltage fluctuations such as common-mode noise in the capacitively isolated semiconductor relay 200. Furthermore, it is possible to prevent malfunction of the semiconductor relay 200 whether the semiconductor relay 200 is in the on state or the off state.

[0149] Furthermore, this modification makes it possible to reduce the size and power consumption of the semiconductor relay 200. Furthermore, it is possible to realize a semiconductor relay 200 that can withstand use in high-temperature environments.

[0150] In the charge pump circuit 80, the number of parallel stages of switches may be three or more, and the number of series-connected switches may be four or more.

[0151] Other Embodiments New embodiments can be created by appropriately combining the components shown in Embodiments 1 to 3 and Modifications 1 and 2. For example, the isolation drive circuit 40 shown in Modification 1 may be applied to the semiconductor relay 200 of Embodiment 2 shown in Fig. 12 or the semiconductor relay 200 of Embodiment 3 shown in Figs.

[0152] The polarities of the FETs and diodes in the semiconductor relay 200 are not limited to the examples shown in the first to fourth embodiments and the first and second modifications. For example, the first MOSFET M1 and the second MOSFET M2 may each be an n-channel MOSFET. Also, the discharge element 51 may be an enhancement type MOSFET.

[0153] When the polarity of the MOSFET or diode is changed in this manner, the polarity of the output of the isolation drive circuit 40 when a first signal is input to the first input terminal 41 and a second signal is input to the second input terminal 42 is not limited to the examples shown in embodiments 1 to 4 and variants 1 and 2.

[0154] In view of this, it can be said that the control circuit 44 disclosed in the present specification controls the potential difference between the first output terminal 45 and the second output terminal 46 even when a transiently fluctuating signal such as common mode noise is applied to the first output terminal 45 as an AC signal.

[0155] When a first signal is input to the first input terminal 41 and a second signal is input to the second input terminal 42, the control circuit 44 controls the potential difference between the first output terminal 45 and the second output terminal 46 to have a first value. When the first signal is not input to the first input terminal 41 and the second signal is not input to the second input terminal 42, the control circuit 44 controls the potential difference between the first output terminal 45 and the second output terminal 46 to have a second value different from the first value.

[0156] The first value is a positive or negative output voltage, and if the discharge element 51 is a depletion type MOSFET, it is a value for turning it off, and if it is an enhancement type MOSFET, it is a value for turning it on.

[0157] The second value is an output voltage of 0 V, which is a value for turning on the discharge element 51 if it is a depletion type MOSFET, and a value for turning off the discharge element 51 if it is an enhancement type MOSFET.

[0158] The semiconductor relay 200 is generally a product in which the insulating drive circuit 40 and the MOSFET to be driven are integrated into a single package.

[0159] The switching circuit 60 and the first and second output terminals 71 and 72 of the semiconductor relay 200 may be eliminated, and the output of the drive circuit 100 may be disposed as an external terminal, resulting in a single packaged product. In other words, the drive circuit 100 is integrated into a single package. In this case, the first drive output terminal 52 and the second drive output terminal 53 become output terminals. In this case, the user can select and use any switching MOSFET.

[0160] In addition, in a typical semiconductor relay 200, the MOSFETs driven by the drive circuit 100 are connected in a common source configuration and have a bidirectional breakdown voltage between the output terminals, but the drive circuit 100 may be connected to only a single MOSFET. In this case, the MOSFET has only a unidirectional breakdown voltage between the output terminals.

[0161] In the switching circuit 60, an IGBT (Insulated Gate Bipolar Transistor), a SiC transistor, a GaN transistor, or the like can be easily used instead of the MOSFET that is the output element.

[0162] Those skilled in the art can easily understand the differences between the drive circuit 100 and the semiconductor relay 200 described above. In addition, those skilled in the art can easily imagine using the above-mentioned elements instead of MOSFETs as output elements.

[0163] When applied to a capacitively isolated semiconductor relay, the isolated drive circuit of the present disclosure is useful because it can prevent malfunctions when transient voltage fluctuations such as common-mode noise occur on the output side.

[0164] 11 First input terminal 12 Second input terminal 20 Oscillator circuit 30 Insulated boost circuit 30A, 30B Rectifier circuit 31 Boost rectifier circuit 40 Insulated drive circuit 41 First input terminal 42 Second input terminal 43 Insulation circuit 44 Control circuit 45 First output terminal 46 Second output terminal 50 Discharge circuit 50A Discharge circuit 51 Discharge element 52 First drive output terminal 53 Second drive output terminal 60 Switching circuit 61 First output element (first FET) 62 Second output element (second FET) 71 First output terminal 72 Second output terminal 80 Charge pump circuit 90 Signal generation circuit 100 Drive circuit 110 Conventional drive circuit 200 Semiconductor relay C1 to C10 First to tenth capacitors (first to tenth capacitances) D1 to D9 First to ninth diodes M1 to M4: 1st to 4th MOSFETs IN1 to IN6: 1st to 6th inverters R1 to R3: 1st to 3rd resistors S1 to S6: 1st to 6th switches

Claims

a first input terminal and a second input terminal to which an input signal is input; an oscillation circuit connected to the first input terminal and the second input terminal, which outputs a first signal and a second signal having an opposite phase to the first signal in response to the input signal; an insulating drive circuit connected to the oscillation circuit; Equipped with The isolated drive circuit comprises: a first input terminal to which the first signal is input; a second input terminal to which the second signal is input; an isolation circuit having a first capacitance connected to the first input terminal and a second capacitance connected to the second input terminal; a diode bridge that rectifies the signal input from the isolation circuit; a control circuit connected to the diode bridge; a first output terminal and a second output terminal respectively connected to the control circuit; and When the first signal is input to the first input terminal and the second signal is input to the second input terminal, the control circuit rectifies the first signal and the second signal to control a potential difference between the first output terminal and the second output terminal to a first value; When the first signal is not input to the first input terminal and the second signal is not input to the second input terminal, the control circuit does not rectify the first signal and the second signal, and controls the potential difference between the first output terminal and the second output terminal to be a second value different from the first value. Drive circuit. 　 The control circuit a first MOSFET having a first gate connected to the first capacitor via the diode bridge, a first source connected to the first output terminal, and a first drain; a second MOSFET having a second gate connected to the second capacitance via the diode bridge, a second drain connected to the second output terminal, and a second source; and the first drain of the first MOSFET is connected to the second source of the second MOSFET; a first voltage generated by inputting the first signal to the diode bridge is input to the first gate of the first MOSFET; a second voltage generated by inputting the second signal to the diode bridge is input to the second gate of the second MOSFET; The drive circuit of claim 1 . 　 The diode bridge comprises: a first diode having a first anode connected to the first capacitor; a second diode having a cathode connected to the second anode of the first diode; a third diode having a third anode connected to the second capacitor; a fourth diode having a fourth cathode connected to the third anode of the third diode; a cathode terminal which is a connection point between a first cathode of the first diode and a third cathode of the third diode; an anode terminal which is a connection point between the second anode of the second diode and the fourth anode of the fourth diode; and the cathode terminal is connected to the first output terminal; the anode terminal is connected to the second output terminal; the first MOSFET and the second MOSFET are P-channel MOSFETs, With respect to the potential of the first output terminal as a reference, while the first voltage is input to the first gate and the second voltage is input to the second gate, the potential of the second output terminal as viewed from the first output terminal is a negative potential.

3. The drive circuit according to claim 2. The diode bridge comprises: a first diode having a first anode connected to the first capacitor; a second diode having a cathode connected to the second anode of the first diode; a third diode having a third anode connected to the second capacitor; a fourth diode having a fourth cathode connected to the third anode of the third diode; a cathode terminal which is a connection point between a first cathode of the first diode and a third cathode of the third diode; an anode terminal which is a connection point between the second anode of the second diode and the fourth anode of the fourth diode; and The cathode terminal is connected to the second output terminal; the anode terminal is connected to the first output terminal; the first MOSFET and the second MOSFET are N-channel MOSFETs, With respect to the potential of the first output terminal as a reference, the potential of the second output terminal as viewed from the first output terminal is a negative potential.

3. The drive circuit according to claim 2. 　 The control circuit a third MOSFET connected in parallel to the first MOSFET and the second MOSFET, the third MOSFET having a third source connected to the cathode terminal, a third gate, and a third drain; a fourth MOSFET connected in parallel to the first MOSFET and the second MOSFET, the fourth MOSFET having a fourth drain connected to the anode terminal, a fourth gate, and a fourth source; and the third drain of the third MOSFET is connected to the fourth source of the fourth MOSFET; the second voltage is input to the third gate of the third MOSFET; the first voltage is input to the fourth gate of the fourth MOSFET; 5. The drive circuit according to claim 3 or 4. 　 the control circuit further includes a third capacitor connected in parallel to the first MOSFET and the second MOSFET; 3. The drive circuit according to claim 2. 　 the control circuit further includes a resistor connected in series with the first MOSFET and the second MOSFET, and connected to the first output terminal and the diode bridge; 3. The drive circuit according to claim 2. 　 a charge pump circuit connected to the first input terminal; a signal generating circuit; Furthermore, the charge pump circuit receives the input signal and outputs a third voltage; the signal generating circuit outputs a third signal and a fourth signal based on the oscillation signal input from the oscillation circuit and the third voltage input from the charge pump circuit. The drive circuit of claim 1 . 　 the isolated drive circuit and the oscillator circuit are formed on a single die; The drive circuit of claim 1 . 　 an isolated boost circuit; A discharge circuit; a first drive output terminal; a second driving output terminal; Furthermore, the discharge circuit has a discharge element connected to the first drive output terminal and the second drive output terminal and controlled by the isolation drive circuit; the discharge element is a depletion-type MOSFET, the isolated voltage boost circuit is connected to the discharge circuit and the second drive output terminal, and applies a predetermined voltage to the discharge element and the second drive output terminal in response to the input signal; the insulating drive circuit controls a potential difference between the first drive output terminal and the second drive output terminal based on the first signal and the second signal.

10. A driving circuit according to claim 1. 　 A drive circuit according to any one of claims 1 to 10; a switching circuit controlled by the control circuit; a first output terminal and a second output terminal; Equipped with The switching circuit a first FET including a fifth drain connected to the first output terminal; the switching circuit controls a conduction state between the first output terminal and the second output terminal in response to an output voltage of the control circuit. Solid state relay. 　 the switching circuit further includes a second FET including a sixth drain connected to the second output terminal; The first FET is connected to the second FET via a common source. The solid state relay according to claim 11.

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