Semiconductor device including heterogeneous structure and manufacturing method thereof

Abstract

A semiconductor device according to an embodiment of the present invention may comprise: a semiconductor substrate which is intrinsic or doped with a first dopant of a first type; an epitaxial semiconductor layer which is formed on the semiconductor substrate, is doped with a second dopant of a second type different from the first type, and contains a semiconductor element different from that of the semiconductor substrate; and a diffusion region which is formed in the semiconductor substrate so as to be in contact with the epitaxial semiconductor layer and contains the second dopant.

Description

Semiconductor device including heterogeneous structure and method for manufacturing the same

[0001] The present application relates to semiconductor technology, and more particularly, to a semiconductor device including a heterostructure formed by bonding between different semiconductor materials, and a method for manufacturing the same.

[0002] Heterostructures formed by joining different semiconductor materials can be utilized in various semiconductor devices, such as optical elements such as optical sensors. For example, a heterostructure in which a semiconductor layer such as germanium (Ge) is arranged on a semiconductor substrate such as silicon (Si) can be utilized. Germanium is a widely used material in the manufacture of optical elements because it is sensitive to short-wave infrared (SWIR) light.

[0003] Here, a pn junction may be formed within a semiconductor substrate or semiconductor layer for various reasons. For example, it may be necessary to form a pn junction within a silicon substrate or germanium layer to enable photonic reactions in optical devices.

[0004] The problem that the embodiments of the present disclosure seek to solve is to provide a semiconductor device and a manufacturing method that can overcome process constraints and secure characteristics.

[0005] According to one embodiment of the present disclosure for solving the above problem, a semiconductor device may include a semiconductor substrate doped with a first dopant of a first type or an intrinsic semiconductor substrate; an epitaxial semiconductor layer formed on the semiconductor substrate, the epitaxial semiconductor layer doped with a second dopant of a second type different from the first type and including a semiconductor element different from the semiconductor substrate; and a diffusion region formed within the semiconductor substrate so as to be in contact with the epitaxial semiconductor layer and containing the second dopant.

[0006] In addition, a semiconductor device according to one embodiment of the present disclosure for solving the above problem includes a semiconductor substrate doped with a first dopant of a first type; and an epitaxial semiconductor layer formed on the semiconductor substrate and including a semiconductor element different from that of the semiconductor substrate, wherein the epitaxial semiconductor layer may include an upper portion doped with a second dopant of a second type different from the first type, and a lower portion containing the first dopant.

[0007] In addition, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure for solving the above problem includes the steps of providing a semiconductor substrate doped with a first dopant of a first type or being intrinsic; and the step of doping a second dopant of a second type different from the first type while epitaxially growing a semiconductor layer on the semiconductor substrate, the semiconductor layer including a semiconductor element different from the semiconductor substrate, wherein the second dopant can diffuse from the semiconductor layer into the semiconductor substrate to form a diffusion region within the semiconductor substrate.

[0008] In addition, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure for solving the above problem includes the steps of providing a semiconductor substrate doped with a first dopant of a first type; and doping a second dopant of a second type different from the first type while epitaxially growing a semiconductor layer on the semiconductor substrate, the semiconductor layer including a semiconductor element different from the semiconductor substrate, wherein the first dopant can diffuse from the semiconductor substrate into the semiconductor layer to form a diffusion region under the semiconductor layer.

[0009] According to the embodiments of the present disclosure described above, a semiconductor device and a manufacturing method thereof capable of overcoming process constraints and securing characteristics can be provided.

[0010] FIG. 1A and FIG. 1B are drawings for explaining a semiconductor structure and a method for manufacturing the same according to one embodiment of the present disclosure.

[0011] Figure 1c is a drawing for explaining an example of a subsequent process performed after the process of Figure 1b.

[0012] FIG. 2A and FIG. 2B are drawings for explaining a semiconductor structure and a method for manufacturing the same according to another embodiment of the present disclosure.

[0013] FIG. 3A and FIG. 3B are drawings for explaining a semiconductor structure and a method for manufacturing the same according to another embodiment of the present disclosure.

[0014] FIG. 4 is a drawing for explaining a semiconductor device according to one embodiment of the present disclosure.

[0015] FIG. 5 is a drawing for explaining a semiconductor device according to another embodiment of the present disclosure.

[0016] FIG. 6 is a drawing for explaining a semiconductor device according to another embodiment of the present disclosure.

[0017] Reference will now be made to specific embodiments, examples of which are illustrated in the accompanying drawings. While the underlying principles are explained in conjunction with the embodiments, it will be understood that the claims are not intended to be limited to these specific embodiments. On the contrary, the claims are intended to cover alternatives, modifications, and equivalents within the scope of the claims.

[0018] Furthermore, in the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, methods, procedures, components, and networks well known to those skilled in the art have not been described in detail to avoid obscuring aspects of the underlying principles.

[0019] Although the terms "first," "second," etc. may be used herein to describe various elements, it will also be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the claims, a first semiconductor region may be referred to as a second semiconductor region, and similarly, a second semiconductor region may be referred to as a first semiconductor region. While the first semiconductor region and the second semiconductor region are both semiconductor regions, they are not the same semiconductor regions.

[0020] The terminology used in the description of the embodiments herein is for the purpose of describing only particular embodiments and is not intended to limit the scope of the claims. As used in the detailed description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and / or," as used herein, refers to and includes any and all possible combinations of one or more of the associated listed items. It will further be understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] The semiconductor devices and / or semiconductor structures of the present embodiments may include a stacked structure of a semiconductor substrate and a semiconductor layer. The semiconductor substrate may include at least one of various semiconductor materials. For example, the semiconductor substrate may include a silicon substrate. The semiconductor layer may include at least one of various semiconductor materials different from the semiconductor substrate. For example, the semiconductor layer may include a germanium layer. As a result, the semiconductor substrate and the semiconductor layer may form a heterostructure.

[0022] If necessary, a pn junction can be formed within a semiconductor substrate or semiconductor layer. To form a pn junction within a semiconductor substrate, an ion implantation process can be used. Alternatively, to form a pn junction within a semiconductor layer, a method of switching a doping gas during the growth of a semiconductor layer using an epitaxial growth method can be used. In particular, the semiconductor layer can be grown in an island shape using a selective epitaxial growth (SEG) method. According to the selective epitaxial growth process, a semiconductor layer can be formed only on a necessary portion of the semiconductor substrate while masking unnecessary portions of the semiconductor substrate with an insulating layer or the like.

[0023] However, each method may have drawbacks. Ion implantation into a semiconductor substrate can damage the crystal structure of the semiconductor substrate, requiring a high-temperature damage repair process, such as recrystallization via high-temperature solid-phase epitaxy. However, due to limitations in thermal budget, these processes are difficult to apply to all semiconductor devices. For example, silicon CMOS (Complementary Metal-Oxide Semiconductor), which is formed in the peripheral circuit area of ​​a semiconductor substrate to drive optical elements, is damaged during this high-temperature process, making it difficult to perform a high-temperature damage repair process on semiconductor devices containing silicon CMOS.

[0024] This thermal budget issue may not be significant in methods that switch dopants while epitaxially growing semiconductor layers. However, when performing a selective epitaxial growth process in which a semiconductor layer is grown while a portion of the semiconductor substrate is masked with an insulating layer, the growth of the semiconductor layer in areas relatively close to the sidewalls of the insulating layer is slower than in areas relatively far from the sidewalls of the insulating layer, resulting in the formation of a semiconductor layer with a pyramidal shape. Consequently, the surface of the pn junction may also have a sloped shape similar to a pyramidal surface. If the surface of the pn junction is not flat, problems may arise that degrade the characteristics of the semiconductor device.

[0025] In the following examples, a semiconductor device and a method for manufacturing the same are described, which can overcome all of the above-described disadvantages by forming a pn junction by diffusing a dopant during the growth of a semiconductor layer using epitaxial growth.

[0026] FIG. 1A and FIG. 1B are drawings for explaining a semiconductor structure and a method for manufacturing the same according to one embodiment of the present disclosure.

[0027] First, the manufacturing method is explained.

[0028] Referring to FIG. 1a, a semiconductor substrate (100) doped with a first dopant of a first type can be provided.

[0029] As an example, the semiconductor substrate (100) may include a silicon substrate. As an example, the first dopant may be a p-type dopant, such as boron. Here, the doping concentration of the first dopant of the semiconductor substrate (100) may be relatively low. This may mean that the doping concentration of the first dopant in the semiconductor substrate (100) is lower than the doping concentration of the dopant in the semiconductor layer (see 120 of FIG. 1B) described below. For example, the semiconductor substrate (100) may be expressed as having p- doping or p-doping. For reference, in describing the doping concentration of the dopant below, p+ and n+ may mean high concentration, p- and n- may mean low concentration, and p and n may mean lower concentration than p+ and n+ and higher concentration than p- and n-.

[0030] Next, an insulating layer (110) can be formed on the semiconductor substrate (100) to cover a portion of the semiconductor substrate (100) and expose the remainder.

[0031] The portion exposed by the insulating layer (110) may correspond to a region of the semiconductor substrate (100) where a device is formed, i.e., an active region, and the region covered by the insulating layer (110) may correspond to a device isolation region for isolating the active region from other active regions. The insulating layer (110) may include at least one of various insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be formed by deposition and selective etching of the insulating material. The insulating layer (110) is intended to provide a space in which a semiconductor layer to be described later is formed, and may have a thickness of several tens of nm to several thousand nm. The insulating layer (110) formation process may be omitted as it is for selective epitaxial growth.

[0032] Next, a semiconductor element-containing gas (see arrow ①) may be supplied toward the upper surface (105) of the semiconductor substrate (100) exposed by the insulating layer (110) to epitaxially grow a semiconductor layer. In addition, while the semiconductor layer is growing, a second type of dopant gas (see arrow ②) may be supplied to dope the semiconductor layer with a second type of dopant (hereinafter, the second dopant).

[0033] Here, the semiconductor element may include an element different from the semiconductor substrate (100). As an example, the semiconductor element may include germanium. In addition, the second type may be different from the first type. As an example, the second dopant may be an n-type dopant, such as phosphorus or arsenic. In addition, the second dopant may be doped at a high concentration. For example, the second dopant may be expressed as an n+ dopant. As a result of this process, as illustrated in FIG. 1B, a semiconductor layer (120) doped with a second dopant of the second type may be formed.

[0034] Referring to FIG. 1b, a semiconductor layer (120) may be formed on a semiconductor substrate (100) exposed by an insulating layer (110). Since the semiconductor layer (120) is formed by an epitaxial growth process, the semiconductor layer (120) may also be referred to as an epitaxial semiconductor layer.

[0035] The semiconductor layer (120) may have an island shape in which the sidewalls are surrounded by the insulating layer (110). Here, since the semiconductor layer (120) selectively grows only on the semiconductor substrate (100) and does not grow on the insulating layer (110), the growth in an area relatively close to the sidewall of the insulating layer (110) may be slower than the growth in an area relatively far from the sidewall of the insulating layer (110). Consequently, an edge of the semiconductor layer (120) that is relatively close to the insulating layer (110) may have a sloped upper surface, and a center of the semiconductor layer (120) that is relatively far from the insulating layer (110) may have a flat upper surface. That is, the upper surface of the center of the semiconductor layer (120) may be substantially parallel to the upper surface (105) of the semiconductor substrate (100).

[0036] As an example, the semiconductor layer (120) may include a germanium layer doped with a second dopant of a second type. Here, the doping concentration of the second dopant in the semiconductor layer (120) may be relatively large. That is, the doping concentration of the second dopant in the semiconductor layer (120) may be greater than the doping concentration of the first dopant in the semiconductor substrate (100). For example, the semiconductor layer (120) may be expressed as having n+ doping or n doping. When the semiconductor substrate (100) has p- doping, the semiconductor layer (120) may be said to have n+ doping or n doping. Alternatively, when the semiconductor substrate (100) has p doping, the semiconductor layer (120) may be said to have n+ doping.

[0037] Meanwhile, since the semiconductor substrate (100) contains a relatively low concentration of the first dopant, while the semiconductor layer (120) contains a relatively high concentration of the second dopant, the second dopant may diffuse from the semiconductor layer (120) to the semiconductor substrate (100), thereby forming a diffusion region (130) within the semiconductor substrate (100).

[0038] The diffusion region (130) may be formed at a predetermined depth from the upper surface (105) of the semiconductor substrate (100). For example, the diffusion region (130) may be formed at a depth of several nm to several tens of nm to form a shallow junction. Accordingly, the maximum thickness (T1) of the diffusion region (130) may be smaller than the maximum thickness (T2) of the semiconductor layer (120). For reference, the maximum thickness of a certain layer may mean the maximum value among several thickness values ​​of the layer.

[0039] The diffusion region (130) can be in direct contact with the semiconductor layer (120) below the semiconductor layer (120). In addition, since the diffusion of the second dopant progresses in the vertical and lateral directions while proceeding downward from the upper surface (105) of the semiconductor substrate (100), the edge of the diffusion region (130) can overlap a portion of the insulating layer (110) below the insulating layer (110).

[0040] Since the diffusion region (130) is formed within the semiconductor substrate (100), it may include the same material as the semiconductor substrate (100), for example, silicon. In addition, since the diffusion region (130) is formed by diffusion of a second dopant, it may include a second dopant, for example, an n-type dopant. The concentration of the second dopant in the diffusion region (130) may be substantially the same as or lower than the concentration of the second dopant in the semiconductor layer (120). For example, when the semiconductor layer (120) has n+ doping, the diffusion region (130) may be said to have n+ doping or n doping. Alternatively, the semiconductor layer (120) and the diffusion region (130) may be said to have n doping.

[0041] By the manufacturing method described above, the semiconductor structure of the present embodiment can be manufactured.

[0042] Referring back to FIG. 1B, the semiconductor structure of the present embodiment may include a semiconductor substrate (100) doped with a first dopant of a first type, an epitaxial semiconductor layer (120) formed on the semiconductor substrate (100) and doped with a second dopant of a second type while including a semiconductor element different from the semiconductor substrate (100), and a diffusion region (130) formed within the semiconductor substrate (100) below the epitaxial semiconductor layer (120) and containing the second dopant.

[0043] The semiconductor substrate (100) may include silicon, and the epitaxial semiconductor layer (120) may include germanium. The first type may be p-type and the second type may be n-type, or conversely, the first type may be n-type and the second type may be p-type. The concentration of the first dopant in the semiconductor substrate (100) may be lower than the concentration of the second dopant in the epitaxial semiconductor layer (120). The concentration of the second dopant in the diffusion region (130) may be lower than or equal to the concentration of the second dopant in the epitaxial semiconductor layer (120).

[0044] In addition, specific components of the semiconductor structure have been described in detail in the process of explaining the manufacturing method, so a more detailed description will be omitted here.

[0045] According to the semiconductor structure and its manufacturing method of the present embodiment, a pn junction can be formed within the semiconductor substrate (100) due to diffusion of the second dopant from the epitaxial semiconductor layer (120). That is, an ion implantation process for forming a pn junction is not performed on the semiconductor substrate (100). Therefore, there is an advantage in that a high-temperature process for repairing damage caused by ion implantation is unnecessary.

[0046] Meanwhile, when manufacturing optical elements or the like using the semiconductor structure of the above example, it may be necessary to process the semiconductor structure of Fig. 1b to have a flat upper surface. To this end, the process of Fig. 1c may be additionally performed after the process of Fig. 1b.

[0047] Figure 1c is a drawing for explaining an example of a subsequent process performed after the process of Figure 1b.

[0048] Referring to Fig. 1c, a planarization process, for example, CMP (Chemical Mechanical Polishing), can be performed on the process result of Fig. 1b.

[0049] This planarization process can be performed until the inclined surface of the upper surface of the semiconductor layer (120) is removed. Accordingly, the insulating layer (110) and the semiconductor layer (120) can be deformed to have planarized upper surfaces. The planarized insulating layer (110) and the planarized semiconductor layer (120) will be referred to as an insulating layer pattern (110') and a semiconductor layer pattern (120'), respectively. The upper surface of the insulating layer pattern (110') and the upper surface of the semiconductor layer pattern (120') can be substantially parallel to the upper surface (105) of the semiconductor substrate (100) and positioned at substantially the same height from the upper surface of the semiconductor substrate (100). The thickness of the insulating layer pattern (110') and the thickness of the semiconductor layer pattern (120') can be reduced compared to the thickness of the insulating layer (110) and the thickness of the semiconductor layer (120), respectively. Even in this case, the maximum thickness (T2') of the semiconductor layer pattern (120') may be greater than the maximum thickness (T1) of the diffusion region (130).

[0050] According to this embodiment, subsequent processes such as depositing a necessary layer on the insulating layer pattern (110') and the semiconductor layer pattern (120') or etching the deposited layer can be facilitated. For example, when manufacturing the device of FIG. 4 or FIG. 5 described below, it can be facilitated to form a gate insulating layer and a gate.

[0051] FIG. 2A and FIG. 2B are drawings for explaining a semiconductor structure and a method for manufacturing the same according to another embodiment of the present disclosure.

[0052] Referring to FIG. 2a, a semiconductor substrate (200) doped with a first dopant of a first type can be provided.

[0053] As an example, the semiconductor substrate (200) may include a silicon substrate. As an example, the first dopant may be a p-type dopant, such as boron. Here, the doping concentration of the first dopant in the semiconductor substrate (200) may be relatively high. That is, the doping concentration of the first dopant in the semiconductor substrate (200) may be greater than the doping concentration of the dopant in the upper portion of the semiconductor layer described later (see 224 in FIG. 2B). For example, the semiconductor substrate (200) may be described as having p+ doping or p doping.

[0054] Next, an insulating layer (210) can be formed on the semiconductor substrate (200) to cover a portion of the semiconductor substrate (200) and expose the remainder.

[0055] Next, a semiconductor element-containing gas (see arrow ③) may be supplied toward the upper surface (205) of the semiconductor substrate (200) exposed by the insulating layer (210) to epitaxially grow a semiconductor layer. In addition, while the semiconductor layer is growing, a second type of dopant gas (see arrow ④) may be supplied to dope the second type of second dopant into the semiconductor layer.

[0056] Here, the semiconductor element may include an element different from the semiconductor substrate (200). As an example, the semiconductor element may include germanium. In addition, the second type may be different from the first type. As an example, the second dopant may be an n-type dopant, such as phosphorus or arsenic. In addition, the second dopant may be doped at a low concentration. For example, the second dopant may be expressed as an n-dopant. As a result of this process, a semiconductor layer (220) as illustrated in FIG. 2B may be formed.

[0057] Referring to FIG. 2B, a semiconductor layer (220) may be formed on a semiconductor substrate (200) exposed by an insulating layer (210). The semiconductor layer (220) may also be referred to as an epitaxial semiconductor layer. The semiconductor layer (220) may have an island shape in which side walls are surrounded by the insulating layer (210). An edge of the semiconductor layer (220) that is relatively close to the insulating layer (210) may have a sloped upper surface, and a center of the semiconductor layer (220) that is relatively far from the insulating layer (210) may have a flat upper surface.

[0058] The semiconductor layer (220) may include, for example, a germanium layer. In addition, the semiconductor layer (220) may include a stacked structure of a lower portion (222) and an upper portion (224). The upper portion (224) of the semiconductor layer (220) may be doped with a second dopant of a second type. Here, the doping concentration of the second dopant in the upper portion (224) of the semiconductor layer (220) may be relatively small. That is, the doping concentration of the second dopant in the upper portion (224) of the semiconductor layer (220) may be smaller than the doping concentration of the first dopant in the semiconductor substrate (200). For example, the upper portion (224) of the semiconductor layer (220) may be expressed as having n-doping or n-doping. When the semiconductor substrate (200) has p+ doping, the upper portion (224) of the semiconductor layer (220) may be said to have n-doping or n-doping. Alternatively, when the semiconductor substrate (200) has p-doping, the upper portion (224) of the semiconductor layer (220) can be said to have n-doping.

[0059] Meanwhile, since the semiconductor substrate (200) contains a relatively high concentration of the first dopant, while the semiconductor material epitaxially grown to form the semiconductor layer (220) contains a relatively low concentration of the second dopant, the first dopant can diffuse from the semiconductor substrate (200) into the semiconductor material. As a result, a diffusion region containing the first dopant diffused from the semiconductor substrate (200) can be formed in the lower portion (222) of the semiconductor layer (220).

[0060] The lower portion (222) of the semiconductor layer (220) may be formed at a predetermined height from the upper surface of the semiconductor substrate (200). Since the lower portion (222) of the semiconductor layer (220) is formed by diffusion, the maximum thickness (T3) of the lower portion (222) of the semiconductor layer (220) may be smaller than the maximum thickness (T4) of the upper portion (224) of the semiconductor layer (220). The lower portion (222) of the semiconductor layer (220) may be in direct contact with the semiconductor substrate (200). The upper surface of the lower portion (222) of the semiconductor layer (220) may form a flat surface. That is, the upper surface of the lower portion (222) of the semiconductor layer (220) may be substantially parallel to the upper surface (205) of the semiconductor substrate (200). This is because diffusion of the first dopant from the semiconductor substrate (200) toward the semiconductor layer (220) occurs uniformly in the vertical direction, that is, at a substantially constant speed.

[0061] The concentration of the first dopant in the lower portion (222) of the semiconductor layer (220) may be substantially the same as or lower than the concentration of the first dopant in the semiconductor substrate (200). For example, when the semiconductor substrate (200) has p+ doping, the lower portion (222) of the semiconductor layer (220) may be said to have p+ doping or p doping. Alternatively, the semiconductor substrate (200) and the lower portion (222) of the semiconductor layer (220) may be said to have p doping.

[0062] By the manufacturing method described above, the semiconductor structure of the present embodiment can be manufactured.

[0063] Referring again to FIG. 2B, the semiconductor structure of the present embodiment may include a semiconductor substrate (200) doped with a first dopant of a first type, and an epitaxial semiconductor layer (220) formed on the semiconductor substrate (200) and including a semiconductor element different from the semiconductor substrate (200). The epitaxial semiconductor layer (220) may include an upper portion (224) doped with a second dopant of a second type and a lower portion (222) containing a first dopant diffused from the semiconductor substrate (200).

[0064] The semiconductor substrate (200) may include silicon, and the epitaxial semiconductor layer (220) may include germanium. The first type may be p-type and the second type may be n-type, or vice versa. The concentration of the first dopant in the semiconductor substrate (200) may be greater than the concentration of the second dopant in the upper portion (224) of the epitaxial semiconductor layer (220). The concentration of the first dopant in the lower portion (222) of the epitaxial semiconductor layer (220) may be less than or equal to the concentration of the first dopant in the semiconductor substrate (200).

[0065] In addition, specific components of the semiconductor structure have been described in detail in the process of explaining the manufacturing method, so a more detailed description will be omitted here.

[0066] According to the semiconductor structure and the manufacturing method thereof of the present embodiment, a pn junction can be formed in the epitaxial semiconductor layer (220) due to diffusion of the first dopant from the semiconductor substrate (200) into the epitaxial semiconductor layer (220). In this case, even if the upper surface of the epitaxial semiconductor layer (220) does not form a flat surface by the selective epitaxial growth process, there is an advantage in that the pn junction surface, i.e., the interface between the lower portion (222) and the upper portion (224) of the epitaxial semiconductor layer (220), can form a flat surface that is substantially parallel to the upper surface (205) of the semiconductor substrate (200).

[0067] Although not illustrated, the process of FIG. 1c described above may be additionally performed to process the semiconductor structure of FIG. 2b to have a flat upper surface.

[0068] Meanwhile, the above embodiments have described cases where a semiconductor substrate doped with a first type of dopant and a semiconductor layer doped with a second type of dopant are in direct contact. However, if necessary, an intrinsic semiconductor material may be interposed between them. Even in such cases, a dopant can be doped while growing an epitaxial semiconductor layer on the intrinsic semiconductor material, thereby forming a dopant diffusion region within the intrinsic semiconductor material. This will be exemplarily described with reference to FIGS. 3A and 3B.

[0069] FIG. 3A and FIG. 3B are drawings for explaining a semiconductor structure and a method for manufacturing the same according to another embodiment of the present disclosure.

[0070] Referring to FIG. 3a, a semiconductor substrate (300) may be provided that includes a lower semiconductor substrate (302) doped with a first type of first dopant and an upper semiconductor substrate (304) that is not doped with a dopant, i.e., is intrinsic.

[0071] As an example, the semiconductor substrate (300) may include a silicon substrate. As an example, the first dopant may be a p-type dopant, such as boron. Since the lower semiconductor substrate (302) does not directly contact the semiconductor layer (see 320 of FIG. 3B) described below, the doping concentration of the first dopant of the lower semiconductor substrate (302) may be variously modified, regardless of the doping concentration of the semiconductor layer. For example, the lower semiconductor substrate (302) may be said to have p- doping, p doping, or p+ doping.

[0072] Next, an insulating layer (310) can be formed on the semiconductor substrate (300) to cover a portion of the semiconductor substrate (300) and expose the remainder.

[0073] Next, a semiconductor element-containing gas (see arrow ⑤) may be supplied toward the upper surface (305) of the semiconductor substrate (300) exposed by the insulating layer (310), i.e., the upper surface (305) of the upper semiconductor substrate (304), to epitaxially grow a semiconductor layer. In addition, while the semiconductor layer is growing, a second type of dopant gas (see arrow ⑥) may be supplied to dope the second type of second dopant into the semiconductor layer.

[0074] Here, the semiconductor element may include an element different from the semiconductor substrate (300). As an example, the semiconductor element may include germanium. In addition, the second type may be different from the first type. As an example, the second dopant may be an n-type dopant, such as phosphorus, arsenic, or the like. Since the second dopant will diffuse into the intrinsic upper semiconductor substrate (304), the doping concentration of the second dopant may be varied. For example, the second dopant may be denoted as an n+ dopant, an n- dopant, or an n- dopant. In particular, for ease of diffusion, the second dopant may be a high-concentration dopant denoted as an n+ dopant. As a result of this process, as illustrated in FIG. 3B, a semiconductor layer (320) doped with a second type of second dopant may be formed on the semiconductor substrate (300).

[0075] Referring to FIG. 3B, a semiconductor layer (320) may be formed on an upper semiconductor substrate (304) exposed by an insulating layer (310). The semiconductor layer (320) may also be referred to as an epitaxial semiconductor layer. The semiconductor layer (320) may have an island shape in which side walls are surrounded by the insulating layer (310). An edge of the semiconductor layer (320) that is relatively close to the insulating layer (310) may have a sloped upper surface, and a center of the semiconductor layer (320) that is relatively far from the insulating layer (310) may have a flat upper surface.

[0076] As an example, the semiconductor layer (320) may include a germanium layer doped with a second dopant of a second type. The semiconductor layer (320) may be described as having n+ doping, n doping, or n- doping.

[0077] Meanwhile, since the semiconductor layer (320) contains a second dopant, and the upper semiconductor substrate (304) in direct contact with the semiconductor layer (320) below the semiconductor layer (320) contains an intrinsic semiconductor material, such as intrinsic silicon, the second dopant may diffuse from the semiconductor layer (320) to the upper semiconductor substrate (304), thereby forming a diffusion region (330) within the upper semiconductor substrate (304).

[0078] The diffusion region (330) may be formed at a predetermined depth from the upper surface (305) of the semiconductor substrate (300). The maximum thickness of the diffusion region (330) may be smaller than the maximum thickness of the semiconductor layer (320). The edge of the diffusion region (330) may overlap a portion of the insulating layer (310) under the insulating layer (310).

[0079] Since the diffusion region (330) is formed within the upper semiconductor substrate (304), it may include the same material as the upper semiconductor substrate (304), for example, silicon. In addition, since the diffusion region (330) is formed by diffusion of a second dopant, it may include a second dopant, for example, an n-type dopant. The concentration of the second dopant in the diffusion region (330) may be substantially the same as or lower than the concentration of the second dopant in the semiconductor layer (320). For example, the diffusion region (330) may be described as having n+ doping, n doping, or n- doping.

[0080] By the manufacturing method described above, the semiconductor structure of the present embodiment can be manufactured.

[0081] Referring again to FIG. 3B, the semiconductor structure of the present embodiment may include a semiconductor substrate (300) including a lower semiconductor substrate (302) doped with a first dopant of a first type and an intrinsic upper semiconductor substrate (304), an epitaxial semiconductor layer (320) formed on the semiconductor substrate (300) and doped with a second dopant of a second type while including a semiconductor element different from the semiconductor substrate (300), and a diffusion region (330) formed in the upper semiconductor substrate (304) below the epitaxial semiconductor layer (320) and containing the second dopant.

[0082] The semiconductor substrate (300) may include silicon, and the epitaxial semiconductor layer (320) may include germanium. The first type may be p-type and the second type may be n-type, or vice versa. The concentration of the second dopant in the diffusion region (330) may be lower than or equal to the concentration of the second dopant in the epitaxial semiconductor layer (320).

[0083] In addition, specific components of the semiconductor structure have been described in detail in the process of explaining the manufacturing method, so a more detailed description will be omitted here.

[0084] According to the semiconductor structure and its manufacturing method of the present embodiment, a pn junction can be formed within the semiconductor substrate (300) with an intrinsic semiconductor material therebetween due to diffusion of the second dopant from the epitaxial semiconductor layer (320). In the present embodiment as well, since an ion implantation process for the semiconductor substrate (300) is not involved, there is an advantage in that a high-temperature process for repairing damage caused by ion implantation is unnecessary.

[0085] Various semiconductor devices can be manufactured using the semiconductor structures of the aforementioned embodiments. In particular, any of the semiconductor structures of the aforementioned embodiments can be used in various optical devices that utilize germanium as a light-absorbing layer. This will be exemplified below with reference to FIGS. 4 through 6.

[0086] FIG. 4 is a drawing for explaining a semiconductor device according to one embodiment of the present disclosure.

[0087] The semiconductor device of the present embodiment may be a light sensor. In particular, the semiconductor device of the present embodiment may be a gate-controlled charge modulated device (GCMD). The semiconductor device of the present embodiment may be formed using a structure substantially identical to the semiconductor structure of FIG. 1b or FIG. 1c.

[0088] Referring to FIG. 4, the semiconductor device of the present embodiment may include a semiconductor substrate (400) doped with a first dopant of a first type, an epitaxial semiconductor layer (420) formed on the semiconductor substrate (400) and doped with a second dopant of a second type while including a semiconductor element different from that of the semiconductor substrate (400), a diffusion region (430) formed in the semiconductor substrate (400) below the epitaxial semiconductor layer (420) and containing the second dopant, an impurity region (440) formed in the epitaxial semiconductor layer (420) at a predetermined depth from an upper surface of the epitaxial semiconductor layer (420) and doped with a first dopant of the first type, and a gate (460) formed on the epitaxial semiconductor layer (420) with a gate insulating layer (450) interposed therebetween. The epitaxial semiconductor layer (420) may have a sidewall surrounded by the insulating layer (410).

[0089] The semiconductor substrate (400), the insulating layer (410), the epitaxial semiconductor layer (420), and the diffusion region (430) may substantially correspond to the semiconductor substrate (100), the insulating layer (110), the epitaxial semiconductor layer (120), and the diffusion region (130) of FIG. 1B.

[0090] The gate insulating layer (450) and the gate (460) may be formed to overlap a portion of the impurity region (440), particularly the channel region (444) described later. The gate insulating layer (450) and the gate (460) may be formed by sequentially depositing an insulating material for forming the gate insulating layer (450) and a conductive material for forming the gate (460) on the epitaxial semiconductor layer (420) and the insulating layer (410) on which the impurity region (440) is formed, and then selectively etching the insulating material and the conductive material. The gate insulating layer (450) may have a single-layer structure or a multi-layer structure including at least one of various insulating materials. For example, the gate insulating layer (440) may include at least one of oxides such as SiO2, GeOx, ZrOx, HfOx, SixNy, SixOyNz, TaxOy, SrxOy, AlxOy, etc., oxynitrides such as SiON, and high-k materials such as HfO2, HfSiO, Al2O3. The gate (460) may have a single-film structure or a multi-film structure including at least one of various conductive materials. For example, the gate (460) may include at least one of polysilicon, amorphous silicon, silicon carbide, and a metal.

[0091] The impurity region (440) may include a source region (442) and a drain region (446) respectively disposed within the epitaxial semiconductor layer (420) on both sides of the gate (460), and a channel region (444) disposed between the source region (442) and the drain region (446). The impurity region (440) may be formed by doping a first dopant into the epitaxial semiconductor layer (420). Accordingly, the impurity region (440) may include a semiconductor material identical to that of the epitaxial semiconductor layer (420), for example, germanium, but may include a dopant of a different type from that of the epitaxial semiconductor layer (420). When the epitaxial semiconductor layer (420) is of the n type, the impurity region (440) may be of the p type, and accordingly, a PMOS semiconductor device may be implemented. Conversely, if the epitaxial semiconductor layer (420) is of p type, the impurity region (440) may be of n type, and accordingly, an NMOS semiconductor device may be implemented.

[0092] When the semiconductor device of the present embodiment is exposed to light, carriers can be generated within the epitaxial semiconductor layer (420), and these carriers can move to the pn junction formed within the semiconductor substrate (400) and be detected.

[0093] According to the present embodiment, the thermal budget problem can be solved because an ion implantation process is not involved in forming a pn junction within the semiconductor substrate (400). In particular, the thermal budget problem can be solved even when the semiconductor device of the present embodiment further includes a silicon CMOS for driving the GCMD.

[0094] In addition, even if a defect exists in the sidewall of the epitaxial semiconductor layer (520), since no defect exists in the pn junction within the semiconductor substrate (400) (see S1), leakage current can be reduced or prevented. Accordingly, the efficiency of optical sensing can be increased.

[0095] FIG. 5 is a drawing for explaining a semiconductor device according to another embodiment of the present disclosure.

[0096] The semiconductor device of the present embodiment may be a light sensor. In particular, the semiconductor device of the present embodiment may be a gate-controlled charge modulation device. The semiconductor device of the present embodiment may be formed using a structure substantially identical to the semiconductor structure of FIG. 2B or a structure obtained by planarizing the semiconductor structure of FIG. 2B.

[0097] Referring to FIG. 5, the semiconductor device of the present embodiment may include a semiconductor substrate (500) doped with a first dopant of a first type, an epitaxial semiconductor layer (520) formed on the semiconductor substrate (500) and including a semiconductor element different from that of the semiconductor substrate (500), wherein the epitaxial semiconductor layer (520) includes an upper portion (524) doped with a second dopant of a second type and a lower portion (522) containing a first dopant diffused from the semiconductor substrate (500), an impurity region (540) formed within the upper portion (524) of the epitaxial semiconductor layer (520) to a predetermined depth from an upper surface of the epitaxial semiconductor layer (520) and doped with a first dopant of the first type, and a gate (560) formed on the epitaxial semiconductor layer (520) with a gate insulating layer (550) interposed therebetween. The epitaxial semiconductor layer (520) may have its side walls surrounded by an insulating layer (510).

[0098] The semiconductor substrate (500), the insulating layer (510), and the epitaxial semiconductor layer (520) may substantially correspond to the semiconductor substrate (200), the insulating layer (210), and the epitaxial semiconductor layer (220) of FIG. 2B, respectively.

[0099] The gate insulating layer (550) and the gate (560) may be formed to overlap a portion of the impurity region (540), particularly the channel region (544) described below.

[0100] The impurity region (540) may include a source region (542) and a drain region (546) respectively disposed within the upper portion (524) of the epitaxial semiconductor layer (520) on both sides of the gate (560), and a channel region (544) disposed between the source region (542) and the drain region (546). The impurity region (540) may be formed by doping a first dopant into the upper portion (524) of the epitaxial semiconductor layer (520). Accordingly, the impurity region (540) may include a different type of dopant from the upper portion (524) of the epitaxial semiconductor layer (520) while including the same semiconductor material as the epitaxial semiconductor layer (520), for example, germanium. When the upper portion (524) of the epitaxial semiconductor layer (520) is of n type, the impurity region (540) may be of p type, and accordingly, a PMOS semiconductor device may be implemented. Conversely, when the upper portion (524) of the epitaxial semiconductor layer (520) is of n type, the impurity region (540) may be of n type, and accordingly, an NMOS semiconductor device may be implemented.

[0101] When the semiconductor device of the present embodiment is exposed to light, carriers may be generated within the upper portion (524) of the epitaxial semiconductor layer (520), and these carriers may migrate to the pn junction within the epitaxial semiconductor layer (520) and be detected.

[0102] According to the present embodiment, since a pn junction is formed within the epitaxial semiconductor layer (520) without an ion implantation process, the thermal budget problem can be solved. In particular, the thermal budget problem can be solved even when the semiconductor device of the present embodiment further includes a silicon CMOS for driving the GCMD.

[0103] In addition, there is an advantage in that a flat pn junction surface can be formed within the epitaxial semiconductor layer (520).

[0104] FIG. 6 is a drawing for explaining a semiconductor device according to another embodiment of the present disclosure.

[0105] The semiconductor device of the present embodiment may be a photodiode. In particular, the semiconductor device of the present embodiment may be a single-photon avalanche diode (SPAD). The semiconductor device of the present embodiment may be formed using a structure substantially identical to the semiconductor structure of FIG. 3b.

[0106] Referring to FIG. 6, the semiconductor device of the present embodiment may include a semiconductor substrate (600) including a lower semiconductor substrate (602) doped with a first type of first dopant and an intrinsic upper semiconductor substrate (604), an epitaxial semiconductor layer (620) formed on the semiconductor substrate (600) and doped with a second type of second dopant while including a semiconductor element different from that of the semiconductor substrate (600), a diffusion region (630) formed in the upper semiconductor substrate (604) under the epitaxial semiconductor layer (620) and containing the second dopant, a first electrode (640) connected to the epitaxial semiconductor layer (620), and a second electrode (650) connected to the lower semiconductor substrate (602). The epitaxial semiconductor layer (620) may have a sidewall surrounded by an insulating layer (610).

[0107] The semiconductor substrate (600), the insulating layer (610), the epitaxial semiconductor layer (620), and the diffusion region (630) may substantially correspond to the semiconductor substrate (300), the insulating layer (310), the epitaxial semiconductor layer (320), and the diffusion region (330) of FIG. 3b.

[0108] The first electrode (640) can be formed on the upper surface of the epitaxial semiconductor layer (620) to be in contact with the epitaxial semiconductor layer (620).

[0109] The second electrode (650) may be formed on the upper surface of the lower semiconductor substrate (602) to be in contact with the lower semiconductor substrate (602). Since the lower semiconductor substrate (302) in the semiconductor structure of FIG. 3B is covered with the upper semiconductor substrate (304), the insulating layer (310), and the epitaxial semiconductor layer (320), in order to form the second electrode (650) on the upper surface of the lower semiconductor substrate (602), it may be necessary to expose a portion of the upper surface of the lower semiconductor substrate (620). To this end, in an area that does not overlap with the epitaxial semiconductor layer (620) and the diffusion region (630), the insulating layer (610) and the upper semiconductor substrate (604) may be selectively etched to form a hole (H) that exposes a portion of the upper surface of the lower semiconductor substrate (602). The exposed upper surface of the lower semiconductor substrate (602) will hereinafter be referred to as an exposed surface (ES). The second electrode (650) can be formed on this exposed surface (ES).

[0110] The first electrode (640) and the second electrode (650) are connected to different types of epitaxial semiconductor layers (620) and lower semiconductor substrates (602), respectively, and can drive the semiconductor device of the present embodiment by applying a required voltage thereto. As an example, the first electrode (640) may correspond to a cathode electrode and the second electrode (650) may correspond to an anode electrode, or conversely, the first electrode (640) may correspond to an anode electrode and the second electrode (650) may correspond to a cathode electrode.

[0111] When the semiconductor device of the present embodiment is exposed to light, carriers may be generated within the epitaxial semiconductor layer (620), and these carriers may move to the semiconductor substrate (600) to cause an avalanche effect.

[0112] According to this embodiment, the thermal budget problem can be solved because an ion implantation process is not involved in forming a pn junction in a semiconductor substrate (600).

[0113] The foregoing detailed description has been provided with reference to specific embodiments for purposes of illustration. However, the foregoing exemplary discussions are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The following embodiments have been chosen and described to best explain the principles of the present disclosure and its practical applications, thereby enabling others skilled in the art to best utilize the present disclosure and various embodiments with various modifications as are suited to the particular use contemplated.

[0114] This work was supported by the Materials and Components Technology Development Project of the Korea Institute of Industrial Technology Planning and Evaluation (Project No. 20021925, Development of eco-friendly security fibers and application products using near-infrared luminescent dyes with a wavelength of 1000 nm or more), the Joint Research R&D Project of the Global Industrial Technology Cooperation Center of the Korea Institute for Advancement of Technology (KIAT) (Project No. P0028324, Development of a new optical-electroencephalographic imaging technology and development of an artificial intelligence-based brain disease and brain surgery monitoring platform using it), and the Small and Medium Business Technology Innovation Development Project of the Korea Institute for Technology and Information Promotion (Project No. RS-2024-00512068, Development of Ge-on-Si short-wavelength infrared image sensor and camera system).

[0115] Examples of the present disclosure can be applied to various semiconductor devices and methods for manufacturing the same.

Claims

1. A semiconductor substrate doped with a first dopant of the first type or an intrinsic semiconductor substrate; An epitaxial semiconductor layer formed on the semiconductor substrate, doped with a second type of dopant different from the first type and including a semiconductor element different from the semiconductor substrate; and A diffusion region formed within the semiconductor substrate to be in contact with the epitaxial semiconductor layer and containing the second dopant. Semiconductor devices.

2. In paragraph 1, When the semiconductor substrate is doped with the first dopant, the concentration of the first dopant in the semiconductor substrate is lower than the concentration of the second dopant in the epitaxial semiconductor layer. Semiconductor devices.

3. In paragraph 1, The concentration of the second dopant in the diffusion region is less than or equal to the concentration of the second dopant in the epitaxial semiconductor layer. Semiconductor devices.

4. In paragraph 1, The semiconductor substrate comprises silicon, The above epitaxial semiconductor layer contains germanium. Semiconductor devices.

5. In paragraph 1, Further comprising an insulating layer formed on the semiconductor substrate and surrounding the side wall of the epitaxial semiconductor layer. Semiconductor devices.

6. In paragraph 5, The above diffusion region partially overlaps with the insulating layer. Semiconductor devices.

7. In paragraph 1, The maximum thickness of the above epitaxial semiconductor layer is greater than the maximum thickness of the above diffusion region. Semiconductor devices.

8. In paragraph 1, If the semiconductor substrate is genuine, it further includes another semiconductor substrate disposed under the semiconductor substrate and doped with the first dopant. Semiconductor devices.

9. In paragraph 1, When the semiconductor substrate is doped with the first dopant, an impurity region formed at a predetermined depth from the upper surface of the epitaxial semiconductor layer within the epitaxial semiconductor layer and doped with the first dopant; and Further comprising a gate formed by interposing a gate insulating layer on the above epitaxial semiconductor layer, Functioning as a gate-controlled charge modulation device Semiconductor devices.

10. In paragraph 1, If the semiconductor substrate is genuine, another semiconductor substrate disposed under the semiconductor substrate and doped with the first dopant; A first electrode connected to the epitaxial semiconductor layer; and Further comprising a second electrode connected to the other semiconductor substrate, Functioning as a single-photon avalanche diode Semiconductor devices.

11. A semiconductor substrate doped with a first dopant of the first type; and An epitaxial semiconductor layer formed on the semiconductor substrate and including a semiconductor element different from that of the semiconductor substrate, The epitaxial semiconductor layer includes an upper portion doped with a second dopant of a second type different from the first type, and a lower portion containing the first dopant. Semiconductor devices.

12. In paragraph 11, The concentration of the first dopant in the semiconductor substrate is greater than the concentration of the second dopant in the upper portion of the epitaxial semiconductor layer. Semiconductor devices.

13. In paragraph 11, The concentration of the first dopant in the lower portion of the epitaxial semiconductor layer is less than or equal to the concentration of the first dopant in the semiconductor substrate. Semiconductor devices.

14. In paragraph 11, The semiconductor substrate comprises silicon, The above epitaxial semiconductor layer contains germanium. Semiconductor devices.

15. In paragraph 11, Further comprising an insulating layer formed on the semiconductor substrate and surrounding the side wall of the epitaxial semiconductor layer. Semiconductor devices.

16. In paragraph 11, The interface between the upper and lower portions of the epitaxial semiconductor layer is parallel to the upper surface of the semiconductor substrate. Semiconductor devices.

17. In paragraph 11, An impurity region formed within the upper portion of the epitaxial semiconductor layer at a predetermined depth from the upper surface of the upper portion of the epitaxial semiconductor layer and doped with the first dopant; and Further comprising a gate formed by interposing a gate insulating layer on the above epitaxial semiconductor layer, Functioning as a gate-controlled charge modulation device Semiconductor devices.

18. A step of providing a semiconductor substrate doped with a first dopant of a first type or an intrinsic semiconductor substrate; and A step of epitaxially growing a semiconductor layer containing a semiconductor element different from that of the semiconductor substrate on the semiconductor substrate, and doping a second dopant of a second type different from the first type, The second dopant diffuses from the semiconductor layer into the semiconductor substrate, thereby forming a diffusion region within the semiconductor substrate. Method for manufacturing a semiconductor device.

19. In paragraph 18, When the semiconductor substrate is doped with the first dopant, the second dopant doping step is performed so that the concentration of the second dopant in the semiconductor layer is greater than the concentration of the first dopant in the semiconductor substrate. Method for manufacturing a semiconductor device.

20. In paragraph 18, The semiconductor substrate comprises silicon, The above semiconductor element includes germanium. Method for manufacturing a semiconductor device.

21. In paragraph 18, Before the epitaxial growth step of the above semiconductor layer, Further comprising a step of forming an insulating layer on the semiconductor substrate, which exposes a portion of the semiconductor substrate; The semiconductor layer is grown on the exposed portion of the semiconductor substrate. Method for manufacturing a semiconductor device.

22. In paragraph 21, The second dopant diffuses beneath the insulating layer so that the diffusion region partially overlaps the insulating layer. Method for manufacturing a semiconductor device.

23. In paragraph 18, If the semiconductor substrate is genuine, the method further comprises the step of providing another semiconductor substrate doped with the first dopant under the semiconductor substrate. Method for manufacturing a semiconductor device.

24. A step of providing a semiconductor substrate doped with a first dopant of a first type; and A step of epitaxially growing a semiconductor layer containing a semiconductor element different from that of the semiconductor substrate on the semiconductor substrate, and doping a second dopant of a second type different from the first type, The first dopant diffuses from the semiconductor substrate into the semiconductor layer, thereby forming a diffusion region at the bottom of the semiconductor layer. Method for manufacturing a semiconductor device.

25. In paragraph 24, The second dopant doping step is performed so that the concentration of the second dopant in the semiconductor layer is lower than the concentration of the first dopant in the semiconductor substrate. Method for manufacturing a semiconductor device.

26. In paragraph 24, The semiconductor substrate comprises silicon, The above semiconductor element includes germanium. Method for manufacturing a semiconductor device.

27. In paragraph 24, Before the epitaxial growth step of the above semiconductor layer, Further comprising a step of forming an insulating layer on the semiconductor substrate, which exposes a portion of the semiconductor substrate; The semiconductor layer is grown on the exposed portion of the semiconductor substrate. Method for manufacturing a semiconductor device.

28. In paragraph 24, When the above diffusion region is formed, the diffusion speed of the second dopant is constant in the vertical direction. Method for manufacturing a semiconductor device.

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