Parallel execution of protocols on a quantum device

By employing parallel execution of quantum protocols on a QPU based on hardware limitations and dependency graphs, the method addresses inefficiencies in quantum device characterization and calibration, significantly reducing execution time.

WO2026029675A1PCT designated stage Publication Date: 2026-02-05ORANGE QUANTUM SYSTEMS HOLDING BV
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Patent Information

Application Number
PCT/NL2025/050382
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-08-01
Filing Date
2025-08-01
Publication Date
2026-02-05

AI Technical Summary

Technical Problem

Existing methods for characterizing, calibrating, and tuning up quantum devices are time-consuming and inefficient, particularly due to the challenges of parallelizing quantum protocols which differ significantly from classical protocols.

Method used

A method for parallel execution of quantum protocols on a quantum processing unit (QPU) by identifying and executing parallelizable operations based on hardware limitations, topology, and dependency graphs, using optimization algorithms to minimize a cost function and adjust control signals to mitigate crosstalk effects.

Benefits of technology

This approach drastically reduces the time required for characterizing, calibrating, and tuning up quantum devices by optimizing the execution of protocols, while accounting for hardware constraints and quantum interactions.

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Abstract

Methods and systems are disclosed for executing a plurality of protocols on a plurality of quantum elements of a quantum device. The method comprises receiving or determining the plurality of protocols, identifying parallelizable operations from the operations defined by the plurality of protocols, selecting a set of parallelizable protocols from the plurality of protocols based on the identified parallelizable operations, and executing the selected set of parallelizable protocols in parallel. The identification of parallelizable operation can comprise identifying operations for which a parallel control sequence is available. The selection of the set of parallelizable protocols from the plurality of protocols can be based on hardware limitations of a controller configured to control the quantum device. Each protocol defines at least an operation and one or more quantum elements from the plurality of quantum elements on which the operation is to be performed.
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Description

[0001] Parallel execution of protocols on a quantum device

[0002] Technical field

[0003] The disclosure relates to parallel execution of protocols on a quantum device, and in particular, though not exclusively, to methods and systems for parallel execution of protocols on a quantum processing unit (QPU), especially QPU calibration and tune-up protocols, and to a computer program product enabling a hybrid quantum computer system to perform such methods.

[0004] The benchmarking and operation of quantum devices such as quantum processing units (QPUs) requires extensive, time-consuming protocols to characterise, calibrate, and / or tune-up quantum elements and control operations of the quantum device. Hence, efforts have been made to automate the calibration process.

[0005] US 2020 / 0394524 A1 describes a method for automatic qubit calibration based on a dependency graph, using machine learning to optimise parameter selection. Nevertheless, the method is still relatively time consuming.

[0006] Hence, from the above, it follows that there is a need in the art for a system and method for more efficient automated characterisation, calibration, and / or tune-up of quantum devices.

[0007] It is an aim of embodiments in this disclosure to provide a system and method for more efficient automated characterisation, calibration, and / or tune-up of quantum devices that avoids, or at least reduces the drawbacks of the prior art.

[0008] In a first aspect, embodiments in this disclosure relate to a method for executing a plurality of protocols on a plurality of quantum elements of a quantum device such as a quantum processing unit. The method comprises receiving or determining the plurality of protocols, identifying parallelizable operations from the operations defined by the plurality of protocols, selecting a set of parallelizable protocols from the plurality of protocols based on the identified parallelizable operations, and executing the selected set of parallelizable protocols in parallel. Each protocol defines at least an operation and one or more quantum elements from the plurality of quantum elements on which the operation is to be performed. The identification of parallelizable operation can comprise identifying operations for which a parallel control sequence is available. The selection of the set of parallelizable protocols from the plurality of protocols can be based on hardware limitations of a controller configured to control the quantum device

[0009] The quantum elements can be, for example, qubits, qudits, couplers, resonators, or other elements of the quantum processing unit or other quantum device. The plurality of protocols may comprise interdependent protocols, i.e. , at least a first protocol from the plurality of quantum protocols may be dependent on at least a second (different) protocol from the plurality of quantum protocols. For example, the first protocol may depend on successful execution of the second protocol, or the first protocol may require as an input an output of the second protocol. A protocol typically comprises a measurement, but this is not necessary; for example, some protocols may define so-called ‘parking’ of one or more quantum elements, e.g., in order to enable measurements on nearby quantum elements without interaction with the parked element. For certain protocols, one or more operation parameters may depend on earlier measurements on the same or other quantum elements.

[0010] By executing the protocols in parallel, the time required for execution all required protocols can be drastically reduced. However, parallelisation of quantum protocols is subject to different constraints than parallelisation of threads on a classical computer, due to, e.g., interaction between quantum elements, interaction between quantum protocols, hardware constraints, et cetera. Hence, methods for automated parallelization of classical protocols cannot readily be used for automated parallelization of quantum protocols.

[0011] The set of parallelizable protocols may be selected using a known optimization algorithm; for example, a one or more sets may of parallelizable protocols may be selected by (possibly repeatedly) minimizing a cost function. Such a cost function may include, for instance, contributions based on one or more of: a number of protocols in the set of parallelizable protocols, an accumulated runtime of all sets of parallelizable protocols, a topological distance between qubits, hardware connectivity, experiment parameters. The contributions to the cost function can be weighted individually, and may receive different weights based on the details of a particular system (i.e., including both the quantum device and the controller used to control the quantum device).

[0012] In an embodiment, the plurality of protocols comprises calibration protocols, characterisation protocols, and / or tune-up protocols. Using a parallelised procedure may drastically speed-up the time needed to characterize, calibrate, and / or tune-up the quantum device. Moreover, in these contexts, typically a fixed set of protocols is performed on a large group of similar quantum elements, greatly increasing the potential of parallel protocols (compared to general computations which may be much more restricted in the protocols that may be combined). It is furthermore noticed that in such context, different parameters may be measured than when performing quantum computations. For example, a quantum device manufacturer may be interested in the temperature effects of certain operations, coherence times of quantum elements, and so on, which are typically less relevant to quantum computations (but are rather relevant as constraints that a device to be purchased has to meet, for example). In other words, the protocols used in characterisation processes, and the possibilities to parallelise those, are typically very different than for computational processes.

[0013] In an embodiment, identifying parallelizable operations comprises identifying a plurality of operations for which a parallel control sequence is available. For example, a database with operations may be queried to identify parallelizable operations, or an operation may be analysed based on operation parameters such as operation type, the unitary transformation implemented by an operation or the coordinates on the device where the operations are executed. In other words, identifying the operations for which a parallel control sequence is available may comprise at least one of: querying a database storing information identifying parallelizable operations, and analysing an operation based on operation parameters, such as operation type, a unitary transformation implemented by the operation or coordinates of the quantum elements on which the operations are performed.

[0014] In an embodiment, the plurality of protocols defines a plurality of nodes of one or more dependency graphs, the one or more dependency graphs defining dependencies between the interdependent protocols. Each node may be associated with a (single) protocol (and hence, one or more operations and one or more quantum elements). In such an embodiment, the selection of the set of parallelizable protocols can be based on the dependencies of the one or more dependency graphs. A first node and a second node are not parallelizable if there is a dependency relation between the first node and the second node. The dependency relation can be direct or indirect. The dependency graph may be implemented as a directed acyclic graph (DAG). Such a dependency graph allows for (automated) selection of an order to execute the relevant quantum protocols.

[0015] In general, such a dependency graph (or, where applicable, a similar high-level process encoding) defining a full test or calibration process is defined for each specific quantum device. Designing such a dependency graph can be time consuming and resource intensive, potentially requiring many test runs. However, once the dependency graph has been designed, the execution of the process may be optimised in a relatively straightforward way for any controller by adjusting the parameters of the graph traversal algorithm (e.g., adjusting the weights or parameters of the cost function for selecting sets of parallelisable protocols). This greatly simplifies the process of changing (or upgrading), e.g., a test device or other control hardware for the quantum device.

[0016] In an embodiment, the dependency graph comprises one or more nodes with one or multiple optional dependencies. An optional dependency typically indicates that a given node should be executed even if an earlier node (on which the given node has an optional dependence) fails.

[0017] In an embodiment, the method further comprises updating the dependency graph based on results obtained from the execution of the selected set of parallelizable protocols. More in general, the dependency graph may be updated based on results obtained from the executed nodes. A result can be, e.g., a (binary) state like pass or fail, or a parameter value associated with one or more quantum elements and / or one or more operations. Updating the dependency graph may comprise removing (or marking as not to be executed) any nodes dependent on a failed node. For example, if a quantum element has been detected to be malfunctioning, further nodes involving determination of parameters associated with that quantum element may be skipped or removed.

[0018] In an embodiment, updating the dependency graph based on results obtained from the execution of the selected set of parallelizable protocols comprises determining, based on the results, that a given quantum element associated with a given node is malfunctioning, and updating a protocol associated with a node with an optional dependency on the given node based on the determined malfunctioning of the given quantum element.

[0019] In some cases, protocols involving a malfunctioning quantum element may still be executed, e.g., to detect an effect of the malfunctioning quantum element on a different quantum element. In some cases, the protocol involving the malfunctioning quantum element may have to be adjusted to take the malfunctioning into account.

[0020] In an embodiment, the method further comprises optimising execution of the dependency graph. The execution of the dependency graph may be re-optimised if the dependency graph has been updated. Optimisation may take place before starting execution of the dependency graph, or during execution. The optimisation may be ‘global’, taking the entire dependency graph into account, or ‘local’, e.g., optimising only the next step or the next few steps. The optimal optimisation horizon typically depends on the expected outcome of the execution of the nodes. The optimisation may be automated using known dependency graph optimisation algorithms.

[0021] In an embodiment, the selection of the set of parallelizable protocols is based on hardware limitations of the quantum device and / or on hardware limitations of a controller configured to control the quantum device. For example, some quantum devices can only address a limited number of quantum elements at the same time, and the same may be true for the controller controlling the quantum device.

[0022] As a further example, hardware switching may be a relatively ‘expensive’ process (e.g. because it is slow or generates a relatively large amount of heat), but at the same time, continuously probing the same part of a quantum device may cause an unwanted heat accumulation, requiring timely switching to a different part of the quantum device (or pausing the probing). As noted above, an optimisation algorithm (e.g., a cost function) may be used to balance, e.g., the cost of switching with the cost of local heat accumulation.

[0023] In an embodiment, the selection of the set of parallelizable protocols is based on a topology of the quantum device. For example, the selection of the set of parallelizable protocols may be based on a distance measure between the quantum elements defined by the respective protocols. The distance measure may be one of: spatial distance between the quantum elements, interaction strength between the quantum elements, or level of connectivity between the quantum elements.

[0024] The topology of the quantum device defines the (relative) positioning of the one or more quantum elements defined in the parallelizable protocols. Typically, parallelizable operations are not performed on neighbouring quantum elements (or for multi-element operations, neighbouring groups of quantum elements), to limit unwanted interactions. If several groupings of quantum elements on which parallel operations are to be executed are possible, the quantum elements may be selected to maximise, e.g., a minimum, median, or average distance between the quantum elements in a group.

[0025] In an embodiment, executing the selected set of parallelizable protocols in parallel comprises: determining control signals for the operations defined in the selected set of parallelizable protocols, determining a timing of the control signals such that at least two operations overlap in time, and executing the operations by applying the control signals to the respective quantum elements defined in the selected set of parallelizable protocols.

[0026] In an embodiment, determining the timing of the control signals comprises aligning the operations such that measurements occur simultaneously. Typically, an operation ends with a measurement on a quantum element. In some quantum systems, measurements may only be performed for all quantum elements simultaneously. Hence, it may be advantageous to align any measurements such that they coincide. It is often desirable to limit any waiting time during execution of the protocol. Hence, the start of any protocol may be timed such that the (final) measurements coincide. In other cases, it may be desirable to apply any signals as much as possible simultaneously, or consecutively, as the case may be.

[0027] In an embodiment, the determining of the control signals comprises adjusting a control signal based on the selected set of parallelizable protocols. This way, crosstalk effects may be compensated for by, e.g., adjusting a pulse shape (such as pulse width and / or pulse height).

[0028] In general, crosstalk effects between control signals (control pulses) can be mitigated by using additional or modified control pulses (compensating pulses) although this may be limited by hardware capabilities; for instance, to mitigate crosstalk, the hardware should be capable of providing the compensating pulses at the right frequencies (typically limited due to bandwidth limitations), and capable of generating a sufficient number of (simultaneous) pulses (typically limited by the number of pulse sequencers). Determining and fine-tuning the compensating pulses generally requires a (time-consuming) measurement to measure the crosstalk magnitude (and phase, in case of microwave-based crosstalk). For testing purposes (e.g., in the context of characterising a quantum device), these experiments can be too time-consuming, and the simple approach of not scheduling nodes for which crosstalk may be an issue in parallel might be preferred to make the characterization process as efficient as possible.

[0029] In addition, crosstalk effects with a quantum mechanical nature (such as residual-ZZ coupling, or measurement-based state collapse) can generally not be compensated for by using control pulses and / or compensating pulses. In these cases, improving dependency graph traversal is a more advantageous way to reduce the detrimental effects of this ‘quantum crosstalk’. As an example, the residual-ZZ coupling can affect the signature of a Hahn Echo experiment by introducing an additional oscillation whose frequency is proportional to the coupling strength.

[0030] One aspect of this disclosure relates to a computer comprising a computer readable storage medium having computer readable program code embodied therewith, and a processor, preferably a microprocessor, coupled to the computer readable storage medium, wherein responsive to executing the computer readable program code, the processor is configured to perform any of the methods described herein.

[0031] One aspect of this disclosure relates to a computer program or suite of computer programs comprising at least one software code portion or a computer program product storing at least one software code portion, the software code portion, when run on a computer system (e.g., a hybrid computer system comprising a classical computer system and a quantum device, such as a quantum processing unit), being configured for executing any of the methods described herein.

[0032] One aspect of this disclosure relates to a non-transitory computer-readable storage medium storing at least one software code portion, the software code portion, when executed or processed by a computer (e.g., the hybrid computer system), is configured to perform any of the methods described herein.

[0033] As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system”. Functions described in this disclosure may be implemented as an algorithm executed by a microprocessor of a computer. Furthermore, aspects of the present embodiments may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied, e.g., stored, thereon.

[0034] Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non- exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fibre, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0035] A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0036] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fibre, cable, RF, etc., or any suitable combination of the foregoing. Computer program code for carrying out operations for aspects of the present embodiments may be written in any combination of one or more programming languages, including a functional or an object oriented programming language such as Java(TM), Scala, C++, Python or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer, server or virtualized server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0037] Aspects of the present embodiments are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the embodiments. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor, in particular a microprocessor or central processing unit (CPU), or graphics processing unit (GPU), of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer, other programmable data processing apparatus, or other devices create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0038] These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function / act specified in the flowchart and / or block diagram block or blocks.

[0039] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0040] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0041] The embodiments will be further illustrated with reference to the attached drawings, which schematically will show embodiments according to the invention. It will be understood that the invention is not in any way restricted to these specific embodiments. Identical reference signs refer to identical, or at least similar elements.

[0042] Brief description of the drawings

[0043] Fig. 1 depicts a schematic of a hybrid computing system including a classical processor and a quantum device; Fig. 2A schematically depicts a characterisation scheme for control pulses for controlling one or more qubits according to an embodiment and Fig. 2B is a flow chart of a method according to an embodiment;

[0044] Fig. 3A schematically shows a Rabi experiment executed on one qubit and Fig. 3B-D schematically show a Rabi experiment executed in parallel on two qubits;

[0045] Fig. 4A-D schematically depict systems with two or three quantum elements and corresponding dependency graphs;

[0046] Fig. 5A-C schematically depict systems with eight quantum elements and corresponding dependency graphs;

[0047] Fig. 6 schematically depicts a system with eight quantum elements and a corresponding dependency graph;

[0048] Fig. 7A schematically depicts a system with twelve quantum elements and a corresponding dependency graph, and Fig. 7B schematically depicts selecting a set of parallel nodes from the dependency graph;

[0049] Fig. 8A and 8B depict quantum circuits;

[0050] Fig. 9 is graph depicting measurements of echo experiments;

[0051] Fig. 10 is a flow chart of a method according to an embodiment; and

[0052] Fig. 11A and 11B are block diagrams illustrating, respectively, an exemplary hybrid data processing system and an exemplary classical data processing system that may be used for executing methods and software products described in this disclosure.

[0053] Detailed description

[0054] Fig. 1 depicts a schematic of a hybrid computing system including a classical processor and a quantum device, such as a quantum processing unit (QPU) 110. The quantum processing unit comprises a plurality of qubits 112i-nor qudits, and possibly other quantum elements such as resonators, couplers, et cetera. A quantum algorithm may be defined in terms of quantum circuits which define sequences of quantum gates, which may be regarded as instructions to manipulate the states of the qubits 112i-nof the quantum device. Quantum gates are typically implemented by applying one or more control signals, e.g., AC signals such as pulses and / or DC signals, to the quantum elements. In the examples provided below, qubits are typically discussed as exemplary quantum elements, but the discussion is generally equally applicable to other quantum elements.

[0055] A classical processor 100, which may include a CPU, GPU and / or other special purpose processors such as an FPGA, may be used to determine or receive a sequence of operations (which may be a sequence of quantum gate operations, but also other operations). The classical processor may be configured to translate the operations to an instruction set 120 that can be executed by a quantum controller 102, which may be configured to convert these instructions into analog signals 122 for controlling the qubits which are sent to the QPU. In some embodiments, the quantum controller may comprise an arbitrary waveform generator (AWG) 104. In some embodiments, the quantum controller may comprise a switch matrix that routes the analog signals to the correct quantum elements. The quantum controller may be limited in the amount and type of signals that can be generated and distributed simultaneously. Other implementations may use a quantum controller with more, fewer, and / or different hardware elements.

[0056] The quantum device 110 may comprise one or more qubits 112-i_n, which may be implemented based on any suitable hardware platform, e.g., superconducting qubits, semiconducting qubits, qubits based on nitrogen vacancy NV centres in a diamond lattice, neutral atoms or trapped ions, et cetera. After the application of the control signals 124, the state of the qubits may be measured resulting in one or more analog measurement signals 126 which are sent back (via the quantum controller 102) to the classical processor 100. The analog measurement signals may be digitized into a digital measurement signal 130 using a digitizer 108, and processed by the classical processor. In some embodiments, the classical processor may update the hardware instructions based on the processed data 132 (when performing automated experiments).

[0057] The shape of the control signals 124 (electro-magnetic and / or optical pulses) sent to the quantum elements 112i-nof the quantum processing unit 110 may need to be calibrated by performing a test protocol on the quantum processing unit to ensure the control pulses realize the gate operations as defined in the quantum circuit that is executed by the system.

[0058] Fig. 2A schematically depicts a scheme for executing a plurality of protocols on a plurality of quantum elements of a quantum processing unit, for example calibration protocols, characterisation protocols, and / or tune-up protocols. Such scheme may be executed in an automated way by a hybrid computing system as described above with refence to Fig. 1. The steps of the scheme may be conceptually divided into two blocks: a first block 202 comprising steps 210-214 related to preparation and configuration of the control signals, and a second block 204 comprising steps 216-220 related to the execution and analysis.

[0059] The plurality of protocols may comprise interdependent protocols, whose dependencies are defined by a dependency graph, which is typically a directed acyclic graph. In some embodiments, several mutually independent dependency graphs may be used. For example, each protocol may correspond to a node of the dependency graph. A protocol defines an operation and one or more quantum elements on which the operation is to be performed, for example, a Rabi experiment on a single qubit, a parallel echo experiment between two qubits, or a crosstalk experiment between two qubits, possibly in combination with activation of a coupler, et cetera. A step 210 comprises selecting one or more parallelizable protocols from the plurality of protocols. Selecting parallelizable protocols may comprise applying one or more of the following constraints: identifying nodes that must be executed; identifying operations for which a parallel control sequence is available; identifying nodes in a dependency graph that are not interdependent (directly or indirectly); identifying operations that satisfy hardware limitations of either the quantum processing unit or the quantum controller; identifying quantum elements that meet a QPU topology constraint (e.g., excluding nearest neighbours).

[0060] These selection criteria will be expanded upon below.

[0061] Additionally or alternatively, the selection may be performed using an optimization algorithm, for example, by minimizing a cost function. Such a cost function may include contributions based on one or more of:

[0062] 1. the topological distance between qubits. This accounts for (quantum-based) crosstalk effects. This may be implemented as an inequality constraint (e.g., disallowing nearest-neighbour qubits), or using a more advanced cost function, e.g., favouring larger distances, for examples through an exponentially decreasing cost. Another embodiment might penalize nodes that represent qubits that have strong microwave crosstalk (after this was measured), in particular if the hardware equipment is unable to apply compensating pulses.

[0063] 2. the connectivity. Since switching may take time and / or lead to undesired heating effects on the quantum device, one can penalize the parallelization or quick succession of nodes defining quantum elements that are not addressable simultaneously.

[0064] 3. the protocol (or experiment). This can be implemented, e.g., as an equality constraint (for example through a Lagrange multiplier), to ensure that nodes that implement non- parallelizable operations are never scheduled for parallel execution.

[0065] One or more (e.g., all) contributions to the cost function can be weighted individually, to suit the needs of the particular system. As shown by the above examples, one or more cost function parameters (e.g., the weights) may be based on the results of earlier measurements. Furthermore, one or more cost function parameters may be specific to the hardware that is being used. As a further example, instead of minimizing a cost function, the optimization algorithm may, e.g., maximise the number of parallelisable protocols in the set for which the cost function does not exceed a predetermined threshold. Other implementations can be readily envisaged.

[0066] A step 212 comprises determining the required operations and, where necessary, the relative timing of the operations. For example, each protocol typically ends with a measurement, and it is often desirable to perform all measurements simultaneously; hence, if protocols with different durations are executed in parallel, their starting time (or an intermediate ‘waiting’ time) may be adjusted such that the final measurement coincides. Additionally, it may be needed to align operations on different quantum elements to a ‘time grid’ that is imposed by the hardware. For example, time may be discretised based on an internal clock speed.

[0067] A step 214 comprises configuring the control signals. This may comprise, for example, determining one or more of: a pulse amplitude, a pulse duration, a pulse frequency, a pulse starting time, et cetera, for each of one or more control pulses. In some cases, one or more control signals (typically electromagnetic pulses) may be adjusted, compared to a nonparallel execution, to take into account effects of the protocols that are executed in parallel. For example, crosstalk effects may be compensated for by adjusting pulse parameters.

[0068] A step 216 comprises executing the protocols in parallel, i.e. , at least partially overlapping in time. This step typically comprises generating the control signals (e.g., using an AWG 104) and sending the control signals to the required quantum elements (e.g., using the switch matrix 106). A step 218 comprises determining an output, i.e., a response by the quantum processing unit to the received control signals. As noted, this response typically comprises measurement data. The determined output can be binary (e.g., success of failure, or a zero or one state), or multivalued. Some protocols may comprise repeated execution of the same experiment to determine a statistical quantity, e.g. an expectation value.

[0069] An optional step 220 comprises re-executing protocols that returned a ‘failed’ status. Depending on the protocols and the implementation, it may be preferable to repeat only the failed experiments (either in parallel or sequentially), or to repeat the entire set of parallel protocols.

[0070] The same steps 210-220 may be repeated as often as necessary until all protocols have been executed. If the protocols are organized in a dependency graph, known methods to traverse a dependency graph may be used to select the subsequent node or nodes. In some cases, the dependency graph may be updated based on results of an executed protocol. In some cases, the parallelisation of the dependency graph may be pre-optimised. In such cases, the traversing of the dependency graph may be re-optimised if the dependency graph is updated.

[0071] The step of identifying operations for which a parallel control sequence is available may comprise querying a database. Such a database may have been filled manually and / or algorithmically. The database may, for example, comprise binary flags whether a parallelizable control sequence is available for any given operation, or a table indicating whether a parallel control sequence is available for a combination of two (or more) operations. In another embodiment, identifying parallelizable operations may comprise analysing an operation or a combination of operations (based on, e.g., operation parameters) to determine whether a parallel protocol is available. It is noted that this criterion may be interrelated with other criteria; for example, in some cases two operations may be parallelizable only if the distance between the quantum elements on which they are to be executed is sufficiently large. As a rule of thumb, the larger the distance between the application of two operations, the less similar they need to be in order to be parallelizable.

[0072] Fig. 2B is a flow chart of a method according to an embodiment. This flow chart corresponds to the workflow of Fig. 2A in the context of traversal of a graph, e.g., a dependency graph. A first step 230 comprises executing a current node of the graph. A step 232 comprises selecting nodes from the graph that may be executed in parallel with this current node. This step may comprise applying one or more filters to select parallelizable nodes from the nodes in the graph, e.g.: selecting nodes defining operations that are parallelizable with the operation defined in the current node; deselecting nodes that are marked as unneeded; deselecting nodes that are dependent on the current node or on which the current node depends, or that are dependent on any of the selected parallelizable nodes or on which any of the parallelizable nodes depends; deselect nodes that do not meet QPU topology I connectivity constraints; deselect nodes that do not meet hardware constraints (e.g., electronics constraints) of the quantum processing unit and / or the quantum controller, et cetera. In general, the filtering may be performed in any order (although it may be less efficient to start with the dependency selection).

[0073] As was explained above with reference to step 210, the selection of the nodes to be executed in parallel may be performed by an optimisation algorithm.

[0074] A step 234 comprises preparing the selected nodes. This step comprises, for each selected node, determining 236 any dependencies, determining 238 which dependencies require execution, and, for each dependency that requires execution, recursively executing steps 230-244. A step 240 comprises determining whether each dependency has been executed successfully; if not, the failed node is removed from the set of parallelizable nodes and the failure is propagated through the dependency graph (as explained in more detail below, e.g., with reference to Figs. 4D and 5C).

[0075] Finally, when all dependencies for the selected nodes have been resolved, a step 244 comprises executing the selected nodes in parallel. As described above, this step may comprise determining the operations (e.g., pulses to play, or acquisitions to execute) defined by the selected nodes, preparing the instruments (e.g., the quantum controller) to play the control signal required to execute the calibration steps, and playing the control signals, acquire and analyze the data. This step may further comprise, based on the outcome of the experiment, declaring whether the experiment passed or failed. This declaration may be node- or element-specific (it is allowed to declare failure on some elements, and success on others). Optionally, this step may also comprise retrying failed protocols. In principle, there are various ways of attempting to recover from failure. In general, it is inefficient to re- execute the entire parallel experiment. To exclude the phenomena arising from the parallelization from causing the failure, one option is to re-execute the failed steps sequentially. Usually, the graph is progressed only for nodes that succeeded.

[0076] In pseudo-code, this might look, for example, as follows: def execute_node(graphj node) :

[0077] # Obtain all nodes that can be executed in parallel with ' node' parallel_nodes = graph . select_parallel_nodes(node)

[0078] # Get all dependencies before executing the parallel node all_dependencies = graph .get_dependencies(parallel_nodes)

[0079] # Ensure the dependencies of all nodes are ready for dependency in all_dependencies : execute_node(graphj dependency)

[0080] # Extract the parallel function execution_function = get_parallel_function(graph nodes)

[0081] # Execute the parallel function return execution_f unction( )

[0082] Fig. 3A schematically show a Rabi experiment executed on one qubit and Fig. 3B-D schematically show a Rabi experiment executed in parallel on two qubits. The Rabi experiment is a typical example of a protocol that is performed during characterization and / or calibration of a quantum device such as a quantum processing unit. The goal of this experiment is to find the pulse amplitude at which a 1 TT rotation of the qubit is achieved. As shown in Fig. 3A, in one implementation of this experiment, a qubit is prepared in the ground state 300, a pulse of increasing amplitude 302I-3 is applied, and the resulting state is measured 304. In the depicted example, the sequence 310 comprises three such measurements with different amplitudes.

[0083] Fig. 3B shows a simple parallel protocol, in which the same sequence 310 is implemented on two different qubits. Such a parallel protocol is typically easy to implement on most hardware, as essentially the same pulses are applied at essentially the same moments to different qubits. As a result, all operations are aligned.

[0084] Fig. 3C shows an example wherein a modified sequence 312 with shorter pulses is executed on one of the qubits (for example, one of the qubits may be more strongly coupled to the drive signal than the other qubit). In this example, the experiments start at the same moment. However, as the durations of the pulses are not equal, the measurements will not align anymore (and neither are the subsequent pulses and the reset operations that prepare the qubit in the ground state). Since a measurement on a qubit can affect the state of another qubit, for example due to the projective nature of a quantum measurement, or because both qubits are connected to the same readout line, this may adversely affect the experiment results, because the measurement on one qubit is not properly aligned with the other. Thus, proper parallel protocols typically align the measurement operations. By violating that constraint, the protocol of Fig. 3C may give less useful or even useless results. It Similar arguments hold if the durations of the measurements or reset operations are not equal, instead of or in addition to the Rabi pulse durations.

[0085] Fig. 3D shows the same example with an improved parallel protocol. In this example, the modified sequence 314 has the same operations and durations as the sequence 312, but the operations have been shifted such that the measurements align. Depending on the implementation, it may be desirable to also align other operations, e.g., the reset operations (leading to a waiting time between the reset and the Rabi pulse, instead of between the measurement and reset operation).

[0086] Consequently, more advanced pulse scheduling is required when parallelizing protocols. Note that this is not limited to parallelizing similar protocols, such as here two Rabi protocols, but may also be applicable to more different protocols. As noted earlier, in general each protocol comprises at least one measurement operation.

[0087] Fig. 4A-D schematically depict systems with two or three quantum elements and corresponding dependency graphs. Elliptical nodes represent protocols that cannot be parallelized, whereas hexagonal nodes represent protocols that can be parallelized. Arrows indicate dependencies, where the ‘B A’ denotes that node B depends on (successful) execution of node A. Optional dependencies are denoted with dashed arrows. In these examples, letters represent protocols and numbers refers to the qubit(s) on which the protocol is executed.

[0088] Fig. 4A depicts a basic example of the characterization (and / or calibration or tune-up) of a system 400 comprising two independent quantum elements 402I,2, here assumed to be qubits. The system may comprise other quantum elements that are not shown. The characterization graph 410 comprises 5 nodes labelled A, B1 , B2, C1, and C2. Node C1 depends on B1 and node C2 depends on B2. Nodes B1 and B2 both depend on node A.

[0089] Execution of this characterization graph requires execution of nodes C1 and C2. Following the flowchart shown in Fig. 2B, a first step comprises selecting nodes that can be executed in parallel with C1 and C2. This is the set {C1 , C2, B1 , B2}. However, since C1 and C2 depend on B1 and B2, respectively, nodes of the set {C1, C2} cannot be executed in parallel with nodes of the set {B1, B2}. C1 and C2 depend on B1, B2 respectively, which both depend on A. Hence, node A is executed first.

[0090] After execution of node A, node B1 can be executed. Since node B1 can be executed in parallel with B2, these nodes may be executed in parallel using a single parallel experiment representing {B1, B2}. If that is successful, a parallel experiment representing {C 1 , C2} is executed. Thus, the execution order is: A - {B 1 , B2} - {C 1 , C2}. In principle, other sequences may also be possible, e.g., A - B1 - {B2, C1} - C2, which could be preferable, for example, in case nodes B2 and C1 take much more time to execute than nodes B1 and C2.

[0091] Fig. 4B depicts an example of a three-qubit system in which one qubit is ignored (for example, it may already be known to be malfunctioning). In this example, although the system of Fig. 4A is extended by adding a third qubit 402s, the metrics of this qubit are considered irrelevant. Hence, execution of all protocols concerning (only) qubit 3 may be skipped, and the corresponding node in the dependency graph 412 have been shaded. Thus, although the nodes for qubit 3 could be executed in parallel with those for qubits 1 and 2, in this example they are not. Hence, the execution order may the same as in the previous example: A - {B 1 , B2} - {C 1 , C2}. It can be useful to have unused nodes in the dependency graph, if, for example, the same graph is used for multiple quantum devices, where the ignored qubit should be characterized (for example, because it is not malfunctioning in another system).

[0092] Fig. 4C depicts the same system as Fig. 4B, but in this case, an additional protocol D is inserted between protocols B and C. This additional protocol D is not parallelizable, and is hence depicted as an ellipsis. Again, the characterization of qubit 3 is ignored. Thus, the execution order becomes: A - {B 1 , B2} - D1 - D2 - {C 1 , C2}. As D1 and D2 do not depend on each other, the order D1 - D2 can also be reversed.

[0093] Fig. 4D depicts the same system as Fig. 4C, but now there is a single node D that depends on all of B1-B3. In certain cases, one wishes to continue with nodes even if a dependency failed. One example is the characterization of crosstalk, which could be represented by node D in Fig. 4D. This requires the elements on which crosstalk is measured to be calibrated to a certain degree (nodes B1-B3).

[0094] As an example, the case of microwave drive crosstalk may be considered, in which the excitation of qubit / due to a microwave drive pulse on qubit j is measured. If element / is malfunctioning, it is not possible to measure the crosstalk of j to / , since the state of / cannot be measured. However, it is still possible to apply a microwave drive signal to qubit / , and hence it is still possible (and sometimes desirable) to measure crosstalk of / to j.

[0095] As a result, when node B3 in dependency graph 416 fails or is not required, it should still be possible to execute node D (unless B1 and B2 also fail). However, it will not be possible (or may not be necessary) to execute node C3. The knowledge that element 3 is malfunctioning may also be passed to node D; for example to ensure that the row in the crosstalk matrix corresponding to measuring the state of this qubit 3 is skipped.

[0096] In general, the failure to execute C3 limits the parallel execution of nodes C1-C3: only C1 and C2 can be executed in parallel (given no other constraints), whereas C3 will be skipped.

[0097] Fig. 5A-C schematically depict systems with eight quantum elements and corresponding dependency graphs. These figures illustrate some exemplary applications of constraints based on QPU topology. The dependency graphs are similar to those described with reference to Fig. 4A-D, but now for eight qubits (or other quantum elements). A solid line between two qubits (e.g., between qubits 1 and 3) denotes an interaction. Qubits connected with a single solid line are considered nearest neighbours, qubits that are two steps away are considered next-nearest neighbours, et cetera. For example, the nearest neighbours of qubit 3 are qubits 1 , 2, 5, and 6, and the next-nearest neighbours are qubits 4, 7, and 8. For the current examples, it is assumed that protocols cannot be executed in parallel on nearest neighbours. This constraint can be generalized to include next-nearest neighbours or quantum elements based on some (other) distance measure, and may depend on the protocol(s) under consideration. For example, experiments which are sensitive to crosstalk to a high degree may require a larger distance than experiments are sensitive to crosstalk to a low degree.

[0098] Various execution orders may be considered to traverse the dependency graph, such as breadth-first, e.g., A - {B1 , B2, B5, B6} - {B3, B4, B7, B8} - C1 - C2 - C3 - C4 - C5 - C6 - C7 - C8 - {D1 , D2, D5, D6} - {D3, D4, D7, D8} or depth-first, e.g.: A - {B1, B2, B5, B6} - C1 - C2 - C5 - C6 - {D1 , D2, D5, D6} - {B3, B4, B7, B8} - C3 - C4 - C7 - C8 - {D3, D4, D7, D8}. Of course, many permutations are also possible; for instance, the order of execution of nodes C1-C8 is mostly arbitrary.

[0099] The current example only comprises single-qubit operations, but in general, the same methodology may be applied to multi-qubit operations (for example interaction experiments as described below with reference to Fig. 8). In that case, a topology or connectivity constraint might require, for instance, that none of the nearest neighbours of any of the qubits involved in an experiment is involved in a parallel experiment. In the shown eight-qubit topology, that would imply that such experiments are effectively not parallelizable, even if a parallelizable protocol is in principle available (and could be applicable to larger QPUs).

[0100] Fig. 5B shows an example where one is interested in only a subset of device elements, favouring a different approach. As an example, one is interested only in elements 1, 4 and 7. In the example of Fig. 5A, 1 and 4 were not executed in parallel, as that would lead to an inefficient distribution of the qubits over parallelizable sets. However, as they are not nearest neighbours, now they are executed in parallel. An exemplary execution order is: A - {B1, B4, B7} - C1 - C4 - C7 - {D1 , D4, D7}.

[0101] Fig. 5C depicts the same example as Fig. 5B, but now qubit 7 is broken. In this case, the parallel experiment representing {B1, B4, B7} may have a return code such that nodes B1 and B4 pass, and B7 fails. Alternatively, the return value may just indicate a general failure, necessitating all elements to be tested separately or in progressively smaller groups to identify the broken qubit.

[0102] If this occurs, one may re-attempt B7, typically in a sequential manner, e.g., to exclude that failure occurred due to parallelization. Furthermore, failure of B7 should be propagated to C7 and D7 (e.g. C7 and D7 should not be executed). The previously identified parallel experiment representing {D1 , D4, D7} should be updated, and a parallel experiment for {D1, D4} should be executed. This way, failure of a single element will not cause blockage of the characterization of the remainder of the device under test. The resulting execution order can then be: A - {B1, B4, B7} - B7 (again, fails) - C1 - C4 - {D1 , D4}.

[0103] Fig. 6 schematically depicts a system with eight quantum elements and a corresponding dependency graph. The system is similar to the one depicted in Fig. 5A, and the dependency graph is identical to the one depicted in Fig. 5A. However, in this case, due to hardware constraints (e.g., connections between the qubits, or between the qubits and the controller), experiments on the qubits in the dotted area (qubits 1 , 3, 5, and 7) cannot be executed simultaneously with experiments on the qubits in the other region (qubits 2, 4, 6, and 8). In this case, execution should take into account both the constraints imposed by the hardware, as well as those imposed by the nearest-neighbour connectivity of the qubits. These kind of restrictions may be dependent on the protocol(s) that are being executed.

[0104] Since typically switching hardware configurations is more expensive (for example because it is done by manually changing cables, or because cryogenic switching may heat up the QPU), a constraint may be imposed that switches between hardware configurations should be minimized: hence, a depth-first traversal of the dependency graph is preferred in this example. Consequently, qubits 1, 3, 5 and 7 are first completely characterised, before moving on to qubits 2, 4, 6 and 8. The resulting execution order can then be: A - {B1, B5} - {B3, B7} - C1 - C3 - C5 - C7 - {D1 , D5} - {D3, D7} — {B2, B6} - {B4, B8} - C2 - C4 - C6 - C8 - {D2, D6} - {D4, D8}.

[0105] It is noted that in other embodiments, switching between hardware configurations may be free or even preferable (e.g., to let heat accumulation due to a series of experiments dissipate before a new series is performed on the same hardware segment).

[0106] Fig. 7A schematically depicts a system 700 with twelve quantum elements and a corresponding dependency graph 702. The shading indicates areas that can simultaneously be controlled by the quantum controller due to limitations of the used electronics, i.e. , the quantum controller can only control either one or more of qubits {1 , 2, 4, 7, 8, 10}, or one or more of qubits {3, 5, 6, 9, 11 , 12}. Qubits 6 and 12 (shown in black) are known to be defect, and therefore need not be characterized.

[0107] Fig. 7B schematically depicts selecting a set of parallel nodes from the dependency graph 702. In this approach, initially all nodes are selected, and then a number of constraints is applied to reduce the number of nodes in the selected set. Other embodiments may use different selection algorithms. In the dependency graphs on the left-hand side, nodes that are deselected in the current step are rendered striped, whereas previously deselected nodes are shown black.

[0108] A step 710 comprises determining nodes associated with a protocol defining an (in principle) parallelisable operation. As a result, nodes A, C, D, E, G, and H are deselected, and nodes B1-12 and nodes F1-12 remain in the set of potentially parallelisable nodes.

[0109] A step 712 comprises removing unneeded nodes, in this case nodes that only affect the defect qubits 6 and 12. As a result, nodes B6, B12, F6, and F12 are deselected, and nodes B1— 5,7— 11 and nodes Fl-5,7-11 remain in the set of potentially parallelisable nodes.

[0110] A step 714 comprises deselecting nodes based on dependencies. In some implementations, this step may comprise two substeps. The first substep may comprise determining sets of nodes that have no interdependencies, in this example a first set comprising nodes B1— 5,7— 11 and a second set comprising nodes Fl-5,7-11. The second substep may comprise determining the set with the lowest dependency rank, in this example set B1— 5,7— 11. In some cases, the algorithm may check whether the selected subset has unresolved dependencies. In the current example, it can be assumed that node A is a ‘logical’ node that is always considered successful, or that node A has already been successfully executed, or that node A will be executed in response to one or more of nodes B being selected. This step may also comprise removing already executed nodes.

[0111] A step 716 comprises application of electronics constraints. In this example, that results in two potential sets of nodes: {B1, B2, B4, B7, B8, B10} and {B3, B5, B9, B11}. The selection of a specific set may be based on, e.g., alphanumeric ordering of the nodes in the sets, a current hardware configuration, size of the set, et cetera. In the current example, the set {B1, B2, B4, B7, B8, B10} is selected.

[0112] A step 718 comprises applying QPU topology constraints, in this example excluding operations executed on nearest neighbours. Therefore, nodes B4 and B10 may not be executed in parallel with the other nodes, resulting in the selection: {B1, B2, B7, B8}.

[0113] In principle, the algorithm may be executed each time a new (set of) node(s) is to be executed. In practice, it can be more efficient to store intermediate values at each step; e.g., in each step where a selection is made, the same step may be repeated for different subsets until all subsets of nodes have been executed.

[0114] A resulting execution order can then be: A - {B1, B2, B7, B8} - {B4, B10} - {B3, B9} - {B5, B11}, C - D - E - {F1 , F2, F7, F8} - {F4, F10} - {F3, F9} - {F5, F11J - G - H.

[0115] Fig. 8A depicts a quantum circuit of an experiment used to measure the residual-ZZ crosstalk between elements. This experiment is designed to maximally amplify the crosstalk between two quantum elements, e.g., two neighbouring qubits. Here, X refers to a Pauli-X gate, i.e. , a rotation over 180° around the X-axis, and X90 refers to a rotation of 90° around the X-axis. The time T may be referred to as the echo time. Fig. 8B depicts a quantum circuit of a parallelized echo experiment, i.e., two singleelement echo experiments that are applied to two quantum elements simultaneously.

[0116] These figures show that the parallelized echo experiment resembles very much the experiment used to measure the residual-ZZ crosstalk between elements. Consequently, the crosstalk in the parallelized echo experiment typically is also strong, as the parallel echo experiment maximally amplifies the effects of residual-ZZ coupling.

[0117] Fig. 9 is graph depicting measurements of echo experiments in parallel and nonparallel modes. The figure shows the difference in qubit state population between a nonparallel (circles) and parallel (diamonds) execution of this experiment. The parallel execution was performed on two neighbouring qubits. The frequency of the parallel curve is proportional to the ZZ coupling strength. This exemplifies the need for clever selection of quantum elements on which an experiment is executed.

[0118] There exists different mitigation strategies. One includes the previously described constraint on nearest-neighbours: the larger the distance between the quantum elements, the smaller the potential cross talk. Other options include using a tuneable coupler to ‘turn off’ the residual ZZ coupling between elements on the QPU, provided the QPU supports this. This may lead to an adjustment of the echo protocol. If no mitigation strategy is available, the protocol may be marked as non-parallelizable.

[0119] Fig. 10 is a flow chart of a method according to an embodiment. A first step 1002 comprises receiving or determining a plurality of (typically interdependent) protocols. Each protocol defines at least an operation and one or more quantum elements from the plurality of quantum elements on which the operation is to be performed. The plurality of protocols may comprise, e.g., calibration protocols, characterisation protocols, and / or tune-up protocols.

[0120] A step 1004 comprises identifying parallelizable operations from the operations defined by the plurality of protocols. This step may comprise identifying operations for which a parallel control sequence is available, e.g., by querying a database storing information identifying parallelizable operations, and / or by analysing an operation based on operation parameters such as operation type, a unitary transformation implemented by the operation or coordinates of the quantum elements on which the operations are performed.

[0121] A step 1006 comprises selecting a set of parallelizable protocols from the plurality of protocols based on the identified parallelizable operations. Optionally, the selection may also be based on hardware limitations of a controller configured to control the quantum device, on hardware limitations of the quantum device, and / or on a topology of the quantum device. Selecting the set of parallelizable protocols may comprise performing an optimisation algorithm to determine one or more optimal sets. In some embodiments, each protocol may be associated with a node in a dependency graph, e.g., a DAG; in such embodiments, the dependency graph may define dependencies between the interdependent protocols, and the selection of the set of parallelizable protocols may be based on the dependencies of the dependency graph. In particular, a first node and a second node are not parallelizable (and hence, will not be selected in the same set of parallelizable protocols) if there is a dependency relation between the first node and the second node.

[0122] A step 1008 comprises executing the selected set of parallelizable protocols in parallel. The execution may comprise determining control signals for the operations defined in the selected set of parallelizable protocols; determining a timing of the control signals such that at least two operations overlap in time; and executing the operations by applying the control signals to the respective quantum elements defined in the selected set of parallelizable protocols.

[0123] Fig. 11A depicts a system for executing a plurality of protocols on a plurality of quantum elements using a hybrid quantum computer system according to an embodiment. The system 1102 may include a quantum computer system 1104 comprising one or more quantum processors 1108, e.g. a gate-based qubit quantum processor, and a controller system 1110 comprising input output (I / O) devices which form an interface between the quantum processor and the outside world, e.g., the one or more classical processors of a classical computer 1106. For example, the controller system may include a system for generating control signals for controlling the quantum processing elements. The control signals may include for example a sequence of pulses, e.g. microwave pulses, voltage pulses and / or optical pulses, which are used to manipulate qubits. Further, the controller may include output device, e.g. readout circuits, for readout of the qubits and the control signals for readout of the quantum processing elements, e.g. a readout pulse for reading a qubit. In some embodiments, at least a part such readout circuit may be located or integrated with the chip that includes the qubits.

[0124] The system may further comprise a (purely classical information) input 1112 and an (purely classical information) output 1114. The data processor systems may be configured to solve an optimization problem using the quantum computer. Input data may include information about the optimisation problem one wishes to solve. This information may include training data such as input-output pairs, a differential equation, boundary conditions, initial values, regularization values, etc. The input data may be used by the system to construct quantum circuits, in particular quantum feature maps and / or parametrized quantum circuits, and to classically calculate values, e.g. sequences of pulses, which may be used to initialize and control qubit operations according to the quantum circuit. To that end, the classical computer may include a quantum circuit generator 1107. The input data may be used by the system to classically calculate values, e.g. parameter settings, which may be used to initialize the quantum circuit that is implemented on the quantum processor. Similarly, output data may include loss function values, sampling results, correlator operator expectation values, optimisation convergence results, optimized quantum circuit parameters and hyperparameters, and other classical data.

[0125] Each of the one or more quantum processors may comprise a set of controllable quantum processing elements, e.g. a set of controllable two-level systems referred to as qubits. The two levels are |0) and |1) and the wave function of a 7V-qubit quantum processor may be regarded as a complex-valued superposition of 2Wof these (distinct) basis states. The embodiments in this application however are not limited to qubits but may include any multi-level quantum processing elements, e.g. qutrits, that is suitable for performing quantum computation. Examples of such quantum processors include noisy intermediate-scale quantum (NISQ) computing devices and fault tolerant quantum computing (FTQC) devices.

[0126] The quantum processor may be configured to execute a quantum algorithm in accordance with the gate operations of a quantum circuit. The quantum processor may be implemented as a gate-based qubit quantum device, which allows initialization of the qubits into an initial state, interactions between the qubits by sequentially applying quantum gates between different qubits and subsequent measurement of the qubits’ states. To that end, the input devices may be configured to configure the quantum processor in an initial state and to control gates that realize interactions between the qubits. Similarly, the output devices may include readout circuitry for readout of the qubits which may be used to determine a measure of the energy associated with the expectation value of the Hamiltonian of the system taken over the prepared state.

[0127] In some embodiments, the first data processor system may be implemented as a software program for simulating a quantum computer system 1104 comprising a quantum processor system 1108. Hence, in that case, the software program may be a classical software program that runs a classical computer 1106 so that quantum algorithms can be developed, executed and tested on a classical computer without requiring access to a hardware implementation of the quantum processor system.

[0128] Fig. 11B is a block diagram illustrating an exemplary classical data processing system described in this disclosure, for example classical computer 1106. Classical data processing system 1106 may include at least one processor 1122 coupled to memory elements 1124 through a system bus 1126. As such, the data processing system may store program code within memory elements 1124. Further, processor 1122 may execute the program code accessed from memory elements 1124 via system bus 1126. In one aspect, data processing system may be implemented as a computer that is suitable for storing and / or executing program code. It should be appreciated, however, that data processing system 1106 may be implemented in the form of any system including a processor and memory that is capable of performing the functions described within this specification.

[0129] Memory elements 1124 may include one or more physical memory devices such as, for example, local memory 1128 and one or more bulk storage devices 1130. Local memory may refer to random access memory or other non-persistent memory device(s) generally used during actual execution of the program code. A bulk storage device may be implemented as a hard drive or other persistent data storage device. The classical data processing system 1106 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code in order to reduce the number of times program code must be retrieved from bulk storage device 1130 during execution.

[0130] Input / output (I / O) devices depicted as key device 1132 and output device 1134 optionally can be coupled to the data processing system. Examples of key device may include, but are not limited to, for example, a keyboard, a pointing device such as a mouse, or the like. Examples of output device may include, but are not limited to, for example, a monitor or display, speakers, or the like. Key device and / or output device may be coupled to data processing system either directly or through intervening I / O controllers. A network adapter 1136 may also be coupled to data processing system to enable it to become coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter may comprise a data receiver for receiving data that is transmitted by said systems, devices and / or networks to said data and a data transmitter for transmitting data to said systems, devices and / or networks. Operation modems, cable operation modems, and Ethernet cards are examples of different types of network adapter that may be used with classical data processing system 1106.

[0131] As pictured in FIG. 11 B, memory elements 1124 may store an application 1138. It should be appreciated that classical data processing system 1106 may further execute an operating system (not shown) that can facilitate execution of the application. Application, being implemented in the form of executable program code, can be executed by classical data processing system 1106, e.g., by processor 1122. Responsive to executing application, data processing system may be configured to perform one or more operations to be described herein in further detail.

[0132] In one aspect, for example, classical data processing system 1106 may represent a client data processing system. In that case, application 1138 may represent a client application that, when executed, configures classical data processing system 1106 to perform the various functions described herein with reference to a “client”. Examples of a client can include, but are not limited to, a personal computer, a portable computer, a mobile phone, or the like.

[0133] In another aspect, data processing system may represent a server. For example, data processing system may represent an (HTTP) server in which case application 1138, when executed, may configure data processing system to perform (HTTP) server operations. In another aspect, data processing system may represent a module, unit or function as referred to in this specification. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

[0134] The description of the present embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

CLAIMS1. A method for executing a plurality of protocols on a plurality of quantum elements, e.g. qubits, of a quantum device, the plurality of protocols comprising interdependent protocols, the method comprising: receiving or determining the plurality of protocols, each protocol defining at least an operation and one or more quantum elements from the plurality of quantum elements on which the operation is to be performed; identifying parallelizable operations from the operations defined by the plurality of protocols, wherein identifying parallelizable operations comprises identifying operations for which a parallel control sequence is available; selecting a set of parallelizable protocols from the plurality of protocols, based on the identified parallelizable operations and based on hardware limitations of a controller configured to control the quantum device; and executing the selected set of parallelizable protocols in parallel.

2. The method as claimed in claim 1, wherein the plurality of protocols comprises calibration protocols, characterisation protocols, and / or tune-up protocols.

3. The method as claimed in claim 1 or 2, wherein identifying the operations for which a parallel control sequence is available comprises at least one of: querying a database storing information identifying parallelizable operations, and analysing an operation based on operation parameters such as operation type, a unitary transformation implemented by the operation or coordinates of the quantum elements on which the operations are performed.

4. The method as claimed in any one of the preceding claims, wherein the plurality of protocols defines a plurality of nodes of a dependency graph, the dependency graph defining dependencies between the interdependent protocols, and wherein the selection of the set of parallelizable protocols is based on the dependencies of the dependency graph, wherein a first node and a second node are not parallelizable if there is a dependency relation between the first node and the second node.

5. The method as claimed in claim 4, wherein the dependency graph comprises one or more nodes with one or multiple optional dependencies.

6. The method as claimed in claim 4 or 5, further comprising updating the dependency graph based on results obtained from the execution of the selected set of parallelizable protocols.

7. The method as claimed in claim 5 and 6, wherein updating the dependency graph based on results obtained from the execution of the selected set of parallelizable protocols comprises: determining, based on the results, that a given quantum element associated with a given node is malfunctioning, and updating a protocol associated with a node with an optional dependency on the given node based on the determined malfunctioning of the given quantum element.

8. The method as claimed in any one of claims 4-7, further comprising optimising execution of the dependency graph and, optionally, re-optimising execution of the dependency graph if the dependency graph has been updated.

9. The method as claimed in any one of the preceding claims, wherein the selection of the set of parallelizable protocols is based on hardware limitations of the quantum device .

10. The method as claimed in any one of the preceding claims, wherein the selection of the set of parallelizable protocols is based on a topology of the quantum device, preferably the selection of the set of parallelizable protocols being based on a distance measure between the quantum elements defined by the respective protocols, preferably the distance measure being one of: spatial distance between the quantum elements, interaction strength between the quantum elements, or level of connectivity between the quantum elements.

11. The method as claimed in any one of the preceding claims, wherein executing the selected set of parallelizable protocols in parallel comprises: determining control signals for the operations defined in the selected set of parallelizable protocols; determining a timing of the control signals such that at least two operations overlap in time; and executing the operations by applying the control signals to the respective quantum elements defined in the selected set of parallelizable protocols.

12. The method as claimed in claim 11 , wherein determining the timing of the control signals comprises aligning the operations such that measurements occur simultaneously.

13. The method as claimed in claim 11 or 12, wherein the determining of the control signals comprises adjusting a control signal based on the selected set of parallelizable protocols.

14. A hybrid computer system comprising a classical computer system and a quantum device, preferably a quantum processing unit, the hybrid computer system being configured to execute a plurality of protocols on a plurality of quantum elements of the quantum device, preferably the plurality of protocols comprising interdependent protocols, the method comprising: at least one processor of the classical computer system receiving or determining the plurality of protocols, each protocol defining at least an operation and one or more quantum elements from the plurality of quantum elements on which the operation is to be performed; the at least one processor identifying parallelizable operations from the operations defined by the plurality of protocols, wherein identifying parallelizable operations comprises identifying operations for which a parallel control sequence is available; the at least one processor selecting a set of parallelizable protocols from the plurality of protocols, based on the identified parallelizable operations and based on hardware limitations of a controller configured to control the quantum device; and the at least one processor causing the quantum device to execute the selected set of parallelizable protocols in parallel.

15. A computer program product comprising software code portions configured for, when executed by a hybrid computer system comprising a classical computer system and a quantum device, preferably a quantum processing unit, executing the method steps according to any one of claims 1-13.

16. A non-transitory computer-readable storage medium storing the computer program product as claimed in claim 15.

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