Word line group dependent read recovery period RAMP-down

Abstract

Methods, systems, and devices for techniques for word line group (WLG) dependent read recovery (RRCV) period ramp down comprise initiating a read recovery process associated with a block of the array of memory cells, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, where the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines. The second group of word lines may comprise an edge group of word lines within the block of the array of memory cells. The first ramp-down voltage may be a ground voltage or a negative voltage, and the second ramp-down voltage may be a voltage greater than the ground voltage.

Description

Micron Ref. No.2023145272-WO 1 WORD LINE GROUP DEPENDENT READ RECOVERY PERIOD RAMP-DOWN CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Patent Application Serial No.19 / 281,408, filed July 25, 2025, entitled “WORD LINE GROUP DEPENDENT READ RECOVERY PERIOD RAMP-DOWN,” and U.S. Provisional Application No.63 / 677,348, filed on July 30, 2024, entitled “WORD LINE GROUP DEPENDENT READ RECOVERY PERIOD RAMP-DOWN.” The contents of both applications are hereby incorporated by reference in their entirety for all purposes. TECHNICAL FIELD

[0002] This disclosure relates to one or more systems for memory, including read recovery techniques for memory devices. BACKGROUND

[0003] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Information (e.g., obsolete information) can also be erased from the memory cells and new information can be stored in the memory cells.

[0004] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in theMicron Ref. No.2023145272-WO 2 absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0006] FIGS.1A and 1B illustrate an example of a host system and a memory system that support techniques for word line group dependent read recovery period ramp-down in accordance with examples as disclosed herein.

[0007] FIG.1C is a block diagram of a memory device in communication with a memory system controller of a memory system, in accordance with examples as disclosed herein.

[0008] FIGS.2A-2C are illustrative schematics of portions of an array of memory calls in a memory device, in accordance with examples as disclosed herein.

[0009] FIG.2D illustrates an example of a memory device including multiple blocks of memory cells in accordance with examples as disclosed herein.

[0010] FIG.3 is a block diagram of an example apparatus for implementing one or more systems and for performing one or more methods described herein, in accordance with examples as disclosed herein.

[0011] FIG.4 is an example timing diagram showing waveforms of signals on select lines and data word lines of a memory device during example operations including read recovery period ramp-down operation of the memory device in accordance with examples as disclosed herein.

[0012] FIG.5 is an example channel potential diagram showing waveforms of channel potential during a read recovery period on select lines and data word lines or word line groups of a memory device during example operations including a read recovery period ramp-down operation of the memory device in accordance with examples as disclosed herein.Micron Ref. No.2023145272-WO 3

[0013] FIG.6 is a graph showing different curves that represent a comparison of latent read disturb during example operations including a read recovery period ramp-down operation of the memory device in accordance with examples as disclosed herein.

[0014] FIG.7 is an example timing diagram showing waveforms of signals on select lines and data word lines of a memory device during example operations including a read recovery period ramp-down operation of the memory device in accordance with examples as disclosed herein.

[0015] FIG.8 is an example channel potential diagram showing waveforms of channel potential during a read recovery period on select lines and data word lines or word line groups of a memory device during example operations including a read recovery period ramp-down operation of the memory device in accordance with examples as disclosed herein.

[0016] FIG.9 is a flow diagram of an example method to perform word line group dependent read recovery period ramp down, in accordance with examples as disclosed herein.

[0017] FIG.10 is an example timing diagram showing waveforms of signals on select lines and data word lines of a memory device during alternative example operations including a read recovery period ramp-down operation of the memory device in accordance with examples as disclosed herein.

[0018] FIG.11 is a flow diagram of an example method to perform word line group dependent read recovery period ramp down, in accordance with examples as disclosed herein. DETAILED DESCRIPTION

[0019] A host system may utilize a memory system that includes one or more components (e.g., memory devices that store data). The host system may provide data to be stored at the memory system and may request data to be retrieved from the memory system. Examples of a memory system are described below in connection with FIGS.1A-C. The memory system may include high density non-volatile memory devices where retention of data is desired when power is not being supplied to the memory device. One example of a non-volatile memory device is a NAND memory device. Non-volatile memory devices, such as flash memory devices, are widely used in computers and many electronic items to store information. A non-volatile memory device is a package of one or more dies. Each die may be comprised of one or more planes. For some types of non-volatile memory devices (e.g.,Micron Ref. No.2023145272-WO 4 NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a group of memory cells (“cells”). The cells are electronic circuits that store information. Depending on the cell type, the cell may store one or more bits of binary information, and have various logic states related to the number of bits stored. A logic state may be represented by binary values, such as "0" and "1," or a combination of such values.

[0020] A memory device may include a plurality of bits arranged in a two-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each memory cell. The intersections of the bit lines and word lines constitute the addresses of the memory cells. Hereinafter, a block refers to a cell of a memory device for storing data, and may include a group of memory cells, a group of word lines, a word line, or a single memory cell. One or more blocks may be combined to form planes of the memory device in order to allow concurrent operations to occur on each plane. A memory device may include circuitry that performs concurrent memory page accesses to two or more memory planes. For example, a memory device may include respective access line driver circuitry and power supply circuitry for each plane of the memory device to facilitate concurrent access to pages of two or more memory planes including different page types. A block of memory in a flash memory device may comprise a grid of memory cells connected by word lines and bit lines such that data may be programmed or read from the flash memory device page-by-page. In a single-level cell (SLC) block of flash memory, every word line contains one page. In a multi-level cell (MLC) block of flash memory, every word line contains two pages. In a triple-level cell (TLC) block of flash memory, every word line contains three pages. In a quad-level cell (QLC) of flash memory, every word line contains four pages. In some cases, pages within a word line can be further interleaved such that each word line may contain additional pages. In each case, such a memory device comprises access lines to access the memory cells during a memory operation (e.g., read, write, or erase operation). The memory device also comprises data lines to carry information (e.g., in the form of signals) to be stored in or read from the memory cells.Micron Ref. No.2023145272-WO 5

[0021] A cell (e.g., a NAND cell) of a block can store data in the form of a threshold voltage, which is a lowest voltage at which the cell can be activated (i.e., switched on). During a read operation of a cell (i.e. a “read cell”), a read reference voltage (Vref) can be applied to an associated word line, and a sense amplifier connected to an associated bit line can be used to sense whether the read cell has been switched on. More specifically, if Vref is higher than a threshold voltage (Vt) of the read cell, then the read cell is turned on. It is noted that only one cell per bit line can be read at a time. Since the cells of a bit line are connected in series, all transistors for cells of the bit line that are not being read (“unread cells”) need to be kept on during the read operation for the read output of the read cell to pass-through to the sense amplifier. To achieve this, a pass-through voltage (Vpass) can be applied to the word lines of the unread cells to keep the unread cells on. More specifically, Vpass is a voltage that is chosen to be higher than the Vt’s of the unread cells, but lower than a programming voltage. Although Vpassis a lower voltage than the programming voltage, the application of Vpass can affect (e.g., increase) the Vt’s and thus alter logic states of the unread cells of the block via tunneling currents. This phenomenon is referred to as “read disturb”. As more read operations are applied within the block, the accumulation of read disturb over time can lead to read disturb errors.

[0022] A process can be performed to implement a read recovery (also referred to herein as “RRCV”) period discharge sequence to discharge the residual electrons in a memory cell. In certain memory devices, all word lines can have a same RRCV discharge sequence. For example, the RRCV discharge sequence in a memory cell can go from an initial voltage (e.g., a pass-through reset voltage (Vpass_rst)) after a first time delay, to a ramping or ramp-down voltage (Vramp) (e.g., an internally generated supply voltage (Vint) or a ground voltage (GND)) after a second time delay, and then to float after a third time delay during a RRCV period. When all word lines discharge at the same time, channel potential recovery relies on leakage through the source / drain. This channel potential recovery can be extremely slow for word lines.

[0023] However, since the poly-silicon channel of a charge storage structure in some non-volatile memory devices is a floating channel that may not be connected to a bulk grounded body (e.g., a pillar channel region in three-dimensional (3D) NAND devices), there is generally no path for the residual electrons in the channel region (e.g., electrons trapped or otherwise remaining inside the poly-silicon channel after an earlier read operation) toMicron Ref. No.2023145272-WO 6 discharge other than through towards the source and / or drain of the memory string. Assuming that the word line is ramped to a ramping voltage, Vramp, the channel can become negatively boosted after RRCV when using a typical RRCV discharge sequence. The electrical field between the word lines and the negatively boosted channel caused by the residual electrons can generate what is referred to herein as “latent read disturb”. Similar to read disturb, latent read disturb can result in memory device read errors and other potential memory device issues. Although the electrical field between the word lines may be relatively minimal, it can be present for orders of magnitude longer than a read and can be sustained by another read. Accordingly, latent read disturb can be an issue for memory devices, such as 3D NAND memory devices, due to the floating body effect.

[0024] Further, channel hot-electron (also referred to herein as “hot-e”) injection refers to when electrons break through the gate oxide and change the threshold voltage of the floating gate. This breakthrough occurs when electrons acquire sufficient energy from the high current in the channel and the attracting charge on the control gate. This hot-electron or hot-e effect can impact operations and performance of the memory device.

[0025] Aspects of the present disclosure address the above and other deficiencies by implementing techniques for word line group-dependent read recovery period ramp down. The various techniques may be implemented, for example, by a memory device comprising a array of memory cells and a controller coupled with the array of memory cells, where the controller is configured to perform the various operations.

[0026] In accordance with examples as disclosed herein, word line group-dependent read recovery period ramp down comprises initiating a read recovery process associated with a block of an array of memory cells (also referred to as a memory array), where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, where the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines. The second group of word lines may comprise an edge group of word lines within the block of the array of memory cells. The first ramp-down voltage may be a ground voltage or a negative voltage, and the second ramp-down voltage may be a voltage greater than the ground voltage.Micron Ref. No.2023145272-WO 7

[0027] In some examples, the first group of word lines may be caused to be ramped from the initial voltage to the first ramp-down voltage before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage.

[0028] In some examples, when the first group of word lines comprises a two or more groups of word lines, each of the two or more groups of word lines may be caused to be ramped from the initial voltage to a respective word line group ramp-down voltage before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage, where the second ramp-down voltage is greater than each of the respective word line group ramp-down voltages.

[0029] In some examples, one or more of the respective word line group ramp-down voltages may be a ground voltage or a negative voltage, and the respective word line group ramp-down voltages may comprise different ramp-down voltages.

[0030] In some examples, the two or more groups of word lines may be caused to be ramped from the initial voltage to the respective word line group ramp-down voltages before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage.

[0031] In some examples, the two or more groups of word lines may comprise a center group of word lines within the block of the array of memory cells, and the center group of word lines may be caused to be ramped from the initial voltage to a center word line group ramp-down voltage before other groups of word lines are caused to be ramped from the initial voltage to a respective word line group ramp-down voltage.

[0032] In accordance with additional and / or alternative examples as disclosed herein, word line group-dependent read recovery period ramp down comprises initiating a read recovery process associated with a block of the array of memory cells, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the first group of word lines to be ramped from the initial voltage to a first ramp-down voltage before causing the second group of word lines of the plurality of groups of word lines to be ramped from the initial voltage to a second ramp-down voltage. The second group of word lines may comprise an edge group of word lines within the block of the array of memory cells.Micron Ref. No.2023145272-WO 8

[0033] In some examples, where the first group of word lines may comprise two or more of groups of word lines, each of the two or more of groups of word lines may be caused to be ramped from the initial voltage to a respective word line group ramp-down voltage before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage. The two or more of groups of word lines may comprise a center group of word lines within the block of the array of memory cells.

[0034] In some examples, the center group of word lines may be caused to be ramped from the initial voltage to a center word line group ramp-down voltage before other groups of word lines of the two or more of groups of word lines are caused to be ramped from the initial voltage to a respective word line group ramp-down voltage.

[0035] According to examples as disclosed herein, the word line group-dependent read recovery (RRCV) period ramp down described herein may be implemented with any suitable memory device architecture. In one embodiment, the ramp-down sequences described herein may be implemented within a memory device implementing 3D NAND technology.

[0036] Advantages of the present disclosure include, but are not limited to, reduced latent read disturb effects and read error rates in memory devices (e.g., memory devices that include NAND flash memory), and overall improved memory device performance.

[0037] FIG.1A illustrates an example of a system 100 that supports techniques for word line group dependent read recovery period ramp-down in accordance with examples as disclosed herein. System 100 includes a host system 105 coupled with a memory system 110. System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0038] A memory system 110 may be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, a memory system 110 may be or include a Universal Flash Storage (UFS) device, an embedded Multi-Media Controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dualMicron Ref. No.2023145272-WO 9 in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0039] System 100 may include a host system 105, which may be coupled with memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause host system 105 to perform various operations in accordance with examples as described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. Host system 105 may be implemented by, for example, an apparatus 300 shown in FIG.3. For example, host system 105 may include an application configured for communicating with memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in host system 105), a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., peripheral component interconnect express (PCIe) controller, serial advanced technology attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although one memory system 110 is shown in FIG.1A, the host system 105 may be coupled with any quantity of memory systems 110.

[0040] Host system 105 may be coupled with memory system 110 via at least one physical host interface. Host system 105 and memory system 110 may, in some cases, be configured to communicate via a physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between memory system 110 and host system 105). Examples of a physical host interface may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fiber Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a Graphical Double Data Rate (GDDR) interface, a DIMM interface (e.g., DIMM socket interface that supports DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of host system 105 and a memory system controller 115 of memory system 110. In some examples, host system 105 may be coupled with memory system 110 (e.g., host system controller 106 may beMicron Ref. No.2023145272-WO 10 coupled with memory system controller 115) via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in memory system 110.

[0041] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. A memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices 130-a and 130-b are shown in the example of FIG.1A, memory system 110 may include any quantity of memory devices 130. Further, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0042] Memory system controller 115 may be coupled with and communicate with host system 105 (e.g., via the physical host interface) and may be an example of a controller or control component configured to cause memory system 110 to perform various operations in accordance with examples as described herein. Memory system controller 115 may also be coupled with and communicate with memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at a memory device 130—among other such operations—which may generically be referred to as access operations. In some cases, memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at memory arrays within the one or more memory devices 130). For example, memory system controller 115 may receive commands or operations from host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of memory devices 130. In some cases, memory system controller 115 may exchange data with host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in association with commands from host system 105). For example, memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0043] Memory system controller 115 may be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 may execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations,Micron Ref. No.2023145272-WO 11 encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory devices 130.

[0044] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations ascribed herein to memory system controller 115. Memory system controller 115 may be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0045] Memory system controller 115 may also include a local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by memory system controller 115 to perform functions ascribed herein to memory system controller 115. In some cases, local memory 120 may additionally, or alternatively, include static random access memory (SRAM) or other memory that may be used by memory system controller 115 for internal storage or calculations, for example, related to the functions ascribed herein to memory system controller 115.

[0046] A memory device 130 may include one or more arrays of non-volatile memory cells. For example, a memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magneto RAM (MRAM), NOR (e.g., NOR flash) memory, Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally, or alternatively, a memory device 130 may include one or more arrays of volatile memory cells. For example, a memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.Micron Ref. No.2023145272-WO 12

[0047] In some examples, a memory device 130 may include (e.g., on a same semiconductor die or within a same package) a local controller 135, which may execute operations on one or more memory cells of the respective memory device 130. A local controller 135 may operate in conjunction with a memory system controller 115 or may perform one or more functions ascribed herein to the memory system controller 115. For example, as illustrated in FIG.1A, a memory device 130-a may include a local controller 135-a and a memory device 130-b may include a local controller 135-b. In this disclosure, a memory system controller 115 and a local controller 135 may both be referred to as memory controllers, or a first memory controller and a second memory controller, for simplicity. It is understood that while they may be different controllers, certain operations disclosed herein may be caused or performed by either or both memory controllers, unless otherwise specified.

[0048] In some cases, a memory device 130 may be or include a NAND device (e.g., NAND flash device). A memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, a memory device 130 may be a package that includes one or more dies 160. A die 160 may, in some examples, be a piece of electronics-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a respective set of memory blocks 170, where each block 170 may include a respective set of pages 175, and each page 175 may include a set of memory cells.

[0049] In some cases, a NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single level cells (SLCs). Additionally, or alternatively, a NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi- level cells (MLCs) if configured to each store two bits of information, as tri-level cells (TLCs) if configured to each store three bits of information, as quad-level cells (QLCs) if configured to each store four bits of information, or more generically as multiple-level memory cells. Multiple-level memory cells may provide greater density of storage relative to SLC memory cells but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

[0050] In some cases, planes 165 may refer to groups of memory blocks 170 and, in some cases, concurrent operations may be performed on different planes 165. For example,Micron Ref. No.2023145272-WO 13 concurrent operations may be performed on memory cells within different blocks 170 so long as the different blocks 170 are in different planes 165. In some cases, an individual memory block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d that are within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, the blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes 165).

[0051] In some cases, a block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in a same page 175 may share (e.g., be coupled with) a common word line, and memory cells in a same string may share (e.g., be coupled with) a common digit line (which may alternatively be referred to as a bit line). Example memory cells structures are shown in more detail below using illustrative schematics.

[0052] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at a page level of granularity, or portion thereof) but may be erased at a second level of granularity (e.g., at a block level of granularity). That is, a page 175 may be the smallest unit of memory (e.g., set of memory cells) that may be independently programmed or read (e.g., programed or read concurrently as part of a single program or read operation), and a memory block 170 may be the smallest unit of memory (e.g., set of memory cells) that may be independently erased (e.g., erased concurrently as part of a single erase operation). Further, in some cases, NAND memory cells may be erased before they can be re-written with new data. Thus, for example, a used page 175 may, inMicron Ref. No.2023145272-WO 14 some cases, not be updated until the entire block 170 that includes the page 175 has been erased.

[0053] In some cases, L2P (logical-to-physical) mapping tables may be maintained and data may be marked as valid or invalid at the page level of granularity, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated, which may be due to a more recent or updated version of the data being stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to the invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the most recent version of such data being stored on the memory device 130. A page 175 that includes no data may be a page 175 that has never been written to or that has been erased.

[0054] In some cases, a memory system 110 may utilize a memory system controller 115 to provide a managed memory system that may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0055] System 100 may include any quantity of non-transitory computer readable media that support techniques for logical-to-physical table compression. For example, host system 105 (e.g., a host system controller 106), memory system 110 (e.g., a memory system controller 115), or a memory device 130 (e.g., a local controller 135) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware, logic, code) for performing the functions ascribed herein to the host system 105, the memory system 110, or a memory device 130. For example, such instructions, if executed by the host system 105 (e.g., by a host system controller 106), by the memory system 110 (e.g., by a memory system controller 115), or by a memory device 130 (e.g., by a local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform associated functions as described herein.

[0056] In some cases, a memory system 110 may compress an L2P mapping to expand the quantity of physical addresses mapped by the L2P mapping. For example, if a set of consecutive entries of an uncompressed L2P mapping includes consecutive physical addresses, memory system 110 may compress the consecutive entries into a single entryMicron Ref. No.2023145272-WO 15 which includes a starting physical address of the consecutive physical addresses. Additionally, memory system 110 may include an indication of a starting logical address corresponding to the starting physical address in the compressed entry. To identify a physical address within the compressed entry, memory system 110 may determine an offset between a logical address corresponding to the physical address (e.g., a logical address included in a read command for data stored at the physical address) and the starting physical address using the indication, and may apply the offset to the starting physical address to determine the physical address. Compressing the L2P mapping may allow the L2P mapping to cover an expanded range of physical address space without increasing the size of the L2P mapping.

[0057] FIG.1B illustrates an example of a system diagram 101 that illustrates communication between host system 105 and memory system 110 via using a kernel and firmware, in accordance with examples as disclosed herein. System diagram 101 may include a memory system 110, a kernel 107, and an application 109. The memory system 110 may include a firmware 119. Firmware 119 may be implemented by a controller and / or other circuitry of the memory system (e.g., memory system controller 115 and / or local controllers 135 shown in FIG.1A). In some examples, a system 123 as described herein may include memory system 110 and kernel 107. Additionally, a host system 105 may include kernel 107 and the application 109.

[0058] As described above, memory system 110 may include multiple memory devices, including non-volatile memory devices and volatile memory devices (e.g., local memory 120), configured to store and retrieve data. Firmware 119 may refer to software stored within a memory array within memory system 110 (e.g., a non-volatile memory device within the memory system 110) and / or a local memory 120 as shown in FIG.1A. Firmware 119 may provide low-level control functions for the memory system 110. For example, firmware 119 may function as an interface between the memory system 110 and other components of the system 123, and host system 105 may issue access operations to memory system 110 by interfacing with firmware 119. In some examples, firmware 119 may be or be included within or implemented by a memory system controller 115, as described herein with reference to FIG.1A. In some examples, memory system 110 may store a logical-to-physical mapping that maps logical addresses to physical addresses within a non-volatile memory device (e.g., in a logical-to-physical table). To perform a memory access operation, memory system 110 may move a portion of the logical-to-physical mapping corresponding to one or more logicalMicron Ref. No.2023145272-WO 16 addresses (e.g., indicated by kernel 107) from the non-volatile memory device to a volatile memory device.

[0059] Kernel 107 may function as an interface between host system 105 and components associated with host system 105, such as an operating system of host system 105. Additionally, kernel 107 may perform resource allocation and file management, among other operations, for host system 105. For example, an application 109 running within host system 105 may access information stored within memory system 110 by issuing commands to kernel 107, which may indicate files to be accessed. Kernel 107 may store mapping information associated with the files. For example, a file may be associated with a file name, and may correspond to a range of logical block addresses. Kernel 107 may store mapping information (e.g., a mapping table) that may track logical block addresses corresponding to files of host system 105. In some examples, application 109 may issue an access command to kernel 107 indicating a file name, and offset, and a length associated with a file to be accessed, and kernel 107 may retrieve a one or more logical block addresses corresponding to the file to be accessed. Kernel 107 may then communicate with firmware 119 to indicate the one or more logical block addresses to memory system 110, and memory system 110 may perform an access operation based on the one or more logical block addresses. Memory system 110 may communicate the accessed information to kernel 107 (e.g., via the firmware 119).

[0060] In some examples, kernel 107 may communicate with firmware 119 using information units (e.g., UFS protocol information units (UPIUs)). For example, kernel 107 may issue or receive commands, responses, data, or other information via information units exchanged with the firmware 119. An information unit may refer to a data packet that may contain a header segment and one or more transaction specific fields. In some examples, an information unit may additionally include one or more extended header segments, one or more data segments, or a combination thereof. The header segments of an information unit may indicate information associated with a destination for the information unit, a source of the information unit, a function request, whether additional data or parameters are to be transmitted, whether the additional data or parameters are included within the information unit or to be sent in a following information unit, or any combination thereof. The transaction specific fields may be used for additional fields depending on the operation associated withMicron Ref. No.2023145272-WO 17 the information unit. The data segments may be used to include data to be transferred from a device to another.

[0061] In some examples, a command information unit (e.g., a command UPIU) may be an example of an information unit associated with the transmission of a command (e.g., an SCSI command) and may indicate a device to perform some operation indicated by the command information unit. For example, the command information unit may include a block descriptor (e.g., a command descriptor block) which may indicate information related to the operation indicated by the command information unit. In some examples, kernel 107 may transfer a command information unit to memory system 110 to indicate memory system 110 of an operation to be performed by memory system 110.

[0062] In some examples, to perform an access operation, memory system 110 may load a L2P mapping associated with information to be accessed. For example, memory system 110 may transfer a portion of a logical-to-physical mapping associated with the information to be accessed from a non-volatile memory device of memory system 110 (e.g., NAND memory) to a volatile memory device (e.g., an SRAM) of the memory system 110. In another example, host system 105 may notify memory system 110 of a logical block address range corresponding to an upcoming access operation (e.g., prior to issuing an access command). Memory system 110 may use the logical block address range to load (e.g., pre-load, pre- fetch) an associated portion of a L2P mapping (e.g., from a non-volatile memory device to a volatile memory device) prior to receiving an access command that indicates memory system 110 to perform the access operation. Accordingly, after host system 105 issues the access command, memory system 110 may issue a response to host system 105 faster as memory system 110 has already loaded relevant portions of the L2P mapping associated with the access operation.

[0063] The above description of the system diagram 101 are illustrative examples of communication between host system 105 and memory system 110 by using a kernel 107, application 109, and firmware 119. It is understood that additional ways of communication, including function calls, commands, responses, messages, etc. can be implemented using host system 105 and memory system 110, and / or additional systems or components.

[0064] FIG.1C is a simplified block diagram of a memory device 130 in communication with a memory system controller 115 of a memory system (e.g., the memory system 110 ofMicron Ref. No.2023145272-WO 18 FIGS.1A and 1B), according to an embodiment. As shown in FIG.1C and described below in more detail, memory device 130 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line) while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells (not shown in FIG.1C) of at least a portion of the array of memory cells 104 are capable of being programmed to one of at least two target data states for storing any number of bits of information.

[0065] With continued reference to FIG.1C, row decode circuitry 108 and column decode circuitry 111 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104. Memory device 130 also includes input / output (I / O) control circuitry 112 to manage input of commands, addresses, and data to memory device 130 as well as output of data and status information from memory device 130. An address register 114 is in communication with I / O control circuitry 112 and row decode circuitry 108 and column decode circuitry 111 to latch the address signals prior to decoding. Row decode circuitry 108 and column decode circuitry 111 may simply be referred to as row decoder 108 and column decoder 111, respectively. A command register 124 is in communication with the I / O control circuitry 112 and local controller 135 to latch incoming commands.

[0066] A memory controller (e.g., the local controller 135 internal to memory device 130) controls access to the array of memory cells 104 in response to the commands and generates status information for the external memory system controller 115, i.e., the local controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on the array of memory cells 104. The local controller 135 is in communication with row decode circuitry 108 and column decode circuitry 111 to control the row decode circuitry 108 and column decode circuitry 111 according to the addresses.

[0067] Local controller 135 is also in communication with a cache register 118 and a data register 121. In some embodiments, one or more cache registers 118 can collectively form at least a part of a cache buffer. Cache register 118 latches or buffers data, either incoming orMicron Ref. No.2023145272-WO 19 outgoing, as directed by local controller 135 to temporarily store data while the array of memory cells 104 is busy writing or reading, respectively, other data. During a program operation (e.g., write operation), data can be passed from cache register 118 to the data register 121 for transfer to the array of memory cells 104; then new data can be latched in cache register 118 from the I / O control circuitry 112. During a read operation, data can be passed from the cache register 118 to the I / O control circuitry 112 for output to the memory system controller 115; then new data can be passed from the data register 121 to cache register 118. In some embodiments, cache register 118 and / or the data register 121 can form at least a portion of a page buffer 152 of the memory device 130. The page buffer 152 can further include sensing devices such as a sense amplifier, to sense a data state of a memory cell of the array of memory cells 104, e.g., by sensing a state of a data line connected to that memory cell. A status register 122 can be in communication with I / O control circuitry 112 and the local memory controller 135 to latch the status information for output to memory system controller 115.

[0068] As shown in FIG.1C, memory device 130 receives various control signals via local controller 135 from memory system controller 115 over a control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be further received over control link 132 depending upon the nature of memory device 130. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory system controller 115 over a multiplexed input / output (I / O) bus 134 and outputs data to the memory system controller 115 over I / O bus 134.

[0069] For example, the commands can be received over input / output (I / O) pins [7:0] of I / O bus 134 at I / O control circuitry 112 and can then be written into a command register 124. The addresses can be received over input / output (I / O) pins [7:0] of I / O bus 134 at I / O control circuitry 112 and can then be written into address register 114. The data can be received over input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device at I / O control circuitry 112 and then can be written into cache register 118. The data can be subsequently written into data register 121 for programming the array of memory cells 104.Micron Ref. No.2023145272-WO 20

[0070] In an embodiment, cache register 118 can be omitted, and the data can be written directly into data register 121. Data can also be output over input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference can be made to I / O pins, they can include any conductive node providing for electrical connection to the memory device 130 by an external device (e.g., the memory system controller 115), such as conductive pads or conductive bumps as are commonly used. While the above description using 16 bits I / O bus 134 as an example, it is understood that bus 134 can be configured to any number of bits (e.g., 64 bits).

[0071] It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that memory device 130 of FIG.1C has been simplified. It should be recognized that the functionality of the various block components described with reference to FIG.1C may not necessarily be segregated to distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device could be adapted to perform the functionality of more than one block component of FIG.1C. Alternatively, one or more components or component portions of an integrated circuit device could be combined to perform the functionality of a single block component of FIG.1C. Additionally, while specific I / O pins are described in accordance with popular conventions for receipt and output of the various signals, it is noted that other combinations or numbers of I / O pins (or other I / O node structures) can be used in the various embodiments.

[0072] FIG.2A-2B are example schematics of portions of an array of memory cells 200A, such as a NAND memory array. Array of memory cells 200A may be an example of memory array 104 of a memory device 130 as described with reference to FIG.1C according to an embodiment. Memory array 200A includes access lines, such as word lines 2020to 202N, and data lines, such as bit lines 2040 to 204M. The word lines 202 can be connected to global access lines (e.g., global word lines), not shown in FIG.2A, in a many-to-one relationship. For some embodiments, memory array 200A can be formed over a semiconductor that, for example, can be doped to have a conductive type, such as a p-type conductivity, e.g., to form a p-well, or an n-type conductivity, e.g., to form an n-well.

[0073] Memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string ofMicron Ref. No.2023145272-WO 21 series-connected memory cells (e.g., non-volatile memory cells), such as one of NAND strings 2060 to 206M. Each NAND string 206 can be connected (e.g., selectively connected) to a common source (SRC) 216 and can include memory cells 2080to 208N. The memory cells 208 can represent non-volatile memory cells for storage of data. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field-effect transistor), such as one of the select gates 2100to 210M(e.g., that can be source select transistors, commonly referred to as select gate source), and a select gate 212 (e.g., a field- effect transistor), such as one of the select gates 2120 to 212M (e.g., that can be drain select transistors, commonly referred to as select gate drain). Select gates 2100 to 210M can be commonly connected to a select line 214, such as a source select line (SGS), and select gates 2120 to 212M can be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as traditional field-effect transistors, the select gates 210 and 212 can utilize a structure similar to (e.g., the same as) the memory cells 208. The select gates 210 and 212 can represent a number of select gates connected in series, with each select gate in series configured to receive a same or independent control signal.

[0074] A source of each select gate 210 can be connected to common source 216. The drain of each select gate 210 can be connected to a memory cell 2080of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to memory cell 2080of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. A control gate of each select gate 210 can be connected to select line 214.

[0075] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120can be connected to the bit line 2040for the corresponding NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208N of the corresponding NAND string 206. For example, the source of select gate 2120can be connected to memory cell 208Nof the corresponding NAND string 2060. Therefore, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to the corresponding bit line 204. A control gate of each select gate 212 can be connected to select line 215.

[0076] The memory array 200A in FIG.2A can be a quasi-two-dimensional memory array and can have a generally planar structure, e.g., where the common source 216, NANDMicron Ref. No.2023145272-WO 22 strings 206 and bit lines 204 extend in substantially parallel planes. Alternatively, the memory array 200A in FIG.2A can be a three-dimensional memory array, e.g., where NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and to a plane containing the bit lines 204 that can be substantially parallel to the plane containing the common source 216.

[0077] Typical construction of memory cells 208 includes a data-storage structure 234 (e.g., a floating gate, charge trap, and the like) that can determine a data state of the memory cell (e.g., through changes in threshold voltage), and a control gate 236, as shown in FIG. 2A. The data-storage structure 234 can include both conductive and dielectric structures while the control gate 236 is generally formed of one or more conductive materials. In some cases, memory cells 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. Memory cells 208 have their control gates 236 connected to (and in some cases form) a word line 202.

[0078] A column of the memory cells 208 can be a NAND string 206 or a number of NAND strings 206 selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can, but need not, include all the memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 can often be divided into one or more groups of physical pages of memory cells 208, and physical pages of the memory cells 208 often include every other memory cell 208 commonly connected to a given word line 202. For example, the memory cells 208 commonly connected to word line 202N and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of the memory cells 208 (e.g., even memory cells) while memory cells 208 commonly connected to word line 202Nand selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of the memory cells 208 (e.g., odd memory cells).

[0079] Although bit lines 2043-2045are not explicitly depicted in FIG.2A, it is apparent from the figure that the bit lines 204 of the array of memory cells 200A can be numbered consecutively from bit line 2040 to bit line 204M. Other groupings of memory cells 208 commonly connected to a given word line 202 can also define a physical page of memory cells 208. For certain memory devices, all memory cells commonly connected to a givenMicron Ref. No.2023145272-WO 23 word line can be deemed a physical page of memory cells. The portion of a physical page of memory cells (which, in some embodiments, could still be the entire row) that is read during a single read operation or programmed during a single programming operation (e.g., an upper or lower page of memory cells) can be deemed a logical page of memory cells. A block of memory cells can include those memory cells that are configured to be erased together, such as all memory cells connected to word lines 2020-202N(e.g., all NAND strings 206 sharing common word lines 202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells. A logical page may or may not be the same as a physical page. Although the example of FIG.2A is discussed in conjunction with NAND flash, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0080] FIG.2B is another schematic of a portion of an array of memory cells 200B as could be used in a memory device described with reference to FIG.1B, e.g., as a portion of the array of memory cells 104. Like numbered elements in FIG.2B correspond to the description as provided with respect to FIG.2A. FIG.2B provides additional detail of one example of a three-dimensional NAND memory array structure. Three-dimensional NAND memory array 200B can incorporate vertical structures which can include semiconductor pillars where a portion of a pillar can act as a channel region of the memory cells of NAND strings 206. NAND strings 206 can be each selectively connected to a bit line 2040-204M by a select transistor 212 (e.g., that can be drain select transistors, commonly referred to as select gate drain) and to a common source 216 by a select transistor 210 (e.g., that can be source select transistors, commonly referred to as select gate source). Multiple NAND strings 206 can be selectively connected to the same bit line 204. Subsets of NAND strings 206 can be connected to their respective bit lines 204 by biasing the select lines 2150-215Kto selectively activate particular select transistors 212 each between a NAND string 206 and a bit line 204. The select transistors 210 can be activated by biasing the select line 214. In some embodiments, each sub-block or string of memory cells has a separate select line 214 from other sub-blocks or strings. In some embodiments, a pair of sub-blocks shares a select line 214. Each word line 202 can be connected to multiple rows of memory cells of theMicron Ref. No.2023145272-WO 24 memory array 200B. Rows of memory cells that are commonly connected to each other by a particular word line 202 can collectively be referred to as tiers.

[0081] The three-dimensional NAND memory array 200B may include multiple stacked layers of levels of memory cells and connected using vertical channels such as semiconductor pillars. The number of layers in three-dimensional NAND memory array 200B can be, for example, 32, 48, 64, 96, 112 layers, or any number of layers. In some examples, a group of layers may be collectively referred to as a deck. A deck in a three-dimensional NAND memory array may be processed together for forming a portion of the semiconductor pillar. A memory device having three-dimensional NAND memory arrays can provide more memory cells on a single chip than a memory device formed by two-dimensional NAND arrays; and therefore provide a higher storage capacity. Furthermore, in a memory device having three-dimensional NAND memory arrays, transistors in memory cells are spaced out, and therefore interference and electron leaks can be reduced.

[0082] As described above, memory cells can be grouped into memory blocks. FIG.2C depicts groupings of NAND strings 206 into blocks of memory cells 250, e.g., blocks of memory cells 2500-250L. Blocks of memory cells 250 can be groupings of memory cells 208 that can be erased together in a single erase operation. The group of memory cells that can be erased together is also referred to as an erase block. Each block of memory cells 250 can represent those NAND strings 206 commonly associated with a single select line 215, e.g., select line 2150. The common source 216 for the block of memory cells 2500can be a same source as the source 216 for the block of memory cells 250L. For example, each block of memory cells 2500-250L can be commonly selectively connected to the source 216. Access lines 202 and select lines 214 and 215 of one block of memory cells 250 can have no direct connection to access lines 202 and select lines 214 and 215, respectively, of any other block of memory cells of the blocks of memory cells 2500-250L.

[0083] The bit lines 2040-204Mcan be connected (e.g., selectively connected) to a buffer portion 240, which can be a portion of the page buffer 152 of the memory device 130. The buffer portion 240 can correspond to a memory plane (e.g., the set of blocks of memory cells 2500-250L). The buffer portion 240 can include sense circuits (which can include sense amplifiers) for sensing data values indicated on respective bit lines 204.

[0084] FIG.2D is a block schematic of a portion of an example array of memory cells 260. Array of memory cells 260 can be used as array 104 in a memory device 130 describedMicron Ref. No.2023145272-WO 25 with reference to FIG.1C. The array of memory cells 260 is depicted as having four memory planes 261 (e.g., memory planes 261a-261d). Each of the memory planes 261 can correspond to planes 165 depicted in FIG.1A. Each memory plane 261 can be in communication with a respective buffer portion 240, which can collectively form a page buffer 262. Page buffer 262 may be used to implement page buffer 152 shown in FIG.1C. While four memory planes 261 are depicted, other numbers of memory planes 261 can be commonly in communication with a page buffer 262. Each memory plane 261 is depicted to include L+1 blocks of memory cells 250 (e.g., blocks of memory cells 2500-250L).

[0085] With continued reference to FIGS.1C and 2A-2C, during a true erase operation (during which memory cells are actually being erased), the local controller 135 (e.g., using an erase operation manager 137) can cause a common source voltage line, e.g., the SRC 216 (FIG.2A), to be ramped to an erase voltage (VERA) with an erase pulse while the select gates 2100to 210M(SGS transistors) are turned on. Ramping to this high bias erase voltage, and the subsequent recovery from this voltage ramping, may take a significant amount of time. Concurrently, the erase operation manager 137 can cause the select gates 2120 to 212m (FIG.2A) to be turned off to enable the drains of the select gates 2120to 212mto float, which causes the bit lines 2040to 204Mto also float. Further, the erase operation manager 137 can couple the word lines 202 (FIG.2A) to ground, e.g., zero volts, or retain the word lines 202 at a low voltage. This set of voltage levels at the memory array 200A can create an erase potential that causes the memory cells 2080to 208Nto be erased, e.g., forces electrons to exit through a body of each memory cell and out the floating bit lines 2040 to 204M. In other embodiments, the reverse can be done so the select gates 2100 to 210M are turned off, causing the SRC line 216 to float while the voltage of the bit lines are ramped to Vera while the select gates 2120 to 212M are turned on. As mentioned earlier, in 3D NAND, one of the channel region, pillar, or bit line can also be ramped up in voltage to cause erasure of attached memory cells. Thus, for simplicity herein, reference to "memory line" should be understood to make reference to any of the SRC line or bit lines in 2D NAND or to any of channel, pillar, or bit lines in 3D NAND. In some embodiments, one or more sub-blocks, to include a physical block, of memory cells are erased during the same true erase operation. A block of memory cells can be generally understood to include four or more sub-blocks, wherein each sub-block includes a separate string of memory cells.Micron Ref. No.2023145272-WO 26

[0086] A high-level block diagram of an example apparatus 300 that may be used to implement systems, apparatus, and methods described herein is illustrated in FIG.3. It is understood that various systems, apparatus, and methods described herein may be implemented using analog and / or digital circuitry, or using one or more computers using well-known computer processors, memory systems, storage devices, computer software, and other components. Typically, a computer includes a processor for executing instructions and one or more memory systems for storing instructions and data. A computer may also include, or be coupled to, one or more mass storage devices, such as one or more magnetic disks, internal hard disks and removable disks, magneto-optical disks, optical disks, etc.

[0087] Various systems, apparatus, and methods described herein may be implemented using computers operating in a client-server relationship. Typically, in such a system, the client computers are located remotely from the server computers and interact via a network. The client-server relationship may be defined and controlled by computer programs running on the respective client and server computers. Examples of client computers can include desktop computers, workstations, portable computers, cellular smartphones, tablets, or other types of computing devices.

[0088] Various systems, apparatus, and methods described herein may be implemented using a computer program product tangibly embodied in an information carrier, e.g., in a non- transitory machine-readable storage device, for execution by a programmable processor; and the method processes and steps described herein, including one or more of the steps of at least some of the FIGS.1A-2D and 4-11, may be implemented using one or more computer programs that are executable by such a processor. A computer program is a set of computer program instructions that can be used, directly or indirectly, in a computer to perform a certain activity or bring about a certain result. A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0089] As shown in FIG.3, apparatus 300 may be used to implement a host system (e.g., host system 105 shown in FIG.1A) that includes, is coupled to, or utilizes a memory system (e.g., memory system 110 of FIG.1A). Apparatus 300 can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to host system controller 106 and / or local controller 135 of FIG.1A).Micron Ref. No.2023145272-WO 27

[0090] In some embodiments, apparatus 300 comprises a processor 310 operatively coupled to a data storage device 320 and a main memory device 330. Processor 310 controls the overall operation of apparatus 300 by executing computer program instructions 324 that define such operations. The instructions 324 include instructions to implement functionality of a controller (e.g., host system controller 106 and / or local controller 135 of FIG.1A). The computer program instructions 324 may be stored in data storage device 320, or other computer-readable medium, and loaded into main memory device 330 when execution of the computer program instructions is desired. For example, processor 310 may be used to implement one or more components and systems described herein, such as host system controller 106 and / or local controller 135 (shown in FIG.1A). Thus, the method steps of at least some of FIGS.1A-2D and 4-11 can be defined by the computer program instructions 324 stored in main memory device 330 and / or data storage device 320 and controlled by processor 310 executing the computer program instructions 324. For example, the computer program instructions 324 can be implemented as computer executable code programmed by one skilled in the art to perform an algorithm defined by the method steps discussed herein in connection with at least some of FIGS.1A-2D and 4-11. Accordingly, by executing the computer program instructions, processor 310 executes an algorithm defined by the method steps of these aforementioned figures to perform operations (e.g., read, program, erase, etc.). Apparatus 300 also includes one or more network interfaces 380 for communicating with other devices via a network. Apparatus 300 may also include one or more input / output devices 390 that enable user interaction with apparatus 300 (e.g., display, keyboard, mouse, speakers, buttons, etc.).

[0091] Processor 310 may include both general and special purpose microprocessors and may be the sole processor or one of multiple processors of apparatus 300. Processor 310 may comprise one or more central processing units (CPUs), and one or more graphics processing units (GPUs), which, for example, may work separately from and / or multi-task with one or more CPUs to accelerate processing, e.g., for various image processing applications described herein. Processor 310, data storage device 320, and / or main memory device 330 may include, be supplemented by, or incorporated in, one or more application-specific integrated circuits (ASICs) and / or one or more field programmable gate arrays (FPGAs).

[0092] Data storage device 320 and main memory device 330 each comprise a tangible non-transitory computer readable storage medium. Data storage device 320, and mainMicron Ref. No.2023145272-WO 28 memory device 330, may each include high-speed random access memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), double data rate synchronous dynamic random access memory (DDR RAM), or other random access solid state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices such as internal hard disks and removable disks, magneto-optical disk storage devices, optical disk storage devices, flash memory devices (NAND memory devices, NOR memory devices), semiconductor memory devices, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM), digital versatile disc read-only memory (DVD-ROM) disks, or other non-volatile solid state storage devices. For example, data storage device 320 may be implemented using memory system 110 (FIG.1A) described herein. In some examples, data storage device 320 and main memory device 330 may include one or more memory devices 130 (FIG.1A).

[0093] Input / output devices 390 may include peripherals, such as a printer, scanner, display screen, etc. For example, input / output devices 390 may include a display device such as a cathode ray tube (CRT), plasma or liquid crystal display (LCD) monitor for displaying information to a user, a keyboard, and a pointing device such as a mouse or a trackball by which the user can provide input to apparatus 300.

[0094] Any or all of the functions of the systems and apparatuses discussed herein may be performed by processor 310, and / or incorporated in, an apparatus or a system such as system 100. Further, system 100 and / or apparatus 300 may utilize one or more neural networks or other deep-learning techniques performed by processor 310 or other systems or apparatuses discussed herein.

[0095] One skilled in the art will recognize that an implementation of an actual computer or computer system may have other structures and may contain other components as well, and that FIG.3 is a high-level representation of some of the components of such a computer for illustrative purposes.

[0096] During a read recovery (RRCV) period of a memory device, e.g., a NAND flash memory device, data word lines (word lines or WLs) can be ramped down to a ground voltage (GND) after selector gates (SGs) are ramped down, e.g., to a ground voltage. Negative channel boosting near edge data word lines (also referred to herein as “edge wordMicron Ref. No.2023145272-WO 29 lines”) can result in hot-e issues on edge WLs where electrons break through the gate oxide of a memory cell and change the threshold voltage (Vt) of the floating gate. Particularly, these hot-e issues can degrade a read window budget (RWB) after read cycling. Hot-e issues are sensitive to both selector gate threshold voltage (Vt) and edge word line channel potential and can be mitigated in various ways. For example, one potential mitigation strategy is to set the selector gate threshold voltage higher such that negative boosting under the selector gate becomes larger compared to a scenario with a lower selector gate threshold voltage setting. This results in reducing the potential difference between edge word lines, such that selector gate Vt should be high enough to have some margin with respect to the hot-e issue. In another strategy, the potential difference between edge word lines can be reduced by techniques that change from ramping edge word lines down to a ground voltage (GND) to ramping edge word lines down to a common collector voltage (Vcc).

[0097] With progress in downsizing the feature sizes and increasing the capacity of semiconductor devices, controlling the selector gate threshold voltage can become difficult, and a lower selector gate drain threshold voltage may cause worse RRCV hot-e issues on higher level word lines.

[0098] For a strategy to ramp down data word lines to Vcc, there is a tradeoff between RRCV hot-e improvements and latent read disturb issues. On the positive side, the potential difference between edge word lines is reduced resulting in improved edge word line threshold voltage degradation due to RRCV hot-e, even with lower selector gate threshold voltage placement. In data collected for tri-level cell (TLC) top row word line threshold voltage distribution with different selector gate drain (SGD) threshold voltages, the data resulting from ramping data word lines to a ground voltage (GND) show clear degradation in post-read cycles for lower SGD threshold voltage settings. On the other hand, by ramping down data word lines to Vcc, no clear threshold voltage difference is observed even for lower SGD threshold voltage settings. Less negative boosting for ramp down to Vccmay result in higher word line potential creep up after word lines turn to be floating and cause worse latent read disturb.

[0099] As described herein, by applying a different ramp down bias voltage to edge word lines or edge word lines group (WLGs) than to other word lines or word line groups, the latent read disturb downside effect can be minimized while retaining the RRCV hot-e improvements.Micron Ref. No.2023145272-WO 30

[0100] FIG.4 is an example timing diagram 400 showing waveforms of signals on select lines and data word lines of a memory device during example operations including an RRCV ramp-down operation of the memory device according to some embodiments. Diagram 400 shows proposed RRCV timing for a ramp-down operation of a memory device. The RRCV timing for the ramp-down operation includes RRCV timing for a select gate 420, a group of one or more edge data word lines 440 and a group of one or more data word lines 450. As shown, at the beginning of the RRCV process, the select gate 420, dummy word lines 430, edge data word lines 440 and other data word lines 450 have an initial pass-through voltage, Vpass. In a first time interval / period of the RRCV process, select gate 420 is caused to ramp down from Vpassto the ground voltage (GND). In a second time interval / period, edge data word lines 440 are caused to be ramped down from Vpass to V0 (e.g., a bias voltage > GND) as a countermeasure against the RRCV hot-e issue. This is so because bias coupling up for edge word lines 440 has been observed to be weaker than for other word lines, e.g., data word lines 450, because negative boosting relaxation has been observed to be larger for edge word lines 440. As such, there is less concern for latent read disturb in edge word lines 440. Other (non-edge) word lines 450 are caused to be ramped down from Vpassto GND to minimize the downsides of latent read disturb.

[0101] FIG.5 is an example channel potential diagram 500 showing waveforms of channel potential during RRCV on select lines and data word lines or word line groups of a memory device during example operations including a RRCV ramp-down operation of the memory device in accordance with examples as disclosed herein. In diagram 500, waveforms of channel potential during a RRCV ramp-down operation of the memory device are shown for a select gate 520, dummy word lines 530, a group of one or more edge data word lines 540 and a group of one or more other data word lines 550. As shown, the ramp- down bias voltage for the edge word lines (or edge word line groups) 540 does not necessarily have to be Vcc545A as a countermeasure against the RRCV hot-e issue. For example, the edge word line bias voltage can be a bias voltage higher than Vcc545B for at least some edge word lines 550. But the edge word line bias voltage should be high enough to be a countermeasure against RRCV hot-e and low enough to mitigate latent read disturb for the other word lines (or word line groups), which are ramped down to GND 555.

[0102] FIG.6 is a graph 600 showing different curves that represent a comparison of latent read disturb during example operations including a RRCV ramp-down operation of theMicron Ref. No.2023145272-WO 31 memory device in accordance with examples as disclosed herein. In graph 600, latent read disturb is shown for a 3D TLC NAND Flash Memory (e.g., the Micron Technology, Inc. 232L B58R). Compared to the result from all word lines ramped down to GND 610 (the Process of Record), changing all word lines to ramp down to Vcc620 degrades LRD across all word lines. However, the result from only edge word lines (a group of one or more edge word lines) ramping down to Vcc630 with other word lines ramped down to GND shows worse LRD for the edge word lines but other word lines show better LRD than the result from ramping down all WLs to Vcc 620.

[0103] Thus, it has been observed that latent read disturb and read recovery (RRCV) period ramp-down operations have “x-pillar” dependence, as edge word lines have been observed to have worse RRCV hot-e margin but read margin after latent read disturb also depends on read margin before latent read disturb, which can be optimized not to be worse than non-edge (e.g., center) word lines. Based on this observation, the embodiments herein propose techniques for word line group dependent RRCV ramp down.

[0104] In one example, a controller may be configured to perform operations to initiate a read recovery process associated with a block of the memory array, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage, and where the word line group-dependent ramp-down bias voltage is higher for the second group of word lines (e.g., a group of one or more edge word lines) than for the first group of word lines (e.g., a group of one or more non-edge word lines). For example, the ramp-down bias voltage for a center group of non-edge word lines may be a ground voltage (GND) or a negative bias voltage as a countermeasure for latent read disturb.

[0105] FIG.7 is an example timing diagram 700 showing waveforms of signals on select lines and data word lines of a memory device during example operations including an RRCV ramp-down operation of the memory device in accordance with examples as disclosed herein. Diagram 700 shows RRCV timing for a ramp-down operation of a memory device during read recovery time intervals / periods 702, 704, and 706 for a select gate 720, dummy word lines 730, a group of one or more edge word lines 740 (e.g., word line group “0” in the memory device), a group of one or more non-edge / non-center word lines 750 (e.g., word line group “1” in the memory device), a group of one or more center word lines 760, and one or more other groups of non-edge / non-center word lines 770 (e.g., word line group(s) “n” inMicron Ref. No.2023145272-WO 32 the memory device). As shown, at the beginning of the RRCV process, select gate 720, dummy word lines 730, edge word lines 740, non-edge / non-center word lines 750, center word lines 760, and other non-edge / non-center word lines 770 have an initial pass-through voltage, Vpass. In a first time interval / period 704, select gate 720 is caused to ramp down from Vpass to the ground voltage (GND) 725. In a third time interval / period 706, dummy word lines 730 are caused to ramp down from Vpassto GND 735, and edge data word lines 740 are caused to be ramped down from Vpassto V0745 (e.g., a bias voltage > GND) as a countermeasure against the RRCV hot-e issue. Non-edge / non-center word lines 750, center word lines 760, and other non-edge / non-center word lines 770 are caused to ramp down from Vpassto V1755, Vneg765, and Vn775, respectively, where the edge data word line bias voltage, V0, is greater than each of V1, Vneg, and Vn. As shown in diagram 700, sequential RRCV ramp-down timing may be performed within a time interval, e.g., t_rec_3706, such that the total RRCV time interval, tRead, is minimized.

[0106] FIG.8 is an example channel potential diagram showing waveforms of channel potential during RRCV on select lines and data word lines or word line groups of a memory device during example operations including a RRCV ramp-down operation of the memory device according to some embodiments. In diagram 800, waveforms of channel potential during a RRCV ramp-down operation of the memory device are shown for s a select gate 820, dummy word lines 830, a group of one or more edge word lines 840 (e.g., word line group “0” in the memory device), a group of one or more non-edge / non-center word lines 850 (e.g., word line group “1” in the memory device), a group of one or more center word lines 860, and one or more other groups of non-edge / non-center word lines 870 (e.g., word line group(s) “n” in the memory device). As shown, edge data word lines 840 are caused to be ramped down to V0845 (e.g., a bias voltage > GND) as a countermeasure against the RRCV hot-e issue. Non-edge / non-center word lines 850, center word lines 860, and other non-edge / non-center word lines 870 are caused to ramp down to V1855, GND or a negative bias Vneg865, and Vn875, respectively, where the edge data word line bias voltage, V0, is greater than each of V1, Vneg, and Vn. As discussed above, the ramp-down bias voltage for the edge word lines (or edge word line groups) 840 does not necessarily have to be Vccas a countermeasure against the RRCV hot-e issue. For example, the edge word line bias voltage V0 can be a bias voltage higher than Vcc. But the edge word line bias voltage should be high enough to be a countermeasure against RRCV hot-e and low enough to mitigate latent readMicron Ref. No.2023145272-WO 33 disturb for the other word lines (or word line groups), which are ramped down to GND or to a negative bias.

[0107] FIG.9 is a flow diagram of an example process 900 to perform word line group dependent read recovery period ramp down in accordance with examples as disclosed herein. For example, a memory device may have a memory array and a controller (e.g., local controller 135), coupled with the memory array, where the controller is configured to perform to perform various operations in accordance with examples as described herein. As described above, the memory device, e.g., memory device 130, may include (e.g., on a same semiconductor die or within a same package) a local controller, e.g., local controller 135, which may execute operations on one or more memory cells of the memory device. The local controller may operate in conjunction with a memory system controller, e.g., memory system controller 115, which may both be referred to as memory controllers for simplicity. It is understood that while they may be different controllers, certain operations disclosed herein may be caused or performed by either or both memory controllers, unless otherwise specified.

[0108] In block 910, the controller (e.g., local controller 135 or system controller 115) is configured to perform operations to initiate a read recovery process associated with a block of the memory array, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage. In block 920, the controller is configured to perform operations to cause the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, where the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines. For example, the first ramp-down voltage may be a ground voltage or a negative voltage, and the second ramp- down voltage may be a voltage greater than the ground voltage. The second group of word lines may comprise an edge group of word lines within the block of the memory array. Further, in some embodiments, the controller may be further configured to perform operations to cause the first group of word lines to be ramped from the initial voltage to the first ramp-down voltage in a first time period, e.g., time period_1, before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage in a second time period, e.g., time period_2.Micron Ref. No.2023145272-WO 34

[0109] In some embodiments, when the first group of word lines comprises a two or more groups of word lines, the controller may be further configured to perform operations to cause each of the two or more groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage in a respective time interval / period (e.g., time period_1, time period_2,… time period_N) before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage, e.g., in a time period_N+1, where the second ramp-down voltage is greater than each of the respective word line group ramp-down voltages. In some embodiments, one or more of the respective word line group ramp-down voltages may be a ground voltage (GND) or a negative voltage, and the respective word line group ramp-down voltages may comprise different ramp-down voltages. For example, when the first group of word lines comprises three groups of word lines, the word line groups may have ramp-down voltages of V1, V2, and V3 respectively, where V1 is not equal to V2 or V3, and V2 is not equal to V3. In some embodiments, the controller may be further configured to cause the two or more groups of word lines to be ramped from the initial voltage to the respective word line group ramp-down voltages in respective time periods, e.g., time period_1, time period_2, …time period_N, before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage, e.g., in time period_N+1. In some embodiments, the two or more groups of word lines may comprise a center group of word lines within the block of the memory array, and the controller may be further configured to cause the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage in an initial time period, e.g., time period_1, before other groups of word lines are caused to be ramped from the initial voltage to a respective word line group ramp-down voltage in respective time periods, e.g., time period_2,…time period_N.

[0110] In an alternative example, the controller may be configured to perform operations to initiate a read recovery process associated with a block of the memory array, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage, and where RRCV ramp-down timing is used to mitigate RRCV hot-e issues and latent read disturb degradation without employing particular ramp-down voltages. For example, the controller may be configured to cause the first (non-edge / center) group of word lines to be ramped first from the initial voltage to a first ramp-down voltage before causing the second (edge) group of word lines to be ramped from the initial voltage toMicron Ref. No.2023145272-WO 35 a second ramp-down voltage. In an embodiment with multiple word line groups, the controller may be configured to cause the word line groups to ramp down sequentially, e.g., from a center word line group to an edge word line group.

[0111] FIG.10 is an example timing diagram showing waveforms of signals on select lines and data word lines of a memory device during alternative example operations including an RRCV ramp-down operation of the memory device in accordance with examples as disclosed herein. Diagram 1000 shows RRCV timing for a ramp-down operation of a memory device during read recovery time intervals / periods 1002, 1004, and 1006 for a select gate 1020, dummy word lines 1030, a group of one or more edge word lines 1040 (e.g., word line group “WLG0” in the memory device), a group of one or more non-edge / non-center word lines 1050 (e.g., word line group “1” in the memory device), a group of one or more center word lines 1060, and one or more other groups of non-edge / non-center word lines 1070 (e.g., word line group “WLG6” in the memory device). Another group of one or more edge word lines 1080 (e.g., word line group “WLGn” in a different location in the memory device from “WLG0” 1040 above) is also shown. As shown, at the beginning of the RRCV process, the select gate 1020, dummy word lines 1030, edge word lines 1040 and 1080, non- edge / non-center word lines 1050, center word lines 1060, and other non-edge / non-center word lines 1070 have an initial pass-through voltage, Vpass. In a first RRCV time interval / period 1002, select gate 1020 is caused to ramp down, e.g., from Vpassto the ground voltage (GND) 1025. A sequential ramp-down sequence is executed in the third time RRCV interval / period 1006. For example, center word lines 1060 and dummy word lines 1030 are caused to ramp down to a bias voltage, e.g., from Vpass to V11065 and GND 1035, before non-edge / non-center word lines 1050 and 1070 are caused to ramp down, e.g., from Vpassto V21055 and 1075. Subsequently, edge data word lines 1040 and 1080 are caused to be ramped down, e.g., from Vpass to V31045 and 1085. As shown in diagram 1000, sequential RRCV ramp-down timing may be performed within a time interval, e.g., t_rec_31006, such that the total RRCV time interval, tRead, is minimized. In some embodiments, where the first group of word lines may comprise two or more of groups of word lines, each of the two or more of groups of word lines may be caused to be ramped from the initial voltage to a respective word line group ramp-down voltage in a respective time interval / period (e.g., time period_1, time period_2,… time period_N) before the second group of word lines is caused to be ramped from the initial voltage to the second ramp-down voltage in a time period_N+1.Micron Ref. No.2023145272-WO 36 Further, the two or more of groups of word lines may comprise a center group of word lines within the block of the memory array. In some embodiments, the center group of word lines may be caused to be ramped from the initial voltage to a center word line group ramp-down voltage in a first time period, e.g., time period_1) before other groups of word lines of the two or more of groups of word lines are caused to be ramped from the initial voltage to a respective word line group ramp-down voltage in respective time periods, e.g., time period_2 to time period_N.

[0112] FIG.11 is a flow diagram of an example process 1100 to perform word line group dependent read recovery period ramp down in accordance with examples as disclosed herein. For example, a memory device may have a memory array and controller (e.g., one or more memory controllers), coupled with the memory array, where the controller is configured to perform to perform various operations in accordance with examples as described herein. As described above, the memory device, e.g., memory device 130, may include (e.g., on a same semiconductor die or within a same package) a local controller, e.g., local controller 135, which may execute operations on one or more memory cells of the memory device. The local controller may operate in conjunction with a memory system controller, e.g., memory system controller 115, which may both be referred to as memory controllers for simplicity. It is understood that while they may be different controllers, certain operations disclosed herein may be caused or performed by either or both memory controllers, unless otherwise specified.

[0113] In block 1110, the controller is configured to perform operations to initiate a read recovery process associated with a block of the memory array, where the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage. For example, each of the first group of word lines and the second group of word lines may comprise at least one word line. In block 1120, the controller is configured to perform operations to cause the first group of word lines to be ramped from the initial voltage to a first ramp-down voltage before causing the second group of word lines of the plurality of groups of word lines to be ramped from the initial voltage to a second ramp-down voltage. For example, the second group of word lines may comprise an edge group of word lines within the block of the memory array. Further, the two or more of groups of word lines may comprise a center group of word lines within the block of the memory array. In some embodiments, the center group of word lines may be caused to be ramped from the initialMicron Ref. No.2023145272-WO 37 voltage to a center word line group ramp-down voltage in a first time period, e.g., time period_1) before other groups of word lines of the two or more of groups of word lines are caused to be ramped from the initial voltage to a respective word line group ramp-down voltage in respective time periods, e.g., time period_2 to time period_N.

[0114] Additional embodiments are described below.

[0115] (1) A memory device, comprising: an array of memory cells; and a controller, coupled with the array of memory cells, the controller configured to perform operations to: initiate a read recovery process associated with a block of the array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and cause the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, wherein the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines.

[0116] (2) The memory device of (1), wherein the first ramp-down voltage is a ground voltage.

[0117] (3) The memory device of (2), wherein the second ramp-down voltage is a voltage greater than the ground voltage.

[0118] (4) The memory device of any of (1)-(3), wherein the first ramp-down voltage is a negative voltage.

[0119] (5) The memory device of any of (1)-(4), wherein the controller is further configured to perform operations to cause the first group of word lines to be ramped from the initial voltage to the first ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0120] (6) The memory device of any of (1)-(5), wherein when the first group of word lines comprises two or more groups of word lines, the controller is further configured to performMicron Ref. No.2023145272-WO 38 operations to cause each of the two or more groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage, wherein the second ramp-down voltage is greater than each of the respective word line group ramp-down voltages.

[0121] (7) The memory device of (6), wherein one or more of the respective word line group ramp-down voltages is a ground voltage.

[0122] (8) The memory device of any of (6)-(7), wherein one or more of the respective word line group ramp-down voltages is a negative voltage.

[0123] (9) The memory device of any of (6)-(8), wherein the respective word line group ramp-down voltages comprise different ramp-down voltages.

[0124] (10) The memory device of any of (6)-(9), wherein the controller is further configured to perform operations to cause the two or more groups of word lines to be ramped from the initial voltage to the respective word line group ramp-down voltages before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0125] (11) The memory device of (10), wherein the two or more groups of word lines comprise a center group of word lines within the block of the array of memory cells.

[0126] (12) The memory device of (11), wherein the controller is further configured to perform operations to cause the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

[0127] (13) The memory device of any of (1)-(12), wherein the second group of word lines comprises an edge group of word lines within the block of the memory array.Micron Ref. No.2023145272-WO 39

[0128] (14) The memory device of any of (1)-(13), wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

[0129] (15) A method comprising: initiating a read recovery process associated with a block of an array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, wherein the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines.

[0130] (16) The method of (15), wherein the first ramp-down voltage is a ground voltage.

[0131] (17) The method of (16), wherein the second ramp-down voltage is a voltage greater than the ground voltage.

[0132] (18) The method of any of (15)-(17), wherein the first ramp-down voltage is a negative voltage.

[0133] (19) The method of any of (15)-(18), further comprising: causing the first group of word lines to be ramped from the initial voltage to the first ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0134] (20) The method of any of (15)-(19), wherein when the first group of word lines comprises a two or more groups of word lines, further comprising: causing each of the two or more groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage, wherein the second ramp-down voltage is greater than each of the respective word line group ramp- down voltages.Micron Ref. No.2023145272-WO 40

[0135] (21) The method of (20), wherein one or more of the respective word line group ramp-down voltages is a ground voltage.

[0136] (22) The method of any of (20)-(21), wherein one or more of the respective word line group ramp-down voltages is a negative voltage.

[0137] (23) The method of any of (20)-(22), wherein the respective word line group ramp- down voltages comprise different ramp-down voltages.

[0138] (24) The method of any of (20)-(23), further comprising: causing the two or more groups of word lines to be ramped from the initial voltage to the respective word line group ramp-down voltages before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0139] (25) The method of (24), wherein the two or more groups of word lines comprise a center group of word lines within the block of the array of memory cells.

[0140] (26) The method of (25), further comprising: causing the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

[0141] (27) The method of any of (15)-(26), wherein the second group of word lines comprises an edge group of word lines within the block of the memory array.

[0142] (28) The method of any of (15)-(27), wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

[0143] (29) A non-transitory computer-readable medium having computer instructions stored thereon, which, when executed by a controller of a memory device comprising an array of memory cells, cause the memory device to:Micron Ref. No.2023145272-WO 41 initiate a read recovery process associated with a block of the array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and cause the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, wherein the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines.

[0144] (30) The non-transitory computer-readable medium of (29), wherein the memory device is further caused to ramp the first group of word lines from the initial voltage to the first ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0145] (31) A memory device, comprising: an array of memory cells; and a controller, coupled with the array of memory cells, the controller configured to perform operations to: initiate a read recovery process associated with a block of the memory array, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and cause the first group of word lines to be ramped from the initial voltage to a first ramp-down voltage before causing the second group of word lines of the plurality of groups of word lines to be ramped from the initial voltage to a second ramp-down voltage.

[0146] (32) The memory device of (31), wherein when the first group of word lines comprises a two or more of groups of word lines, the controller is further configured to perform operations to cause each of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0147] (33) The memory device of (32), wherein the two or more of groups of word lines comprise a center group of word lines within the block of the memory array.Micron Ref. No.2023145272-WO 42

[0148] (34) The memory device of (33), wherein the controller is further configured to perform operations to cause the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

[0149] (35) The memory device of any of (31)-(34), wherein the second group of word lines comprises an edge group of word lines within the block of the memory array.

[0150] (36) The memory device of any of (31)-(35), wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

[0151] (37) A method comprising: initiating a read recovery process associated with a block of an array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the first group of word lines to be ramped from the initial voltage to a first ramp-down voltage before causing the second group of word lines of the plurality of groups of word lines to be ramped from the initial voltage to a second ramp-down voltage.

[0152] (38) The method of (37), wherein when the first group of word lines comprises a two or more of groups of word lines, further comprising: causing each of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

[0153] (39) The method of (38), wherein the two or more of groups of word lines comprise a center group of word lines within the block of the memory array.

[0154] (40) The method of (39), further comprising: causing the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines of the two or moreMicron Ref. No.2023145272-WO 43 of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

[0155] (41) The method of any of (37)-(40), wherein the second group of word lines comprises an edge group of word lines within the block of the array of memory cells.

[0156] (42) The method of any of (37)-(41), wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

[0157] It should be noted that the described techniques include possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

[0158] Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols of signaling that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0159] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for aMicron Ref. No.2023145272-WO 44 time, for example, using one or more intermediate components such as switches or transistors.

[0160] The term “coupling” (e.g., “electrically coupling”) may refer to a condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

[0161] The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other if the switch is open. If a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

[0162] The terms “if,” “when,” “based on,” or “based at least in part on” may be used interchangeably. In some examples, if the terms “if,” “when,” “based on,” or “based at least in part on” are used to describe a conditional action, a conditional process, or connection between portions of a process, the terms may be interchangeable.

[0163] The term “in response to” may refer to one condition or action occurring at least partially, if not fully, as a result of a previous condition or action. For example, a first condition or action may be performed and second condition or action may at least partially occur as a result of the previous condition or action occurring (whether directly after or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0164] The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such asMicron Ref. No.2023145272-WO 45 silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

[0165] A switching component or a transistor discussed herein may represent a field- effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may comprise a heavily- doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” if a voltage greater than or equal to the transistor’s threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” if a voltage less than the transistor’s threshold voltage is applied to the transistor gate.

[0166] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to provide an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0167] In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a hyphen and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the descriptionMicron Ref. No.2023145272-WO 46 is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0168] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor (e.g., processor 310 of FIG.3), the functions may be stored on or transmitted over, as one or more instructions or code, a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, the described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0169] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0170] The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

Micron Ref. No.2023145272-WO 47 CLAIMS What is claimed is:

1. A memory device, comprising: an array of memory cells; and a controller, coupled with the array of memory cells, the controller configured to perform operations to: initiate a read recovery process associated with a block of the array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and cause the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, wherein the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines.

2. The memory device of claim 1, wherein the first ramp-down voltage is a ground voltage.

3. The memory device of claim 2, wherein the second ramp-down voltage is a voltage greater than the ground voltage.

4. The memory device of any of claims 1-3, wherein the first ramp-down voltage is a negative voltage.

5. The memory device of any of claims 1-3, wherein the controller is further configured to perform operations to cause the first group of word lines to be ramped from the initial voltage to the first ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

6. The memory device of any of claims 1-3, wherein when the first group of word lines comprises two or more groups of word lines, the controller is further configured to perform operations to cause each of the two or more groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the secondMicron Ref. No.2023145272-WO 48 group of word lines to be ramped from the initial voltage to the second ramp-down voltage, wherein the second ramp-down voltage is greater than each of the respective word line group ramp-down voltages.

7. The memory device of claim 6, wherein one or more of the respective word line group ramp-down voltages is a ground voltage.

8. The memory device of claim 6, wherein one or more of the respective word line group ramp-down voltages is a negative voltage.

9. The memory device of claim 6, wherein the respective word line group ramp-down voltages comprise different ramp-down voltages.

10. The memory device of claim 6, wherein the controller is further configured to perform operations to cause the two or more groups of word lines to be ramped from the initial voltage to the respective word line group ramp-down voltages before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

11. The memory device of claim 10, wherein the two or more groups of word lines comprise a center group of word lines within the block of the array of memory cells.

12. The memory device of claim 11, wherein the controller is further configured to perform operations to cause the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

13. The memory device of any of claims 1-3, wherein the second group of word lines comprises an edge group of word lines within the block of the memory array.

14. The memory device of any of claims 1-3, wherein each of the first group of word lines and the second group of word lines comprises at least one word line.Micron Ref. No.2023145272-WO 49 15. A method comprising: initiating a read recovery process associated with a block of an array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, wherein the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines.

16. The method of claim 15, wherein the first ramp-down voltage is a ground voltage.

17. The method of claim 16, wherein the second ramp-down voltage is a voltage greater than the ground voltage.

18. The method of any of claims 15-17, wherein the first ramp-down voltage is a negative voltage.

19. The method of any of claims 15-17, further comprising: causing the first group of word lines to be ramped from the initial voltage to the first ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

20. The method of any of claims 15-17, wherein when the first group of word lines comprises a two or more groups of word lines, further comprising: causing each of the two or more groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage, wherein the second ramp-down voltage is greater than each of the respective word line group ramp- down voltages.

21. The method of claim 20, wherein one or more of the respective word line group ramp- down voltages is a ground voltage.Micron Ref. No.2023145272-WO 50 22. The method of claim 20, wherein one or more of the respective word line group ramp- down voltages is a negative voltage.

23. The method of claim 20, wherein the respective word line group ramp-down voltages comprise different ramp-down voltages.

24. The method of claim 20, further comprising: causing the two or more groups of word lines to be ramped from the initial voltage to the respective word line group ramp-down voltages before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

25. The method of claim 24, wherein the two or more groups of word lines comprise a center group of word lines within the block of the array of memory cells.

26. The method of claim 25, further comprising: causing the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

27. The method of claim 15, wherein the second group of word lines comprises an edge group of word lines within the block of the memory array.

28. The method of claim 15, wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

29. A non-transitory computer-readable medium having computer instructions stored thereon, which, when executed by a controller of a memory device comprising an array of memory cells, cause the memory device to: initiate a read recovery process associated with a block of the array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; andMicron Ref. No.2023145272-WO 51 cause the second group of word lines to be ramped from the initial voltage to a second ramp-down voltage, wherein the second ramp-down voltage is greater than a first ramp-down voltage for the first group of word lines.

30. The non-transitory computer-readable medium of claim 29, wherein the memory device is further caused to ramp the first group of word lines from the initial voltage to the first ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

31. A memory device, comprising: an array of memory cells; and a controller, coupled with the array of memory cells, the controller configured to perform operations to: initiate a read recovery process associated with a block of the memory array, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and cause the first group of word lines to be ramped from the initial voltage to a first ramp-down voltage before causing the second group of word lines of the plurality of groups of word lines to be ramped from the initial voltage to a second ramp-down voltage.

32. The memory device of claim 31, wherein when the first group of word lines comprises a two or more of groups of word lines, the controller is further configured to perform operations to cause each of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

33. The memory device of claim 32, wherein the two or more of groups of word lines comprise a center group of word lines within the block of the memory array.

34. The memory device of claim 33, wherein the controller is further configured to perform operations to cause the center group of word lines to be ramped from the initialMicron Ref. No.2023145272-WO 52 voltage to a center word line group ramp-down voltage before causing other groups of word lines of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.

35. The memory device of any of claims 31-34, wherein the second group of word lines comprises an edge group of word lines within the block of the memory array.

36. The memory device of any of claims 31-34, wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

37. A method comprising: initiating a read recovery process associated with a block of an array of memory cells, wherein the block comprises a first group of word lines at an initial voltage and a second group of word lines at the initial voltage; and causing the first group of word lines to be ramped from the initial voltage to a first ramp- down voltage before causing the second group of word lines of the plurality of groups of word lines to be ramped from the initial voltage to a second ramp-down voltage.

38. The method of claim 37, wherein when the first group of word lines comprises a two or more of groups of word lines, further comprising: causing each of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage before causing the second group of word lines to be ramped from the initial voltage to the second ramp-down voltage.

39. The method of claim 38, wherein the two or more of groups of word lines comprise a center group of word lines within the block of the memory array.

40. The method of claim 39, further comprising: causing the center group of word lines to be ramped from the initial voltage to a center word line group ramp-down voltage before causing other groups of word lines of the two or more of groups of word lines to be ramped from the initial voltage to a respective word line group ramp-down voltage.Micron Ref. No.2023145272-WO 53 41. The method of any of claims 37-40, wherein the second group of word lines comprises an edge group of word lines within the block of the array of memory cells.

42. The method of any of claims 37-40, wherein each of the first group of word lines and the second group of word lines comprises at least one word line.

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