Half-duplex data communication system

Abstract

A half-duplex data communication system, comprising a first communication device and a second communication device, wherein the first communication device is connected to the second communication device by means of a communication link. The first communication device sends a first signal to the second communication device; the second communication device sends a second signal to the first communication device; the first signal comprises a synchronization frame; the second communication device recovers a data frame synchronization signal on the basis of the received synchronization frame; the second communication device communicates with a peripheral device on the basis of the data frame synchronization signal; a local clock generation module in the second communication device generates a local clock of the second communication device; the clock for sending the second signal by the second communication device is the local clock of the second communication device; and the first signal and the second signal are transmitted on the communication link in a time-division manner.

Description

A half-duplex data communication system TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a half-duplex data communication system. BACKGROUND

[0002] In a vehicle audio transmission system, in order to simplify the wiring harness design, a chain topology structure is often used to connect each communication device (node), and the transmission link can include multiple communication devices, for example, a first communication device is connected to a second communication device, and the second communication device is connected to a third communication device, and each communication device is connected to its own processor / microphone / power amplifier and other external devices / modules.

[0003] When the first communication device has data to send to the third communication device, it can first send it to the second communication device, which in turn sends it to the third communication device. The second communication device can also receive data from the external devices connected to it and send it to the third communication device.

[0004] In order to save wire material, there is often no clock line dedicated to transmitting clock signals in a vehicle audio transmission system. Currently, vehicle audio transmission systems often use time-division transmission to transmit audio data, transmitting one or more audio sampling points per time slice. The system may have intermittent data transmission between time slices, that is, the clock recovery circuit cannot rely on continuous data transmission, and cannot use methods similar to PCIe, USB 3.0, etc. to recover the clock.

[0005] In a vehicle audio transmission system that sequentially includes multiple communication devices such as a first communication device, a second communication device, and a third communication device on a transmission link, a method used for clock recovery and data transmission is as follows: the first communication device sends data to the second communication device, the second communication device performs clock and data recovery based on the received data, and sends the recovered clock as a transmission clock to the third communication device. After receiving the data, the third communication device also performs clock and data recovery based on the received data, and sends the recovered clock as a transmission clock.

[0006] With this method, the clock generated after clock recovery has a certain jitter compared to the source clock, and the clock of the next stage communication device on the transmission link has greater clock jitter than the clock of the previous stage communication device, resulting in greater phase noise. When the number of communication devices on the transmission link is large, the clock phase noise of the last stage communication device is large, making it difficult to correctly sample the data, resulting in a high bit error rate.

[0007] In a vehicle audio transmission system containing a plurality of communication devices in sequence on a transmission link, the second method for clock recovery and data transmission is that the first communication device sends data to the second communication device, the second communication device recovers clock and data based on the received data, and the second communication device generates a transmission clock by using a local clock generation circuit to send data to the third communication device, and the transmission clock is independent of the data received by the second communication device from the first communication device.

[0008] With this method, the clock phase noise of the subsequent communication device does not increase with the number of communication devices, and the bit error rate is low. However, for an audio system, the sampling signal of the audio data also needs to be transmitted, which contains the sampling frequency and phase.

[0009] Currently, there is a lack of a transmission system and method in which the clock phase noise does not increase with the number of communication devices, the bit error rate is low, and the sampling frequency and phase of the data can be transmitted. SUMMARY

[0010] The technical problem to be solved by the present application is how to make the clock phase noise not increase with the number of communication devices in the transmission system, and the system can transmit audio data of multiple sampling frequencies.

[0011] To solve the above technical problems, the technical scheme adopted by the present application is:

[0012] As a communication device of the present application, it comprises an upstream device interface module, a data frame synchronization signal recovery module, a local clock generation module, and a peripheral interface module. The upstream device interface module is connected to the upstream device through an uplink. The upstream device sends a first signal, and the upstream device interface module receives the first signal from the upstream device through the uplink. The upstream device interface module sends a second signal to the upstream device through the uplink. The first signal contains a synchronization frame, and the upstream device interface module receives the synchronization frame. The data frame synchronization signal recovery module is connected to the upstream device interface module. The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the received synchronization frame. The local clock generation module generates a first local clock. The clock of the second signal sent by the upstream device interface module is the first local clock. The first signal and the second signal are transmitted in time on the uplink.

[0013] Preferably, the slave communication device further comprises a downstream device interface module, the downstream device interface module is connected with a downstream device through a downlink, the downstream device interface module sends a third signal to the downstream device through the downlink, the downstream device interface module receives a fourth signal from the downstream device through the downlink, the slave communication device sends the received synchronization frame to the downstream device through the downlink in the third signal, the local clock generation module further generates a second local clock, the clock of the downstream device interface module sending the third signal is the second local clock, the third signal and the fourth signal are transmitted on the downlink in time division mode.

[0014] Preferably, the peripheral interface module is connected with an external device, the peripheral interface module communicates with the external device based on the data frame synchronization signal, including: the peripheral interface module sends data to the external device, or receives data from the external device, or sends data to the external device and receives data from the external device based on the data frame synchronization signal; it can also include: the peripheral interface module sends the data frame synchronization signal to the external device.

[0015] Preferably, the slave communication device is an integrated circuit chip, the local clock generation module generates the first local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

[0016] Preferably, the slave communication device is an integrated circuit chip, the local clock generation module generates the first local clock and the second local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

[0017] Preferably, the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the timing signal of the received synchronization frame.

[0018] Further, the synchronization frame comprises a sequence number field, the sequence number field comprises a sequence number of the synchronization frame, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the sequence number field and the timing signal of the received synchronization frame.

[0019] Preferably, the synchronization frame comprises a phase field, the phase field comprises phase relationship information between the synchronization frame and the data frame synchronization signal, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field.

[0020] Preferably, the synchronization frame comprises a phase field and a count field, the phase field comprises phase relationship information between the synchronization frame and the data frame synchronization signal, and the count field comprises a count value of the data frame synchronization signal, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field and the count field.

[0021] Further, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

[0022] Preferably, the first signal further comprises a first data frame, the first data frame is received from the communication device, and part or all of the data contained in the first data frame is transmitted to the external device.

[0023] Preferably, the first signal further comprises a first data frame, the third signal comprises a third data frame, the first data frame is received from the communication device, and part or all of the data contained in the first data frame is transmitted to the downstream device in the third data frame.

[0024] Preferably, the peripheral interface module is connected to the external device, the third signal comprises a third data frame, data is received from the external device by the communication device, and part or all of the data is transmitted to the downstream device in the third data frame.

[0025] Preferably, the peripheral interface module is connected to the external device, the first signal further comprises a first data frame, the third signal comprises a third data frame, the first data frame is received from the communication device, and data is received from the external device by the communication device, part or all of the data contained in the first data frame and part or all of the data received from the external device by the communication device are transmitted to the downstream device in the third data frame.

[0026] Preferably, the peripheral interface module is connected to the external device, the fourth signal comprises a fourth data frame, the fourth data frame is received from the communication device, and part or all of the data contained in the fourth data frame is transmitted to the external device.

[0027] Preferably, the second signal comprises a second data frame, the fourth signal comprises a fourth data frame, the fourth data frame is received from the communication device, and part or all of the data contained in the fourth data frame is transmitted to the upstream device in the second data frame.

[0028] Preferably, the second signal comprises a second data frame, data is received from the external device by the communication device, and part or all of the data is transmitted to the upstream device in the second data frame.

[0029] Preferably, the peripheral interface module is connected to the external device, the second signal comprises a second data frame, the fourth signal comprises a fourth data frame, the fourth data frame is received from the communication device, and data is received from the external device by the communication device, part or all of the data contained in the fourth data frame and part or all of the data received from the external device by the communication device are transmitted to the upstream device in the second data frame.

[0030] Preferably, the second signal comprises a synchronization response frame, and the upstream device interface module sends the synchronization response frame to the upstream device within a preset time after receiving the synchronization frame.

[0031] Further, the upstream device interface module sends the synchronization response frame to the upstream device at a time earlier than any other data sent to the upstream device after receiving the synchronization frame.

[0032] Preferably, the fourth signal comprises a synchronization response frame, and the communication device judges the status of the downlink according to whether the synchronization response frame comprised in the fourth signal is received within a preset time after sending the synchronization frame comprised in the third signal.

[0033] As a master communication device of the present application, it comprises a host interface module, a downstream device interface module, and a local clock generation module, the host interface module is connected to a host, the host interface module receives a data frame synchronization signal from the host, the downstream device interface module is connected to a downstream device through a downlink, the downstream device interface module sends a first signal to the downstream device through the downlink, the downstream device sends a second signal, the downstream device interface module receives the second signal from the downstream device through the downlink, the first signal comprises a synchronization frame, the downstream device interface module sends the synchronization frame, the synchronization frame comprises data frame synchronization signal information, the downstream device can recover the data frame synchronization signal according to the synchronization frame, the local clock generation module generates a local clock, the clock of the downstream device interface module sending the first signal is the local clock, and the first signal and the second signal are transmitted in time division on the downlink.

[0034] Preferably, the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers.

[0035] Further, the synchronization frame comprises a sequence number field, and the sequence number field comprises the sequence number of the synchronization frame.

[0036] Preferably, the synchronization frame comprises a phase field, and the phase field comprises the phase relationship information of the synchronization frame and the data frame synchronization signal.

[0037] Preferably, the synchronization frame comprises a phase field and a count field, the phase field comprises the phase relationship information of the synchronization frame and the data frame synchronization signal, and the count field comprises the count value of the data frame synchronization signal.

[0038] Further, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

[0039] Preferably, the first signal comprises a first data frame, the master communication device receives data from the host, and sends part or all of the data in the first data frame to the downstream device.

[0040] Preferably, the second signal comprises a second data frame, the master communication device receives the second data frame, and sends part or all of the data contained in the second data frame to the host.

[0041] Preferably, the master communication device does not send any data to the downstream device within a preset time after sending the synchronization frame.

[0042] Preferably, the second signal comprises a synchronization response frame, the master communication device judges the state of the downstream link according to whether the synchronization response frame is received within a preset time after sending the synchronization frame.

[0043] Preferably, the master communication device is an integrated circuit chip, and the local clock generation module generates the local clock according to a local reference clock, which is generated by a crystal-free reference clock generation circuit on the integrated circuit chip.

[0044] As a master communication device of the application, it comprises a downstream device interface module, a data frame synchronization signal generation module, and a local clock generation module. The data frame synchronization signal generation module generates a data frame synchronization signal. The downstream device interface module is connected to a downstream device through a downstream link. The downstream device interface module sends a first signal to the downstream device through the downstream link. The downstream device sends a second signal. The downstream device interface module receives the second signal from the downstream device through the downstream link. The first signal comprises a synchronization frame. The downstream device interface module sends the synchronization frame. The synchronization frame contains the data frame synchronization signal information. The downstream device can recover the data frame synchronization signal according to the synchronization frame. The local clock generation module generates a local clock. The clock of the downstream device interface module sending the first signal is the local clock. The first signal and the second signal are transmitted on the downstream link in time division mode.

[0045] Preferably, the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers.

[0046] Further, the synchronization frame comprises a sequence number field, which contains the sequence number of the synchronization frame.

[0047] Preferably, the synchronization frame comprises a phase field, which contains the phase relationship information of the synchronization frame and the data frame synchronization signal.

[0048] Preferably, the synchronization frame comprises a phase field and a count field. The phase field contains the phase relationship information of the synchronization frame and the data frame synchronization signal. The count field contains the count value of the data frame synchronization signal.

[0049] Further, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

[0050] Preferably, the first signal comprises a first data frame, the host communication device generates data based on the data frame synchronization signal, and the host communication device sends the generated data to the downstream device in the first data frame.

[0051] Preferably, the second signal comprises a second data frame, and the host communication device receives the second data frame.

[0052] Preferably, the host communication device further comprises a host interface module, the host interface module is connected to the host, and the host interface module sends the data frame synchronization signal to the host.

[0053] Further, the first signal comprises a first data frame, the host generates data based on the data frame synchronization signal, the host communication device receives the data from the host, and the host communication device sends part or all of the data to the downstream device in the first data frame. The second signal comprises a second data frame, and the host communication device receives the second data frame and sends part or all of the data contained in the second data frame to the host.

[0054] Preferably, the host communication device does not send any data to the downstream device within a preset time after sending the synchronization frame.

[0055] Preferably, the second signal comprises a synchronization response frame, and the host communication device judges the status of the downstream link according to whether the synchronization response frame is received within a preset time after sending the synchronization frame.

[0056] Preferably, the host communication device is an integrated circuit chip, the local clock generation module generates the local clock based on a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

[0057] As a half-duplex data communication system of the present application, it comprises a first communication device and a second communication device, the first communication device is connected with the second communication device through a communication link, the first communication device comprises a downstream device interface module, which sends a first signal to the second communication device through the communication link and receives a second signal from the second communication device through the communication link, the second communication device comprises an upstream device interface module, which sends the second signal to the first communication device through the communication link and receives the first signal from the first communication device through the communication link, the first signal comprises a synchronization frame, the second communication device receives the synchronization frame, and the second communication device further comprises a data frame synchronization signal recovery module, which recovers a data frame synchronization signal according to the received synchronization frame, the first communication device and the second communication device further respectively comprise a local clock generation module, the clock for sending the first signal by the first communication device is a first communication device local clock generated by the local clock generation module comprised by the first communication device, the clock for sending the second signal by the second communication device is a second communication device local clock generated by the local clock generation module comprised by the second communication device, and the first signal and the second signal are transmitted on the communication link in time division mode.

[0058] Preferably, the first communication device is a master communication device, and the second communication device is a slave communication device.

[0059] Further, the first communication device does not send any data to the downstream device within a preset time after sending the synchronization frame.

[0060] Preferably, the first communication device and the second communication device are both slave communication devices.

[0061] Preferably, the second communication device further comprises a peripheral interface module, the peripheral interface module is connected with an external device, and the peripheral interface module communicates with the external device based on the data frame synchronization signal.

[0062] Further, the peripheral interface module communicates with the external device based on the data frame synchronization signal, which comprises that the peripheral interface module sends data to the external device, or receives data from the external device, or sends data to the external device and receives data from the external device based on the data frame synchronization signal; or it can also comprise that the peripheral interface module sends the data frame synchronization signal to the external device.

[0063] Preferably, the second signal comprises a synchronization response frame, and the second communication device sends the synchronization response frame to the first communication device within a preset time after receiving the synchronization frame.

[0064] Further, the second communication device sends the synchronization response frame to the first communication device before sending any other data to the first communication device after receiving the synchronization frame. The first communication device judges the state of the communication link according to whether the synchronization response frame is received within a preset time after sending the synchronization frame included in the first signal.

[0065] Preferably, the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the time sequence signal of receiving the synchronization frame.

[0066] Further, the synchronization frame includes a sequence number field, the sequence number field includes the sequence number of the synchronization frame,

[0067] The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the sequence number field and the time sequence signal of receiving the synchronization frame.

[0068] Preferably, the synchronization frame includes a phase field, the phase field includes the phase relationship information between the synchronization frame and the data frame synchronization signal, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field.

[0069] Preferably, the synchronization frame includes a phase field and a count field, the phase field includes the phase relationship information between the synchronization frame and the data frame synchronization signal, and the count field includes the count value of the data frame synchronization signal.

[0070] The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field and the count field.

[0071] Further, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

[0072] Preferably, the first communication device is an integrated circuit chip, and the local clock generation module included in the first communication device generates the local clock of the first communication device according to the local reference clock of the first communication device, and the local reference clock of the first communication device is generated by the on-chip crystalless reference clock generation circuit included in the integrated circuit chip of the first communication device.

[0073] Preferably, the second communication device is an integrated circuit chip, and the local clock generation module included in the second communication device generates the local clock of the second communication device according to the local reference clock of the second communication device, and the local reference clock of the second communication device is generated by the on-chip crystalless reference clock generation circuit included in the integrated circuit chip of the second communication device.

[0074] The application provides a half-duplex data communication system, which can not increase clock phase noise with the increase of communication equipment levels in a transmission system, can transmit audio data with various sampling frequencies, and has low error code rate and good compatibility. BRIEF DESCRIPTION OF DRAWINGS

[0075] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0076] Fig. 1 is a schematic diagram of the half-duplex data communication system of the present application;

[0077] Fig. 2 is a structural block diagram of a master communication system of the half-duplex data communication system of the present application;

[0078] Fig. 3 is a structural block diagram of another master communication system of the half-duplex data communication system of the present application;

[0079] Fig. 4 is a structural block diagram of a slave communication system of the half-duplex data communication system of the present application;

[0080] Fig. 5 is a structural block diagram of another slave communication system of the half-duplex data communication system of the present application;

[0081] Fig. 6 is a schematic diagram of a first signal, a second signal, a third signal and a fourth signal in the half-duplex data communication system of the present application;

[0082] Fig. 7 is a structural diagram of a data frame in the half-duplex data communication system of the present application;

[0083] Fig. 8 is a master-slave structural diagram of the half-duplex data communication system of the present application;

[0084] Fig. 9 is a slave-slave structural diagram of the half-duplex data communication system of the present application;

[0085] Fig. 10 is a signal timing diagram of a method for recovering a data frame synchronization signal in the half-duplex data communication system of the present application;

[0086] Fig. 11 is a structural diagram of a synchronization frame in the half-duplex data communication system of the present application;

[0087] Fig. 12 is a signal timing diagram of another method for recovering a data frame synchronization signal in the half-duplex data communication system of the present application;

[0088] Fig. 13 is another structural diagram of a synchronization frame in the half-duplex data communication system of the present application;

[0089] Figure 14 is a signal timing diagram of another method of recovering a data frame synchronization signal in a half duplex data communication system of the present application;

[0090] Figure 15 is another structure diagram of a synchronization frame in a half duplex data communication system of the present application;

[0091] Figure 16 is a signal timing diagram of another method of recovering a data frame synchronization signal in a half duplex data communication system of the present application.

[0092] wherein:

[0093] 10: master communication device

[0094] 11: slave communication device

[0095] 100: downstream device interface module in master communication device

[0096] 101: local clock generation module in master communication device

[0097] 102: host interface module

[0098] 103: data frame synchronization signal generation module

[0099] 110: upstream device interface module

[0100] 111: local clock generation module in slave communication device

[0101] 112: peripheral interface module

[0102] 113: data frame synchronization signal recovery module

[0103] 114: downstream device interface module in slave communication device DETAILED DESCRIPTION

[0104] In order to make the above and other features and advantages of the present application more comprehensible, the present application will be further described below with reference to the drawings. It should be understood that the specific embodiments given herein are by way of example only and are not to be considered limiting.

[0105] As shown in Figure 1, as one half duplex data communication system of the present application, it contains one master communication device, and one or more slave communication devices, wherein the master communication device can be optionally connected with a host computer, and the rest of the communication devices are slave communication devices. Each communication device is connected in a chain topology, the master communication device is connected with the first slave communication device through a communication link, the first slave communication device is connected with the second slave communication device through a communication link, and so on, until the last slave communication device is connected with the second last slave communication device through a communication link.

[0106] In the present invention, the slave communication devices are divided into end slave communication devices and non-end slave communication devices. The last slave communication device is called end slave communication device, and the other slave communication devices except the end slave communication device are called non-end slave communication devices.

[0107] The direction from the master communication device to the end slave communication device is called downlink direction, and the direction from the end slave communication device to the master communication device is called uplink direction. For a specified communication device, the communication device connected through the communication link in the downlink direction is called the downstream device of the specified communication device, and the communication link is called the downlink of the specified communication device. For a specified communication device, the communication device connected through the communication link in the uplink direction is called the upstream device of the specified communication device, and the communication link is called the uplink of the specified communication device.

[0108] The master communication device has downstream device and downlink, and has no upstream device and uplink. The downstream device of the master communication device is slave communication device. The end slave communication device has upstream device and uplink, and has no downstream device and downlink. The upstream device of the end slave communication device can be master communication device or slave communication device. If there is no non-end slave communication device, the upstream device of the end slave communication device is master communication device. If there is non-end slave communication device, the upstream device of the end slave communication device is slave communication device. The non-end slave communication device has upstream device and uplink, and has downstream device and downlink. The upstream device of the non-end slave communication device can be master communication device or slave communication device. The downstream device of the non-end slave communication device is slave communication device.

[0109] A communication link is the downlink of the communication device connected in the uplink direction. A communication link is the uplink of the communication device connected in the downlink direction.

[0110] Figure 2 is an embodiment of a master communication device 10, including a downstream device interface module 100, a local clock generation module 101, and a host interface module 102. The downstream device interface module 100 is connected to a downstream device via a downstream link. The downstream device interface module 100 sends a first signal to the downstream device via the downstream link. The downstream device sends a second signal. The downstream device interface module 100 receives the second signal from the downstream device via the downstream link. The local clock generation module 101 of the master communication device 10 generates a local clock clockO. The clock of the downstream device interface module 100 sending the first signal is the local clock clockO. The host interface module 102 is connected to a host. The host interface module 102 receives a data frame synchronization signal from the host. The first signal includes a synchronization frame. The downstream device interface module 100 sends the synchronization frame. The synchronization frame includes the data frame synchronization signal information. The downstream device can recover the data frame synchronization signal from the synchronization frame. The first signal also includes a first data frame. The host interface module 102 receives data from the host. The downstream device interface module 100 sends some or all of the data in the first data frame to the downstream device. The second signal includes a second data frame. The downstream device interface module 100 receives the second data frame. The host interface module 102 sends some or all of the data in the second data frame to the host. The first signal and the second signal are transmitted on the downstream link of the master communication device 10 at different times.

[0111] Figure 3 is another embodiment of the master communication device 10 in the present application, which includes a downstream device interface module 100, a local clock generation module 101, a host interface module 102, and a data frame synchronization signal generation module 103. The downstream device interface module 100 is connected to a downstream device through a downstream link. The downstream device interface module 100 sends a first signal to the downstream device through the downstream link. The downstream device sends a second signal. The downstream device interface module 100 receives the second signal from the downstream device through the downstream link. The local clock generation module 101 of the master communication device 10 generates a local clock clock0. The clock for sending the first signal by the downstream device interface module 100 is the local clock clock0. The data frame synchronization signal generation module 103 generates a data frame synchronization signal. The host interface module 102 is connected to a host. The host interface module 102 sends the data frame synchronization signal to the host. The first signal includes a synchronization frame. The downstream device interface module 100 sends the synchronization frame. The synchronization frame includes the data frame synchronization signal information. The downstream device can recover the data frame synchronization signal according to the synchronization frame. The first signal also includes a first data frame. The host can generate data based on the data frame synchronization signal. The host interface module 102 receives the data from the host. The downstream device interface module 100 sends part or all of the data in the first data frame to the downstream device. The second signal includes a second data frame. The downstream device interface module 100 receives the second data frame. The host interface module 102 sends part or all of the data in the second data frame to the host. The first signal and the second signal are transmitted in time division on the downstream link of the master communication device 10. In the embodiment shown in Figure 3, the master communication device 10 can also only include the downstream device interface module 100, the local clock generation module 101, and the data frame synchronization signal generation module 103, but not the host interface module 102 and the host connected thereto. The downstream device interface module 100 is connected to a downstream device through a downstream link. The downstream device interface module 100 sends a first signal to the downstream device through the downstream link. The downstream device sends a second signal. The downstream device interface module 100 receives the second signal from the downstream device through the downstream link. The local clock generation module 101 of the master communication device 10 generates a local clock clock0. The clock for sending the first signal by the downstream device interface module 100 is the local clock clock0. The data frame synchronization signal generation module 103 generates a data frame synchronization signal. The first signal includes a synchronization frame. The downstream device interface module 100 sends the synchronization frame. The synchronization frame includes the data frame synchronization signal information. The downstream device can recover the data frame synchronization signal according to the synchronization frame. The first signal also includes a first data frame. The master communication device 10 can generate data based on the data frame synchronization signal. The master communication device 10 sends the generated data in the first data frame to the downstream device. The second signal includes a second data frame. The downstream device interface module 100 receives the second data frame. The master communication device 10 can process the data included in the received second data frame.The first signal and the second signal are transmitted in time division on the downlink of the master communication device 10.

[0112] For the master communication device 10 in FIG. 2 and FIG. 3, the second signal further comprises a synchronization response frame, after the master communication device 10 transmits the synchronization frame included in the first signal, within a preset time, different embodiments of the master communication device 10 can choose to transmit or not to transmit any data to the downstream device. The master communication device 10 judges the state of its downlink according to whether the synchronization response frame is received within the preset time after transmitting the synchronization frame included in the first signal.

[0113] As shown in the master communication device 10 in FIG. 2 and FIG. 3, the local clock generation module 101 generates the local clock clock0 according to the local reference clock. The local reference clock generation circuit (not shown in FIG. 2 and FIG. 3) is generally based on a quartz crystal to achieve high frequency accuracy. However, when the master communication device 10 is an integrated circuit chip, the local reference clock can also be generated by the integrated circuit chip on-chip reference clock generation circuit without quartz crystal, so as to reduce the cost and volume. The present application does not limit the implementation method of the local clock generation module 101. The commonly used implementation method of the local clock generation module 101 is a phase-locked loop circuit (PLL).

[0114] FIG. 4 is an embodiment of a slave communication device 11 in the present application. The slave communication device is a terminal slave communication device, which comprises an upstream device interface module 110, a local clock generation module 111, a peripheral interface module 112, and a data frame synchronization signal recovery module 113.

[0115] The upstream device interface module 110 is connected to the upstream device through the uplink. The upstream device transmits the first signal, and the upstream device interface module 110 receives the first signal from the upstream device through the uplink. The upstream device interface module 110 transmits the second signal to the upstream device through the uplink. The local clock generation module 111 of the slave communication device 11 generates the first local clock clock1, and the clock of the second signal transmitted by the upstream device interface module 110 is the first local clock clock1. The first signal comprises a synchronization frame, and the upstream device interface module 110 receives the synchronization frame. The data frame synchronization signal recovery module 113 is connected to the upstream device interface module 110, and the data frame synchronization signal recovery module 113 recovers the data frame synchronization signal according to the received synchronization frame.

[0116] The peripheral interface module 112 is connected to the external device, and the peripheral interface module 112 can select to communicate with the external device based on the data frame synchronization signal, including that the peripheral interface module 112 transmits data to the external device, or receives data from the external device, or transmits data to the external device and receives data from the external device based on the data frame synchronization signal, and the peripheral interface module 112 communicating with the external device based on the data frame synchronization signal also includes that the peripheral interface module 112 transmits the data frame synchronization signal to the external device.

[0117] The first signal also contains a first data frame, and the upstream device interface module 110 receives the first data frame, and the peripheral interface module 112 transmits part or all of the data in the first data frame to the external device. The second signal contains a second data frame, and the peripheral interface module 112 receives data from the external device, and the upstream device interface module 110 transmits part or all of the data in the second data frame to the upstream device. The first signal and the second signal are transmitted in time division on the uplink of the slave communication device 11.

[0118] For the slave communication device 11 in FIG. 4, the second signal can also contain a synchronization response frame, and after the upstream device interface module 110 receives the synchronization frame in the first signal, the synchronization response frame is transmitted to the upstream device within a preset time. In an embodiment, the slave communication device 11 transmits the synchronization response frame to the upstream device earlier than any other data transmitted to the upstream device, for example, the preset time can be set to that the slave communication device 11 transmits the synchronization response frame to the upstream device immediately after receiving the synchronization frame in the first signal, earlier than any other data transmitted to the upstream device.

[0119] As shown in the slave communication device 11 in FIG. 4, the local clock generation module 111 generates the first local clock clock1 according to the local reference clock. The local reference clock generation circuit (not shown in FIG. 4) is generally based on a quartz crystal to achieve high frequency accuracy. However, when the slave communication device 11 is an integrated circuit chip, the local reference clock can also be generated by the integrated circuit chip on-chip reference clock generation circuit without a quartz crystal, so as to avoid the quartz crystal and reduce the cost and volume. The present application does not limit the implementation method of the local clock generation module 111, and the commonly used implementation method of the local clock generation module 111 is a phase-locked loop circuit (PLL).

[0120] Figure 5 is another embodiment of the slave communication device 11 of the present application, which is a non-terminal slave communication device, comprising an upstream device interface module 110, a downstream device interface module 114, a local clock generation module 111, a peripheral device interface module 112, and a data frame synchronization signal recovery module 113. The upstream device interface module 110 is connected to an upstream device through an uplink, the upstream device transmits a first signal, the upstream device interface module 110 receives the first signal from the upstream device through the uplink, and the upstream device interface module 110 transmits a second signal to the upstream device through the uplink. The first signal comprises a synchronization frame, and the upstream device interface module 110 receives the synchronization frame. The data frame synchronization signal recovery module 113 is connected to the upstream device interface module 110, and the data frame synchronization signal recovery module 113 recovers a data frame synchronization signal according to the received synchronization frame.

[0121] The peripheral device interface module 112 is connected to an external device, and the peripheral device interface module 112 can selectively communicate with the external device based on the data frame synchronization signal, including that the peripheral device interface module 112 transmits data to the external device based on the data frame synchronization signal, or receives data from the external device based on the data frame synchronization signal, or transmits data to the external device and receives data from the external device based on the data frame synchronization signal, and the communication between the peripheral device interface module 112 and the external device based on the data frame synchronization signal also includes that the peripheral device interface module 112 transmits the data frame synchronization signal to the external device.

[0122] The downstream device interface module 114 is connected to a downstream device through a downlink, the downstream device interface module 114 transmits a third signal to the downstream device through the downlink, and the downstream device interface module 114 receives a fourth signal from the downstream device through the downlink. The local clock generation module 111 of the slave communication device 11 generates a first local clock clockl and a second local clock clock2, the clock of the second signal transmitted by the upstream device interface module 110 is the first local clock clockl, and the clock of the third signal transmitted by the downstream device interface module 114 is the second local clock clock2. The third signal comprises a synchronization frame, and the downstream device interface module 114 transmits the synchronization frame contained in the first signal to the downstream device through the downlink and contains it in the third signal, and the downstream device can recover a data frame synchronization signal according to the synchronization frame. The first signal and the second signal are transmitted on the uplink of the slave communication device 11 at different times, and the third signal and the fourth signal are transmitted on the downlink of the slave communication device 11 at different times.

[0123] As shown in the slave communication device 11 in Fig. 5, the local clock generating module 111 generates the first local clock clockl and the second local clock clock2 according to a local reference clock. The local reference clock generating circuit (not shown in Fig. 5) is generally based on a quartz crystal to achieve high frequency accuracy. However, when the slave communication device 11 is an integrated circuit chip, the local reference clock can also be generated by a crystalless reference clock generating circuit on the integrated circuit chip to eliminate the quartz crystal, thereby reducing the cost and size. The present application does not limit the implementation method of the local clock generating module 111. A commonly used implementation method of the local clock generating module 111 is a phase-locked loop circuit (PLL).

[0124] Simple variations and combinations of the embodiments shown in the present application are also within the scope of the present application. For example, in the embodiment shown in Fig. 5, clockl and clock2 can be the same clock, i.e., the upstream device interface module 110 and the downstream device interface module 114 can send the second signal and the third signal based on the same clock, or clockl and clock2 can be generated by two different local clock generating modules 111 based on the same local reference clock or two different local reference clocks, respectively.

[0125] For the slave communication device 11 in Fig. 5, the fourth signal can contain a synchronization response frame. After the slave communication device 11 sends the synchronization frame contained in the third signal, the state of the downlink is determined according to whether the synchronization response frame contained in the fourth signal is received within a predetermined time.

[0126] For the slave communication device 11 in Fig. 5, the second signal contains a synchronization response frame. After the upstream device interface module 110 receives the synchronization frame in the first signal, the synchronization response frame is sent to the upstream device within a predetermined time. In one embodiment, the time at which the slave communication device 11 sends the synchronization response frame to the upstream device is earlier than the time at which any other data is sent to the upstream device, e.g., the predetermined time can be set to the time at which the slave communication device 11 sends the synchronization response frame to the upstream device immediately after receiving the synchronization frame in the first signal, which is earlier than the time at which any other data is sent to the upstream device.

[0127] In the present application, the time at which the upstream device interface module 110 sends the synchronization response frame to the upstream device is independent of whether and when the downstream device interface module 114 receives the synchronization response frame in the fourth signal, and is also independent of whether and when the downstream device interface module 114 receives any other data in the fourth signal.

[0128] For a slave communication device 11 (as shown in FIG. 4 and FIG. 5), the first signal and the second signal are transmitted on its uplink in time division manner, the first signal contains a synchronization frame and can also contain a first data frame, the second signal can contain a synchronization response frame and can also contain a second data frame. For a slave communication device 11 when it contains a downstream device interface module 114 (as shown in FIG. 5), the third signal and the fourth signal are transmitted on its downlink in time division manner, the third signal contains a synchronization frame and can also contain a third data frame, the fourth signal can contain a synchronization response frame and can also contain a fourth data frame, as shown in FIG. 6.

[0129] The slave communication device 11 (as shown in FIG. 4 and FIG. 5) receives the first signal from its upstream device, i.e. receives the synchronization frame contained in the first signal and the first data frame, and sends the second signal to its upstream device, i.e. sends the synchronization response frame contained in the second signal and the second data frame. When a slave communication device 11 contains a downstream device interface module 114 (as shown in FIG. 5), it sends the third signal to the downstream device, i.e. sends the synchronization frame contained in the third signal and the third data frame, and receives the fourth signal from the downstream device, i.e. receives the synchronization response frame and the fourth data frame.

[0130] For a master communication device 10 (as shown in FIG. 2 and FIG. 3), the first signal and the second signal are transmitted on its downlink in time division manner, the first signal contains a synchronization frame and can also contain a first data frame, the second signal can contain a synchronization response frame and can also contain a second data frame, as shown in FIG. 6.

[0131] The master communication device 10 (as shown in FIG. 2 and FIG. 3) receives the second signal from its downstream device, i.e. receives the synchronization response frame contained in the second signal and the second data frame, and sends the first signal to its downstream device, i.e. sends the synchronization frame contained in the first signal and the first data frame.

[0132] In the present application, as shown in FIG. 5, after the slave communication device 11 receives the synchronization frame contained in the first signal from the upstream device, it forwards the received synchronization frame contained in the third signal to the downstream device, as shown in FIG. 6. In the process of forwarding, the slave communication device 11 in the present application can choose to modify the content of the synchronization frame.

[0133] Because the first signal and the second signal are transmitted on the same communication link in time division manner, in order to avoid conflict, a certain time interval should be maintained between the transmission of the first signal (i.e. the transmission of the synchronization frame and the first data frame contained in the first signal) and the transmission of the second signal (i.e. the transmission of the synchronization response frame and the second data frame contained in the second signal), such as the time interval between the synchronization frame contained in the first signal and the synchronization response frame contained in the second signal as shown in FIG. 6, or the time interval between the synchronization response frame contained in the second signal and the first data frame contained in the first signal as shown in FIG. 6.

[0134] Because the third signal and the fourth signal are transmitted in time division on the same communication link, to avoid conflict, a time interval should be kept between the transmission of the third signal (i.e. the transmission of the synchronization frame and the third data frame contained in the third signal) and the transmission of the fourth signal (i.e. the transmission of the synchronization response frame and the fourth data frame contained in the fourth signal), such as the time interval between the synchronization frame contained in the third signal and the synchronization response frame contained in the fourth signal as shown in Fig. 6, or the time interval between the synchronization response frame contained in the fourth signal and the third data frame contained in the third signal as shown in Fig. 6.

[0135] In the present application, the multiple data frames contained in the same first signal, second signal, third signal or fourth signal can be transmitted continuously or discontinuously, such as the two first data frames contained in the first signal are transmitted continuously without time interval in between, and the two third data frames contained in the third signal are transmitted discontinuously with time interval in between as shown in Fig. 6.

[0136] For a slave communication device 11 (as shown in Fig. 4 and Fig. 5), which can choose to send a synchronization response frame within a preset time after receiving the synchronization frame contained in the first signal, as shown in Fig. 6, the slave communication device 11 sends a synchronization response frame after receiving the synchronization frame contained in the first signal, and the time of sending the synchronization response frame is within the preset time and earlier than any other data sent by the slave communication device 11 to the upstream device. The time of sending the synchronization response frame by the slave communication device 11 is irrelevant to whether or not the downstream device interface module 114 receives the synchronization response frame in the fourth signal and when it receives the synchronization response frame, and is also irrelevant to whether or not the downstream device interface module 114 receives any other data in the fourth signal and when it receives the other data.

[0137] For a master communication device 10 (as shown in Fig. 2 and Fig. 3), which can choose to send or not to send any data to the downstream device within a preset time after sending the synchronization frame contained in the first signal. As shown in Fig. 6, the master communication device 10 sends the first signal, the slave communication device 11 (as shown in Fig. 4 and Fig. 5) receives the first signal and sends the second signal, and the master communication device 10 does not send any data to the downstream device within the preset time after sending the synchronization frame contained in the first signal, i.e. does not send the first data frame contained in the first signal within the preset time, and the slave communication device 11 sends a synchronization response frame within the preset time after receiving the synchronization frame contained in the first signal, and the time of sending the synchronization response frame is earlier than the time of sending the first data frame contained in the first signal by the master communication device 10.

[0138] The first data frame, the second data frame, the third data frame and the fourth data frame are collectively referred to as data frames in the present application. The present application does not limit the structure and processing method of the data frames. As a structure and processing method of the data frames, as shown in FIG. 7, the data frame includes a data frame header and a data field. Each communication device uses the data frame header to identify the data frame. The data field includes a plurality of data slots for carrying data payloads. Each communication device can add or delete a data slot, and can initialize, replace or empty the data payload in the data slot. Each communication device can be allocated one or more data slots. When the communication device needs to send data, the data payload can be placed in the corresponding data slot in the data frame, or a data slot of the data frame can be added and the data payload can be placed in the data slot. When the communication device needs to receive data, the data payload can be read out from the corresponding data slot, or the data slot can be deleted from the data frame after the data payload is read out from the corresponding data slot. When the communication device needs to send and receive data, the data payload can be read out from the corresponding data slot, and the data payload in the data slot can be replaced.

[0139] As shown in FIGS. 4 and 5, from the communication device 11, the first data frame can be received, and part or all of the data contained in the first data frame can be sent to an external device.

[0140] As shown in FIGS. 4 and 5, from the communication device 11, data can be received from an external device, and part or all of the data can be contained in the second data frame and sent to an upstream device.

[0141] As shown in FIG. 5, from the communication device 11, the first data frame can be received, and part or all of the data contained in the first data frame can be contained in the third data frame and sent to a downstream device.

[0142] As shown in FIG. 5, from the communication device 11, data can be received from an external device, and part or all of the data can be contained in the third data frame and sent to a downstream device.

[0143] As shown in FIG. 5, from the communication device 11, the first data frame can be received, and data can be received from an external device by the communication device 11. Part or all of the data contained in the first data frame and part or all of the data received from the external device by the communication device 11 can be contained in the third data frame and sent to a downstream device by the communication device 11.

[0144] As shown in FIG. 5, from the communication device 11, the fourth data frame can be received, and part or all of the data contained in the fourth data frame can be sent to an external device.

[0145] As shown in FIG. 5, from the communication device 11, the fourth data frame can be received, and part or all of the data contained in the fourth data frame can be contained in the second data frame and sent to an upstream device.

[0146] As shown in Fig. 5, the fourth data frame can be received from the slave communication device 11, and the slave communication device receives data from the external device, and the slave communication device sends the second data frame containing part or all of the data contained in the fourth data frame and part or all of the data received from the external device to the upstream device.

[0147] The present application does not limit the encoding method of the first signal, the second signal, the third signal and the fourth signal. In one embodiment of the present application, the first signal, the second signal, the third signal and the fourth signal can use an encoding method with clock information, such as 8b / 10b, 4b / 5b, Manchester encoding, etc.

[0148] For a slave communication device 11 (as shown in Fig. 4 and Fig. 5), the clock of the upstream device sending the first signal is the local clock generated by the upstream device, and the clock of the slave communication device 11 sending the second signal is the first local clock clock1 generated by the slave communication device 11. The local clock generated by the upstream device and the first local clock clock1 generated by the slave communication device 11 are not of the same source, i.e. the upstream device and the slave communication device 11 use their own local reference clock respectively, so the local clock generated by the upstream device and the first local clock clock1 generated by the slave communication device 11 are asynchronous clocks, and the first local clock clock1 generated by the slave communication device 11 is not locked to the first signal rate sent by the upstream device. For a slave communication device 11 (as shown in Fig. 5), the clock of the downstream device sending the fourth signal is the local clock generated by the downstream device, and the clock of the slave communication device 11 sending the third signal is the second local clock clock2 generated by the slave communication device 11. The local clock generated by the downstream device and the second local clock clock2 generated by the slave communication device 11 are not of the same source, i.e. the downstream device and the slave communication device 11 use their own local reference clock respectively, so the local clock generated by the downstream device and the second local clock clock2 generated by the slave communication device 11 are asynchronous clocks, and the second local clock clock2 generated by the slave communication device 11 is not locked to the fourth signal rate sent by the downstream device.

[0149] For a master communication device 10 (as shown in Fig. 2 and Fig. 3), the clock of the downstream device sending the second signal is the local clock generated by the downstream device, and the clock of the master communication device 10 sending the first signal is the local clock clock0 generated by the master communication device 10. The local clock generated by the downstream device and the local clock clock0 generated by the master communication device 10 are not of the same source, i.e. the downstream device and the master communication device 10 use their own local reference clock respectively, so the local clock generated by the downstream device and the local clock clock0 generated by the master communication device 10 are asynchronous clocks, and the local clock clock0 generated by the master communication device 10 is not locked to the second signal rate sent by the downstream device.

[0150] The clock and data recovery (CDR) circuit can be used to receive the encoded first signal or fourth signal in the application. The CDR circuit commonly used in the industry is an oversampling receiving circuit. The application does not specify the selection of the CDR circuit. Any applicable CDR circuit can be used to receive the first signal or fourth signal in the application.

[0151] As shown in FIG. 8 and FIG. 9, a half-duplex data communication system (master-slave structure) according to an embodiment of the application includes a first communication device and a second communication device. The first communication device and the second communication device are connected through a communication link. The first communication device is an upstream device of the second communication device, and the second communication device is a downstream device of the first communication device. The first communication device can be a master communication device (as shown in FIG. 8) or a slave communication device (as shown in FIG. 9). The second communication device is a slave communication device. If the second communication device is a slave non-terminal communication device, the second communication device is also connected to its downstream device through a downstream link.

[0152] The first communication device sends a first signal to the second communication device through a downstream link and receives a second signal from the second communication device through the downstream link. The second communication device sends the second signal to the first communication device through an upstream link and receives the first signal from the first communication device through the upstream link. The first signal and the second signal are transmitted on the downstream link of the first communication device at different times. The first signal includes a synchronization frame and can also include a first data frame. The second signal can include a synchronization response frame and can also include a second data frame.

[0153] If the second communication device is a slave non-terminal communication device, the second communication device sends a third signal to its downstream device through a downstream link and receives a fourth signal from its downstream device through the downstream link. The third signal and the fourth signal are transmitted on the downstream link of the second communication device at different times. The third signal includes a synchronization frame and can also include a third data frame. The fourth signal can include a synchronization response frame and can also include a fourth data frame.

[0154] In the embodiment shown in FIG. 8, the first communication device is a master communication device. The master communication device shown in FIG. 8 is the same as the master communication device 10 shown in FIG. 2 and FIG. 3 and the related description above. Therefore, the description is not repeated here.

[0155] In the embodiment shown in FIG. 9, the first communication device is a slave communication device. The slave communication device shown in FIG. 9 is the same as the slave communication device 11 shown in FIG. 4 and FIG. 5 and the related description above. Therefore, the description is not repeated here.

[0156] In the application, the slave communication device 11 receives a synchronization frame from its upstream device. The synchronization frame contains data frame synchronization signal information. The slave communication device 11 recovers the data frame synchronization signal according to the synchronization frame.

[0157] In the present application, the synchronization frame is initially sent by the master communication device 10 to its downstream device (the downstream device of the master communication device 10 is the slave communication device 11), the slave communication device 11 receives the synchronization frame from its upstream device (the upstream device of the slave communication device 11 is the master communication device 10 or the slave communication device 11), in an embodiment of the master communication device 10 as shown in Fig. 2, the host interface module 102 is connected to the host, the host interface module 102 receives the data frame synchronization signal as shown in Fig. 10 and Fig. 12 from the host, in another embodiment of the master communication device 10 as shown in Fig. 3, the master communication device 10 comprises a data frame synchronization signal generation module 103, the data frame synchronization signal generation module 103 generates the data frame synchronization signal as shown in Fig. 10 and Fig. 12.

[0158] In the present application, the synchronization frame is initially sent by the master communication device 10, the slave communication device 11 receives and forwards the synchronization frame, the synchronization frame comprises the data frame synchronization signal information, including: the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, wherein M and N are both positive integers, that is, the frame frequency of the synchronization frame is locked to the frequency of the data frame synchronization signal according to the ratio of M / N, the data frame synchronization signal recovery module 113 (contained in the slave communication device 11) recovers the data frame synchronization signal according to the time sequence signal received by the synchronization frame. The following gives several values of M and N, when M=1, N=1, the frame frequency of the synchronization frame is the same as the frequency of the data frame synchronization signal, that is, for every data frame synchronization signal pulse, one synchronization frame is sent, when M=1, N=2, the frame frequency of the synchronization frame is half of the frequency of the data frame synchronization signal, that is, for every two data frame synchronization signal pulses, one synchronization frame is sent, when M=2, N=1, the frame frequency of the synchronization frame is twice the frequency of the data frame synchronization signal, that is, for every data frame synchronization signal pulse, two synchronization frames are sent.

[0159] As shown in the embodiment of Fig. 10, an implementation method for recovering the data frame synchronization signal from the synchronization frame is given. The data frame synchronization signal shown in Fig. 10 is the data frame synchronization signal used by the master communication device 10 to send the synchronization frame, and the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, in this example, M=1, N=2, i.e. the frame frequency of the synchronization frame is half of the frequency of the data frame synchronization signal. The data frame synchronization signal recovered from the communication device 11 (indicated as the data frame synchronization signal recovered from the communication device in Fig. 10) is recovered from the synchronization frame timing signal (the synchronization frame timing signal generated after the synchronization frame is received) received by the communication device 11. In one embodiment, after the synchronization frame is received by the communication device 11, the synchronization frame timing signal is generated, and the synchronization frame timing signal can be sent to a phase-locked loop circuit (included in the data frame synchronization signal recovery module 113) to generate a high frequency clock. If the frequency of the high frequency clock is K times the frequency of the synchronization frame timing signal, the high frequency clock is counted by the communication device 11, in this embodiment, the count value is 0 when the synchronization frame timing signal is high, and the count value is counted from 0 to the maximum value K-1 and loops. The communication device 11 generates a high level pulse of the data frame synchronization signal when the count value is n1 and (K / 2)+n1, thereby recovering the data frame synchronization signal (indicated as the data frame synchronization signal recovered from the communication device in Fig. 10). The frequency of the recovered data frame synchronization signal is twice the frame frequency of the synchronization frame, equal to the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. At the same time, because of the existence of the high frequency clock count value 0 to K-1, the recovered data frame synchronization signal can be selected to be output at a predetermined high frequency clock count value (phase) position, i.e. the delay of the recovered data frame synchronization signal relative to the synchronization frame timing signal can be selected. In other embodiments, the frequency of the recovered data frame synchronization signal can also be different from the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame, for example, if the communication device 11 only generates a high level pulse of the data frame synchronization signal when the count value is n1, the frequency of the recovered data frame synchronization signal is equal to the frame frequency of the synchronization frame, which is half of the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. If the communication device 11 only generates a high level pulse of the data frame synchronization signal when the count value is n1, (K / 4)+n1, (K / 2)+n1, (3K / 4)+n1, the frequency of the recovered data frame synchronization signal is twice the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame.

[0160] In the application, the synchronization frame can contain a serial number field. The synchronization frame contains data frame synchronization signal information, including: the ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers, i.e. the frame frequency of the synchronization frame is locked to the frequency of the data frame synchronization signal at a ratio of M / N. The synchronization frame contains a serial number field, which contains the sequence number of the synchronization frame. The data frame synchronization signal recovery module 113 (contained in the slave communication device 11) recovers the data frame synchronization signal according to the synchronization frame serial number field and the time sequence signal of the received synchronization frame.

[0161] As shown in the embodiment of FIG. 11, the synchronization frame contains a synchronization frame header and a serial number field. The slave communication device 11 uses the synchronization frame header to identify the synchronization frame. The serial number field contains the sequence number of the synchronization frame, i.e. the count value of the synchronization frame.

[0162] As shown in the embodiment of FIG. 12, another implementation method for recovering the data frame synchronization signal according to the synchronization frame is given. The data frame synchronization signal shown in FIG. 12 is the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. The ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N. In this example, M=2 and N=1, i.e. the frame frequency of the synchronization frame is twice the frequency of the data frame synchronization signal, i.e. for each data frame synchronization signal pulse, two synchronization frames are sent. The sequence number count value of the synchronization frame contained in the serial number field is 0 to 3 and cycles back and forth. The slave communication device 11 recovers the data frame synchronization signal (indicated as the data frame synchronization signal recovered by the slave communication device in FIG. 12) according to the synchronization frame serial number field and the time sequence signal of the received synchronization frame (the synchronization frame time sequence signal generated after the synchronization frame is received),

[0163] In one embodiment, after receiving the synchronization frame from the communication device 11, a synchronization frame timing signal is generated, and the synchronization frame timing signal can be sent to a phase-locked loop circuit (included in the data frame synchronization signal recovery module 113) to generate a high-frequency clock. If the frequency of the high-frequency clock is K times the frequency of the synchronization frame timing signal, the high-frequency clock is counted from the communication device 11. In this embodiment, when the synchronization frame timing signal is high, the count value is 0, and the count value is counted from 0 to the maximum value K-1 and loops. The communication device 11 generates a high-level pulse of the data frame synchronization signal when the count is n1 and the synchronization frame sequence number is odd, thereby recovering the data frame synchronization signal (indicated as the recovered data frame synchronization signal from the communication device in FIG. 12). The frequency of the recovered data frame synchronization signal is half the frame frequency of the synchronization frame, which is equal to the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame. At the same time, because of the existence of the high-frequency clock count value 0 to K-1, the recovered data frame synchronization signal can be selected to be output at a preset high-frequency clock count value (phase) position, that is, the delay of the recovered data frame synchronization signal relative to the synchronization frame timing signal can be selected. Further, because of the existence of the synchronization frame sequence number, the data frame synchronization signal can be selected to be output only at a preset synchronization frame sequence number and a preset high-frequency clock count value (phase) position. In other embodiments, the communication device 11 can select to generate a high-level pulse of the data frame synchronization signal at a different high-frequency clock count value or a different synchronization frame sequence number than shown in FIG. 12, thereby recovering the data frame synchronization signal. For example, the communication device 11 can generate a high-level pulse of the data frame synchronization signal when the count is n1 and the synchronization frame sequence number is 2 (this case is not shown in FIG. 12), and the frequency of the recovered data frame synchronization signal is one-fourth of the frame frequency of the synchronization frame, which is half the frequency of the data frame synchronization signal used by the master communication device 10 to send the synchronization frame.

[0164] In the present application, the synchronization frame can include a phase field, and the phase field includes phase relationship information between the synchronization frame and the data frame synchronization signal. The data frame synchronization signal recovery module 113 (included in the communication device 11) recovers the data frame synchronization signal according to the phase field.

[0165] As shown in FIG. 13, the synchronization frame includes a synchronization frame header and a phase field. The communication device 11 uses the synchronization frame header to identify the synchronization frame, and the phase field includes phase relationship information between the synchronization frame and the data frame synchronization signal.

[0166] In the application, the synchronization frame is initially sent by the master communication device 10 to its downstream device (the downstream device of the master communication device 10 is the slave communication device 11), the slave communication device 11 receives the synchronization frame from its upstream device (the upstream device of the slave communication device 11 is the master communication device 10 or the slave communication device 11), in an embodiment of the master communication device 10 as shown in Fig. 2, the host interface module 102 is connected with the host, the host interface module 102 receives the data frame synchronization signal as shown in Fig. 14 and Fig. 16 from the host, in another embodiment of the master communication device 10 as shown in Fig. 3, the master communication device 10 comprises a data frame synchronization signal generation module 103, the data frame synchronization signal generation module 103 generates the data frame synchronization signal as shown in Fig. 14 and Fig. 16.

[0167] An implementation method of recovering the data frame synchronization signal according to the synchronization frame is given in the embodiment as shown in Fig. 14. The data frame synchronization signal as shown in Fig. 14 is the data frame synchronization signal in the master communication device 10, the data frame synchronization signal can be sent into a phase-locked loop circuit (included in the master communication device 10) to generate a high frequency clock, if the frequency of the high frequency clock is K times of the frequency of the synchronization frame timing signal, the master communication device 10 counts from 0 to K-1 for the high frequency clock and loops. The master communication device 10 sends the synchronization frame, the frame frequency of the synchronization frame can be independent of the frequency of the data frame synchronization signal, i.e. the frame frequency of the synchronization frame is not required to be locked to the frequency of the data frame synchronization signal according to a determined proportional relationship (the frame frequency of the synchronization frame is not required to be locked to the frequency of the data frame synchronization signal according to a determined proportional relationship), of course, the frame frequency of the synchronization frame can be locked to the frequency of the data frame synchronization signal according to a determined proportional relationship, the embodiment does not limit how the master communication device 10 determines the frame frequency of the synchronization frame. In the embodiment as shown in Fig. 14, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal, further, the interval between two adjacent synchronization frames can be fixed or variable, in the embodiment as shown in Fig. 14, the interval between two adjacent synchronization frames is variable. When the master communication device 10 sends the synchronization frame, the phase field of the synchronization frame can be the count value of the high frequency clock of the master communication device 10 at the time of sending the synchronization frame, so that the phase field contains the phase relationship information between the synchronization frame and the data frame synchronization signal.

[0168] The data frame synchronization signal is recovered from the communication device 11 according to the phase field. In one embodiment, after receiving the synchronization frame from the communication device 11, a synchronization frame timing signal is generated and the phase field of the synchronization frame is read from the communication device 11, and the synchronization frame timing signal and the read phase field of the synchronization frame can be sent to the data frame synchronization signal recovery module 113, and the data frame synchronization signal is recovered by the data frame synchronization signal recovery module 113. The present application does not limit the implementation method of the data frame synchronization signal recovery module 113, and in one embodiment, the data frame synchronization signal recovery module 113 can include a high-frequency clock generation circuit and a high-frequency clock counter, and the counting range of the high-frequency clock counter can be 0 to K-1 and loop back and forth, as shown in FIG. 14, and the high-frequency clock counting range in the communication device 11 can be selected to be the same as the high-frequency clock counting range in the master communication device 10.

[0169] At the moment of receiving the synchronization frame, that is, when the synchronization frame timing signal is a high-level pulse, the data frame synchronization signal recovery module 113 compares the difference between the phase field read from the synchronization frame and the high-frequency clock counting value of the data frame synchronization signal recovery module 113, and this difference can be used as a phase error signal to adjust the frequency and phase of the high-frequency clock generated by the high-frequency clock generation circuit included in the data frame synchronization signal recovery module 113, so as to minimize the phase error, thereby recovering the high-frequency clock and the high-frequency clock counting value in the data frame synchronization signal recovery module 113 that are locked with the frequency and phase of the high-frequency clock in the master communication device 10.

[0170] As shown in FIG. 14, the values of the synchronization frame phase field are n1, n2, n3, and n4, and the values of the high-frequency clock counting value recovered from the communication device 11 at the moment when the synchronization frame timing signal is a high-level pulse are also n1, n2, n3, and n4, and in this example, the phase error has been reduced to 0. As shown in the embodiment of FIG. 14, the communication device 11 generates a high-level pulse of the data frame synchronization signal when counting to m, thereby recovering the data frame synchronization signal (indicated as the data frame synchronization signal recovered from the communication device in FIG. 14). The recovered data frame synchronization signal can be output at a preset high-frequency clock counting value (phase) position from the communication device 11, because the high-frequency clock counting value recovered in the data frame synchronization signal recovery module 113 is locked with the high-frequency clock counting value in the master communication device 10, so the delay of the recovered data frame synchronization signal relative to the data frame synchronization signal in the master communication device 10 can be preset.

[0171] In the present application, the synchronization frame can include a phase field and a counting field, the phase field includes the phase relationship information between the synchronization frame and the data frame synchronization signal, and the counting field includes the data frame synchronization signal counting value, and the data frame synchronization signal recovery module 113 recovers the data frame synchronization signal according to the phase field and the counting field.

[0172] As shown in Fig. 15, the synchronization frame contains a synchronization frame header, a phase field and a count field. The synchronization frame header is used by the communication device 11 to identify the synchronization frame. The phase field contains the phase relationship information between the synchronization frame and the data frame synchronization signal. The count field contains the count value of the data frame synchronization signal.

[0173] As shown in the embodiment of Fig. 16, an implementation method for recovering the data frame synchronization signal from the synchronization frame is given. The data frame synchronization signal shown in Fig. 16 is the data frame synchronization signal in the main communication device 10. The data frame synchronization signal can be input into a phase-locked loop circuit (included in the main communication device 10) to generate a high frequency clock. If the frequency of the high frequency clock is K times the frequency of the synchronization frame timing signal, the main communication device 10 counts from 0 to K-1 and loops, and the main communication device 10 further includes a data frame synchronization signal counter for counting the data frame synchronization signal. In the embodiment shown in Fig. 16, the count value of the data frame synchronization signal is from 0 to 3 and loops. The main communication device 10 sends the synchronization frame. The frame frequency of the synchronization frame can be independent of the frequency of the data frame synchronization signal, i.e. the frame frequency of the synchronization frame does not need to have a certain proportional relationship with the frequency of the data frame synchronization signal (i.e. the frame frequency of the synchronization frame does not need to be locked to the frequency of the data frame synchronization signal according to a certain proportional relationship). Of course, the frame frequency of the synchronization frame can also have a certain proportional relationship with the frequency of the data frame synchronization signal, i.e. the frame frequency of the synchronization frame is locked to the frequency of the data frame synchronization signal according to a certain proportional relationship. The embodiment does not limit how the main communication device 10 determines the frame frequency of the synchronization frame. In the embodiment shown in Fig. 16, the frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal, and further, the interval between two adjacent synchronization frames can be fixed or variable. In the embodiment shown in Fig. 16, the interval between two adjacent synchronization frames is variable. When the main communication device 10 sends the synchronization frame, the phase field of the synchronization frame can be the count value of the high frequency clock of the main communication device 10 at the time of sending the synchronization frame, so that the phase field contains the phase relationship information between the synchronization frame and the data frame synchronization signal. The count field of the synchronization frame can be the count value of the data frame synchronization signal of the main communication device 10 at the time of sending the synchronization frame.

[0174] The data frame synchronization signal is recovered from the communication device 11 according to the phase field and the count field. In one embodiment, after receiving the synchronization frame from the communication device 11, the synchronization frame timing signal is generated and the phase field and the count field of the synchronization frame are read from the communication device 11, and the synchronization frame timing signal and the read phase field and count field of the synchronization frame can be sent to the data frame synchronization signal recovery module 113, and the data frame synchronization signal is recovered by the data frame synchronization signal recovery module 113. The present application does not limit the implementation method of the data frame synchronization signal recovery module 113. In one embodiment, the data frame synchronization signal recovery module 113 can include a high-frequency clock generation circuit, a high-frequency clock counter and a data frame synchronization signal counter. The counting range of the high-frequency clock counter can be 0 to K-1 and loop back, and the counting range of the data frame synchronization signal counter can be 0 to 3 and loop back. When the counting value of the high-frequency clock counter jumps from K-1 to 0, the data frame synchronization signal counter is incremented by 1, as shown in FIG. 16. The high-frequency clock counting range and the data frame synchronization signal counting range in the communication device 11 can be selected to be the same as the high-frequency clock counting range and the data frame synchronization signal counting range in the master communication device 10.

[0175] At the moment of receiving the synchronization frame, that is, when the synchronization frame timing signal is a high-level pulse, the data frame synchronization signal recovery module 113 compares the difference between the phase field and the count field read from the synchronization frame and the high-frequency clock counting value and the data frame synchronization signal counting value of the data frame synchronization signal recovery module 113. This difference can be used as a phase error signal to adjust the frequency and phase of the high-frequency clock generated by the high-frequency clock generation circuit included in the data frame synchronization signal recovery module 113 to minimize the phase error, so as to recover the high-frequency clock, the high-frequency clock counting value and the data frame synchronization signal counting value in the data frame synchronization signal recovery module 113 which are locked with the high-frequency clock frequency and phase in the master communication device 10.

[0176] As shown in Fig. 16, the values of the phase field / counter field of the synchronization frame are n1 / 0, n2 / 1, n3 / 2, n4 / 3, and the values of the high-frequency clock counter value / data frame synchronization signal counter value recovered from the communication device 11 are also n1 / 0, n2 / 1, n3 / 2, n4 / 3 at the time when the synchronization frame timing signal is a high level pulse, and in this example, the phase error has been reduced to 0. As shown in the example of Fig. 16, a high level pulse of the data frame synchronization signal is generated from the communication device 11 when the high-frequency clock counter reaches m and the data frame synchronization signal counter value is even, and thus the data frame synchronization signal is recovered (indicated as the data frame synchronization signal recovered from the communication device in Fig. 16), and in this example, the frequency of the recovered data frame synchronization signal is half of the frequency of the data frame synchronization signal in the main communication device 10. The recovered data frame synchronization signal can be outputted from the communication device 11 at a preset high-frequency clock counter value (phase) and a preset data frame synchronization signal counter value, because the high-frequency clock counter value and the data frame synchronization signal counter value recovered in the data frame synchronization signal recovery module 113 are locked to the high-frequency clock counter value and the data frame synchronization signal counter value in the main communication device 10, and thus the delay of the recovered data frame synchronization signal relative to the data frame synchronization signal in the main communication device 10 can be preset, and the frequency can also be different from the frequency of the data frame synchronization signal in the main communication device 10.

[0177] The above merely illustrates the preferred embodiments of the present application, but the protection scope of the present application is not limited thereto, and any modification, replacement, and change of the above-mentioned embodiments within the technical scope disclosed by the present application should be covered within the protection scope of the present application.

Claims

1. A slave communication device, comprising an upstream device interface module, a data frame synchronization signal recovery module, a local clock generation module, and a peripheral interface module, wherein: the upstream device interface module is connected to an upstream device through an uplink, the upstream device transmits a first signal, the upstream device interface module receives the first signal from the upstream device through the uplink, and the upstream device interface module transmits a second signal to the upstream device through the uplink, the first signal comprises a synchronization frame, the upstream device interface module receives the synchronization frame, the data frame synchronization signal recovery module is connected to the upstream device interface module, and the data frame synchronization signal recovery module recovers a data frame synchronization signal according to the received synchronization frame, the local clock generation module generates a first local clock, and a clock for transmitting the second signal by the upstream device interface module is the first local clock, and the first signal and the second signal are transmitted on the uplink in time division.

2. The slave communication device according to claim 1, wherein: the slave communication device further comprises a downstream device interface module, the downstream device interface module is connected to a downstream device through a downlink, the downstream device interface module transmits a third signal to the downstream device through the downlink, the downstream device interface module receives a fourth signal from the downstream device through the downlink, the slave communication device transmits the received synchronization frame to the downstream device through the downlink by including the synchronization frame in the third signal, the local clock generation module further generates a second local clock, and a clock for transmitting the third signal by the downstream device interface module is the second local clock, and the third signal and the fourth signal are transmitted on the downlink in time division.

3. The slave communication device according to claim 1, wherein: the peripheral interface module is connected to an external device, and the peripheral interface module communicates with the external device based on the data frame synchronization signal.

4. The slave communication device according to claim 3, wherein: the peripheral interface module communicates with the external device based on the data frame synchronization signal, including that the peripheral interface module transmits data to the external device, or receives data from the external device, or transmits data to the external device and receives data from the external device based on the data frame synchronization signal.

5. The slave communication device according to claim 3, wherein: the peripheral interface module communicates with the external device based on the data frame synchronization signal, including that the peripheral interface module transmits the data frame synchronization signal to the external device.

6. The slave communication device according to claim 1, wherein: the slave communication device is an integrated circuit chip, the local clock generation module generates the first local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

7. The slave communication device according to claim 2, wherein: the slave communication device is an integrated circuit chip, the local clock generation module generates the first local clock and the second local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

8. The slave communication device according to claim 1, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the time sequence signal of receiving the synchronization frame.

9. The slave communication device of claim 8, wherein: The synchronization frame includes a sequence number field, the sequence number field including a sequence number of the synchronization frame, and the data frame synchronization signal recovery module recovers the data frame synchronization signal according to the sequence number field and the time sequence signal of receiving the synchronization frame.

10. The slave communication device of claim 1, wherein: The synchronization frame includes a phase field, the phase field including phase relationship information between the synchronization frame and the data frame synchronization signal, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field.

11. The slave communication device of claim 1, wherein: The synchronization frame includes a phase field and a count field, the phase field including phase relationship information between the synchronization frame and the data frame synchronization signal, and the count field including a count value of the data frame synchronization signal, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field and the count field.

12. The slave communication device of claim 10 or 11, wherein: The frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

13. The slave communication device of claim 3, wherein: The first signal further includes a first data frame, the first data frame is received from the slave communication device, and part or all of the data included in the first data frame is transmitted to the external device.

14. The slave communication device of claim 2, wherein: The first signal further includes a first data frame, the third signal includes a third data frame, the first data frame is received from the slave communication device, and part or all of the data included in the first data frame is transmitted to the downstream device in the third data frame.

15. The slave communication device of claim 2, wherein: The peripheral interface module is connected to the external device, the third signal includes a third data frame, data is received from the external device by the slave communication device, and part or all of the data is transmitted to the downstream device in the third data frame.

16. The slave communication device of claim 2, wherein: The peripheral interface module is connected to the external device, the first signal further includes a first data frame, the third signal includes a third data frame, the first data frame is received from the slave communication device, data is received from the external device by the slave communication device, and part or all of the data included in the first data frame and part or all of the data received from the external device by the slave communication device are transmitted to the downstream device in the third data frame.

17. The slave communication device of claim 2, wherein: The peripheral interface module is connected to the external device, the fourth signal includes a fourth data frame, the fourth data frame is received from the slave communication device, and part or all of the data included in the fourth data frame is transmitted to the external device.

18. The slave communication device of claim 2, wherein: The second signal comprises a second data frame, the fourth signal comprises a fourth data frame, the slave communication device receives the fourth data frame from the external device, and the slave communication device sends part or all of the data contained in the fourth data frame to the upstream device in the second data frame.

19. The slave communication device of claim 3, wherein: The second signal comprises a second data frame, the slave communication device receives data from the external device, and the slave communication device sends part or all of the data from the external device to the upstream device in the second data frame.

20. The slave communication device of claim 2, wherein: The external device interface module is connected to the external device, the second signal comprises a second data frame, the fourth signal comprises a fourth data frame, the slave communication device receives the fourth data frame from the external device, and the slave communication device receives data from the external device, and the slave communication device sends part or all of the data contained in the fourth data frame and part or all of the data received from the external device to the upstream device in the second data frame.

21. The slave communication device of claim 1, wherein: The second signal comprises a synchronization response frame, and the slave communication device sends the synchronization response frame to the upstream device within a predetermined time after the upstream device interface module receives the synchronization frame.

22. The slave communication device of claim 21, wherein: The slave communication device sends the synchronization response frame to the upstream device within a time earlier than any other data sent to the upstream device after the upstream device interface module receives the synchronization frame.

23. The slave communication device of claim 2, wherein: The fourth signal comprises a synchronization response frame, and the slave communication device determines the status of the downlink according to whether the synchronization response frame contained in the fourth signal is received within a predetermined time after the slave communication device sends the synchronization frame contained in the third signal to the downstream device.

24. A master communication device, comprising a host interface module, a downstream device interface module, and a local clock generation module, wherein: The host interface module is connected to a host, and the host interface module receives a data frame synchronization signal from the host, The downstream device interface module is connected to a downstream device through a downlink, the downstream device interface module sends a first signal to the downstream device through the downlink, the downstream device sends a second signal, and the downstream device interface module receives the second signal from the downstream device through the downlink, The first signal comprises a synchronization frame, the downstream device interface module sends the synchronization frame, the synchronization frame contains data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal according to the synchronization frame, The local clock generation module generates a local clock, and the clock of the first signal sent by the downstream device interface module is the local clock, The first signal and the second signal are transmitted on the downlink in time division.

25. The master communication device of claim 24, wherein: The ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers.

26. The master communication device of claim 25, wherein: The synchronization frame comprises a sequence number field, and the sequence number field contains the sequence number of the synchronization frame.

27. The master communication device of claim 24, wherein: The synchronization frame comprises a phase field, and the phase field comprises phase relationship information between the synchronization frame and the data frame synchronization signal.

28. The master communication device of claim 24, wherein: The synchronization frame comprises a phase field and a count field, the phase field comprises phase relationship information between the synchronization frame and the data frame synchronization signal, and the count field comprises a count value of the data frame synchronization signal.

29. The master communication device of claim 27 or 28, wherein: The frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

30. The master communication device of claim 24, wherein: The first signal comprises a first data frame, and the master communication device receives data from the host and sends part or all of the data to the downstream device in the first data frame.

31. The master communication device of claim 24, wherein: The second signal comprises a second data frame, and the master communication device receives the second data frame and sends part or all of the data contained in the second data frame to the host.

32. The master communication device of claim 24, wherein: The master communication device does not send any data to the downstream device within a preset time after sending the synchronization frame.

33. The master communication device of claim 24, wherein: The second signal comprises a synchronization response frame, and the master communication device judges the state of the downstream link according to whether the synchronization response frame is received within a preset time after sending the synchronization frame.

34. The master communication device of claim 24, wherein: The master communication device is an integrated circuit chip, the local clock generation module generates the local clock according to a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

35. A master communication device, comprising a downstream device interface module, a data frame synchronization signal generation module, and a local clock generation module, wherein: The data frame synchronization signal generation module generates a data frame synchronization signal, The downstream device interface module is connected to a downstream device through a downstream link, the downstream device interface module sends a first signal to the downstream device through the downstream link, the downstream device sends a second signal, and the downstream device interface module receives the second signal from the downstream device through the downstream link, The first signal comprises a synchronization frame, the downstream device interface module sends the synchronization frame, the synchronization frame comprises data frame synchronization signal information, and the downstream device can recover the data frame synchronization signal according to the synchronization frame, The local clock generation module generates a local clock, and the clock for sending the first signal by the downstream device interface module is the local clock, The first signal and the second signal are transmitted on the downstream link in time division mode.

36. The master communication device of claim 35, wherein: The ratio of the frame frequency of the synchronization frame to the frequency of the data frame synchronization signal is M / N, where M and N are positive integers.

37. The master communication device of claim 36, wherein: The synchronization frame comprises a serial number field, and the serial number field comprises a serial number of the synchronization frame.

38. The master communication device of claim 35, wherein: The synchronization frame comprises a phase field, and the phase field comprises phase relationship information between the synchronization frame and the data frame synchronization signal.

39. The master communication device of claim 35, wherein: The synchronization frame comprises a phase field and a count field, the phase field comprises phase relationship information between the synchronization frame and the data frame synchronization signal, and the count field comprises a count value of the data frame synchronization signal.

40. The master communication device of claim 38 or 39, wherein: The frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

41. The master communication device of claim 35, wherein: The first signal comprises a first data frame, the master communication device generates data based on the data frame synchronization signal, and the master communication device sends the generated data to the downstream device in the first data frame.

42. The master communication device of claim 35, wherein: The second signal comprises a second data frame, and the master communication device receives the second data frame.

43. The master communication device of claim 35, wherein: The master communication device further comprises a host interface module, the host interface module is connected to a host, and the host interface module sends the data frame synchronization signal to the host.

44. The master communication device of claim 43, wherein: The first signal comprises a first data frame, the host generates data based on the data frame synchronization signal, the master communication device receives the data from the host, and the master communication device sends part or all of the data to the downstream device in the first data frame.

45. The master communication device of claim 43, wherein: The second signal comprises a second data frame, the master communication device receives the second data frame, and the master communication device sends part or all of the data contained in the second data frame to the host.

46. The master communication device of claim 35, wherein: The master communication device does not send any data to the downstream device within a preset time after sending the synchronization frame.

47. The master communication device of claim 35, wherein: The second signal comprises a synchronization response frame, the master communication device judges the status of the downstream link according to whether the synchronization response frame is received within a preset time after sending the synchronization frame.

48. The master communication device of claim 35, wherein: The master communication device is an integrated circuit chip, the local clock generation module generates the local clock based on a local reference clock, and the local reference clock is generated by a crystalless reference clock generation circuit on the integrated circuit chip.

49. A half-duplex data communication system comprising a first communication device and a second communication device, the first communication device and the second communication device being connected through a communication link, wherein: The first communication device comprises a downstream device interface module, the downstream device interface module sends a first signal to the second communication device through the communication link and receives a second signal from the second communication device through the communication link, The second communication device comprises an upstream device interface module, the upstream device interface module sends the second signal to the first communication device through the communication link and receives the first signal from the first communication device through the communication link, The first signal comprises a synchronization frame, and the second communication device receives the synchronization frame, The second communication device further comprises a data frame synchronization signal recovery module configured to recover a data frame synchronization signal according to the received synchronization frame, The first communication device and the second communication device each further comprise a local clock generation module, a clock for sending the first signal is a first communication device local clock generated by the local clock generation module comprised by the first communication device, and a clock for sending the second signal is a second communication device local clock generated by the local clock generation module comprised by the second communication device, The first signal and the second signal are transmitted on the communication link in time division.

50. The data communication system according to claim 49, wherein: The first communication device is a master communication device, and the second communication device is a slave communication device.

51. The data communication system according to claim 50, wherein: The first communication device does not send any data to a downstream device within a preset time after sending the synchronization frame.

52. The data communication system according to claim 49, wherein: The first communication device and the second communication device are each a slave communication device.

53. The data communication system according to claim 49, wherein: The second communication device further comprises a peripheral interface module connected to an external device, and the peripheral interface module communicates with the external device based on the data frame synchronization signal.

54. The data communication system according to claim 53, wherein: The peripheral interface module communicates with the external device based on the data frame synchronization signal, including that the peripheral interface module sends data to the external device, or receives data from the external device, or sends data to the external device and receives data from the external device based on the data frame synchronization signal.

55. The data communication system according to claim 53, wherein: The peripheral interface module communicates with the external device based on the data frame synchronization signal, including that the peripheral interface module sends the data frame synchronization signal to the external device.

56. The data communication system according to claim 49, wherein: The second signal comprises a synchronization response frame, and the second communication device sends the synchronization response frame to the first communication device at a preset time after receiving the synchronization frame.

57. The data communication system according to claim 56, wherein: The second communication device sends the synchronization response frame to the first communication device at a time earlier than any other data sent to the first communication device after receiving the synchronization frame.

58. The data communication system according to claim 56, wherein: The first communication device judges a state of the communication link according to whether the synchronization response frame comprised in the second signal is received within a preset time after sending the synchronization frame comprised in the first signal.

59. The data communication system according to claim 49, wherein: A ratio of a frame frequency of the synchronization frame to a frequency of the data frame synchronization signal is M / N, where M and N are positive integers, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the time sequence signal of receiving the synchronization frame.

60. The data communication system of claim 59, wherein: The synchronization frame comprises a sequence number field, the sequence number field comprising a sequence number of the synchronization frame, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the sequence number field and the time sequence signal of receiving the synchronization frame.

61. The data communication system of claim 49, wherein: The synchronization frame comprises a phase field, the phase field comprising phase relationship information between the synchronization frame and the data frame synchronization signal, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field.

62. The data communication system of claim 49, wherein: The synchronization frame comprises a phase field and a count field, the phase field comprising phase relationship information between the synchronization frame and the data frame synchronization signal, and the count field comprising a count value of the data frame synchronization signal, The data frame synchronization signal recovery module recovers the data frame synchronization signal according to the phase field and the count field.

63. The data communication system of claim 61 or 62, wherein: The frame frequency of the synchronization frame is independent of the frequency of the data frame synchronization signal.

64. The data communication system of claim 49, wherein: The first communication device is an integrated circuit chip, and the local clock generation module comprised in the first communication device generates the local clock of the first communication device according to a local reference clock of the first communication device, the local reference clock of the first communication device being generated by an on-chip crystalless reference clock generation circuit comprised in the integrated circuit chip of the first communication device.

65. The data communication system of claim 49, wherein: The second communication device is an integrated circuit chip, and the local clock generation module comprised in the second communication device generates the local clock of the second communication device according to a local reference clock of the second communication device, the local reference clock of the second communication device being generated by an on-chip crystalless reference clock generation circuit comprised in the integrated circuit chip of the second communication device.

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