Display panel and display driving method therefor, and display device

Abstract

The present invention relates to the technical field of display, and provides a display panel and a display driving method therefor, and a display device. Each pixel in the display panel comprises a pixel circuit and a plurality of light-emitting elements which are stacked and have different colors. On the basis of gate control signals provided by a plurality of gate control lines in one-to-one correspondence with the plurality of light-emitting elements, the pixel circuit can control the plurality of light-emitting elements to independently emit light of different colors. In this way, a good display effect can be ensured to lay a good foundation for full-color light emission, and a high-resolution design of the display panel can be facilitated.

Description

Display panel, display driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202411087453.2, filed on August 8, 2024, and entitled "Display panel, display driving method thereof and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel, a display driving method thereof and a display device. BACKGROUND

[0003] With the resolution of display products becoming higher and higher, in some display fields such as virtual reality (VR), augmented reality (AR), naked-eye 3D and silicon-based, ultra-high resolution is urgently needed to support the brightness of display products. At present, the conventional organic light-emitting diode (OLED) has been unable to meet the display requirements. SUMMARY

[0004] A display panel, a display driving method thereof and a display device are provided. The technical solutions are as follows:

[0005] In one aspect, a display panel is provided, comprising: a substrate, and a plurality of pixels on the substrate, at least one of the pixels comprising: a pixel circuit, and at least two light-emitting elements stacked on the substrate and different in color, the pixel circuit comprising:

[0006] a first control circuit connected with a first gate control line, a first light-emitting control line, a data line, a first power supply line, a first node and a second node respectively, and configured to control the data line and the first node to be connected or disconnected in response to a first gate control signal provided by the first gate control line, and control the first power supply line and the second node to be connected or disconnected in response to a first light-emitting control signal provided by the first light-emitting control line;

[0007] a driving circuit connected with the first node, the second node and a third node respectively, and configured to control the second node and the third node to be connected or disconnected in response to the potential of the first node, and control the potential of the third node based on the potential of the first node and the potential of the second node, the at least two light-emitting elements being connected in series between the third node and a second power supply line;

[0008] a second control circuit, connected with the at least two second gate control lines respectively, and the first electrode and the second electrode of each of the light emitting elements, the at least two second gate control lines corresponding to the at least two light emitting elements one by one, and used for controlling the on-off between the first electrode and the second electrode of the corresponding light emitting element in response to a second gate control signal provided by each of the second gate control lines.

[0009] Optionally, the first control circuit comprises:

[0010] a first control sub-circuit, connected with the first gate control line, the data line and the first node respectively, and used for controlling the on-off between the data line and the first node in response to the first gate control signal;

[0011] a second control sub-circuit, connected with the first light emitting control line, the first power supply line and the second node respectively, and used for controlling the on-off between the first power supply line and the second node in response to the first light emitting control signal.

[0012] Optionally, the first control sub-circuit comprises a first transistor, and the second control sub-circuit comprises a second transistor;

[0013] a gate of the first transistor is connected with the first gate control line, a first electrode of the first transistor is connected with the data line, and a second electrode of the first transistor is connected with the first node;

[0014] a gate of the second transistor is connected with the first light emitting control line, a first electrode of the second transistor is connected with the first power supply line, and a second electrode of the second transistor is connected with the second node.

[0015] Optionally, the second control circuit comprises:

[0016] at least two third control sub-circuits corresponding to the at least two second gate control lines one by one, each of the third control sub-circuits being connected with a corresponding one of the second gate control lines, and the first electrode and the second electrode of one light emitting element corresponding to the corresponding one of the second gate control lines, and used for controlling the on-off between the first electrode and the second electrode of the corresponding one of the light emitting elements in response to a second gate control signal provided by the corresponding one of the second gate control lines.

[0017] Optionally, each of the third control sub-circuits comprises a third transistor;

[0018] a gate of the third transistor is connected with the corresponding one of the second gate control lines, and a first electrode and a second electrode of the third transistor are connected with the first electrode and the second electrode of the corresponding one of the light emitting elements respectively.

[0019] Optionally, the driving circuit comprises a fourth transistor.

[0020] a gate of the fourth transistor is connected with the first node, a first pole of the fourth transistor is connected with the second node, and a second pole of the fourth transistor is connected with the third node.

[0021] Optionally, the pixel circuit further comprises:

[0022] a third control circuit connected with the second light-emitting control line, the initial power supply line and the second node respectively, and configured to control the initial power supply line and the second node in response to a second light-emitting control signal provided by the second light-emitting control line.

[0023] Optionally, the third control circuit comprises a fifth transistor.

[0024] a gate of the fifth transistor is connected with the second light-emitting control line, a first pole of the fifth transistor is connected with the initial power supply line, and a second pole of the fifth transistor is connected with the second node.

[0025] Optionally, at least two of the plurality of pixels comprise pixel circuits sharing at least one target circuit.

[0026] the third control circuit;

[0027] and a second control sub-circuit in the first control circuit connected with the first light-emitting control line.

[0028] Optionally, the plurality of pixels are arranged in an array, and the at least two pixels sharing the target circuit are located in the same row.

[0029] Optionally, at least two target circuits are shared by a plurality of pixels located in the same row, and the two target circuits are located on both sides of the plurality of pixels in the row direction.

[0030] Optionally, the substrate has a display area and a peripheral area at least partially surrounding the display area.

[0031] the at least two light-emitting elements are located in the display area.

[0032] each of the pixel circuits is located in the display area; or, in the pixel circuit, the at least one target circuit shared by the pixel circuits is located in the peripheral area, and other circuits except the at least one target circuit are located in the display area.

[0033] Optionally, the pixel circuit further comprises:

[0034] a fourth control circuit, connected with the third gate control line, the reference power supply line and the first node respectively, and configured to control the reference power supply line and the first node in response to a third gate control signal provided by the third gate control line.

[0035] Optionally, the fourth control circuit comprises a sixth transistor.

[0036] The gate of the sixth transistor is connected with the third gate control line, the first pole of the sixth transistor is connected with the reference power supply line, and the second pole of the sixth transistor is connected with the first node.

[0037] Optionally, the pixel circuit further comprises a potential adjusting circuit.

[0038] The potential adjusting circuit is connected with the first node and the third node respectively, and configured to adjust the potential of one node based on the potential of the other node.

[0039] Optionally, the potential adjusting circuit comprises a storage capacitor.

[0040] One end of the storage capacitor is connected with the first node, and the other end of the storage capacitor is connected with the third node.

[0041] Optionally, at least one of the pixels comprises three light emitting elements.

[0042] And the colors of the light emitted by the three light emitting elements are red, blue and green respectively.

[0043] In another aspect, a display driving method of a display panel is provided, which is used for driving the display panel in the aspect above, and the method comprises: in each frame scanning, sequentially lighting at least two subframes of at least two light emitting elements in a pixel, and each of the subframes comprises: a data writing stage and a light emitting stage executed in sequence.

[0044] In the data writing stage, the first control circuit controls the data line and the first node to be conductive in response to a first gate control signal provided by the first gate control line, and the second control circuit controls the first pole and the second pole of the light emitting element to be conductive with the third node and the second power supply line respectively in response to a second gate control signal provided by the second gate control line which does not correspond to the light emitting element to be lighted among at least two second gate control lines.

[0045] In the light emitting stage, the first control circuit controls the first power supply line and the second node to be conductive in response to a first light emitting control signal provided by the first light emitting control line, the second control circuit controls the first electrode and the second electrode of the to-be-lit light emitting element to be conductive with the third node and the second power supply line respectively in response to a second gate control signal provided by the second gate control line corresponding to the to-be-lit light emitting element among the at least two second gate control lines, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node, and outputs a light emitting driving signal to the third node based on the potential of the first node and the potential of the second node, so as to drive the to-be-lit light emitting element to emit light.

[0046] Optionally, each of the subframes further comprises a reset stage and a compensation stage which are sequentially performed in the data writing stage.

[0047] In the reset stage, the third control circuit controls the initial power supply line and the second node to be conductive in response to a second light emitting control signal provided by the second light emitting control line, the fourth control circuit controls the reference power supply line and the first node to be conductive in response to a third gate control signal provided by the third gate control line, the second control circuit controls the first electrode and the second electrode of the target light emitting element to be conductive in response to a second gate control signal provided by the second gate control line corresponding to the target light emitting element among the at least two second gate control lines, the target light emitting element is a light emitting element whose second electrode is not directly connected to the second power supply line, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node.

[0048] In the compensation stage, the fourth control circuit controls the reference power supply line and the first node to be conductive in response to a third gate control signal provided by the third gate control line, the first control circuit controls the first power supply line and the second node to be conductive in response to a first light emitting control signal provided by the first light emitting control line, the second control circuit controls the first electrode and the second electrode of the to-be-lit light emitting element to be conductive with the third node and the second power supply line respectively in response to a second gate control signal provided by the second gate control line corresponding to the to-be-lit light emitting element among the at least two second gate control lines, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node.

[0049] In yet another aspect, a display device is provided, which comprises a display driving circuit and a display panel as described in the above aspect.

[0050] The display driving circuit is connected with each signal line in the display panel and is configured to provide a signal to the each signal line. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0052] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0053] FIG. 2 is a structural schematic diagram of a pixel in a display panel according to an embodiment of the present application;

[0054] FIG. 3 is a structural schematic diagram of a pixel in another display panel according to an embodiment of the present application;

[0055] FIG. 4 is a structural schematic diagram of a pixel in yet another display panel according to an embodiment of the present application;

[0056] FIG. 5 is a circuit structural schematic diagram of a pixel in a display panel according to an embodiment of the present application;

[0057] FIG. 6 is a pixel arrangement schematic diagram in a display panel according to an embodiment of the present application;

[0058] FIG. 7 is a pixel arrangement schematic diagram in another display panel according to an embodiment of the present application;

[0059] FIG. 8 is a pixel arrangement schematic diagram in yet another display panel according to an embodiment of the present application;

[0060] FIG. 9 is a flow schematic diagram of a display driving method of a display panel according to an embodiment of the present application;

[0061] FIG. 10 is a driving timing schematic diagram of a pixel circuit in a display panel according to an embodiment of the present application;

[0062] FIG. 11 is a timing simulation schematic diagram according to an embodiment of the present application;

[0063] FIG. 12 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will make a further detailed description of the embodiments of the present application in combination with the drawings.

[0065] It should be noted that the transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. The transistors used in the embodiments of the present application are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistors used here are symmetrical, the source and drain can be interchangeable. The source is referred to as the first pole and the drain is referred to as the second pole, or the drain is referred to as the first pole and the source is referred to as the second pole. According to the configuration in the drawings, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistors used in the embodiments of the present application can include any one of P-type transistors and N-type transistors or a combination thereof. Among them, the P-type transistor is turned on when the gate is low voltage, and is turned off when the gate is high voltage. The N-type transistor is turned on when the gate is high voltage, and is turned off when the gate is low voltage.

[0066] The embodiment of the present application provides a display panel. As shown in FIG. 1, the display panel comprises a substrate 10 and a plurality of pixels 00 on the substrate 10.

[0067] Based on FIG. 1, it can be seen from FIG. 2 that at least one pixel 00 (for example, each pixel 00) comprises a pixel circuit 01 and at least two light emitting elements 02. The at least two light emitting elements 02 are stacked on the substrate 10 and have different colors. That is, the at least two light emitting elements 02 are located on one side of the substrate 10 and are sequentially stacked or stacked in a direction away from the substrate 10, and the colors of the light emitting elements 02 are different.

[0068] For example, referring to FIG. 2, the pixels 00 shown therein each comprise three light emitting elements 02, and the colors of the light emitted by the three light emitting elements 02 are red (R), blue (B) and green (G) respectively. That is, the three light emitting elements 02 can be red light emitting elements (or red sub-pixels) R, blue light emitting elements (or blue sub-pixels) B and green light emitting elements (or green sub-pixels) G respectively. For distinction, the red light emitting element R is identified as 02-1 / R in the figure, the blue light emitting element B is identified as 02-2 / B, and the green light emitting element G is identified as 02-3 / G. Of course, the number and color here are only illustrative.

[0069] Alternatively, the light emitting element 02 can be an OLED. Correspondingly, the pixel 00 comprising the at least two light emitting elements 02 stacked can also be a stacked OLED device. Of course, it can also be other types of light emitting elements. For example, active-matrix OLED (AMOLED).

[0070] Continuing to refer to FIG. 2, the pixel circuit 01 comprises a first control circuit 011, a driving circuit 012 and a second control circuit 013.

[0071] The first control circuit 011 is connected with the first gate control line G1, the first light-emitting control line EM1, the data line Data, the first power supply line VDD, the first node N1 and the second node N2 respectively. The first control circuit 011 is configured to control the connection between the data line Data and the first node N1 in response to a first gate control signal provided by the first gate control line G1, and control the connection between the first power supply line VDD and the second node N2 in response to a first light-emitting control signal provided by the first light-emitting control line EM1.

[0072] For example, the first control circuit 011 can control the data line Data to be connected to the first node N1 when the first gate control signal provided by the first gate control line G1 has a first potential, so that a data signal provided by the data line Data can be transmitted to the first node N1, and can control the data line Data to be disconnected from the first node N1 when the first gate control signal provided by the first gate control line G1 has a second potential.

[0073] Similarly, the first control circuit 011 can control the first power supply line VDD to be connected to the second node N2 when the first light-emitting control signal provided by the first light-emitting control line EM1 has a first potential, so that a first power signal provided by the first power supply line VDD can be transmitted to the second node N2, and can control the first power supply line VDD to be disconnected from the second node N2 when the first light-emitting control signal provided by the first light-emitting control line EM1 has a second potential.

[0074] Optionally, the first potential can be an effective potential, and the second potential can be an ineffective potential, and the first potential can be a high potential relative to the second potential, that is, the first potential can be a high potential, and the second potential can be a low potential. It can also be known that the transistor in the pixel circuit provided in the embodiments of the present application can be an N-type transistor with a high potential. Of course, in some other embodiments, the first potential can be a low potential relative to the second potential, and the corresponding transistor can be a P-type transistor with a high potential. The following embodiments are the same, and will not be described one by one.

[0075] The driving circuit 012 is connected with the first node N1, the second node N2 and the third node N3 respectively. The driving circuit 012 is configured to control the connection between the second node N2 and the third node N3 in response to the potential of the first node N1, and control the potential of the third node N3 based on the potential of the first node N1 and the potential of the second node N2. At least two light-emitting elements 02 are connected in series between the third node N3 and the second power supply line VSS.

[0076] For example, the driving circuit 012 can control the second node N2 and the third node N3 to be conductive when the potential of the first node N1 is the first potential, and can control the second node N2 and the third node N3 to be disconnected when the potential of the first node N1 is the second potential. Moreover, the driving circuit 012 can transmit a light-emitting driving signal to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, to drive the at least two light-emitting elements 02 to emit light. For example, each light-emitting element 02 can emit light under the pressure difference between the light-emitting driving signal and the second power signal provided by the second power line VSS.

[0077] Optionally, the potential of the first power signal provided by the first power line VDD can be a high potential, and the potential of the second power signal provided by the second power line VSS can be a low potential. Moreover, in combination with FIG. 2, the at least two light-emitting elements 02 connected in series between the third node N3 and the second power line VSS can mean that, in each two series-connected light-emitting elements 02, the first pole of one light-emitting element 02 is connected to the second pole of the other light-emitting element 02, and the first pole and the second pole of the two light-emitting elements 02 at the head and tail are respectively connected to the third node N3 and the second power line VSS.

[0078] For example, in the three light-emitting elements 02-1 / R, 02-2 / B and 02-3 / G shown in FIG. 2, the first pole of the light-emitting element 02-1 / R is connected to the third node N3, the second pole of the light-emitting element 02-1 / R is connected to the first pole of the light-emitting element 02-2 / B, the second pole of the light-emitting element 02-2 / B is connected to the first pole of the light-emitting element 02-3 / G, and the second pole of the light-emitting element 02-3 / G is connected to the second power line VSS. For distinction, the series connection node between the light-emitting element 02-1 / R and the light-emitting element 02-2 / B is identified as P-1, and the series connection node between the light-emitting element 02-2 / B and the light-emitting element 02-3 / G is identified as P-2. Optionally, the first pole of the light-emitting element 02 can mean an anode, and the second pole can mean a cathode. Of course, the first pole and the second pole can also be interchanged.

[0079] The second control circuit 013 is connected to the first pole and the second pole of each light-emitting element 02, and is connected to at least two second gate control lines G2 corresponding to the at least two light-emitting elements 02. The second control circuit 013 is configured to control the on-off between the first pole and the second pole of the corresponding light-emitting element 02 in response to a second gate control signal provided by each second gate control line G2.

[0080] For example, in combination with FIG. 2, assuming that the pixel circuit 01 includes three light emitting elements 02 shown in the figure, the second control circuit 013 can be connected with three second gate control lines G2 corresponding to the three light emitting elements 02 one by one, and can control the first pole and the second pole of the corresponding one light emitting element 02 to be connected through the second control circuit 013 when the potential of the second gate control signal provided by each second gate control line G2 is the first potential, and can control the first pole and the second pole of the corresponding one light emitting element 02 to be disconnected through the second control circuit 013 when the potential of the second gate control signal provided by each second gate control line G2 is the second potential. For distinction, the three second gate control lines G2 corresponding to the three light emitting elements 02-1 / R, 02-2 / B and 02-3 / G are respectively marked as G2-1, G2-2 and G2-3 in the figure.

[0081] In this way, in combination with the above-mentioned driving mode of the driving circuit 012 for driving the light emitting element 02 to emit light, it can be known that in the embodiment of the present application, the second gate control signal provided by different second gate control lines G2 can be flexibly set to make different light emitting elements 02 in one pixel 00 respectively and independently emit light of different colors, laying a foundation for full-color light emission. For example, on the basis that the pixel 00 includes a red light emitting element 02-1 / R, a blue light emitting element 02-2 / B and a green light emitting element 02-3 / G, field sequential light emission of the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G can be controlled to realize full-color light emission. Among them, field sequential light emission refers to a display technology, which sequentially controls the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G to emit red light, green light and blue light in turn, and then uses the visual persistence of the human eye to form a colorful video image display.

[0082] In addition, because the plurality of light emitting elements 02 included in the pixel 00 in the embodiment of the present application are stacked, compared with the traditional OLED display panel arranged at intervals, the pixel 00 can also reduce the occupied area, which is beneficial to the ultra-high PPI design of the display panel. Among them, PPI (pixels per inch) is also called pixel density unit, which represents the number of pixels per inch, and is commonly used to represent the resolution of the display panel.

[0083] In summary, this application provides a display panel. The pixels in this display panel include pixel circuits and multiple light-emitting elements stacked and of different colors. The pixel circuits can control the multiple light-emitting elements to independently emit light of different colors based on gate control signals provided by multiple gate control lines corresponding one-to-one with the multiple light-emitting elements. This not only ensures good display effects and lays a good foundation for full-color illumination, but also facilitates high-resolution design of the display panel.

[0084] Optionally, Figure 3 is a schematic diagram of another pixel circuit provided in an embodiment of this application. As shown in Figure 3, the first control circuit 011 may include: a first control sub-circuit 0111 and a second control sub-circuit 0112.

[0085] The first control sub-circuit 0111 is connected to the first gate control line G1, the data line Data, and the first node N1. The first control sub-circuit 0111 is used to control the connection and disconnection of the data line Data and the first node N1 in response to the first gate control signal. That is, the first control sub-circuit 0111 can control the connection and disconnection of the data line Data and the first node N1.

[0086] For example, the first control sub-circuit 0111 can control the data line Data to be connected to the first node N1 when the potential of the first gate control signal is the first potential, and can control the data line Data to be disconnected from the first node N1 when the potential of the first gate control signal is the second potential.

[0087] The second control sub-circuit 0112 can be connected to the first light-emitting control line EM1, the first power supply line VDD, and the second node N2, respectively. This second control sub-circuit 0112 can be used to control the on / off state of the first power supply line VDD and the second node N2 in response to the first light-emitting control signal. That is, the second control sub-circuit 0112 can control the on / off state of the first power supply line VDD and the second node N2.

[0088] For example, the second control sub-circuit 0112 can control the first power line VDD to conduct with the second node N2 when the potential of the first light-emitting control signal is the first potential, and can control the first power line VDD to disconnect from the second node N2 when the potential of the first light-emitting control signal is the second potential.

[0089] Optionally, referring further to Figure 3, it can also be seen that the second control circuit 013 may include at least two third control sub-circuits 0131 corresponding to at least two second gate control lines G2.

[0090] Each third control sub-circuit 0131 can be connected with a corresponding second gate control line G2 and a first pole and a second pole of a corresponding light emitting element 02, and be configured to control the connection between the first pole and the second pole of the corresponding light emitting element 02 in response to a second gate control signal provided by the corresponding second gate control line G2.

[0091] For example, in combination with FIG. 2 and FIG. 3, on the basis of including three light emitting elements 02-1 / R, 02-2 / B and 02-3 / G, the second control circuit 013 can include three third control sub-circuits 0131 corresponding to the three second gate control lines G2-1, G2-2 and G2-3. For distinction, the third control sub-circuit 0131 connected with the second gate control line G2-1 is identified as 0131-1, the third control sub-circuit 0131 connected with the second gate control line G2-2 is identified as 0131-2, and the third control sub-circuit 0131 connected with the second gate control line G2-3 is identified as 0131-3. On this basis, taking the third control sub-circuit 0131-1 as an example, the light emitting element 02 corresponding to the third control sub-circuit 0131-1 is the red light emitting element 02-1 / R. Correspondingly, the third control sub-circuit 0131-1 can control the first pole and the second pole of the red light emitting element 02-1 / R to be connected through it when the potential of the second gate control signal provided by the connected second gate control line G2-1 is the first potential, and can control the first pole and the second pole of the red light emitting element 02-1 / R to be disconnected through it when the potential of the second gate control signal provided by the connected second gate control line G2-1 is the second potential. The other third control sub-circuits 0131 are the same, and are not described here.

[0092] Optionally, FIG. 4 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application. As shown in FIG. 4, the pixel circuit 01 can further include a third control circuit 014.

[0093] The third control circuit 014 can be connected with the second light emitting control line EM2, the initial power supply line Vinit and the second node N2 respectively. The third control circuit 014 can be configured to control the connection between the initial power supply line Vinit and the second node N2 in response to a second light emitting control signal provided by the second light emitting control line EM2.

[0094] For example, the third control circuit 014 can control the initial power supply line Vinit and the second node N2 to be connected when the potential of the second light emitting control signal provided by the second light emitting control line EM2 is the first potential, so that the initial power signal provided by the initial power supply line Vinit can be transmitted to the second node N2, and can control the initial power supply line Vinit and the second node N2 to be disconnected when the potential of the second light emitting control signal provided by the second light emitting control line EM2 is the second potential.

[0095] Optionally, the initial power signal provided by the initial power supply line Vinit can have a second potential. In this way, the second node N2 can be reset when the initial power signal is transmitted to the second node N2. In addition, if the driving circuit 012 also controls the second node N2 and the third node N3 to be conductive at this time, and the second control circuit 013 also controls the first electrode and the second electrode of each light emitting element 02 to be conductive through the second control circuit 013, the third node N3 and the series nodes (e.g., P-1 and P-2) of each two light emitting elements 02 can also be connected to the initial power supply line Vinit, that is, the initial power supply line Vinit can also transmit the initial power signal to the third node N3 and each series node, so as to reset the third node N3 and each series node.

[0096] It can be understood that by resetting the above nodes, the potential of each node in different pixels 00 can be ensured to jump from a uniform potential to a certain potential, and then the light emitting uniformity of different pixels 00 can be ensured to be good, so that the display effect of the display panel is good.

[0097] Optionally, as can be seen from FIG. 4, the pixel circuit 01 can also include a fourth control circuit 015.

[0098] The fourth control circuit 015 can be connected with the third gate control line G3, the reference power supply line Vref and the first node N1 respectively. The fourth control circuit 015 can be used to control the connection and disconnection between the reference power supply line Vref and the first node N1 in response to the third gate control signal provided by the third gate control line G3.

[0099] For example, the fourth control circuit 015 can control the reference power supply line Vref and the first node N1 to be conductive when the potential of the third gate control signal provided by the third gate control line G3 is the first potential, so that the reference power signal provided by the reference power supply line Vref can be transmitted to the first node N1, and can control the reference power supply line Vref and the first node N1 to be disconnected when the potential of the third gate control signal provided by the third gate control line G3 is the second potential.

[0100] It can be understood that by transmitting the reference power signal to the first node N1, the driving circuit 012 can write the threshold voltage Vth of the transistor included in the driving circuit 012 to the third node N3 based on the potential of the first node N1, so that the driving circuit 012 can offset the influence of the threshold voltage Vth when generating the light emitting driving signal based on the potential of the first node N1 and the potential of the second node N2 to drive the light emitting element 02 to emit light in the subsequent, avoid the influence of the threshold voltage Vth on the light emitting driving signal due to the threshold voltage Vth offset, and ensure that the light emitting effect of the light emitting element 02 is good.

[0101] Optionally, continuing to refer to FIG. 4, it can be seen that the pixel circuit 01 can further include a potential adjusting circuit 016.

[0102] The potential adjusting circuit 016 can be connected with the first node N1 and the third node N3 respectively, and can be used to adjust the potential of one node based on the potential of the other node.

[0103] For example, the potential adjusting circuit 016 can adjust the potentials of the first node N1 and the third node N3 through coupling effect, and serve the purpose of storing the potentials of the first node N1 and the third node N3.

[0104] Optionally, based on FIG. 4, FIG. 5 shows a circuit structure schematic diagram of a pixel circuit. Referring to FIG. 5, it can be seen that the first control sub-circuit 0111 can include a first transistor T1. The second control sub-circuit 0112 can include a second transistor T2.

[0105] The gate of the first transistor T1 can be connected with the first gate control line G1, the first pole of the first transistor T1 can be connected with the data line Data, and the second pole of the first transistor T1 can be connected with the first node N1.

[0106] The gate of the second transistor T2 can be connected with the first light-emitting control line EM1, the first pole of the second transistor T2 can be connected with the first power supply line VDD, and the second pole of the second transistor T2 can be connected with the second node N2.

[0107] Optionally, continuing to refer to FIG. 5, it can be seen that each third control sub-circuit 0131 can include a third transistor T3.

[0108] The gate of the third transistor T3 can be connected with a corresponding second gate control line G2, and the first pole and the second pole of the third transistor T3 can be connected with the first pole and the second pole of a corresponding light-emitting element 02 respectively.

[0109] For example, for distinction, FIG. 5 identifies the third transistor T3 connected with the second gate control line G2-1 as T3-1, identifies the third transistor T3 connected with the second gate control line G2-2 as T3-2, and identifies the third transistor T3 connected with the second gate control line G2-3 as T3-3.

[0110] Optionally, continuing to refer to FIG. 5, it can be seen that the driving circuit 012 can include a fourth transistor T4. Of course, the fourth transistor T4 can also be referred to as a driving transistor DTFT.

[0111] The gate of the fourth transistor T4 can be connected with the first node N1, the first pole of the fourth transistor T4 can be connected with the second node N2, and the second pole of the fourth transistor T4 can be connected with the third node N3.

[0112] It can be understood that the first node N1 can refer to the gate g of the driving transistor DTFT, the second node N2 can refer to the drain d of the driving transistor DTFT, and the third node N3 can refer to the source s of the driving transistor DTFT.

[0113] Optionally, continuing to refer to FIG. 5, it can be seen that the third control circuit 014 can include a fifth transistor T5.

[0114] The gate of the fifth transistor T5 can be connected with the second light-emitting control line EM2, the first pole of the fifth transistor T5 can be connected with the initial power supply line Vinit, and the second pole of the fifth transistor T5 can be connected with the second node N2.

[0115] Optionally, continuing to refer to FIG. 5, it can be seen that the fourth control circuit 015 can include a sixth transistor T6.

[0116] The gate of the sixth transistor T6 can be connected with the third gate control line G3, the first pole of the sixth transistor T6 can be connected with the reference power supply line Vref, and the second pole of the sixth transistor T6 can be connected with the first node N1.

[0117] Optionally, continuing to refer to FIG. 5, it can be seen that the potential adjusting circuit 016 can include a storage capacitor Cst.

[0118] One end of the storage capacitor Cst can be connected with the first node N1, and the other end of the storage capacitor Cst can be connected with the third node N3.

[0119] It can be understood that the pixel 00 shown in FIG. 5 includes a pixel circuit which can be referred to as an 8T1C structure. That is, the pixel 00 can include 8 transistors, 1 storage capacitor, in addition to 1 data line Data, 7 control lines: G1, G2, G3-1, G3-2, G3-3, EM1 and EM2, 2 power supply lines VDD and VDD, 1 initial power supply line Vinit, and 1 reference power supply line Vref, and the plurality of light-emitting elements 02 included in the pixel 00 can be a stacked device. Among them, the 7 control lines can be driven by a GOA circuit, and the stacked device can be driven by a field sequential light-emitting mode, so as to realize full-color light-emitting. The GOA circuit is a display driving circuit formed on the substrate 10 by using an array substrate row driver (gate driver on array, GOA), also known as a gate driving circuit / light-emitting driving circuit. Of course, in some other embodiments, the pixel circuit can also be other structures, such as 7T1C.

[0120] Optionally, the transistors in the pixel circuit shown in FIG. 5 are all N-type transistors. Correspondingly, the effective potential can be a high potential relative to the ineffective potential. Of course, in some other embodiments, the transistors in the pixel circuit can also be all P-type transistors, or can include both P-type transistors and N-type transistors. In addition, the material of the active layer in the P-type transistor can be a P-type transistor of low temperature poly-silicon (LTPS) material. The material of the active layer in the N-type transistor can be an oxide material.

[0121] Optionally, as can be known from FIG. 5 and the foregoing, at least one pixel 00 according to the embodiments of the present application can include three light emitting elements 02. In addition, the colors of the light emitted by the three light emitting elements 02 can be red, blue and green respectively. That is, the three light emitting elements 02 can be a red light emitting element 02-1 / R, a blue light emitting element 02-2 / B and a green light emitting element 02-3 / G respectively.

[0122] Optionally, taking the structure shown in FIG. 5 as an example, FIG. 6 shows a pixel arrangement diagram, and FIG. 7 shows another pixel arrangement diagram.

[0123] As can be seen from FIGS. 6 and 7, the plurality of pixels 00 can be arranged in an array, that is, the display panel can include a plurality of rows and a plurality of columns of pixels 00. Among them, the two pixels 00 shown in FIGS. 6 and 7 are pixels 00 located in the same row and adjacent to each other, and each pixel 00 shown therein can include three light emitting elements 02: a red light emitting element 02-1 / R, a blue light emitting element 02-2 / B and a green light emitting element 02-3 / G.

[0124] In addition, as an optional implementation manner, as shown in FIG. 6, the nodes in each pixel 00 can be independent of each other. The nodes herein can include, for example, a second node N2 (also referred to as a PortA node).

[0125] As another optional implementation manner, as shown in FIG. 7, at least two pixels 00 in the plurality of pixels 00 include pixel circuits 01 that can share at least one target circuit as follows:

[0126] a third control circuit 014.

[0127] and a second control sub-circuit 0112 in the first control circuit 011 connected to the first light emitting control line EM1.

[0128] That is, the pixel circuits 01 included in the at least two pixels 00 can share the second transistor T2 and / or the fifth transistor T5 connected to the PortA node, or also referred to as sharing the PortA node.

[0129] For example, the two pixels 00 shown in FIG. 7 include the pixel circuit 01 which shares the third control circuit 014 and shares the second control sub-circuit 0112. That is, the second transistor T2 and the fifth transistor T5 are shared.

[0130] Thus, in the light emitting stage, the first light emitting control signal provided by the first light emitting control line EM1 has the first potential, so that the N-type second transistor T2 is turned on, and then the first power supply line VDD is connected to the PortA node to drive the light emitting element 02 to emit light. Since the first power signal transmitted by the first power supply line VDD to the PortA node has the high potential, the PortA node can be used as the drain at this time. In the reset stage, the second light emitting control signal provided by the second light emitting control line EM2 has the first potential, so that the N-type fifth transistor T5 is turned on, and then the initial power supply line Vinit is connected to the PortA node to reset the PortA node. Since the initial power signal transmitted by the initial power supply line Vinit to the PortA node has the low potential, the PortA node can be used as the source at this time. That is, the PortA node can separate the driving transistor DTFT through the light emitting transistor (i.e., the second transistor T2) and the reset transistor (i.e., the fifth transistor T5).

[0131] It can be understood that by setting the pixel circuit 01 in at least two pixels 00 to share the at least one target circuit, the number of transistors included in the pixel 00 can be reduced, thereby further facilitating the ultra-high PPI design of the display panel.

[0132] Optionally, it can be seen from FIG. 7 that the at least two pixels 00 sharing the target circuit can be located in the same row. That is, the PortA node can be shared by the multiple pixels 00 located in the same row. Of course, in some other embodiments, the PortA node can also be set to be shared by the multiple pixels 00 located in different rows.

[0133] Optionally, based on FIG. 7, FIG. 8 shows another pixel arrangement diagram. It can be seen from FIG. 8 that the multiple pixels 00 located in the same row can share at least two target circuits, and the two target circuits are located on both sides of the multiple pixels 00 in the row direction X1.

[0134] That is, as shown in FIG. 8, the plurality of pixels 00 in the same row share two target circuits respectively, and each target circuit includes the third control circuit 014 and the second control sub-circuit 0112, that is, includes the second transistor T2 and the fifth transistor T5. And the two target circuits are respectively located on both sides of the plurality of pixels 00 in the same row in the row direction X1. That is, one target circuit is located on the left side and connected with the plurality of pixels 00 in the same row; and the other target circuit is located on the right side and connected with the plurality of pixels 00 in the same row. In this way, not only the wiring can be simplified and the connection is facilitated, but also the IR drop on the connection line can be reduced, so that the uniformity of the potential of the PortA node of each pixel 00 can be ensured to be better, and then the light emitting uniformity of each pixel 00 can be ensured to be better, and the display effect of the display panel is better.

[0135] Optionally, FIG. 8 takes the display panel including n rows of pixels as an example, n is an integer greater than 1. And FIG. 8 identifies the PortA node shared by the first row of pixels 00 as A<1>, and identifies the PortA node shared by the n-th row of pixels 00 as A <n>.

[0136] Optionally, with reference back to FIG. 8, the substrate 10 can have a display area AA and a peripheral area BB (also referred to as a frame area) at least partially surrounding the display area.

[0137] Also, in combination with FIGS. 6 and 7, the at least two light emitting elements 02 can be located in the display area AA.

[0138] Each of the circuits in the pixel circuit 01 can be located in the display area AA.

[0139] Alternatively, as shown in FIG. 8, in the pixel circuit 01, at least one target circuit that is shared can be located in the peripheral area BB, and other circuits except the at least one target circuit can be located in the display area AA. In this way, compared with arranging each of the circuits in the pixel circuit 01 in the display area AA, the number of transistors arranged in the display area AA can be reduced, thereby further facilitating the ultra-high PPI design of the display panel.

[0140] For example, with reference to FIG. 8, in the pixel circuit 01 of the 8T1C structure shown in FIG. 8, the second transistor T2 and the fifth transistor T5 connected to the first light emitting control line EM1 and the second light emitting control line EM2, respectively, can be arranged as the shared target circuit in the frame area, and the other six transistors and the storage capacitor Cst except the two transistors T2 and T5 can be located in the display area AA. In this way, compared with arranging all the transistors in the pixel circuit 01 of the 8T1C structure in the display area AA, the number of transistors arranged in the display area AA can be reduced from eight to six, thereby providing technical support for the ultra-high PPI.

[0141] Based on the above description, it can be known that the embodiment of the present application provides a novel stacked OLED pixel. On the one hand, the independent light emission of the plurality of light emitting elements 02 can be flexibly controlled by the plurality of second gate control lines G2 corresponding to the plurality of light emitting elements 02, thereby laying a foundation for full-color light emission. On the other hand, the threshold voltage shift Vth shift of the driving transistor DFTF can be compensated by using the source follower type internal compensation technology, and each node can be reset by using the initial power supply line Viint, thereby ensuring good light emission uniformity and good display effect. On the other hand, in terms of layout, the number of transistors can be reduced by arranging shared nodes for different pixels, thereby facilitating the ultra-high PPI design of the display panel. That is, the scheme provided by the embodiment of the present application can realize the internal compensation pixel design of the ultra-high PPI, improve the service life of the display panel, and provide good technical support for the ultra-high PPI display product.

[0142] In summary, the embodiment of the present application provides a display panel. The pixel in the display panel includes a pixel circuit and a plurality of light emitting elements which are stacked and have different colors. The pixel circuit can control the plurality of light emitting elements to independently emit light of different colors based on the gate control signals provided by the plurality of gate control lines corresponding to the plurality of light emitting elements. In this way, not only can the display effect be ensured to be better, and a better foundation for full-color light emission be laid, but also the high-resolution design of the display panel can be facilitated.

[0143] The embodiment of the present application also provides a display driving method of a display panel, which can be used to drive the display panel shown in any one of FIGS. 1 to 8. The method includes: in each frame scanning, sequentially lighting at least two subframes of at least two light emitting elements in a pixel, and each subframe includes: a data writing stage and a light emitting stage which are executed in sequence. As shown in FIG. 9:

[0144] In step 901, in the data writing stage, the first control circuit controls the data line and the first node to be conductive in response to the first gate control signal provided by the first gate control line, and the second control circuit controls the first electrode and the second electrode of the light emitting element to be lit to be conductive with the third node and the second power supply line respectively in response to the second gate control signal provided by the second gate control line corresponding to the light emitting element to be lit among the at least two second gate control lines.

[0145] In step 902, in the light emitting stage, the first control circuit controls the first power supply line and the second node to be conductive in response to the first light emitting control signal provided by the first light emitting control line, the second control circuit controls the first electrode and the second electrode of the light emitting element to be lit to be conductive with the third node and the second power supply line respectively in response to the second gate control signal provided by the second gate control line corresponding to the light emitting element to be lit among the at least two second gate control lines, the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node, and outputs the light emitting driving signal to the third node based on the potential of the first node and the potential of the second node, so as to drive the light emitting element to be lit to emit light.

[0146] Optionally, in some embodiments, as can be seen in combination with FIG. 4, the pixel circuit can further include a third control circuit 014 connected to an initial power supply line Vinit to reset each node, and a fourth control circuit 015 connected to a reference power supply line Vref to compensate the threshold voltage Vth of the driving transistor DTFT. On this basis, as can be further seen in combination with FIG. 9, each subframe can further include a reset stage and a compensation stage which are executed in sequence in the data writing stage.

[0147] In the reset stage, the third control circuit controls the initial power supply line to be conductive with the second node in response to the second light emitting control signal provided by the second light emitting control line, the fourth control circuit controls the reference power supply line to be conductive with the first node in response to the third gate control signal provided by the third gate control line, the second control circuit controls the first electrode and the second electrode of the target light emitting element to be conductive in response to the second gate control signal provided by the second gate control line corresponding to the target light emitting element among the at least two second gate control lines, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node.

[0148] In the compensation stage, the fourth control circuit controls the reference power supply line to be conductive with the first node in response to the third gate control signal provided by the third gate control line, the first control circuit controls the first power supply line to be conductive with the second node in response to the first light emitting control signal provided by the first light emitting control line, the second control circuit controls the first electrode and the second electrode of the light emitting element to be conductive with the third node and the second power supply line respectively in response to the second gate control signal provided by the second gate control line not corresponding to the light emitting element to be lightened among the at least two second gate control lines, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node.

[0149] Optionally, in the structure shown in FIG. 5, the transistors in the pixel circuit 01 are all N-type transistors, and the pixel 00 includes three light emitting elements 02, for example, a red light emitting element 02-1 / R, a blue light emitting element 02-2 / B and a green light emitting element 02-3 / G, FIG. 10 shows a driving timing diagram of a pixel circuit, and FIG. 11 shows a signal simulation diagram based on FIG. 10. In combination with FIG. 10 and FIG. 11, the driving principle of the pixel circuit 01 provided by the embodiment of the present application is described as follows:

[0150] One frame (One Frame) scanning can be divided into three sub-frame (Sub Frame) scanning, that is, divided into three parts, and the three parts can correspond to the light emitting time periods of the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G respectively. For example, FIG. 10 divides one frame scanning into three sub-frame scanning 1 / 3Frame. On this basis, the light emitting time period of each light emitting element (that is, each sub-frame) can be further divided into four stages T01, T02, T03 and T04 executed in sequence, which correspond to the reset stage, the compensation stage, the data writing stage and the light emitting stage shown in FIG. 9 respectively.

[0151] To distinguish, FIG. 10 identifies the subframe corresponding to the light emitting period of the red light emitting element 02-1 / R as 1 / 3Frame: Red Emitting, and identifies the four stages T01, T02, T03, and T04 included in the 1 / 3Frame: Red Emitting as T01-R, T02-R, T03-R, and T04-R, respectively. FIG. 10 identifies the subframe corresponding to the light emitting period of the blue light emitting element 02-2 / B as 1 / 3Frame: Blue Emitting, and identifies the four stages T01, T02, T03, and T04 included in the 1 / 3Frame: Blue Emitting as T01-B, T02-B, T03-B, and T04-B, respectively. FIG. 10 identifies the subframe corresponding to the light emitting period of the green light emitting element 02-3 / G as 1 / 3Frame: Green Emitting, and identifies the four stages T01, T02, T03, and T04 included in the 1 / 3Frame: Green Emitting as T01-G, T02-G, T03-G, and T04-G, respectively.

[0152] For the red light emitting element 02-1 / R, i.e., in the 1 / 3Frame: Red Emitting:

[0153] (1) In the T01-R stage, i.e., in the reset stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control lines G2-3, and the potential of the first emission control signal provided by the first emission control line EM1 can all be low potentials. The potential of the second gate control signal provided by the second gate control lines G2-1 and G2-2, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the second emission control signal provided by the second emission control line EM2 can all be high potentials.

[0154] Thus, the first transistor T1, the second transistor T2 and the third transistor T3-3 can be all turned off, and the third transistor T3-1 and T3-2, the fifth transistor T5 and the sixth transistor T6 can be all turned on. Further, the third node N3 can be connected to the series node P-1 (i.e. the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, the series node P-1 and P-2 (i.e. the anode and the cathode of the blue light emitting element 02-2 / B) can be connected through the turned-on third transistor T3-2, the initial power supply line Vinit can be connected to the second node N2 through the turned-on fifth transistor T5, and the reference power supply line Vref can be connected to the first node N1 through the turned-on sixth transistor T6. Accordingly, the reference power supply line Vref can transmit the reference power supply signal to the first node N1, so that the fourth transistor T4 (i.e. the driving transistor DTFT) is initially turned on, and further the second node N2 can be connected to the third node N3 through the turned-on fourth transistor T4. It can be known that, on this basis, the initial power supply line Vinit can transmit the initial power supply signal to the second node N2, and the initial power supply signal transmitted to the second node N2 can be further transmitted to the third node N3 and the series node P-2 and P-1. That is, the series node P-2 and P-1, and the third node N3 and the second node N2 can be connected to the initial power supply line Vinit to receive the initial power supply signal. That is, in the reset stage, the potential of the first node N1 can be the potential Vref1 of the reference power supply signal, and the potentials of the series node P-2 and P-1, and the third node N3 and the second node N2 can all be the potential Vinit1 of the initial power supply signal.

[0155] (2) In the T02-R stage, i.e. in the compensation stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-1, and the potential of the second emission control signal provided by the second emission control line EM2 can all be low potentials. The potential of the second gate control signal provided by the second gate control line G2-2 and G2-3, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the first emission control signal provided by the first emission control line EM1 can all be high potentials.

[0156] In this way, the first transistor T1, the third transistor T3-1 and the fifth transistor T5 can be turned off, and the second transistor T2, the third transistor T3-2 and T3-3, and the sixth transistor T6 can be turned on. Further, the first power supply line VDD can be connected to the second node N2 through the turned-on second transistor T2, the series node P-1 can be connected to the series node P-2 (i.e., the anode and the cathode of the blue light emitting element 02-2 / B) through the turned-on third transistor T3-2, the series node P-2 can be connected to the pull-down power supply line VSS (i.e., the anode and the cathode of the green light emitting element 02-3 / G) through the turned-on third transistor T3-3, and the reference power supply line Vref can be connected to the first node N1 through the turned-on sixth transistor T6. Accordingly, the reference power supply line Vref can continue to transmit the reference power supply signal to the first node N1, i.e., the potential of the first node N1 can be kept as the potential Vref1 of the reference power supply signal in the last stage, so that the fourth transistor T4 is kept turned on, and further the second node N2 can be connected to the third node N3 through the turned-on fourth transistor T4. The first power supply line VDD can transmit the first power supply signal to the second node N2. On this basis, through the coupling effect of the storage capacitor Cst, the potential of the third node N3 can be raised, and the fourth transistor T4 can be turned off when the potential of the third node N3 is raised to Vref1+Vth. Wherein, Vth can refer to the threshold voltage of the fourth transistor T4.

[0157] (3) In the T03-R stage, i.e., in the data writing stage, the potential of the second gate control signal provided by the second gate control line G2-1, the potential of the third gate control signal provided by the third gate control line G3, the potential of the first emission control signal provided by the first emission control line EM1, and the potential of the second emission control signal provided by the second emission control line EM2 can all be low potentials. The potential of the first gate control signal provided by the first gate control line G1, and the potential of the second gate control signal provided by the second gate control lines G2-2 and G2-3 can all be high potentials.

[0158] In this way, the second transistor T2, the third transistor T3-1, the fifth transistor T5 and the sixth transistor T6 can be all turned off, and the first transistor T1, and the third transistors T3-2 and T3-3 can be all turned on. Further, the data line Data can be connected to the first node N1 through the turned-on first transistor T1, and the series node P-1 and the series node P-2 (i.e., the anode and the cathode of the blue light emitting element 02-2 / B) can be connected through the turned-on third transistor T3-2, and the series node P-2 and the pull-down power line VSS (i.e., the anode and the cathode of the green light emitting element 02-3 / G) can be connected through the turned-on third transistor T3-3. Accordingly, the data line Data can transmit a data signal to the first node N1. For distinction, the potential of the data signal driving the red light emitting element 02-1 / R is denoted as Vdatar. That is, in this data writing stage, the potential of the first node N1 can be updated to Vdatar.

[0159] (4) In the T04-R stage, i.e., in the light emitting stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-1, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be low potentials. The potential of the second gate control signal provided by the second gate control lines G2-2 and G2-3, and the potential of the first light emitting control signal provided by the first light emitting control line EM1 can all be high potentials.

[0160] Thus, the first transistor T1, the third transistor T3-1, the fifth transistor T5 and the sixth transistor T6 can be all turned off, and the second transistor T2, and the third transistors T3-2 and T3-3 can be all turned on. Further, the first power supply line VDD can be connected to the second node N2 through the turned-on second transistor T2, and the series node P-1 and the series node P-2 (i.e., the anode and the cathode of the blue light emitting element 02-2 / B) can be connected through the turned-on third transistor T3-2, and the series node P-2 and the pull-down power supply line VSS (i.e., the anode and the cathode of the green light emitting element 02-3 / G) can be connected through the turned-on third transistor T3-3. In addition, the fourth transistor T4 can be further fully turned on under the coupling of the storage capacitor Cst. Accordingly, the first power supply line VDD can transmit the first power supply signal to the second node N2. And for the red light emitting element 02-1 / R, a path can be formed between the first power supply line VDD and the second power supply line VSS, and the fourth transistor T4 can transmit the light emitting driving signal to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, so that the red light emitting element 02-1 / R emits light under the pressure difference effect of the light emitting driving signal and the second power supply signal provided by the second power supply line VSS.

[0161] For the blue light emitting element 02-2 / B, i.e., in 1 / 3 Frame: Blue Emitting:

[0162] (1) In the T01-B stage, i.e., in the reset stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-3, and the potential of the first light emitting control signal provided by the first light emitting control line EM1 can all be low potentials. The potential of the second gate control signal provided by the second gate control lines G2-1 and G2-2, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be high potentials.

[0163] Thus, the first transistor T1, the second transistor T2 and the third transistor T3-3 can be all turned off, and the third transistor T3-1 and T3-2, the fifth transistor T5 and the sixth transistor T6 can be all turned on. Further, the third node N3 can be connected to the series node P-1 (i.e. the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, the series node P-1 and P-2 (i.e. the anode and the cathode of the blue light emitting element 02-2 / B) can be connected through the turned-on third transistor T3-2, the initial power supply line Vinit can be connected to the second node N2 through the turned-on fifth transistor T5, and the reference power supply line Vref can be connected to the first node N1 through the turned-on sixth transistor T6. Accordingly, the reference power supply line Vref can transmit the reference power supply signal to the first node N1, so that the fourth transistor T4 is initially turned on, and further, the second node N2 can be connected to the third node N3 through the turned-on fourth transistor T4. Based on this, the initial power supply line Vinit can transmit the initial power supply signal to the second node N2, and the initial power supply signal transmitted to the second node N2 can be further transmitted to the third node N3 and the series node P-2 and P-1. That is, the series node P-2 and P-1, and the third node N3 and the second node N2 can be connected to the initial power supply line Vinit to receive the initial power supply signal. That is, in the reset stage, the potential of the first node N1 can be the potential Vref1 of the reference power supply signal, and the potentials of the series node P-2 and P-1, and the third node N3 and the second node N2 can all be the potential Vinit1 of the initial power supply signal.

[0164] (2) In the T02-B stage, i.e. in the compensation stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-2, and the potential of the second emission control signal provided by the second emission control line EM2 can all be low potentials. The potential of the second gate control signal provided by the second gate control line G2-1 and G2-3, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the first emission control signal provided by the first emission control line EM1 can all be high potentials.

[0165] In this way, the first transistor T1, the third transistor T3-2 and the fifth transistor T5 can be turned off, and the second transistor T2, the third transistor T3-1 and T3-3, and the sixth transistor T6 can be turned on. Further, the first power supply line VDD can be connected to the second node N2 through the turned-on second transistor T2, the third node N3 can be connected to the series node P-1 (i.e., the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, the series node P-2 can be connected to the pull-down power supply line VSS (i.e., the anode and the cathode of the green light emitting element 02-3 / G) through the turned-on third transistor T3-3, and the reference power supply line Vref can be connected to the first node N1 through the turned-on sixth transistor T6. Accordingly, the reference power supply line Vref can continue to transmit the reference power supply signal to the first node N1, i.e., the potential of the first node N1 can be kept as the potential Vref1 of the reference power supply signal in the last stage, so that the fourth transistor T4 is kept turned on, and further the second node N2 can be connected to the third node N3 through the turned-on fourth transistor T4. The first power supply line VDD can transmit the first power supply signal to the second node N2. On this basis, through the coupling effect of the storage capacitor Cst, the potential of the third node N3 can be raised, and the fourth transistor T4 can be turned off when the potential of the third node N3 is raised to Vref1+Vth. Wherein, Vth can refer to the threshold voltage of the fourth transistor T4.

[0166] (3) In the T03-B stage, i.e., in the data writing stage, the potential of the second gate control signal provided by the second gate control line G2-2, the potential of the third gate control signal provided by the third gate control line G3, the potential of the first light emitting control signal provided by the first light emitting control line EM1, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be low potentials. The potential of the first gate control signal provided by the first gate control line G1, and the potential of the second gate control signal provided by the second gate control lines G2-1 and G2-3 can all be high potentials.

[0167] In this way, the second transistor T2, the third transistor T3-1, the fifth transistor T5 and the sixth transistor T6 can be all turned off, and the first transistor T1, the third transistor T3-1 and the third transistor T3-3 can be all turned on. Further, the data line Data can be connected to the first node N1 through the turned-on first transistor T1, the third node N3 can be connected to the series node P-1 (i.e., the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, and the series node P-2 can be connected to the pull-down power line VSS (i.e., the anode and the cathode of the green light emitting element 02-3 / G) through the turned-on third transistor T3-3. Accordingly, the data line Data can transmit a data signal to the first node N1. For distinction, the potential of the data signal driving the red light emitting element 02-2 / B is denoted as Vdatab. That is, in this data writing stage, the potential of the first node N1 can be updated to Vdatab.

[0168] (4) In the T04-B stage, i.e., in the light emitting stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-2, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be low potentials. The potential of the second gate control signal provided by the second gate control line G2-1 and G2-3, and the potential of the first light emitting control signal provided by the first light emitting control line EM1 can all be high potentials.

[0169] Thus, the first transistor T1, the third transistor T3-2, the fifth transistor T5 and the sixth transistor T6 can be all turned off, and the second transistor T2, and the third transistors T3-1 and T3-3 can be all turned on. Further, the first power supply line VDD can be connected to the second node N2 through the turned-on second transistor T2, and the third node N3 can be connected to the series node P-1 (i.e., the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, and the series node P-2 can be connected to the pull-down power supply line VSS (i.e., the anode and the cathode of the green light emitting element 02-3 / G) through the turned-on third transistor T3-3. In addition, the fourth transistor T4 can be further fully turned on under the coupling of the storage capacitor Cst. Accordingly, the first power supply line VDD can transmit the first power supply signal to the second node N2. And for the blue light emitting element 02-2 / B, a path can be formed between the first power supply line VDD and the second power supply line VSS, and the fourth transistor T4 can transmit the light emitting driving signal to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, so that the blue light emitting element 02-2 / B emits light under the pressure difference effect of the light emitting driving signal and the second power supply signal provided by the second power supply line VSS.

[0170] For the green light emitting element 02-3 / G, i.e., in 1 / 3 Frame: Green Emitting:

[0171] (1) In the T01-G stage, i.e., in the reset stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-3, and the potential of the first light emitting control signal provided by the first light emitting control line EM1 can all be low potentials. The potential of the second gate control signal provided by the second gate control lines G2-1 and G2-2, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be high potentials.

[0172] Thus, the first transistor T1, the second transistor T2 and the third transistor T3-3 can be all turned off, and the third transistor T3-1 and T3-2, the fifth transistor T5 and the sixth transistor T6 can be all turned on. Further, the third node N3 can be connected to the series node P-1 (i.e. the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, the series node P-1 and P-2 (i.e. the anode and the cathode of the blue light emitting element 02-2 / B) can be connected through the turned-on third transistor T3-2, the initial power supply line Vinit can be connected to the second node N2 through the turned-on fifth transistor T5, and the reference power supply line Vref can be connected to the first node N1 through the turned-on sixth transistor T6. Accordingly, the reference power supply line Vref can transmit the reference power supply signal to the first node N1, so that the fourth transistor T4 is initially turned on, and further, the second node N2 can be connected to the third node N3 through the turned-on fourth transistor T4. Based on this, the initial power supply line Vinit can transmit the initial power supply signal to the second node N2, and the initial power supply signal transmitted to the second node N2 can be further transmitted to the third node N3 and the series node P-2 and P-1. That is, the series node P-2 and P-1, and the third node N3 and the second node N2 can be connected to the initial power supply line Vinit to receive the initial power supply signal. That is, in the reset stage, the potential of the first node N1 can be the potential Vref1 of the reference power supply signal, and the potentials of the series node P-2 and P-1, and the third node N3 and the second node N2 can all be the potential Vinit1 of the initial power supply signal.

[0173] (2) In the T02-G stage, i.e. in the compensation stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-3, and the potential of the second emission control signal provided by the second emission control line EM2 can all be low potentials. The potential of the second gate control signal provided by the second gate control line G2-1 and G2-2, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the first emission control signal provided by the first emission control line EM1 can all be high potentials.

[0174] In this way, the first transistor T1, the third transistor T3-3 and the fifth transistor T5 can be turned off, and the second transistor T2, the third transistor T3-1 and T3-2, and the sixth transistor T6 can be turned on. Further, the first power supply line VDD can be connected to the second node N2 through the turned-on second transistor T2, the third node N3 can be connected to the series node P-1 (i.e., the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, the series node P-1 can be connected to the series node P-2 (i.e., the anode and the cathode of the blue light emitting element 02-2 / B) through the turned-on third transistor T3-2, and the reference power supply line Vref can be connected to the first node N1 through the turned-on sixth transistor T6. Accordingly, the reference power supply line Vref can continue to transmit the reference power supply signal to the first node N1, i.e., the potential of the first node N1 can be kept as the potential Vref1 of the reference power supply signal in the last stage, so that the fourth transistor T4 is kept turned on, and further the second node N2 can be connected to the third node N3 through the turned-on fourth transistor T4. The first power supply line VDD can transmit the first power supply signal to the second node N2. On this basis, through the coupling effect of the storage capacitor Cst, the potential of the third node N3 can be raised, and the fourth transistor T4 can be turned off when the potential of the third node N3 is raised to Vref1+Vth. Wherein, Vth can refer to the threshold voltage of the fourth transistor T4.

[0175] (3) In the T03-G stage, i.e., in the data writing stage, the potential of the second gate control signal provided by the second gate control line G2-3, the potential of the third gate control signal provided by the third gate control line G3, the potential of the first light emitting control signal provided by the first light emitting control line EM1, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be low potentials. The potential of the first gate control signal provided by the first gate control line G1, and the potential of the second gate control signal provided by the second gate control lines G2-1 and G2-2 can all be high potentials.

[0176] Thus, the second transistor T2, the third transistor T3-3, the fifth transistor T5 and the sixth transistor T6 can be all turned off, and the first transistor T1, the third transistor T3-1 and T3-2 can be all turned on. Further, the data line Data can be connected to the first node N1 through the turned-on first transistor T1, the third node N3 can be connected to the serial node P-1 (i.e. the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, and the serial node P-1 can be connected to the serial node P-2 (i.e. the anode and the cathode of the blue light emitting element 02-2 / B) through the turned-on third transistor T3-2. Accordingly, the data line Data can transmit the data signal to the first node N1. For distinction, the potential of the data signal driving the green light emitting element 02-3 / G is denoted as Vdatag. That is, in the data writing stage, the potential of the first node N1 can be updated to Vdatag.

[0177] (4) In the T04-G stage, i.e. in the light emitting stage, the potential of the first gate control signal provided by the first gate control line G1, the potential of the second gate control signal provided by the second gate control line G2-3, the potential of the third gate control signal provided by the third gate control line G3, and the potential of the second light emitting control signal provided by the second light emitting control line EM2 can all be low potentials. The potential of the second gate control signal provided by the second gate control line G2-1 and G2-2, and the potential of the first light emitting control signal provided by the first light emitting control line EM1 can all be high potentials.

[0178] In this way, the first transistor T1, the third transistor T3-3, the fifth transistor T5 and the sixth transistor T6 can be all turned off, and the second transistor T2, the third transistor T3-1 and the third transistor T3-2 can be all turned on. In turn, the first power supply line VDD can be connected to the second node N2 through the turned-on second transistor T2, the third node N3 can be connected to the serial node P-1 (i.e., the anode and the cathode of the red light emitting element 02-1 / R) through the turned-on third transistor T3-1, and the serial node P-1 can be connected to the serial node P-2 (i.e., the anode and the cathode of the blue light emitting element 02-2 / B) through the turned-on third transistor T3-2. In addition, the fourth transistor T4 can be further turned on under the coupling of the storage capacitor Cst. Accordingly, the first power supply line VDD can transmit the first power supply signal to the second node N2. And for the green light emitting element 02-3 / G, a path can be formed between the first power supply line VDD and the second power supply line VSS, and the fourth transistor T4 can transmit the light emitting driving signal to the third node N3 based on the potential of the first node N1 and the potential of the second node N2, so that the green light emitting element 02-3 / G emits light under the pressure difference between the light emitting driving signal and the second power supply signal provided by the second power supply line VSS.

[0179] Optionally, FIG. 11 also schematically shows the driving current I DTFT flowing through the driving transistor DTFT, and the light emitting driving currents I oledr, I oledb and I oledg flowing through the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G, respectively. It can be seen from FIGS. 10 and 11 that the embodiment of the present application can realize the field sequential light emission of the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G by sequentially lighting the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G, and the brightness of the red light emitting element 02-1 / R, the blue light emitting element 02-2 / B and the green light emitting element 02-3 / G can be independently controlled by flexibly setting the potentials Vdata r, Vdata b and Vdata g of the data signals. In this way, the full-color light emitting effect can be realized within a fixed frame frequency.

[0180] It can be understood that the display driving method has basically the same technical effects as the display panel, and therefore the technical effects of the display driving method will not be described again for the purpose of brevity.

[0181] The embodiment of the present application also provides a display device. As shown in FIG. 12, the display device comprises the display driving circuit 100 and the display panel 000 as described above.

[0182] The display driving circuit 100 is connected with each signal line in the display panel 000, and is configured to provide signals to each signal line. Optionally, the display driving circuit 100 can be the GOA circuit described above.

[0183] Optionally, the display device can be an OLED display device, an AMOLED display device, or the like. The OLED display technology has been widely recognized in the market due to its advantages such as high resolution and high contrast. The display device can also be any product or component with display function, such as a mobile phone, a tablet computer, a flexible display device, a television, and a display.

[0184] It can be understood that the display device has substantially the same technical effects as the display panel described above, and therefore the technical effects of the display device will not be described again for the purpose of brevity.

[0185] It should be understood that the terms used in the embodiments of the present application are used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meaning understood by a person with ordinary skills in the art to which the present application belongs.

[0186] As in the embodiments of the present application, the terms "first" and "second" are only used for descriptive purposes, and should not be understood as indicating or implying relative importance. The term "a plurality of" refers to two or more, unless otherwise defined. Similarly, "one" or "an" and the like do not represent a quantitative limitation, but represent the existence of at least one. The terms "include" or "contain" and the like mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0187] The above description is only optional embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.< / n>

Claims

1. A display panel, the display panel comprising: A substrate and a plurality of pixels on the substrate, at least one of the pixels comprising: pixel circuitry and at least two light emitting elements stacked on the substrate and having different colors, the pixel circuitry comprising: a first control circuit connected to a first gate control line, a first light emitting control line, a data line, a first power supply line, a first node and a second node respectively, and configured to control the data line and the first node in response to a first gate control signal provided by the first gate control line, and control the first power supply line and the second node in response to a first light emitting control signal provided by the first light emitting control line; a driving circuit connected to the first node, the second node and a third node respectively, and configured to control the second node and the third node in response to a potential of the first node, and control a potential of the third node based on the potential of the first node and a potential of the second node, the at least two light emitting elements being connected in series between the third node and a second power supply line; a second control circuit connected to at least two second gate control lines and a first electrode and a second electrode of each of the light emitting elements respectively, the at least two second gate control lines corresponding to the at least two light emitting elements one by one, and configured to control the first electrode and the second electrode of the corresponding light emitting element in response to a second gate control signal provided by each of the second gate control lines.

2. The display panel of claim 1, wherein, The first control circuit comprises: a first control sub-circuit connected to the first gate control line, the data line and the first node respectively, and configured to control the data line and the first node in response to the first gate control signal; a second control sub-circuit connected to the first light emitting control line, the first power supply line and the second node respectively, and configured to control the first power supply line and the second node in response to the first light emitting control signal.

3. The display panel of claim 2, wherein, The first control sub-circuit comprises a first transistor, and the second control sub-circuit comprises a second transistor; a gate of the first transistor is connected to the first gate control line, a first electrode of the first transistor is connected to the data line, and a second electrode of the first transistor is connected to the first node; a gate of the second transistor is connected to the first light emitting control line, a first electrode of the second transistor is connected to the first power supply line, and a second electrode of the second transistor is connected to the second node.

4. The display panel according to any one of claims 1 to 3, wherein, The second control circuit comprises: at least two third control sub-circuits corresponding to the at least two second gate control lines one by one, each of the third control sub-circuits being connected to a corresponding one of the second gate control lines and a first electrode and a second electrode of a corresponding one of the light emitting elements respectively, and configured to control the first electrode and the second electrode of the corresponding one of the light emitting elements in response to a second gate control signal provided by the corresponding one of the second gate control lines.

5. The display panel of claim 4, wherein, Each of the third control sub-circuits comprises a third transistor. A gate of the third transistor is connected with a corresponding second gate control line, and a first electrode and a second electrode of the third transistor are connected with a first electrode and a second electrode of a corresponding light emitting element respectively.

6. The display panel according to any one of claims 1 to 5, wherein, The driving circuit comprises a fourth transistor. A gate of the fourth transistor is connected with the first node, a first electrode of the fourth transistor is connected with the second node, and a second electrode of the fourth transistor is connected with the third node.

7. The display panel according to any one of claims 1 to 6, wherein, The pixel circuit further comprises: A third control circuit is connected with a second light emitting control line, an initial power supply line and the second node respectively, and is configured to control the initial power supply line and the second node in response to a second light emitting control signal provided by the second light emitting control line.

8. The display panel of claim 7, wherein, The third control circuit comprises a fifth transistor. A gate of the fifth transistor is connected with the second light emitting control line, a first electrode of the fifth transistor is connected with the initial power supply line, and a second electrode of the fifth transistor is connected with the second node.

9. The display panel of claim 7 or 8, wherein, At least two of the plurality of pixels comprise pixel circuits sharing at least one target circuit. The third control circuit; And a second control sub-circuit in the first control circuit connected with the first light emitting control line.

10. The display panel of claim 9, wherein, The plurality of pixels are arranged in an array, and the at least two pixels sharing the target circuit are located in the same row.

11. The display panel of claim 10, wherein, At least two target circuits are shared by the plurality of pixels located in the same row, and the two target circuits are located on both sides of the plurality of pixels in the row direction.

12. The display panel of any of claims 9 to 11, wherein, The substrate has a display area and a peripheral area at least partially surrounding the display area; The at least two light emitting elements are located in the display area; Each of the pixel circuits is located in the display area; or, in the pixel circuit, the at least one target circuit shared is located in the peripheral area, and other circuits except the at least one target circuit are located in the display area.

13. The display panel according to any one of claims 1 to 12, wherein, The pixel circuit further comprises: A fourth control circuit is connected with a third gate control line, a reference power supply line and the first node respectively, and is configured to control the reference power supply line and the first node in response to a third gate control signal provided by the third gate control line.

14. The display panel of claim 13, wherein, The fourth control circuit comprises a sixth transistor. A gate of the sixth transistor is connected with the third gate control line, a first electrode of the sixth transistor is connected with the reference power supply line, and a second electrode of the sixth transistor is connected with the first node.

15. The display panel according to any one of claims 1 to 14, wherein, The pixel circuit further comprises a potential adjusting circuit; The potential adjusting circuit is connected with the first node and the third node respectively, and is configured to adjust a potential of one node based on a potential of the other node.

16. The display panel of claim 15, wherein, The potential adjusting circuit comprises a storage capacitor. One end of the storage capacitor is connected with the first node, and the other end of the storage capacitor is connected with the third node.

17. The display panel of any of claims 1 to 16, wherein, At least one of the pixels comprises three light emitting elements; And the colors of the light emitted by the three light emitting elements are red, blue and green respectively.

18. A display driving method of a display panel, for driving the display panel as claimed in any one of claims 1 to 17, the method comprising: In each frame scanning, at least two sub-frames of at least two light emitting elements in a pixel are sequentially lighted, and each of the sub-frames comprises: a data writing stage and a light emitting stage which are sequentially performed; In the data writing stage, the first control circuit controls the data line and the first node to be conductive in response to the first gate control signal provided by the first gate control line, and the second control circuit controls the first electrode and the second electrode of the light emitting element to be lighted to be conductive with the third node and the second power line in response to the second gate control signal provided by the second gate control line which does not correspond to the light emitting element to be lighted among the at least two second gate control lines; In the light emitting stage, the first control circuit controls the first power line and the second node to be conductive in response to the first light emitting control signal provided by the first light emitting control line, the second control circuit controls the first electrode and the second electrode of the light emitting element to be lighted to be conductive with the third node and the second power line in response to the second gate control signal provided by the second gate control line which does not correspond to the light emitting element to be lighted among the at least two second gate control lines, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node, and outputs a light emitting driving signal to the third node based on the potential of the first node and the potential of the second node, so as to drive the light emitting element to be lighted to emit light.

19. The method of claim 18, wherein, Each of the sub-frames further comprises: a reset stage and a compensation stage which are sequentially performed in the data writing stage; In the reset stage, the third control circuit controls the initial power line and the second node to be conductive in response to the second light emitting control signal provided by the second light emitting control line, the fourth control circuit controls the reference power line and the first node to be conductive in response to the third gate control signal provided by the third gate control line, the second control circuit controls the first electrode and the second electrode of the target light emitting element to be conductive in response to the second gate control signal provided by the second gate control line which corresponds to the target light emitting element among the at least two second gate control lines, the target light emitting element is the light emitting element whose second electrode is not directly connected to the second power line, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node; In the compensation stage, the fourth control circuit controls the reference power line and the first node to be conductive in response to the third gate control signal provided by the third gate control line, the first control circuit controls the first power line and the second node to be conductive in response to the first light emitting control signal provided by the first light emitting control line, the second control circuit controls the first electrode and the second electrode of the light emitting element to be lighted to be conductive with the third node and the second power line in response to the second gate control signal provided by the second gate control line which does not correspond to the light emitting element to be lighted among the at least two second gate control lines, and the driving circuit controls the second node and the third node to be conductive in response to the potential of the first node.

20. A display device comprising: The display driving circuit and the display panel as claimed in any one of claims 1 to 17. The display driving circuit is connected with each signal line in the display panel and is used for providing signals to the signal lines.

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