Semiconductor device

Abstract

Provided is a novel semiconductor device. The semiconductor device has: a functional circuit having a first transistor; and a power supply circuit having a second transistor, wherein the first transistor is formed on a front surface side of a substrate, the second transistor is formed on a rear surface side of the substrate, the first transistor is electrically connected to the second transistor via a conductive layer formed on a rear surface side, the first transistor includes silicon in a semiconductor layer in which a channel is formed, and the second transistor includes an oxide semiconductor in a semiconductor layer in which a channel is formed.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), and memories (storage devices) has progressed. These semiconductor devices are used in a variety of electronic devices such as computers and personal digital assistants. Furthermore, with the development of electronic devices, there is a demand for further miniaturization, higher integration, multi-functionality, power saving, improved operating speed, and reduced occupied area for these semiconductor devices.

[0004] Aiming at further integration of semiconductor devices, research and development is being actively conducted on a configuration in which multiple dies (e.g., silicon dies) each having circuits with different functions are stacked in a three-dimensional manner (e.g., Non-Patent Documents 1 and 2).

[0005] The stacked multiple dies are designed to reduce the wiring load by using technologies such as through-electrodes such as TSVs (Through Silicon Vias) or Cu-Cu (Copper-Copper) direct bonding technology, thereby achieving power savings and high speed (low delay) in the semiconductor device.

[0006] W. Gomes et al., ISSCC Dig. Tech. Papers, pp. 42-43, 2022. M. Park et al., ISSCC Dig. Tech. Papers, pp. 444-445, 2022. Takashi Koida, "High Mobility Transparent Conductive Films," National Research and Development Agency, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] A stable voltage supply is important for semiconductor devices to achieve the desired performance. However, as semiconductor devices become increasingly miniaturized, the width of wiring becomes thinner, which can lead to a deterioration in the uniformity of the voltage supplied by the power supply circuit within the semiconductor device.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device capable of stable voltage supply, a power-saving semiconductor device, or the like, a semiconductor device with improved operation speed, a highly reliable semiconductor device, or a novel semiconductor device, or the like.

[0009] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification, drawings, etc., and can be extracted as appropriate from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and / or other problems.

[0010] (1) One aspect of the present invention is a semiconductor device including a first functional circuit having a first transistor and a power supply circuit having a second transistor, wherein the first transistor is formed on a first surface side of a substrate, the second transistor is formed on a second surface side of the substrate, the first transistor is electrically connected to the second transistor via a conductive layer formed on the second surface side, the first transistor includes silicon in a semiconductor layer in which a channel is formed, and the second transistor includes an oxide semiconductor in the semiconductor layer in which a channel is formed.

[0011] (2) Another aspect of the present invention is a semiconductor device including a first functional circuit having a first transistor, a power supply circuit having a second transistor, and a second functional circuit having a third transistor, wherein the first transistor is formed on a first surface side of a substrate, the second transistor is formed on a second surface side of the substrate, and the third transistor is formed on the second surface side of the substrate so as to overlap with the power supply circuit, the first transistor is electrically connected to the second transistor via a conductive layer formed on the second surface side, and the third transistor is electrically connected to the conductive layer, the first transistor includes silicon in a semiconductor layer in which a channel is formed, and the second transistor and the third transistor each include an oxide semiconductor in the semiconductor layer in which a channel is formed.

[0012] The oxide semiconductor preferably contains indium.

[0013] Each of the first and second functional circuits may include at least one of a CPU, a graphics processing unit (GPU), a field programmable gate array (FPGA), a memory, a digital circuit, and an analog circuit. The power supply circuit may include at least one of a switching regulator circuit, a linear regulator circuit, and a charge pump circuit.

[0014] The conductive layer formed on the second surface side can function as, for example, a power supply line or a clock signal line.

[0015] According to one embodiment of the present invention, a semiconductor device capable of stable voltage supply, a power-saving semiconductor device, an improved operating speed, a highly reliable semiconductor device, or a novel semiconductor device can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be derived by a person skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions.

[0017] FIGS. 1A and 1B are perspective views of a semiconductor device. FIG. 2 is a perspective view of a semiconductor device. FIG. 3 is a perspective view of a semiconductor device. FIGS. 4A, 4B, and 4C are diagrams illustrating a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a semiconductor device. FIGS. 6A and 6B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 7A and 7B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 8A, 8B, and 8C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 9A and 9B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 10A, 10B, and 10C are diagrams illustrating a power supply circuit. FIGS. 11A and 11B are diagrams illustrating a power supply circuit. FIGS. 12A, 12B, and 12C are diagrams illustrating a power supply circuit. FIG. 13 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 14A, 14B, 14C, 14D, 14E, and 14F are diagrams illustrating circuit configuration examples of memory cells. FIGS. 15A and 15B are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 16A, 16B, 16C, and 16D are diagrams illustrating an example of a transistor configuration. FIGS. 17A and 17B are diagrams illustrating an example of a transistor configuration. FIGS. 18A and 18B are diagrams illustrating an example of a transistor configuration. FIGS. 19A and 19B are diagrams illustrating an example of a transistor configuration. FIGS. 20A and 20B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 20C is a cross-sectional view illustrating an indium oxide film. FIGS. 21A and 21B are diagrams illustrating an example of an electronic component. FIGS. 22A and 22B are diagrams illustrating an example of an electronic device, and FIGS. 22C, 22D, and 22E are diagrams illustrating an example of a mainframe computer. FIG. 23A is a diagram illustrating an example of space equipment. FIG. 23B is a diagram illustrating an example of a storage system applicable to a data center.

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0021] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the descriptions of some components may be omitted in plan views, cross-sectional views, perspective views, etc.

[0022] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0023] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0024] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0025] In this specification and the like, terms such as "overlap" and "superimpose" do not limit the stacking order or stacking direction of components. For example, the expression "electrode B overlapping insulating layer A" is not limited to a state in which electrode B is formed on insulating layer A, but does not exclude a state in which electrode B is formed under insulating layer A or a state in which electrode B is formed on the right (or left) side of insulating layer A.

[0026] In this specification, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expressions "B adjacent to A" or "B close to A" do not require A and B to be in direct contact with each other, and do not exclude the inclusion of other components between A and B.

[0027] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0028] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" can be replaced with terms such as "region" and "conductive layer."

[0029] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0030] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions adjacent to a channel formation region in a semiconductor layer. The source electrode refers to a conductive layer including a portion connected to the source region. Note that a part of the source wiring may function as the source electrode. The source wiring may also be composed of multiple conductive layers.

[0031] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions adjacent to a channel formation region in a semiconductor layer. The drain electrode refers to a conductive layer including a portion connected to the drain region. Note that a part of the drain wiring may function as the drain electrode. The drain wiring may also be composed of multiple conductive layers.

[0032] The functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are used or when the direction of current flow changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification and elsewhere.

[0033] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance value between the source and drain of the transistor depending on a voltage supplied thereto. Note that a part of the gate wiring may function as the gate electrode. In addition, the gate wiring may be composed of multiple conductive layers.

[0034] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal of the transistor", and the other of the source or the drain of the transistor may be referred to as a "second terminal of the transistor".

[0035] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0036] In this specification, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0037] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0038] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0039] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in an electrically conductive state (a state in which electricity can be passed), and the "off state" of a transistor means that the source and drain of the transistor are in an electrically non-conductive state (a state that can be considered to be electrically disconnected).

[0040] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0041] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS.

[0042] In addition, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and no distinction is made between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0043] Generally, "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator. In addition, in this specification, one electrode of a capacitance element may be referred to as a "first terminal of the capacitance element." In addition, the other electrode of the capacitance element may be referred to as a "second terminal of the capacitance element."

[0044] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0045] In this specification, "connection" includes "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0046] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0047] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0048] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0049] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described. Fig. 1A is a schematic perspective view of a semiconductor device 100A according to one embodiment of the present invention. Fig. 1B is a schematic perspective view of a portion of the semiconductor device 100A. Fig. 2 is a schematic perspective view illustrating a configuration of the semiconductor device 100A.

[0050] 1A, 1B, and 2, the semiconductor device 100A has an element layer 20 below an element layer 10 including a substrate 51 that is a semiconductor substrate, and has a support substrate 90 above the element layer 10 via an insulating layer 89. The element layer 10 has a plurality of transistors 50 that constitute a functional circuit 110. The element layer 20 has a plurality of transistors 60 and a plurality of conductive layers 41 that constitute a power supply circuit 120.

[0051] The transistor 50 included in the element layer 10 is formed on a first surface (also referred to as the "front surface") of the substrate 51. The element layer 20 is formed on a second surface (the surface opposite to the first surface, also referred to as the "back surface") of the substrate 51. Therefore, the transistor 60 included in the element layer 20 is formed on the second surface of the substrate 51.

[0052] At least some of the plurality of transistors 50 included in the functional circuit 110 are connected to at least some of the plurality of conductive layers 41. At least some of the plurality of transistors 60 included in the power supply circuit 120 are connected to at least some of the plurality of conductive layers 41. At least some of the plurality of transistors 50 included in the functional circuit 110 are connected to at least some of the plurality of transistors 60 included in the power supply circuit 120 via at least some of the plurality of conductive layers 41.

[0053] 2 illustrates a CPU 111, a GPU 112, and a memory 113 as the functional circuit 110. Also, a first power supply circuit 121, a second power supply circuit 122, a third power supply circuit 123, and a fourth power supply circuit 124 as the power supply circuit 120.

[0054] FIG. 4A is a block diagram illustrating an example configuration of the semiconductor device 100A. FIG. 4A illustrates a state in which an external power supply PW is connected to a first power supply circuit 121, a second power supply circuit 122, a third power supply circuit 123, and a fourth power supply circuit 124 via a conductive layer 35e. The first power supply circuit 121 is connected to the CPU 111 via a conductive layer 41[1], and the second power supply circuit 122 is connected to the CPU 111 via a conductive layer 41[2]. The first power supply circuit 121 and the second power supply circuit 122 may be power supply circuits that supply different voltages. Alternatively, the first power supply circuit 121 and the second power supply circuit 122 may be power supply circuits that supply the same voltage. Alternatively, one or both of the first power supply circuit 121 and the second power supply circuit 122 may be power supply circuits that can change the voltage supplied to any value. The third power supply circuit 123 is connected to the GPU 112 via a conductive layer 41[3]. The fourth power supply circuit 124 is connected to the memory 113 via the conductive layer 41[4].

[0055] Power supply circuits having a function of supplying a constant voltage can be used as the first power supply circuit 121 to the fourth power supply circuit 124. For example, it is possible to use power supply circuits having a function of supplying the same voltage to each of the first power supply circuit 121 to the fourth power supply circuit 124. It is also possible to use power supply circuits having a function of supplying a different voltage to one or more of the first power supply circuit 121 to the fourth power supply circuit 124.

[0056] Furthermore, it is possible to use a power supply circuit capable of changing the voltage supplied to any value for one or more of the first power supply circuit 121 to the fourth power supply circuit 124. By using such a power supply circuit, it is possible to change the voltage supplied to the circuits included in the functional circuit 110 as needed. For example, by increasing the voltage supplied to a specific circuit included in the functional circuit 110, it is possible to increase the operating speed of that circuit. Furthermore, by reducing the voltage supplied to a circuit whose operating speed can be reduced, it is possible to reduce the power consumption of the semiconductor device 100A.

[0057] The voltage required for operation may differ depending on the functional circuit. By supplying an appropriate voltage depending on the circuits included in the functional circuit 110, the operation of the functional circuit 110 can be stabilized and reliability can be improved. In addition, the power consumption of the functional circuit 110 can be reduced. Therefore, the operation of the semiconductor device 100A can be stabilized and reliability can be improved. In addition, the power consumption of the semiconductor device 100A can be reduced. Furthermore, by changing the voltage supplied to the circuits included in the functional circuit 110 as needed, the semiconductor device 100A can be operated efficiently.

[0058] The circuits included in the functional circuit 110 are not limited to the CPU 111, the GPU 112, and the memory 113, and one or more of these may be used. Furthermore, the functional circuit 110 may also include circuits having functions other than these. For example, the functional circuit 110 may include an FPGA, a digital circuit, an analog circuit, etc.

[0059] Examples of digital circuits include logical operation circuits such as NOT circuits, NAND circuits, and NOR circuits, flip-flop circuits, shift register circuits, adder circuits, and multiplier circuits. Examples of analog circuits include amplifier circuits, oscillator circuits, modulator circuits, filter circuits, and high-frequency circuits.

[0060] The power supply circuits included in the power supply circuit 120 are not limited to the first power supply circuit 121, the second power supply circuit 122, the third power supply circuit 123, and the fourth power supply circuit 124. The power supply circuit 120 may have one or more power supply circuits. It may also include circuits having functions other than these. For example, it is possible to provide the power supply circuit 120 with a clock signal generation circuit (not shown). Depending on the circuit configuration of the semiconductor device, it is also possible to use the clock signal generation circuit as a power supply circuit.

[0061] To achieve improved operating speed, improved packaging density, and reduced power consumption in the semiconductor device 100A, the functional circuit 110 requires miniaturization and thinning of transistors, wiring, and the like, and a reduction in power supply voltage. Furthermore, to ensure stable operation of the functional circuit 110 and fully demonstrate its functions, a highly reliable power supply circuit 120 with a high power supply capacity is required. Generally, the power supply circuit 120 is supplied with a voltage higher than the output voltage of the power supply circuit 120 from the outside. The power supply circuit 120 has a function of converting the externally supplied voltage into the voltage required by the functional circuit 110. Therefore, the transistors constituting the power supply circuit 120 require a high withstand voltage. One effective way to increase the withstand voltage of a transistor is to thicken the gate insulating film. Thus, the transistors 50 and 60 require different performance characteristics. Therefore, different strategies for improving the characteristics of the transistors 50 and 60 are required. Note that a transistor containing an oxide semiconductor, a type of metal oxide, in a semiconductor layer in which a channel is formed (also referred to as an "OS transistor") is suitable as a transistor constituting the power supply circuit.

[0062] Furthermore, miniaturization and thinning of the functional circuit 110 are required. Therefore, if the power supply circuit 120 is constructed using the same process node as the functional circuit 110, not only the routing wiring but also the wiring (power supply line) for supplying voltage will become thinner, making it impossible to supply the necessary voltage to the functional circuit 110. Furthermore, when wiring resistance increases due to miniaturization, a voltage drop phenomenon known as "IR drop" is likely to cause uneven power supply voltage within the functional circuit 110. To stably supply the necessary voltage to the functional circuit 110, it is preferable that the wiring constituting the power supply circuit 120 have lower wiring resistance than the wiring constituting the functional circuit 110. In particular, it is preferable that the wiring functioning as a power supply line have lower wiring resistance than the wiring constituting the functional circuit 110. One effective means for reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer functioning as the wiring. However, to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase either the width or the height of the conductive layer or both.

[0063] In this way, it is preferable to use different process nodes for the functional circuit 110 and the power supply circuit 120. By providing the functional circuit 110 and the power supply circuit 120 in different element layers, they can be formed at different process nodes.

[0064] One embodiment of the present invention includes a plurality of conductive layers 41 functioning as power supply lines under the functional circuit 110, and a power supply circuit 120 is disposed under the conductive layer 41. Since the functional circuit 110, the conductive layer 41, and the power supply circuit 120 can be disposed in an overlapping manner, the area occupied by the semiconductor device 100A can be reduced. Furthermore, the element layer 20 provided to overlap the element layer 10 is preferably formed by a thin film formation technique such as a CVD method or a sputtering method. Therefore, the transistor 60 included in the element layer 20 is preferably a thin film transistor.

[0065] At least some of the conductive layers 41 included in the element layer 20 can function as power supply lines. When the element layer 20 includes a clock signal generation circuit, at least some of the conductive layers 41 can function as clock signal lines. One or both of power supply power and a clock signal supplied from the outside can be supplied to the functional circuit 110 included in the element layer 10 via at least some of the conductive layers 41.

[0066] Furthermore, by providing the conductive layer 41 between the functional circuit 110 and the power supply circuit 120, it is possible to reduce the propagation of noise generated by the power supply circuit 120 to the functional circuit 110. Similarly, it is possible to reduce the propagation of noise generated by the functional circuit 110 to the power supply circuit 120. That is, the conductive layer 41 can function as an electric field shielding layer (also referred to as a "shield layer"). By providing the conductive layer 41 between the functional circuit 110 and the power supply circuit 120, it is possible to stabilize the operation of the semiconductor device 100A and improve its reliability.

[0067] Furthermore, by providing the conductive layer 41 between the functional circuit 110 and the power supply circuit 120, the conductive layer 41 has a heat dissipation effect of dissipating heat from both the functional circuit 110 and the power supply circuit 120. The heat dissipation effect of the conductive layer 41 stabilizes the operation of the semiconductor device 100A and improves its reliability.

[0068] The wiring width of the conductive layer 41 is preferably larger than the size of the transistors included in the functional circuit 110 when viewed in a plane. By making the wiring width of the conductive layer 41 larger than the size of the transistors included in the functional circuit 110 when viewed in a plane, the electric field shielding effect (also referred to as the "shielding effect") can be improved. In addition, the heat dissipation effect of the conductive layer 41 can be improved.

[0069] 3, it is preferable to provide the conductive layer 41 in a mesh pattern. By providing the conductive layer 41 in a mesh pattern, the in-plane uniformity of the power supply voltage can be further improved. Furthermore, the power supply capacity of the power supply circuit 120 can be increased. Furthermore, the shielding effect of the conductive layer 41 can be further improved. Furthermore, the heat dissipation effect of the conductive layer 41 can be further improved. Therefore, the operation of the semiconductor device 100A can be stabilized and the reliability can be improved.

[0070] FIG. 4B is a block diagram illustrating a configuration example of semiconductor device 100B, which is a modified example of semiconductor device 100A. In this embodiment and the like, in order to reduce repetition of explanation, differences between semiconductor device 100B and semiconductor device 100A will be mainly described. Note that, unless explicitly stated, the configuration example of semiconductor device 100A can be read as the configuration example of semiconductor device 100B. Therefore, for portions not explained regarding semiconductor device 100B, the explanation of semiconductor device 100A can be used as a reference.

[0071] The semiconductor device 100B according to one embodiment of the present invention can have a structure in which a plurality of conductive layers 41 and a transistor functioning as a power switch are provided in the element layer 20 without providing the power supply circuit 120. In FIG. 4B , an external power supply PW is connected to one of the source or drain of the transistor PS1, one of the source or drain of the transistor PS2, and one of the source or drain of the transistor PS3 via the conductive layer 35e[1].

[0072] The other of the source or drain of transistor PS1 is connected to the CPU 111 via conductive layer 41[1]. The other of the source or drain of transistor PS2 is connected to the GPU 112 via conductive layer 41[3]. The other of the source or drain of transistor PS3 is connected to the memory 113 via conductive layer 41[4].

[0073] A clock signal source CK is connected to one of the source and drain of the transistor PS4 via a conductive layer 35e[2]. The other of the source and drain of the transistor PS4 is connected to the CPU 111 via a conductive layer 41[2].

[0074] By providing transistors PS1 to PS3, which function as power switches that control the supply or stop of power, between the external power supply PW and the functional circuit 110, it is possible to realize power gating, which cuts off the power supply to the functional circuit in standby mode to reduce power consumption. By realizing power gating, it is possible to reduce the power consumption of the semiconductor device 100B.

[0075] Furthermore, by providing a transistor PS4 between the clock signal source CK and the functional circuit 110, which functions as a switch that controls whether to supply or stop the clock signal, clock gating can be realized, which stops the supply of the clock signal to the functional circuit in standby mode to reduce power consumption. Clock gating may be less effective in reducing power consumption than power gating. On the other hand, clock gating has a shorter recovery time for a stopped functional circuit than power gating, and is therefore suitable for cases where the functional circuit is stopped and restarted frequently.

[0076] When adding a function that enables clock gating to the semiconductor device 100B, it is preferable to use a NAND circuit 151. For example, it is preferable to connect one of the source or drain of the transistor PS4 to one input terminal of the NAND circuit 151, which has two input terminals and one output terminal, and to connect the clock signal source CK to the other input terminal (see FIG. 4C ). Furthermore, when the clock signal is a signal that alternates between a potential H and a potential L, it is preferable to supply a potential equal to or lower than the potential L to the other of the source or drain of the transistor PS4.

[0077] The NAND circuit 151 has a function of outputting an inverted signal of a signal input to one input terminal when a potential H is supplied to the other input terminal. Furthermore, the NAND circuit 151 has a function of always outputting a potential H when a potential L is supplied to one input terminal. Therefore, while the transistor PS4 is in the on state, the output of the NAND circuit 151 is always at a potential H. By always keeping the output of the NAND circuit 151 at a potential H, it is possible to prevent the connected destination from being in a floating state, thereby improving the reliability of the semiconductor device 100B.

[0078] It is also possible to provide a power supply circuit 120 or the like in the element layer 20, and to provide a transistor that functions as a power switch for realizing power gating between the external power supply PW and the power supply circuit 120, or between the power supply circuit 120 and the functional circuit 110. It is also possible to provide a transistor that functions as a switch for realizing clock gating between the clock signal source CK and the power supply circuit 120, or the like.

[0079] The control for switching the transistors PS1 to PS4 between the on state and the off state can be performed by, for example, the CPU 111. The control for switching the transistors PS1 to PS4 between the on state and the off state can also be performed by an external signal.

[0080] Furthermore, an OS transistor has a high withstand voltage between the source and drain, making it suitable for use as a power switch. Furthermore, since an OS transistor has an extremely low off-state current, it has a low leakage current even when power supply and clock signal supply are stopped, making it suitable for power saving.

[0081] A transistor used as a power switch is required to have a high on-state current and a low off-state current. Therefore, an oxide semiconductor containing a large amount of indium is preferably used for a semiconductor layer of the transistor. In particular, indium oxide (also referred to as "indium oxide") is preferably used.

[0082] The element layer 10 having the functional circuit 110 and the element layer 20 having the power supply circuit 120 can be manufactured separately as a die (semiconductor chip) including the functional circuit 110 and a die including the power supply circuit 120, and then mechanically bonded together using three-dimensional integration technology. In this case, good-quality dies including the functional circuit 110 and good-quality dies including the power supply circuit 120 can be bonded together, preventing a decrease in the manufacturing yield of the semiconductor device 100A. Furthermore, the die including the functional circuit 110 and the die including the power supply circuit 120 can be manufactured in parallel, thereby increasing the productivity of the semiconductor device 100A.

[0083] However, when the two are mechanically bonded together using three-dimensional integration technology, it is difficult to improve the alignment accuracy, it is difficult to reduce the size of the bumps used to connect the two, and so it is difficult to narrow the pitch of the connection points. As a result, there is a problem in that it is difficult to shorten the wiring distance for supplying the necessary voltage to the necessary parts of the functional circuit 110.

[0084] According to one aspect of the present invention, the element layer 20 including the power supply circuit 120 is formed on the back surface side of the substrate 51 using a thin film formation technique, a photolithography technique, or the like. Therefore, the semiconductor device 100A according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0085] By forming the element layer 20 by a thin film formation technique, a photolithography technique, or the like, high-precision alignment at a photolithography level can be achieved. Furthermore, a conductive layer functioning as a power supply line can be connected to a necessary location in the functional circuit 110 over an extremely short distance. Therefore, a necessary voltage can be supplied to a necessary location in the functional circuit 110. Furthermore, in the semiconductor device 100A according to one embodiment of the present invention, the connection distance between the power supply circuit 120 and the functional circuit 110 is short, which reduces power loss due to power transmission and reduces power consumption.

[0086] FIG. 5A shows a semiconductor device 100C, which is a modification of the semiconductor device 100A, and FIG. 5B shows a semiconductor device 100D, which is a modification of the semiconductor device 100A. In this embodiment and the like, in order to reduce repetition of explanation, differences between the semiconductor device 100C and the semiconductor device 100D and the semiconductor device 100A will be mainly described. Note that, unless explicitly stated, the configuration example of the semiconductor device 100A can be interpreted as the configuration example of the semiconductor device 100C or the semiconductor device 100D, respectively. Furthermore, the semiconductor device 100C or the semiconductor device 100D is also a modification of the semiconductor device 100B. Therefore, for portions not explained regarding the semiconductor device 100C or the semiconductor device 100D, the explanations of the semiconductor device 100A and the semiconductor device 100B can be used as a reference.

[0087] 5A , an element layer 30 can be provided overlapping the element layer 20. The semiconductor device 100C shows an example in which the element layer 10 and the element layer 30 are provided overlapping with the element layer 20 interposed therebetween. The element layer 30 has a plurality of transistors 70 that constitute a functional circuit 130.

[0088] The element layer 30 provided over the element layer 20 is preferably formed by a thin film formation technique such as a CVD method or a sputtering method. Therefore, the transistor 70 included in the element layer 30 is preferably a thin film transistor. A transistor similar to the transistor 60 can be used as the transistor 70.

[0089] At least some of the multiple transistors 70 included in the functional circuit 130 are connected to at least some of the multiple conductive layers 41. Fig. 5A shows a configuration example in which the functional circuit 130 has a memory 131 and a memory 132. In Fig. 5A, an example is shown in which the memory 131 is connected to the first power supply circuit 121 via the conductive layer 41[1]. In addition, the memory 132 is connected to the third power supply circuit 123 without via the conductive layer 41.

[0090] As the memory 131 and the memory 132, a DRAM, an SRAM, a flash memory, a ferroelectric memory (Ferroelectric Random Access Memory: FeRAM), a magnetoresistive memory (Magnetoresistive Random Access Memory: MRAM), a phase change memory (Phase Change Memory: PCM), a resistive random access memory (Resistive Random Access Memory: ReRAM), or the like can be used.

[0091] The circuits included in the functional circuit 130 are not limited to the memory 131 and the memory 132. The functional circuit 130 may also include circuits having functions other than memories. For example, the functional circuit 130 may also include a CPU, a GPU, an FPGA, a digital circuit, an analog circuit, etc. The functional circuit 130 may include one or more of these.

[0092] As with the element layer 10, the element layer 20 and the element layer 30 can be fabricated separately and mechanically bonded together using three-dimensional integration technology. On the other hand, the element layer 30 is preferably formed using thin-film formation technology, photolithography technology, or the like. By forming the element layer 30 using thin-film formation technology, photolithography technology, or the like, highly accurate alignment at the photolithography level can be achieved. Furthermore, when the element layer 20 is formed using thin-film formation technology, photolithography technology, or the like, the element layer 30 can be formed immediately after the element layer 20. This improves the productivity of the semiconductor device.

[0093] By providing the element layer 20 including the power supply circuit between the element layer 10 and the element layer 30, it is possible to shorten both the length of the wiring connecting the functional circuit 110 and the power supply circuit 120 and the length of the wiring connecting the functional circuit 130 and the power supply circuit 120. This reduces the IR drop and stabilizes the power supply to both the functional circuit 110 and the functional circuit 130. Furthermore, the power consumption of the semiconductor device 100C is reduced.

[0094] Furthermore, the shielding effect and heat dissipation effect of the conductive layer 41 reduce the propagation of noise and heat generated by both the functional circuits 110 and 130. This stabilizes the operation of the semiconductor device 100C and improves its reliability.

[0095] Furthermore, the element layer 20 including the power supply circuit handles power, specifically, converts and controls power. Therefore, materials with high insulation, high heat dissipation, and high heat resistance are required around the element layer 20. Therefore, it is preferable to use a material with high thermal conductivity near the element layer 20. Typical examples of materials with high thermal conductivity include diamond-like carbon (DLC), aluminum nitride (AlNx, x is any number), and silicon nitride (SiNx, x is any number).

[0096] As in the semiconductor device 100D shown in FIG. 5B , it is also possible to provide n stacked element layers 30 (n is an integer of 2 or more). In FIG. 5B , the first element layer 30 is shown as element layer 30[1], and the nth element layer 30 is shown as element layer 30[n]. The functional circuit 130, memory 131, and memory 132 included in element layer 30[1] are shown as functional circuit 130[1], memory 131[1], and memory 132[1], respectively. The functional circuit 130, memory 131, and memory 132 included in element layer 30[n] are shown as functional circuit 130[n], memory 131[n], and memory 132[n], respectively.

[0097] Also, Figure 5B shows an example in which memory 131 (memory 131[1] to memory 131[n]) and memory 132 (memory 132[1] to memory 132[n]) are connected to the second power supply circuit 122, but they can also be configured to be connected to another power supply circuit or multiple power supply circuits.

[0098] By stacking a plurality of element layers 30, it is possible to increase the functionality without increasing the occupied area of ​​the semiconductor device 100D. For example, by stacking a plurality of element layers 30 including a memory, it is possible to increase the memory capacity without increasing the occupied area of ​​the semiconductor device 100D.

[0099] <Manufacturing Method Example> Next, a manufacturing method example of the semiconductor device 100A will be described. First, an element layer 10 in which a transistor 50 is formed on a surface of a substrate 51 is prepared (see FIG. 6A).

[0100] In this embodiment, a single-crystal semiconductor substrate is used as the substrate 51. The transistor 50 has a semiconductor region 51c formed in a part of the substrate 51. The substrate 51 can typically be made of single-crystal silicon. Alternatively, a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride can be used. Furthermore, a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate, can also be used. Alternatively, a substrate having a thin semiconductor film provided on an insulating substrate such as a glass substrate, a quartz substrate, a sapphire substrate, a YSZ substrate, or a resin substrate can also be used.

[0101] The transistor 50 includes a conductive layer 53 that functions as a gate, an insulating layer 52 that functions as a gate insulating layer, a semiconductor region 51c formed of a part of the substrate 51, and a pair of low-resistance regions 54 that function as a source region or a drain region. The transistor 50 can be a p-type transistor or an n-type transistor. An element isolation layer 81 is provided between two adjacent transistors 50.

[0102] The transistor 50 has a semiconductor region 51c in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 6A, a conductive layer 53 is provided to cover the side and top surfaces of the semiconductor region 51c in the depth direction via an insulating layer 52. Such a transistor 50 is also called a FIN-type transistor.

[0103] Furthermore, an insulating layer 82 is formed on the element isolation layer 81, and an insulating layer 83a is formed on the insulating layer 82. Next, a plurality of plugs 61a are formed that penetrate the insulating layer 83a and the insulating layer 82. Next, an insulating layer 83b and a plurality of conductive layers 71a are formed on the insulating layer 83a. The plurality of conductive layers 71a are formed so as to be embedded in the insulating layer 83b. At least one of the plurality of conductive layers 71a is connected to the low-resistance region 54 via the plug 61a.

[0104] An insulating layer 83c is formed on the conductive layer 71a and the insulating layer 83b. Next, a plurality of plugs 61b are formed penetrating the insulating layer 83c. At least one of the plurality of plugs 61b is connected to one of the plurality of conductive layers 71a. Next, an insulating layer 83d and a plurality of conductive layers 71b are formed on the insulating layer 83c. The plurality of conductive layers 71b are formed so as to be embedded in the insulating layer 83b. At least one of the plurality of conductive layers 71b is connected to one of the plugs 61b.

[0105] An insulating layer 83e is formed on the conductive layer 71b and the insulating layer 83d. Next, a plurality of plugs 61c are formed penetrating the insulating layer 83e. At least one of the plurality of plugs 61c is connected to one of the plurality of conductive layers 71b. Next, an insulating layer 83f and a plurality of conductive layers 71c are formed on the insulating layer 83e. The plurality of conductive layers 71c are formed so as to be embedded in the insulating layer 83f. At least one of the plurality of conductive layers 71c is connected to one of the plugs 61c.

[0106] An insulating layer 83g is formed on the conductive layer 71c and the insulating layer 83f. Next, a plurality of plugs 61d are formed penetrating the insulating layer 83g. At least one of the plurality of plugs 61d is connected to one of the plurality of conductive layers 71c. Next, an insulating layer 83h and a plurality of conductive layers 71d are formed on the insulating layer 83g. The plurality of conductive layers 71d are formed so as to be embedded in the insulating layer 83h. At least one of the plurality of conductive layers 71d is connected to one of the plugs 61d. Next, an insulating layer 85 is formed to cover the insulating layer 83h and the conductive layers 71d.

[0107] The plugs 61a to 61d can be made of a conductive material. The insulating layers 83a to 83h, the conductive layers 71a to 71d, and the plugs 61a to 61d may not all be formed as needed. It is also possible to provide other insulating layers, conductive layers, or plugs.

[0108] Next, the support substrate 90 on which the insulating layer 89 has been formed is bonded to the element layer 10 (see FIG. 6B ). The support substrate 90 and the element layer 10 are bonded by stacking the support substrate 90 on the element layer 20 so that the insulating layer 89 and the insulating layer 85 face each other. The support substrate 90 can be made of the same material as the substrate 51. The insulating layer 89 is preferably made of a material with the same composition as the insulating layer 85. Using materials with the same composition for the insulating layers 89 and 85 makes it easier to bond the support substrate 90 and the element layer 10.

[0109] Silicon oxide can typically be used for the insulating layers 89 and 85. Alternatively, an insulating material such as silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, or hafnium oxide can be used. The insulating layer 89 can be formed by the same film formation method as that for the insulating layer 85, such as a sputtering method or a CVD method. In order to improve the flatness, the upper surfaces of the insulating layers 89 and 85 can also be planarized by a CMP (Chemical Mechanical Polishing) process, an etching process, or the like.

[0110] After the support substrate 90 is stacked on the element layer 10, pressing one point on the support substrate 90 or the element layer 10 can spread van der Waals bonds, hydrogen bonds, and the like across the entire bonding surface starting from that point. If one or both of the bonding surfaces have a hydrophilic surface, hydroxyl groups, water molecules, and the like act as adhesives, and subsequent heat treatment causes the water molecules to diffuse, with the remaining components forming silanol groups (Si—OH) and forming a bond through hydrogen bonds. Furthermore, as hydrogen escapes from this bond, siloxane bonds (O—Si—O) are formed, which become covalent bonds, resulting in a stronger bond.

[0111] Next, the element layer 10 to which the support substrate 90 is bonded is turned upside down (see FIG. 7A). After turning it upside down, the back surface of the substrate 51 is subjected to a CMP process or an etching process to thin the substrate 51 to a degree that the low-resistance region 54 is not exposed (see FIG. 7B).

[0112] Next, an insulating layer 91 is provided on the back surface of the substrate 51 (see FIG. 8A ). Subsequently, in a region overlapping one of a pair of low-resistance regions 54 of the transistor 50, a portion of the insulating layer 91 and the substrate is removed to form an opening 93 reaching one of the low-resistance regions 54 (see FIG. 8B ).

[0113] Next, a conductive layer 92 is provided on the insulating layer 91 and the opening 93 (see FIG. 8C). The conductive layer 92 is also formed inside the opening 93, and has a region in contact with one of the low-resistance regions .

[0114] Next, the conductive layer 92 is subjected to CMP treatment, etching treatment, or the like to expose the insulating layer 91 (see FIG. 9A ). At this time, part of the insulating layer 91 may also be removed, resulting in a thinner insulating layer 91. Note that the conductive layer 92 formed inside the opening 93 remains inside the opening 93 and functions as a contact plug. In this manner, the element layer 10 can be formed.

[0115] Next, an element layer 20 including a transistor 60 is formed on the back surface side of the substrate 51 of the element layer 10 (see FIG. 9B ). The element layer 20 includes an insulating layer 25, an insulating layer 31, an insulating layer 32, insulating layers 33a to 33g, plugs 34a to 34f, conductive layers 35a to 35e, a conductive layer 41, an insulating layer 42, and an insulating layer 43.

[0116] The transistor 60 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate, and a pair of conductive layers 24 functioning as a source or a drain.

[0117] A plurality of conductive layers 41 are formed on the insulating layer 91. At least one of the plurality of conductive layers 41 has a region in contact with the conductive layer 92. Next, an insulating layer 42 is formed on the conductive layer 41. After the insulating layer 42 is formed, it is preferable to perform a CMP process, an etching process, or the like to improve the flatness of the surface of the insulating layer 42. By improving the flatness of the surface of the insulating layer 42, the coverage of insulating layers, conductive layers, and the like formed in subsequent steps can be improved.

[0118] Next, a plurality of plugs 34a are formed penetrating the insulating layer 42. At least one of the plurality of plugs 34a is connected to one of the plurality of conductive layers 41. Next, an insulating layer 43 and a plurality of conductive layers 35a are formed on the insulating layer 42. The plurality of conductive layers 35a are formed so as to be embedded in the insulating layer 43. At least one of the plurality of conductive layers 35a is connected to one of the plugs 34a. Next, an insulating layer 31 is formed to cover the insulating layer 43 and the conductive layers 35a, and an insulating layer 25 is formed on the insulating layer 31.

[0119] A single layer or a stack of insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and hafnium aluminate can be used as the insulating layer 25. The insulating layer 25 can be formed by a film formation method such as a sputtering method, a CVD method, or an ALD method.

[0120] Next, the semiconductor layer 21 is formed on the insulating layer 25. The semiconductor layer 21 can be made of an oxide semiconductor, which is a type of metal oxide. In particular, it is preferable to use an oxide containing indium, tin, or zinc as a main component. Among these, indium oxide is preferable because it combines high mobility with high reliability. The semiconductor layer 21 can be formed by a method such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), or a wet method.

[0121] The oxide semiconductor used for the semiconductor layer 21 is preferably indium oxide having a polycrystalline structure or a single-crystalline structure. In particular, by using indium oxide having a single-crystalline structure, carrier scattering at grain boundaries can be suppressed, and a transistor with high field-effect mobility and high reliability can be realized.

[0122] When using indium oxide having a polycrystalline structure, it is preferable that no grain boundaries are observed at least in the channel formation region, so that even if the indium oxide has a polycrystalline structure, it can achieve the same effects as when it has a single-crystalline structure.

[0123] The semiconductor layer 21 is preferably formed while the surface to be formed is heated. In other words, the insulating layer 25 is preferably formed while the surface to be formed is heated. This allows a single crystal film with fewer defects to be obtained. Furthermore, a higher heating temperature is preferable because it can purify the surface to be formed and reduce lattice defects. On the other hand, if the heating temperature is too high, oxygen in the insulating layer 25 may be desorbed, making it impossible to obtain a film with the desired composition. Therefore, it is preferable to set the processing temperature during the formation of the semiconductor layer 21 to a range from room temperature to 1200°C, preferably from 100°C to 600°C.

[0124] As described above, it is particularly preferable to use indium oxide for the semiconductor layer 21. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Furthermore, by using indium oxide having a polycrystalline or single-crystalline structure for the channel formation region of the transistor, a highly reliable transistor can be realized. Furthermore, the band gap of indium oxide is 2.5 eV or more and 3.7 eV or less. By using indium oxide with a wide band gap for the channel formation region of the transistor, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0125] Next, a conductive layer 24 is formed on the semiconductor layer 21. The conductive layer 24 can be made of a conductive material that does not easily diffuse oxygen, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. This prevents the conductive layer 24 from being oxidized by oxygen contained in the semiconductor layer 21 or the like, which would otherwise cause a decrease in conductivity. The conductive layer 24 can be formed by a sputtering method, an ALD method, a CVD method, or the like.

[0126] For example, a conductive film that will become the conductive layer 24 is formed on top of a semiconductor film that will become the semiconductor layer 21, a resist mask is formed on the conductive film that will become the conductive layer 24 by photolithography, and unnecessary portions of the conductive film that will become the conductive layer 24 and the semiconductor film that will become the semiconductor layer 21 are removed by etching, thereby forming the island-shaped conductive layer 24 and the semiconductor layer 21. Thereafter, the resist mask is removed. Although dry etching or wet etching can be used for the etching, dry etching is preferred because it facilitates fine processing.

[0127] Subsequently, an insulating layer 32 having a region covering the semiconductor layer 21 and the conductive layer 24 is formed, and an insulating layer 33a is formed on the insulating layer 32. The insulating layer 32 and the insulating layer 33a can be formed by a sputtering method, an ALD method, a CVD method, or the like.

[0128] The insulating layer 32 functions as a barrier layer. It is preferable to use an insulating material such as silicon nitride, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulating layer 32. These have barrier properties against oxygen, hydrogen, and water, and can prevent these impurities from diffusing into the semiconductor layer 21.

[0129] The insulating layer 33 a functions as an interlayer insulating film. The insulating layer 33 a is preferably made of an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride oxide. By using a material with a low dielectric constant as the interlayer insulating film, parasitic capacitance can be reduced.

[0130] Next, parts of the insulating layer 33a, the insulating layer 32, and the conductive layer 24 are removed to form a groove reaching the semiconductor layer 21 and the insulating layer 31. At this time, the conductive layer 24 is divided into two at the groove. After that, an insulating film that becomes the insulating layer 22 is formed along the groove, and then a conductive film that becomes the conductive layer 23 is formed on the insulating layer 22 so as to fill the groove. Next, planarization is performed by CMP until the insulating layer 33a is exposed, thereby forming the insulating layer 22 and the conductive layer 23 in the groove. The insulating layer 22 functions as a gate insulating layer, and the conductive layer 23 functions as a gate electrode. Furthermore, the pair of conductive layers 24 divided on the semiconductor layer 21 function as a source electrode and a drain electrode, respectively. In this manner, the transistor 60 can be manufactured.

[0131] The insulating layer 22 can be formed of a single layer or a laminate of insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, hafnium aluminate, etc. The insulating layer 22 can be formed by a film formation method such as sputtering, CVD, or ALD, but the ALD method, which has high step coverage, is preferred from the viewpoint of withstand voltage because it allows the layer to be formed to a uniform thickness even inside the trench.

[0132] It is preferable to use a low-resistance conductive material such as tungsten, molybdenum, copper, or aluminum for the conductive layer 23. It is also preferable to form the conductive layer 23 in a laminated structure, and to provide a film of a conductive material that is difficult for oxygen to diffuse into, which can be used for the conductive layer 24, on the side in contact with the insulating layer 22. This makes it possible to prevent the conductive layer 23 from being oxidized by oxygen diffusing from the insulating layer 22 or the like, and thereby preventing a decrease in conductivity.

[0133] Thereafter, an insulating layer 33b is formed on the transistor 60. Next, a plurality of plugs 34b are formed that penetrate the insulating layers 33b, 33a, 32, 25, and 31, and a plurality of plugs 34c are formed that penetrate the insulating layers 33b and 33a. At least one of the plurality of plugs 34b is connected to one of the plurality of conductive layers 35a. At least one of the plurality of plugs 34c is connected to one of the plurality of conductive layers 24.

[0134] Next, an insulating layer 33c and a plurality of conductive layers 35b are formed on the insulating layer 33b. The plurality of conductive layers 35b are formed so as to be embedded in the insulating layer 33c. At least one of the plurality of conductive layers 35b is connected to one or both of the plugs 34b and 34c.

[0135] Next, an insulating layer 33d is formed on the conductive layer 35b and the insulating layer 33c. Next, a plurality of plugs 34d are formed penetrating the insulating layer 33d. At least one of the plurality of plugs 34d is connected to one of the plurality of conductive layers 35b. Next, an insulating layer 33e and a plurality of conductive layers 35c are formed on the insulating layer 33d. The plurality of conductive layers 35c are formed so as to be embedded in the insulating layer 33e. At least one of the plurality of conductive layers 35c is connected to one of the plugs 34d.

[0136] Next, an insulating layer 33f is formed on the conductive layer 35c and the insulating layer 33e. Next, a plurality of plugs 34e are formed penetrating the insulating layer 33f. At least one of the plurality of plugs 34e is connected to one of the plurality of conductive layers 35c. Next, an insulating layer 33g and a plurality of conductive layers 35d are formed on the insulating layer 33f. The plurality of conductive layers 35d are formed so as to be embedded in the insulating layer 33g. At least one of the plurality of conductive layers 35d is connected to one of the plugs 34e.

[0137] Next, an insulating layer 33h is formed on the conductive layer 35d and the insulating layer 33g. Next, a plurality of plugs 34f are formed penetrating the insulating layer 33h. At least one of the plurality of plugs 34f is connected to one of the plurality of conductive layers 35d. Next, a plurality of conductive layers 35e are formed on the insulating layer 33h. At least one of the plurality of conductive layers 35e is connected to one of the plugs 34f. In this manner, a semiconductor device according to one embodiment of the present invention can be fabricated.

[0138] It is also possible to configure a circuit by combining the transistor 50 formed in the element layer 10 and the transistor 60 formed in the element layer 20. For example, it is possible to form a CMOS circuit by combining the transistor 50, which is a p-type transistor, and the transistor 60, which is an n-type transistor. The transistor 60 can also be formed in the element layer 10. That is, it is possible to form the transistor 60 on the surface side of the substrate 51.

[0139] [Insulating Layer] Unless otherwise specified, various inorganic insulators can be used for the insulating layers (insulating layer 82, insulating layer 83 (insulating layers 83a to 83h), insulating layer 85, insulating layer 89, insulating layer 42, insulating layer 43, insulating layer 31, insulating layer 25, insulating layer 32, insulating layer 33 (insulating layers 33a to 33h), insulating layer 91, etc.) in the semiconductor device of one embodiment of the present invention. For example, an oxide insulator, a nitride insulator, an oxynitride insulator, or a nitride oxide insulator can be used.

[0140] Examples of oxide insulators include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitride insulators include silicon nitride and aluminum nitride. Examples of oxynitride insulators include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxide insulators include silicon nitride oxide and aluminum nitride oxide. Furthermore, an organic insulator can also be used for the insulating layer of the semiconductor device of one embodiment of the present invention.

[0141] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0142] For example, as transistors become more miniaturized and highly integrated, problems such as increased leakage current may occur due to thinner gate insulating layers. Using a high-k material for the insulating layer that functions as the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for a thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as the interlayer insulating film (e.g., insulating layer 33, insulating layer 83, etc.) can reduce the parasitic capacitance that occurs between conductive layers such as wiring. Therefore, it is important to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0143] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0144] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0145] [Conductive Layer] Unless otherwise specified, for the conductive layers (the conductive layer 71 (conductive layers 71a to 71d), the plug 61 (plugs 61a to 61d), the conductive layer 41, the plug 34 (plugs 34a to 34f), the conductive layer 35 (conductive layers 35a to 35e), the conductive layer 92, and the like) of the semiconductor device of one embodiment of the present invention, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, an alloy containing any of the above metal elements, an alloy combining any of the above metal elements, or the like can be used.

[0146] As the alloy containing the above-mentioned metal elements as components, nitrides or oxides of the alloys can be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can be used. In addition, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0147] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, and ruthenium are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, indium tin oxide doped with silicon (ITSO), indium zinc oxide (IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.

[0148] It is also possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. Also, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. Also, a stacked structure can be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0149] When an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 21, the conductive layer 24 is a conductive layer in contact with the semiconductor layer 21. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an "oxide conductive layer"), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 24.

[0150] By using an oxide conductive layer as the conductive layer 24, the conductive layer 24 can maintain its conductivity even if it absorbs oxygen. For example, even when an insulating layer containing oxygen that is desorbed by heating (also referred to as "excess oxygen") is used as an insulating layer in contact with the conductive layer 24, the conductive layer 24 can maintain its conductivity, which is preferable. For example, ITO, ITSO, IZO (registered trademark), or the like can be used as the conductive layer 24.

[0151] [Semiconductor Layer] As the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. It is preferable to use a single crystal semiconductor or a crystalline semiconductor for the semiconductor layer in which a channel is formed, because this can suppress deterioration of transistor characteristics.

[0152] As the semiconductor material, for example, a semiconductor made of an element such as silicon or germanium can be used. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can be used. As the compound semiconductor, an organic material having semiconductor properties (also called an "organic semiconductor"), a metal nitride having semiconductor properties (also called a "nitride semiconductor"), or a metal oxide having semiconductor properties (also called an "oxide semiconductor") can be used. Note that these semiconductor materials can contain impurities as dopants.

[0153] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon.

[0154] Two-dimensional materials that function as semiconductors can also be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0155] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0156] [Metal Oxide Layer] The transistor 60 preferably includes an oxide semiconductor, which is a type of metal oxide, in the semiconductor layer 21 including a channel formation region. That is, the transistor 60 is preferably an OS transistor.

[0157] An OS transistor is a transistor that has an oxygen vacancy (V Ｏ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0158] On the other hand, the source and drain regions in a metal oxide that functions as a semiconductor of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, and have a high carrier concentration and low resistance due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0159] The band gap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide functioning as a semiconductor and having a wide band gap for the semiconductor layer 21, the off-state current of the transistor 60 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0160] A metal oxide that can be used for a semiconductor layer of an OS transistor preferably contains at least indium (In). The metal oxide preferably contains at least one of indium (In) and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0161] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0162] For example, examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide (In oxide, indium oxide). Examples of the metal oxide include zinc oxide (Zn oxide, zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0163] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0164] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0165] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0166] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0167] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0168] Embodiment 2 This embodiment describes a configuration example of a circuit that can be applied to the power supply circuit 120. A circuit 55 illustrated in Figures 10A and 10B functions as an LDO (Low Drop Out) regulator circuit, which is a type of linear regulator circuit.

[0169] A linear regulator circuit has the function of controlling the output voltage or current to keep it constant at all times. Linear regulator circuits also have the function of outputting a voltage lower than the input voltage. The difference between the input voltage and output voltage of a linear regulator circuit is called the dropout voltage. Since the dropout voltage of a linear regulator circuit is about 2V, an input voltage of 5.3V or more is required to obtain an output voltage of 3.3V.

[0170] An LDO regulator circuit is a linear regulator circuit with a small dropout voltage. For example, an LDO regulator circuit with a dropout voltage of 0.5 V can reduce the input voltage required to obtain an output voltage of 3.3 V to 3.8 V. By using circuit 55 that functions as an LDO regulator circuit in power supply circuit 120, it is possible to reduce the power consumption of semiconductor device 100A.

[0171] 10A includes a control amplifier 64 and a transistor M75. One of the source or drain of the transistor M75 is connected to a terminal IN of the circuit 55. The other of the source or drain of the transistor M75 is connected to a terminal OUT of the circuit 55. The transistor M75 functions as an output transistor or a pass transistor.

[0172] 10A shows an example in which an operational amplifier is used as the control amplifier 64. The output terminal of the control amplifier 64 is connected to the gate of the transistor M75. The non-inverting input terminal of the control amplifier 64 is connected to the terminal OUT and the other of the source or drain of the transistor M75. The non-inverting input terminal of the control amplifier 64 is connected to the terminal Ref.

[0173] An input voltage Vin is supplied to a terminal IN. A reference voltage Vref is supplied to a terminal Ref. A control amplifier 64 compares an output voltage Vout supplied to a terminal OUT with the reference voltage Vref, and adjusts the on-resistance of a transistor M75 so that the two are equal.

[0174] As shown in Figure 10B, the control amplifier 64 can be configured with n-type transistors. Since there is no need to form p-type transistors, the productivity of the semiconductor device can be improved. In Figure 10B, the control amplifier 64 includes transistors M65 to M69. One of the source or drain of the transistor M65, the gate of the transistor M65, one of the source or drain of the transistor M67, and the gate of the transistor M67 are connected to the terminal IN and one of the source or drain of the transistor M75.

[0175] The other of the source or drain of transistor M65 is connected to the other of the source or drain of transistor M66. The gate of transistor M66 is connected to terminal Ref. The other of the source or drain of transistor M67 is connected to the gate of transistor M75 and the other of the source or drain of transistor M68. The gate of transistor M68 is connected to terminal OUT and the other of the source or drain of transistor M75.

[0176] The other of the source or drain of transistor M66 and the other of the source or drain of transistor M68 are connected to one of the source or drain of transistor M69. The other of the source or drain of transistor M69 is connected to terminal Gd. The gate of transistor M69 is connected to terminal Bias. GND or VSS is supplied to terminal Gd, and voltage Vbias is supplied to terminal Bias.

[0177] The circuit 55 shown in Fig. 10B functions in the same manner as the circuit 55 shown in Fig. 10A. Transistors M65 to M69 and M75 can be transistors having back gates. When transistors having back gates are used as transistors constituting the circuit 55, it is preferable that the gate and the back gate are connected. Fig. 10C shows a circuit symbol of a transistor whose gate and back gate are connected.

[0178] 11A and 11B is a step-down charge pump circuit. By supplying a low power supply potential VSS to a terminal IN of the circuit 56, a potential (negative potential) lower than the low power supply potential VSS can be output from a terminal OUT of the circuit 56. While FIGS. 11A and 11B show an example in which the number of stages of basic circuits constituting the charge pump circuit is four, the number of stages is not limited thereto and the charge pump circuit can be configured with any number of stages.

[0179] 11A includes transistors M41 to M45 and capacitors C41 to C45. Note that the transistors M41 to M45 can be configured using n-channel transistors.

[0180] The transistors M41 to M45 are connected in series between the terminal IN and the terminal OUT. In each of the transistors M41 to M45, the gate is connected to one of the source and the drain. Therefore, the transistors M41 to M45 function as a diode. In each of the transistors M41 to M45, one of the source and the drain functions as the anode of the diode, and the other of the source and the drain functions as the cathode.

[0181] 11A, one of the source or drain of transistor M45 is connected to terminal OUT, and the other is connected to one of the source or drain of transistor M44. The other of the source or drain of transistor M44 is connected to one of the source or drain of transistor M43. The other of the source or drain of transistor M43 is connected to one of the source or drain of transistor M42. The other of the source or drain of transistor M42 is connected to one of the source or drain of transistor M41. The other of the source or drain of transistor M41 is connected to terminal IN.

[0182] Also, one electrode of a capacitance element C41 is connected to the gate of transistor M41. One electrode of a capacitance element C42 is connected to the gate of transistor M42. One electrode of a capacitance element C43 is connected to the gate of transistor M43. One electrode of a capacitance element C44 is connected to the gate of transistor M44. One electrode of a capacitance element C45 is connected to the gate of transistor M45.

[0183] A clock signal CLK is input to the other electrodes of the capacitive elements C41 and C43 via a terminal CL, and an inverted clock signal CLKB is input to the other electrodes of the capacitive elements C42 and C44 via a terminal CLB. The signal CLKB is an inverted clock signal obtained by inverting the phase of the signal CLK. A fixed potential such as VSS or GND is supplied to the other electrode of the capacitive element C45.

[0184] The circuit 56 can generate a potential lower than the low power supply potential VSS simply by receiving the signals CLK and CLKB.

[0185] 11B, transistors having back gates can be used as the transistors M41 to M45. In each of the transistors M41 to M45 shown in FIG. 11B, the gate and the back gate are connected to each other.

[0186] Here, a transistor having a back gate will be described. The gate and back gate of the transistor are arranged to sandwich a channel formation region of a semiconductor layer. Both the gate and the back gate are formed of a conductive layer or a semiconductor layer with low resistivity. The back gate can function in the same way as the gate. When the gate is used to control the on and off states of the transistor, the potential of the back gate can be set to the same potential as the gate. Furthermore, the back gate can be set to GND or any other potential.

[0187] For example, when turning on a transistor, supplying a potential that turns the transistor on to both the gate and the back gate increases the on-state current compared to supplying a potential to only one of them. By connecting the gate and back gate, it is possible to keep the gate and back gate at the same potential. In addition, by controlling the back gate potential independently of the gate, the threshold voltage of the transistor can be adjusted.

[0188] Furthermore, a fixed potential such as GND can be supplied to the back gate. Since the gate and the back gate are formed of a conductive layer or the like, sandwiching the channel formation region of the semiconductor layer between the gate and the back gate makes it difficult for an electric field generated outside the transistor and an electric field related to the drain voltage to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a semiconductor device including the transistor can be improved. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are electrically floating (also referred to as a "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0189] Note that the power supply circuit 120 may also be a switching regulator circuit shown as an example in FIGS. 12A to 12C.

[0190] 12A shows an example of a step-down switching regulator circuit as the circuit 57. The circuit 57 includes a transistor M81, a transistor M82, an inductor L91 (coil), a capacitance element C45, and a capacitance element C46.

[0191] In the circuit 57, one of the source or drain of the transistor M81 is connected to one terminal of the capacitive element C45 and the terminal IN. The other of the source or drain of the transistor M81 is connected to one of the source or drain of the transistor M82 and one terminal of the inductor L91. The other terminal of the inductor L91 is connected to one terminal of the capacitive element C46 and the terminal OUT. The other of the source or drain of the transistor M82 is connected to the other terminal of the capacitive element C45, the other terminal of the capacitive element C46, ​​and the terminal Gd. GND or VSS is supplied to the terminal Gd.

[0192] The gates of the transistors M81 and M82 are connected to a control circuit 99. The control circuit 99 has a function of controlling the on and off states of the transistors M81 and M82. By using the control circuit 99 to control the frequency and timing of switching the transistors M81 and M82 between on and off, a voltage smaller than the input voltage Vin can be supplied to the terminal OUT as the output voltage Vout.

[0193] 12B shows an example of a step-up switching regulator circuit as the circuit 58. The circuit 58 includes a transistor M81, an inductor L91, a rectifying element D92 (diode), a capacitance element C45, and a capacitance element C46.

[0194] In circuit 58, one terminal of capacitive element C45 is connected to one terminal of inductor L91 and terminal IN. The other terminal of inductor L91 is connected to one of the source or drain of transistor M81 and the anode of rectifying element D92. The cathode of rectifying element D92 is connected to one terminal of capacitive element C46 and terminal OUT. The other terminal of capacitive element C45 is connected to the other of the source or drain of transistor M81, the other terminal of capacitive element C46, ​​and terminal Gd.

[0195] The gate of the transistor M81 is connected to a control circuit 99. The control circuit 99 has a function of controlling the on and off states of the transistor M81. By using the control circuit 99 to control the frequency and timing of switching the transistor M81 between the on and off states, a voltage greater than the input voltage Vin can be supplied to the terminal OUT as the output voltage Vout.

[0196] 12C shows an example of a step-up / step-down switching regulator circuit as the circuit 59. The circuit 59 includes a transistor M81, a transistor M82, a transistor M83, a transistor M84, an inductor L91, a capacitor C45, and a capacitor C46.

[0197] In the circuit 59, one terminal of the capacitance element C45 is connected to one of the source or drain of the transistor M81 and the terminal IN. The other of the source or drain of the transistor M81 is connected to one of the source or drain of the transistor M82 and one terminal of the inductor L91. One terminal of the capacitance element C46 is connected to one of the source or drain of the transistor M83 and the terminal OUT. The other of the source or drain of the transistor M83 is connected to one of the source or drain of the transistor M84 and the other terminal of the inductor L91. The other terminal of the capacitance element C45 is connected to the other of the source or drain of the transistor M82, the other of the source or drain of the transistor M84, the other terminal of the capacitance element C46, ​​and the terminal Gd.

[0198] The gates of the transistors M81, M82, M83, and M84 are connected to a control circuit 99. The control circuit 99 has a function of controlling the on and off states of the transistors M81 to M84. By using the control circuit 99 to control the frequency and timing of switching the on and off states of the transistors M81 to M84, a voltage different from the input voltage Vin can be supplied to the terminal OUT as the output voltage Vout.

[0199] The above describes an example of a circuit configuration of a DC-DC converter that can output a DC voltage that is different from the input DC voltage. However, power supply circuits that can be used for the power supply circuit 120 are not limited to this. For example, it is also possible to use a circuit configuration of an AC-DC converter that converts an AC voltage input to the power supply circuit 120 into a DC voltage.

[0200] As described above, the power supply circuit 120 according to one embodiment of the present invention is formed in the element layer 20. As described above, various semiconductor materials can be used for the semiconductor layers of the transistors included in the circuits 55 and 56 applicable to the power supply circuit 120, but OS transistors are preferred. In particular, it is preferable to use OS transistors containing In and / or Zn in the semiconductor layers of the transistors. In particular, OS transistors using an In oxide for the semiconductor layer are preferred for the power supply circuit 120 because they can achieve high field-effect mobility.

[0201] Furthermore, the characteristics of an OS transistor are less likely to fluctuate even in a high-temperature environment, allowing stable operation. Therefore, even when the element layer 20 including the OS transistor is provided overlapping with the element layer 10 including a transistor containing silicon (also referred to as a "Si transistor") in a semiconductor layer in which a channel is formed, the OS transistor is less susceptible to heat generation from the Si transistor, allowing stable circuit operation. Therefore, the reliability of the semiconductor device 100A can be improved.

[0202] Furthermore, OS transistors have a high withstand voltage between the source and drain, making them suitable for use as transistors in the circuits 55 and 56 that function as power supply circuits. In particular, OS transistors are suitable for the transistor M75 that functions as an output transistor. By using an OS transistor as the transistor M75, a power supply circuit with a high withstand voltage and stable output even in a high-temperature environment can be realized.

[0203] Furthermore, it is preferable to use an OS transistor using an In oxide as the transistor M75. In addition to the above, by using an OS transistor using an In oxide as the transistor M75, a power supply circuit with a higher current supply capability can be realized. Note that OS transistors using an In oxide can also be used as transistors other than the transistor M75.

[0204] Furthermore, if necessary, a part of the circuit 55, a part of the circuit 56, etc. formed in the element layer 20 can be formed in the element layer 10. That is, a part of the circuit formed in the element layer 20 can be formed in the element layer 10.

[0205] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0206] In this embodiment, a configuration example of a memory device 900 that can be applied to a semiconductor device of one embodiment of the present invention will be described. The memory device 900 can be used for the memory 113, the memory 131, the memory 132, or the like described in the above embodiments.

[0207] Fig. 13 is a block diagram showing a configuration example of a memory device 900. The memory device 900 shown in Fig. 13 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 13 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0208] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928. Note that the power supply circuit 120 can be used as the voltage generating circuit 928.

[0209] In the storage device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside or the functional circuit 110, and the signal RDA is an output signal to the outside or the functional circuit 110. The signal CLK is a clock signal.

[0210] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0211] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the memory device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0212] The voltage generation circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage. The power supply circuit 120 can be used as the voltage generation circuit 928.

[0213] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0214] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0215] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the memory device 900. The data output from the output circuit 926 is a signal RDA.

[0216] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the memory device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 13, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, it is preferable to provide a power switch for each power domain.

[0217] 14A to 14F, 15A, and 15B, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0218] 14A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0219] The transistor M1 may have a gate and a back gate. The back gate may be connected to the gate. The back gate may also be connected to a wiring that is supplied with a constant potential or a signal.

[0220] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0221] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0222] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0223] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 can have the configuration of a memory cell 952 as shown in FIG. 14B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0224] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0225] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0226] 14C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0227] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0228] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0229] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0230] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0231] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 14D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0232] 14E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 14F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0233] Note that it is preferable to use an OS transistor for at least the transistor M2, and particularly for the transistors M2 and M3.

[0234] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time. This reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the OS transistor has an extremely low current, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0235] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0236] Note that a Si transistor can be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0237] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0238] 15A shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0239] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0240] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0241] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0242] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0243] Note that at least the transistor M4 is preferably an OS transistor.

[0244] Note that Si transistors can be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0245] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0246] 15B shows an example of a static random access memory (SRAM) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxide semiconductor SRAM (OS-SRAM). Note that a memory cell 958 shown in FIG. 15B is a memory cell of an SRAM capable of backing up data.

[0247] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0248] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0249] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0250] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0251] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0252] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0253] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0254] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0255] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0256] The following describes how data is read. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. Since the potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0257] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0258] Note that Si transistors can be used as the transistors MS1 to MS4.

[0259] For example, when the memory device 900 is provided in the element layer 30, both the driving circuit 910 and the memory array 920 can be provided in the element layer 30. It is also possible to provide the driving circuit 910 in the functional circuit 110 of the element layer 10, and the memory array 920 in the functional circuit 130 of the element layer 30.

[0260] A memory cell using an OS transistor, such as a DOSRAM, a NOSRAM, or an OS-SRAM, described in this embodiment (also referred to as an "OS memory"), has excellent rewrite endurance because it does not involve structural changes at the atomic level, as in a ferroelectric memory (FeRAM) or a resistive random access memory (ReRAM). Furthermore, the OS memory does not exhibit instability due to an increase in electron trap centers caused by repeated rewrite operations, as is observed in a flash memory.

[0261] Since the OS memory can be configured using thin film transistors, it can be provided overlapping with Si transistors. This facilitates high integration of semiconductor devices. For example, an OS transistor can be used for the element layer 10. Furthermore, the OS transistor used for the OS memory can be manufactured using the same manufacturing equipment as that for Si transistors. This allows the OS memory to be manufactured at low cost.

[0262] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0263] Embodiment 4 In this embodiment, a structural example of a transistor that can be used in a semiconductor device of one embodiment of the present invention will be described.

[0264] As a transistor included in a semiconductor device of one embodiment of the present invention, transistors with various structures can be used. For example, transistors with various structures can be used, such as a top-gate transistor (a planar transistor, a staggered transistor, or the like), a bottom-gate transistor (an inverted planar transistor, an inverted staggered transistor, or the like), a dual-gate transistor (a structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region), a fin transistor (a fin-type transistor), a tri-gate transistor (a tri-gate transistor), or a gate-all-around transistor (a gate-all-around transistor) can be used. Furthermore, for example, a vertical transistor (a transistor whose channel length direction is a vertical direction (also referred to as a height direction or a direction perpendicular to a surface where the transistor is formed)) can be used.

[0265] <Transistor Configuration Example 1> FIGS. 16A to 16D are plan views and cross-sectional views of a transistor 200A. FIG. 16A is a plan view of the transistor 200A, and FIGS. 16B to 16D are schematic cross-sectional views corresponding to the cut lines A1-A2, A3-A4, and A5-A6 in FIG. 16A, respectively. FIG. 16B corresponds to a cross-section of the transistor 200A in the channel length direction, and FIGS. 16C and 16D correspond to cross-sections in the channel width direction, respectively. FIGS. 17A and 17B are cross-sectional views of the transistor 200A corresponding to an enlarged view of FIG. 16B. As mentioned above, in order to make the drawings easier to understand, some components may be omitted in plan views, cross-sectional views, etc.

[0266] The transistor 200A includes a semiconductor layer 230 provided on an insulating layer 201 provided on a substrate (not shown), a conductive layer 242 (conductive layers 242a and 242b) on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. An insulating layer 275 is provided to cover the semiconductor layer 230 and the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 275. A groove is provided in the insulating layer 280 and the insulating layer 275 to reach the semiconductor layer 230, and the conductive layer 242a and the conductive layer 242b are separated by the groove. The insulating layer 250 is provided inside the groove along surfaces of the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, and the semiconductor layer 230. The conductive layer 260 is provided on the insulating layer 250 so as to fill the groove. In addition, an insulating layer 282 and an insulating layer 285 are provided in this order to cover the insulating layer 280 , the insulating layer 250 , and the conductive layer 260 .

[0267] For example, the insulating layer 201 corresponds to the insulating layer 25 described in the above embodiment. The semiconductor layer 230 corresponds to the semiconductor layer 21 described in the above embodiment. The conductive layer 242 corresponds to the conductive layer 24 described in the above embodiment. The insulating layer 275 corresponds to the insulating layer 32 described in the above embodiment. The insulating layer 280 corresponds to the insulating layer 33a described in the above embodiment. The insulating layer 250 corresponds to the insulating layer 22 described in the above embodiment. The conductive layer 260 corresponds to the conductive layer 23 described in the above embodiment.

[0268] The semiconductor layer 230 includes a region that functions as a channel formation region of the transistor 200A. The conductive layer 260 functions as a gate electrode of the transistor 200A. The insulating layer 250 functions as a gate insulator of the transistor 200A. A region of the semiconductor layer 230 that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween functions as a channel formation region.

[0269] The conductive layer 242a functions as one of a source electrode and a drain electrode of the transistor 200A, and the conductive layer 242b functions as the other.

[0270] The conductive layer 242a and the conductive layer 242b preferably have a stacked structure. A conductor that is resistant to oxidation, such as a metal nitride, is preferably used on the side in contact with the semiconductor layer 230. This can prevent the conductive layer 242a and the conductive layer 242b from being excessively oxidized by oxygen contained in the semiconductor layer 230. Furthermore, a metal or alloy having higher conductivity than the layer in contact with the semiconductor layer 230 is preferably used on the side not in contact with the semiconductor layer 230. This allows the conductive layer 242a and the conductive layer 242b to function as wirings or electrodes with high conductivity.

[0271] In the conductive layers 242a and 242b, a metal nitride is preferably used on the side in contact with the semiconductor layer 230. For example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. Alternatively, for example, ruthenium, an oxide containing ruthenium, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel can be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0272] The insulating layer 201 is a film in contact with the semiconductor layer 230 and is preferably an oxide insulating film. For example, the insulating layer 201 is preferably made of silicon oxide or silicon oxynitride.

[0273] Note that an insulating layer (also referred to as a "barrier insulating layer") functioning as a barrier layer can be provided between the insulating layer 201 and the semiconductor layer 230. The insulating layer preferably has a barrier property against at least hydrogen. For example, examples of a barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. In particular, when silicon oxide is used for the insulating layer 201, it is particularly preferable to provide an insulating layer having a barrier property against hydrogen because silicon oxide has the characteristic of easily diffusing hydrogen. This makes it possible to keep the hydrogen concentration in the semiconductor layer 230 low, thereby improving the reliability of the transistor 200A.

[0274] In order to stabilize the electrical characteristics of the transistor 200A, it is effective to reduce the impurity concentration in the semiconductor layer 230. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 230 refer to, for example, elements other than the main components constituting the semiconductor layer 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0275] As described in the above embodiment, it is preferable to use an oxide semiconductor for the semiconductor layer 230. It is preferable to use indium oxide for the semiconductor layer 230. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 230, and it is particularly preferable to use indium oxide having a single-crystal structure. By using indium oxide having a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0276] Note that indium oxide having a polycrystalline structure or a microcrystalline structure can also be used for the semiconductor layer 230. When indium oxide having a polycrystalline structure is used, it is preferable that no crystal grain boundaries are observed at least in the channel formation region (the region overlapping with the conductive layer 260). Thus, even indium oxide having a polycrystalline structure can achieve the same effects as in the case of indium oxide having a single crystal structure.

[0277] When an oxide semiconductor is used for the semiconductor layer 230, the thickness of the semiconductor layer 230 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved.

[0278] The insulating layer 250 functioning as a gate insulating layer preferably has a function of capturing and fixing hydrogen, which can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 230. As a result, the channel formation region can be made i-type or substantially i-type.

[0279] Here, the insulating layer 250 preferably has a stacked structure of a first layer in contact with the semiconductor layer 230, a second layer over the first layer, and a third layer over the second layer. In this case, it is preferable that the first layer has a function of capturing hydrogen and fixing hydrogen.

[0280] Examples of insulators capable of capturing and fixing hydrogen include metal oxides having an amorphous structure. For the first layer, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0281] Furthermore, it is preferable to use a high-k material for the first layer. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the first layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Furthermore, it is possible to reduce the EOT of the insulator that functions as the gate insulator.

[0282] For the first layer, it is preferable to use an oxide containing one or both of aluminum and hafnium, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0283] Next, the second layer preferably uses an insulator having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0284] It is also possible to provide a structure in which a fourth layer is provided on the second layer. In this case, the fourth layer can be an insulator that can be used for the first layer. For example, hafnium oxide can be used for the fourth layer. Here, by providing the fourth layer between the third layer and the second layer, hydrogen contained in the second layer can be more effectively captured and fixed.

[0285] The third layer preferably has a barrier property against oxygen. The third layer is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The third layer is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the third layer. In this case, the third layer is an insulator containing at least nitrogen and silicon.

[0286] Furthermore, the third layer preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0287] The insulating layer 275 preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242a and the conductive layer 242b. Therefore, it is possible to prevent the conductive layer 242a and the conductive layer 242b from being oxidized by the oxygen contained in the insulating layer 280, which increases the resistivity and reduces the on-current.

[0288] The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. In addition, it is preferably less permeable to hydrogen. For example, silicon nitride is preferably used as the insulating layer 275. In this case, the insulating layer 275 is an insulator containing at least nitrogen and silicon.

[0289] In addition, in this embodiment, it is preferable to use a structure that suppresses diffusion of hydrogen from the outside into the transistor 200A and the like. For example, it is preferable to provide an insulator that has a function of suppressing hydrogen diffusion so as to cover the transistor 200A. In the semiconductor device described in this embodiment, the insulator is, for example, an insulating layer 282. Furthermore, as shown in FIG. 17B , a similar film can also be provided under the transistor 200A. FIG. 17B shows an example in which an insulating layer 283 is provided under the insulating layer 201.

[0290] The insulating layers 282 and 283 preferably function as barrier insulating layers that suppress diffusion of impurities such as water and hydrogen from the outside into the transistor 200A. Therefore, the insulating layers 282 and 283 can suppress diffusion of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２It is preferable that the insulating material has a function of suppressing the diffusion of impurities such as copper atoms (for example, copper atoms), or ...

[0291] The insulating layers 282 and 283 preferably include an insulator that has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layer 283 is preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, the insulating layer 282 preferably includes aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen. This can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulating layer 283 to the transistor 200A and the like. Furthermore, oxygen contained in the insulating layer 280 and the like can be suppressed from diffusing upward from the transistor 200A and the like through the insulating layer 282 and the like. Furthermore, providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200A can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200A and the like.

[0292] 17A and 17B, an insulating layer 271a may be provided between the conductive layer 242a and the insulating layer 275 on the conductive layer 242a, and an insulating layer 271b may be provided between the conductive layer 242b and the insulating layer 275 on the conductive layer 242b. The insulating layers 271a and 271b function as etching stoppers during processing of the conductive layers 242a and 242b, protecting the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, they are preferably made of inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, the insulating layers 271a and 271b may have a stacked structure, with silicon nitride used on the side in contact with the conductive layers 242a and 242b and silicon oxide used elsewhere.

[0293] 17A and 17B , openings reaching conductive layer 242a are formed in insulating layers 285, 283, 282, 280, 275, and 271a, and conductive layer 240a and insulating layer 241a are provided in the openings. Insulating layer 241a is provided in contact with the sidewalls of the openings, and conductive layer 240a is provided inside insulating layer 241a. Furthermore, openings reaching conductive layer 242b are formed in insulating layers 285, 283, 282, 280, 275, and 271b, and conductive layer 240b and insulating layer 241b are provided in the openings. Insulating layer 241b is provided in contact with the sidewalls of the openings, and conductive layer 240b is provided inside insulating layer 241b. The conductive layer 240a and the conductive layer 240b function as a via that connects a conductive layer provided over the transistor 200A to the source or drain of the transistor 200A. Note that the conductive layer 240 (the conductive layer 240a and the conductive layer 240b) corresponds to the plug 34c described in the above embodiment.

[0294] The conductive layers 240a and 240b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 240a and 240b may also have a stacked structure.

[0295] 17A and 17B, the conductive layer 240a and the conductive layer 240b may have a two-layer laminated structure. The conductive layer 240a includes a conductive layer 240a1 formed along the opening and a conductive layer 240a2 formed inside the conductive layer 240a1. The conductive layer 240b includes a conductive layer 240b1 formed along the opening and a conductive layer 240b2 formed inside the conductive layer 240b1.

[0296] The conductive layers 240a1 and 240b1 are preferably made of a conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, which has a function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen can be used in a single layer or a stacked layer. Providing the conductive layers 240a1 and 240b1 can suppress the diffusion of impurities such as water and hydrogen into the semiconductor layer 230 through the conductive layers 240a2 and 240b2. Note that the conductive layers 240a2 and 240b2 may be made of the same conductive materials that can be used for the conductive layers 240a and 240b.

[0297] 16B, the upper surfaces of the conductive layers 240a and 240b may be formed to coincide or substantially coincide with the upper surface of the insulating layer 285. Also, as shown in FIGS. 17A and 17B, the lower portion of the conductive layer 240a may be formed to be embedded in the conductive layer 242a. Similarly, the lower portion of the conductive layer 240b may be formed to be embedded in the conductive layer 242b.

[0298] The insulating layers 241a and 241b may be barrier insulating layers that can be used for the insulating layer 275, for example. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, 275, 271a, and 271b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 from diffusing into the semiconductor layer 230 through the conductive layers 240a and 240b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 240a and 240b.

[0299] The conductive layer 260 functions as a gate electrode of the transistor 200A. Here, the conductive layer 260 is preferably provided to extend in the channel width direction, as shown in Figures 16A and 16C. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0300] The conductive layer 260 can also have a stacked structure. Figures 17A and 17B show an example in which the conductive layer 260 includes a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b thereon. In this case, the conductive layer 260a is preferably made of a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion. The conductive layer 260b is preferably made of a low-resistance conductive material, such as tungsten, copper, or aluminum.

[0301] The insulating layer 280 and the insulating layer 285 preferably have a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For example, the insulating layer 280 and the insulating layer 285 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form a region containing oxygen that is desorbed by heating.

[0302] <Transistor Configuration Example 2> The following describes a configuration example of a transistor 200B that is partially different from the transistor 200A. Note that the following mainly describes the differences from the above. Therefore, descriptions of parts that overlap with the above may be omitted.

[0303] 18A and 18B are enlarged cross-sectional views of the transistor 200B, which is a variation of the transistor 200A. The transistor 200B includes a conductive layer 205 that functions as a back gate. The transistor 200B shown in FIG. 18A includes the conductive layer 205 and the insulating layer 202 under the insulating layer 201.

[0304] 18A, the conductive layer 205 is provided to be embedded in the insulating layer 202. The insulating layer 201 is provided to cover the insulating layer 202 and the conductive layer 205.

[0305] The conductive layer 260 functions as a first gate of the transistor 200B, and the conductive layer 205 functions as a second gate (back gate) of the transistor 200B. The conductive layer 260 and the conductive layer 205 overlap with each other with the semiconductor layer 230 interposed therebetween. The conductive layer 205 can be formed using any of the materials that can be used for the conductive layer 260. The conductive layer 205 can also have a stacked structure.

[0306] The insulating layer 250 functions as a first gate insulating layer, and the insulating layer 201 functions as a second gate insulating layer. In this case, the insulating layer 201 may have a stacked structure, and a high-dielectric-constant material such as hafnium oxide, aluminum oxide, or hafnium aluminate may be used as part of the stacked structure. The insulating layer 202 may be made of, for example, silicon oxide.

[0307] Further, it is preferable to provide an insulating film having a barrier property against oxygen, such as silicon nitride or aluminum oxide, between the insulating layer 202 and the conductive layer 205 because oxidation of the conductive layer 205 can be suppressed.

[0308] As in a transistor 200B illustrated in FIG. 18B, an insulating layer 283 functioning as a barrier insulating layer can be provided between the insulating layer 201 and the conductive layer 205.

[0309] <Transistor Configuration Example 3> Fig. 19A is a plan view of a transistor 200C having a different configuration from the transistors 200A and 200B. Fig. 19B is a cross-sectional view corresponding to the cutting line A1-A2 in Fig. 19A. Note that the following mainly describes differences from the above. Therefore, descriptions of parts that overlap with the above may be omitted.

[0310] The transistor 200C includes a conductive layer 255 over the insulating layer 201. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0311] An opening 262 penetrating the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 is provided in a region overlapping with part of the conductive layer 255. The semiconductor layer 230 is provided to cover the inner wall of the opening 262.

[0312] The semiconductor layer 230 has a region overlapping with the bottom of the opening 262 and a region overlapping with the side surface of the opening 262. That is, the semiconductor layer 230 has a region in contact with the insulating layer 256 inside the opening 262. The semiconductor layer 230 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 inside the opening 262.

[0313] An insulating layer 250 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 230. A conductive layer 265 is provided over the insulating layer 250. The conductive layer 265 has a region overlapping with the semiconductor layer 230. The conductive layer 265 has a region overlapping with the semiconductor layer 230 with the insulating layer 250 interposed therebetween. The conductive layer 265 functions as a gate electrode. Therefore, the conductive layer 265 corresponds to the conductive layer 260 in the transistor 200A and the transistor 200B.

[0314] The insulating layer 250 and the conductive layer 265 each have a region that overlaps with the opening 262. The insulating layer 250 and the conductive layer 265 each have a region that overlaps with the inside of the opening 262. Inside the opening 262, the semiconductor layer 230 has a region that overlaps with the conductive layer 265 with the insulating layer 250 interposed therebetween and a region that overlaps with the side surface of the opening 262 (the side surface of the insulating layer 256).

[0315] Furthermore, an insulating layer 285 is provided on the insulating layer 250. Note that the upper surface of the insulating layer 285 is preferably flat. Alternatively, it is preferable that the heights (positions in the Z direction) of the upper surfaces of the insulating layer 285 and the conductive layer 265 are the same or approximately the same. For example, the flatness of the upper surface of the insulating layer 285 can be improved by performing chemical mechanical polishing (CMP) processing or the like. Furthermore, by performing CMP processing, the positions of the upper surfaces of the insulating layer 285 and the conductive layer 265 can be made to be the same or approximately the same. By performing CMP processing, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0316] When an oxide semiconductor is used for the semiconductor layer 230, the conductive layer 255 in contact with the semiconductor layer 230 and the conductive layer 261 in contact with the semiconductor layer 230 are preferably made of a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0317] When an oxide semiconductor is used for the semiconductor layer 230, it is preferable to use a material containing oxygen and in which hydrogen is reduced for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 230, which is an oxide semiconductor, and the insulating layer 258 in which hydrogen is reduced makes it difficult for the semiconductor layer 230 to become n-type. Furthermore, contact between the semiconductor layer 230, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 230, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0318] In the case where an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in an amount of 1.0×10 converted into oxygen atoms as determined by thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C.

[0319] Furthermore, when a material containing excess oxygen is used for the insulating layer 258, a material through which oxygen is not easily transmitted may be used for the insulating layers 257 and 259. Examples of the material through which oxygen is not easily transmitted include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material through which oxygen is not easily transmitted for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is not easily released into the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure in which an insulating layer containing silicon and oxygen (the insulating layer 258) is provided between two insulating layers containing silicon and nitrogen (the insulating layer 257 and the insulating layer 259) is preferable.

[0320] When an oxide semiconductor is used for the semiconductor layer 230, by using a material containing hydrogen for the insulating layers 257 and 259, hydrogen is supplied to a region of the semiconductor layer 230 in contact with the insulating layer 257 and a region of the semiconductor layer 230 in contact with the insulating layer 259, and these regions become n-type depending on the composition of the oxide semiconductor used for the semiconductor layer 230. Therefore, the region of the semiconductor layer 230 in contact with the conductive layer 261 and the region of the semiconductor layer 230 in contact with the insulating layer 259 function as one of the source region and the drain region. The region of the semiconductor layer 230 in contact with the conductive layer 255 and the region of the semiconductor layer 230 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0321] The conductive layer 261 serves as one of the source and drain electrodes of the transistor 200C. The conductive layer 255 serves as the other of the source and drain electrodes of the transistor 200C. Thus, the conductive layer 261 serves as one of the conductive layers 242a and 242b in the transistors 200A and 200B. The conductive layer 255 serves as the other of the conductive layers 242a and 242b in the transistors 200A and 200B.

[0322] The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source and the drain of the transistor 200C are arranged at different heights. In other words, the source and the drain of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0323] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 158 as viewed from the X direction or the Y direction is the channel length L (channel length L1) (see FIG. 19B). Therefore, the channel length L of the transistor 200C is determined depending on the thickness t1 of the insulating layer 258.

[0324] Alternatively, the insulating layers 257 and 259 can be made of a material that does not contain hydrogen or contains very little hydrogen. When silicon nitride containing very little hydrogen or silicon nitride oxide containing very little hydrogen is used for the insulating layers 257 and 259, the region of the semiconductor layer 230 in contact with the insulating layer 257 and the region of the semiconductor layer 230 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 230 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 230 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 230 in contact with the insulating layer 258 functions as a channel formation region.

[0325] In this case, the sum of the lengths of the side surfaces of the insulating layers 257, 258, and 259 as viewed from the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 200C is determined according to the total thickness t2 of the insulating layers 257, 258, and 259. In this manner, the transistor 200C has a channel formation region that extends along the side surface of the insulating layer 256.

[0326] Furthermore, because the semiconductor layer 230 is provided in the opening 262, the perimeter of the opening 262 as viewed from the Z direction is the channel width W of the transistor 200C (see FIG. 19A ). The perimeter can be determined, for example, at a position halfway between the thickness t1 or the thickness t2 of the insulating layer 258. If necessary, the perimeter of any position on the opening 262 can be used as the channel width W. For example, the perimeter of the bottom of the opening 262 can be used as the channel width W, or the perimeter of the top of the opening 262 can be used as the channel width W. Although FIG. 19A shows the outline (planar shape) of the opening 262 as viewed from the Z direction as a circle, this is not limiting. For example, the outline of the opening 262 as viewed from the Z direction can be an ellipse, a rectangle, or the like.

[0327] In order to improve the coverage of the semiconductor layer 230, the insulating layer 250, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the side surface of the opening 262, i.e., the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, is preferably set to 45° or more and less than 90°, and more preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 19B ).

[0328] A vertical transistor can occupy a smaller area than a transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane (also called a "horizontal transistor"). Therefore, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical channel transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0329] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-state current of the transistor 200C, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0330] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0331] Embodiment 5 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0332] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0333] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0334] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 20A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 20B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0335] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 20B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 20A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 20A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 20A.

[0336] 20A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0337] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0338] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0339] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0340] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 20A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0341] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0342] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0343] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0344] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0345] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0346] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0347] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0348] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0349] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0350] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 20C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0351] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0352] Furthermore, as shown in FIG. 20C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0353] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0354] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0355]

[0356] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0357] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0358] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0359] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0360] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0361] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0362] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in improving performance such as miniaturization and low power consumption.

[0363] [Electronic Component] FIG. 21A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in FIG. 21A has a semiconductor device 710 inside a mold 711. FIG. 21A omits some parts in order to show the interior of the electronic component 709. The electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are connected to electrode pads 713, and the electrode pads 713 are connected to the semiconductor device 710 via wires 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on the printed circuit board 702 to complete the mounting substrate 704.

[0364] Furthermore, the semiconductor device 710 can be any of the semiconductor devices 100 (semiconductor devices 100A to 100D) according to one embodiment of the present invention. Therefore, the semiconductor device 710 can have a monolithic stacked structure in which a plurality of element layers are stacked. With the monolithic stacked structure, the layers can be connected to each other without using through-electrode technology such as TSV or bonding technology such as Cu-Cu direct bonding. By configuring the plurality of element layers as a monolithic stacked structure, it is possible to increase the speed of operation, particularly of the interface portions between the plurality of element layers.

[0365] Furthermore, by using a monolithic stacked structure, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins.

[0366] 21B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a system in package (SiP) or a multi-chip module (MCM). The electronic component 730 includes an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 710 and a plurality of semiconductor devices 720 provided on the interposer 731. The semiconductor device 710 and the plurality of semiconductor devices 720 can be the semiconductor device 100 according to one embodiment of the present invention.

[0367] In the electronic component 730, an example is shown in which a semiconductor device 720 using the semiconductor device 100 according to one embodiment of the present invention is used as a high bandwidth memory (HBM). In addition, in the electronic component 730, a semiconductor device 710 using the semiconductor device 100 according to one embodiment of the present invention can be used for an integrated circuit such as a CPU, a GPU, or an FPGA.

[0368] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0369] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, a TSV can also be used as the through electrode.

[0370] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0371] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0372] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space such as the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. It is possible to create a composite structure that combines a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0373] It is also preferable to provide a heat sink (heat sink) overlapping the electronic component 730. By providing a heat sink, the operation of the electronic component can be stabilized and reliability can be improved. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 720.

[0374] In order to mount the electronic component 730 on another substrate, electrodes 733 can be provided on the bottom of the package substrate 732. FIG. 21B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 can also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0375] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0376] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 22A . The electronic device 6500 shown in FIG. 22A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 has one or more functions selected from a CPU, a GPU, and a memory device, for example. The semiconductor device 100 according to one embodiment of the present invention can be used for the control device 6509, etc.

[0377] 22B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 has one or more functions selected from the group consisting of a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be used for the display portion 6615, the control device 6616, and the like. Note that the semiconductor device 100 of one embodiment of the present invention can be used for the control device 6616, and the like.

[0378] 22C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 22C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0379] The computer 5620 can have the configuration shown in the perspective view in Fig. 22D, for example. In Fig. 22D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0380] 22E is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 includes a board 5622. The board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that the semiconductor device 100 according to one embodiment of the present invention can be used for at least one of the semiconductor device 5626, the semiconductor device 5627, the semiconductor device 5628, and the connection terminal 5629, for example.

[0381] Note that Figure 22E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, reference can be made to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

[0382] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0383] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0384] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0385] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0386] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 709 can be used as the semiconductor device 5628.

[0387] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0388] [Space Equipment] A semiconductor device according to one embodiment of the present invention can be used in space equipment such as equipment for processing and storing information.

[0389] A semiconductor device according to one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space.

[0390] Fig. 23A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 23A, a planet 6804 is shown in outer space. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification also includes the thermosphere, mesosphere, and stratosphere.

[0391] 23A , a battery management system (also referred to as a “BMS”) or a battery control circuit can be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0392] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0393] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0394] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0395] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 has, for example, one or more functions selected from a CPU, a GPU, and a memory device. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and is therefore suitable for the control device 6807. The semiconductor device 100 according to one embodiment of the present invention can be used for the control device 6807, for example.

[0396] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0397] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0398] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0399] [Data Center] A semiconductor device according to one aspect of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, and ensuring cooling equipment required for maintaining the data.

[0400] By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. This leads to a reduction in the size of the storage system, the size of the power supply for storing data, and the size of the cooling equipment. This leads to a reduction in the space required for the data center.

[0401] Furthermore, the semiconductor device according to one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device according to one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0402] Fig. 23B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 23B has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0403] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 can be connected to each other via a network.

[0404] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0405] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0406] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0407] Note that by applying a semiconductor device according to one embodiment of the present invention to one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of a semiconductor device according to one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0408] This embodiment mode can be implemented in appropriate combination with other embodiment modes described in this specification.

[0409] 10: element layer, 20: element layer, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 24: conductive layer, 25: insulating layer, 30: element layer, 30[1]: element layer, 30[n]: element layer, 31: insulating layer, 32: insulating layer, 33: insulating layer, 33a: insulating layer, 33b: insulating layer, 33c: insulating layer, 33d: insulating layer, 33e: insulating layer, 33f: insulating layer, 33g: insulating layer, 33h: insulating layer, 34: plug, 34a: plug, 34b: plug, 34c: plug, 34d: plug, 34e: plug, 34f: plug, 35: conductive layer, 35a: conductive layer, 35b: conductive layer, 35c: conductive layer, 35 d: conductive layer, 35e: conductive layer, 35e[1]: conductive layer, 35e[2]: conductive layer, 41: conductive layer, 41[1]: conductive layer, 41[2]: conductive layer, 41[3]: conductive layer, 41[4]: conductive layer, 42: insulating layer, 43: insulating layer, 50: transistor, 51: substrate, 51c: semiconductor region, 52: insulating layer, 53: conductive layer, 54: low resistance region, 55: circuit, 56: circuit, 57: circuit, 58: circuit, 59: circuit, 60: transistor, 61: plug, 61a: plug, 61b: plug, 61c: plug, 61d: plug, 64: control amplifier, 70: transistor, 71: conductive layer , 71a: conductive layer, 71b: conductive layer, 71c: conductive layer, 71d: conductive layer, 81: element isolation layer, 82: insulating layer, 83: insulating layer, 83a: insulating layer, 83b: insulating layer, 83c: insulating layer, 83d: insulating layer, 83e: insulating layer, 83f: insulating layer, 83g: insulating layer, 83h: insulating layer, 85: insulating layer, 89: insulating layer, 90: supporting substrate, 91: insulating layer, 92: conductive layer, 93: opening, 99: control circuit, 100: semiconductor device, 100A: semiconductor device, 100B: semiconductor device, 100C: semiconductor device, 100D: semiconductor device, 110: functional circuit, 111: CPU, 112: GPU, 1 13: memory, 120: power supply circuit, 121: first power supply circuit, 122: second power supply circuit, 123: third power supply circuit, 124: fourth power supply circuit, 130: functional circuit, 130[1]: functional circuit, 130[n]: functional circuit, 131: memory, 131[1]: memory, 131[n]: memory, 132: memory, 132[1]: memory, 132[n]: memory, 151: NAND circuit, 200A: transistor, 200B: transistor, 200C: transistor, 201: insulating layer, 202: insulating layer, 205: conductive layer, 230: semiconductor layer, 240: conductive layer, 240a: conductive layer,240b: conductive layer, 241a: insulating layer, 241b: insulating layer, 242: conductive layer, 242a: conductive layer, 242b: conductive layer, 250: insulating layer, 255: conductive layer, 256: insulating layer, 257: insulating layer, 258: insulating layer, 259: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 261: conductive layer, 262: opening, 265: conductive layer, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 702: printed circuit board, 704: mounting board, 709: electronic component, 710: semiconductor device, 71 1: mold, 712: land, 713: electrode pad, 714: wire, 720: semiconductor device, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 900: memory device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server,7002: storage control circuit, 7003: storage, 7003md: storage device, ADDR: signal, Bias: terminal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, C41: capacitance element, C42: capacitance element, C43: capacitance element, C44: capacitance element, C45: capacitance element, C46: capacitance element, CA: capacitance element, CAL: wiring, CB: capacitance element, CC: capacitance element, CE: signal, CK: clock signal source, CL: terminal, CLB: terminal, CLK: signal, CLKB: signal, D92: rectifier element, Gd: terminal, GNDL: wiring, GW: signal, IN: terminal, L91: inductor, M10: transistor, M41 : transistor, M44: transistor, M65: transistor, M66: transistor, M67: transistor, M68: transistor, M69: transistor, M75: transistor, M81: transistor, M82: transistor, M83: transistor, M84: transistor, OUT: terminal, PW: external power supply, RBL: wiring, RDA: signal, Ref: terminal, RWL: wiring, SL: wiring, Vbias: voltage, VDD: high power supply potential, VDL: wiring, Vin: input voltage, Vout: output voltage, Vref: reference voltage, VSS: low power supply potential, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring,

Claims

1. A semiconductor device comprising: a first functional circuit having a first transistor; and a power supply circuit having a second transistor, wherein the first transistor is formed on a first surface side of a substrate, and the second transistor is formed on a second surface side of the substrate, the first transistor being electrically connected to the second transistor via a conductive layer formed on the second surface side, the first transistor including silicon in a semiconductor layer in which a channel is formed, and the second transistor including an oxide semiconductor in the semiconductor layer in which a channel is formed.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor contains indium.

3. A semiconductor device according to claim 1 or 2, wherein the first functional circuit has at least one of a CPU, a GPU, an FPGA, a memory, a digital circuit, and an analog circuit.

4. A semiconductor device according to claim 1 or 2, wherein the power supply circuit has at least one of a linear regulator circuit and a charge pump circuit.

5. A semiconductor device according to claim 1 or 2, wherein the conductive layer functions as a power supply line or a clock signal line.

6. A semiconductor device comprising: a first functional circuit having a first transistor; a power supply circuit having a second transistor; and a second functional circuit having a third transistor, wherein the first transistor is formed on a first surface side of a substrate; the second transistor is formed on a second surface side of the substrate; the third transistor is formed on the second surface side of the substrate so as to overlap with the power supply circuit; the first transistor is electrically connected to the second transistor via a conductive layer formed on the second surface side; the third transistor is electrically connected to the conductive layer; the first transistor includes silicon in a semiconductor layer in which a channel is formed; and each of the second transistor and the third transistor includes an oxide semiconductor in the semiconductor layer in which a channel is formed.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor contains indium.

8. The semiconductor device according to claim 6 or 7, wherein each of the first function circuit and the second function circuit has at least one of a CPU, a GPU, an FPGA, a memory, a digital circuit, and an analog circuit.

9. A semiconductor device according to claim 6 or 7, wherein the power supply circuit has at least one of a linear regulator circuit and a charge pump circuit.

10. A semiconductor device according to claim 6 or 7, wherein the conductive layer functions as a power supply line or a clock signal line.

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