Gate drive device

Abstract

This gate drive device comprises: an on-drive unit (11) that supplies an on-drive signal to the gate of an element (3) to be driven, thereby turning on the element to be driven; an off-drive unit (12) that supplies an off-drive signal to the gate of the element to be driven, thereby turning off the element to be driven; a drive control unit (18) that generates an on-drive command to output the on-drive command to the on-drive unit and generates an off-drive command to output the off-drive command to the off-drive unit, thereby controlling the on / off of the element to be driven; a limit command generation unit (23, 44) that generates and outputs a limit command for commanding the limit of the gate voltage of the element to be driven; and a gate voltage limiting unit (22, 22A) that limits the gate voltage of the element to be driven to a predetermined limit voltage higher than a mirror voltage by blocking the supply path of the on-drive signal leading from the on-drive unit to the gate of the element to be driven when the limit command is given in a period during which the on-drive command is input to the on-drive unit.

Description

Gate Driver CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2024-133964, filed on August 9, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a gate driver that drives one of two gate-driven semiconductor switching elements connected in series between a pair of DC power supply lines.

[0003] For example, in a gate drive device that drives gate-drive semiconductor switching elements that make up the upper and lower arms of an inverter circuit that drives a load such as a motor winding, it is required to minimize short-circuit energy when the upper and lower arms are short-circuited, as well as minimize conduction loss during normal operation. However, there is a trade-off between the short-circuit energy and conduction loss during normal operation, as described below.

[0004] That is, in the event of a short circuit, it is necessary to ensure that the short-circuit energy is below the short-circuit withstand capability of the semiconductor switching element to prevent failure of the element. If the short-circuit energy exceeds the short-circuit withstand capability of the element, one possible solution is to increase the short-circuit withstand capability of the element. However, this solution increases the size of the semiconductor switching element, resulting in another problem of an increased size of the configuration.

[0005] Therefore, when the short-circuit energy exceeds the short-circuit withstand capability of the element, it is possible to take measures to reduce the short-circuit energy. A specific example of such a measure is to reduce the gate voltage applied to the gate of the semiconductor switching element, thereby suppressing the current flowing through the semiconductor switching element during a short circuit and reducing the short-circuit energy. However, this configuration increases the on-resistance of the semiconductor switching element under normal conditions, which results in increased conduction loss under normal conditions.

[0006] A two-stage turn-on technique can be cited as a technique for improving the trade-off between short-circuit energy and conduction loss. In the two-stage turn-on technique, the gate voltage at turn-on is changed in two stages, first to a relatively low second voltage and then to a relatively high first voltage. Specifically, in the two-stage turn-on technique, the gate voltage is clamped, or limited, to the second voltage during turn-on control. A short circuit is determined within a predetermined time from that point. If no short circuit is determined, the device is considered normal, the clamp is released, and the gate voltage is increased to the first voltage.

[0007] According to this two-stage turn-on technique, when a short circuit occurs, the gate voltage is kept at a relatively low second voltage, thereby reducing short-circuit energy, and during normal operation, the gate voltage is raised to a relatively high first voltage, thereby suppressing an increase in conduction loss during normal operation without increasing the on-resistance of the semiconductor switching element. Patent Document 1 discloses a configuration for realizing this two-stage turn-on technique.

[0008] Patent No. 5761215

[0009] As exemplified by the configuration disclosed in Patent Document 1, conventional configurations for realizing two-stage ON technology require the addition of an additional circuit for drawing current from the gate of a semiconductor switching element when the element is turned ON. Such an additional circuit requires a size equivalent to that of the circuit for turning the semiconductor switching element ON. Therefore, in conventional configurations, the area of ​​the additional circuitry required to realize two-stage ON is inevitably large, resulting in a problem of an increase in the size of the gate driver configuration.

[0010] An object of the present disclosure is to provide a gate driver that can reduce short-circuit energy during a short circuit and suppress an increase in conduction loss during normal operation without increasing the size of the configuration.

[0011] In one aspect of the present disclosure, a gate drive device drives one of two gate-driven semiconductor switching elements connected in series between a pair of DC power supply lines, and includes an ON drive unit, an OFF drive unit, a drive control unit, a limit command generation unit, and a gate voltage limiting unit. When an ON drive command is input to command ON drive of a drive target element, which is the semiconductor switching element to be driven, of the two semiconductor switching elements, the ON drive unit supplies an ON drive signal to the gate of the drive target element to drive ON the drive target element.

[0012] When an off drive command instructing to drive the element to be driven off is input, the off drive unit supplies an off drive signal to the gate of the element to be driven, thereby driving the element to be driven off. The drive control unit generates the on drive command and outputs it to the on drive unit, and generates the off drive command and outputs it to the off drive unit, thereby controlling the on / off of the element to be driven. The limit command generation unit generates and outputs a limit command instructing to limit the gate voltage of the element to be driven. When the limit command is given during a period in which the on drive command is input to the on drive unit, the gate voltage limit unit limits the gate voltage of the element to be driven to a predetermined limit voltage higher than a mirror voltage by blocking the supply path of the on drive signal from the on drive unit to the gate of the element to be driven.

[0013] According to the above configuration, when controlling the turn-on of a semiconductor switching element, the gate voltage of the element to be driven can be limited by the action of the gate voltage limiting unit. In this case, the gate voltage limiting unit only needs to be configured to block the supply path of the on-drive signal, so its size can be kept smaller than conventional configurations. Therefore, according to the above configuration, it is possible to obtain the excellent effect of keeping short-circuit energy small in the event of a short circuit and suppressing an increase in conduction loss during normal operation without increasing the size of the configuration.

[0014] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is a diagram schematically illustrating the configuration of a gate driver and a half-bridge circuit according to a first embodiment, Fig. 2 is a diagram illustrating a specific configuration example of the gate driver according to the first embodiment, Fig. 3 is a diagram illustrating a specific configuration example of a gate driver according to a comparative example, Fig. 4 is a diagram illustrating example waveforms of the gate voltage, drain current, drain voltage, etc. of a driven element under normal and short-circuit conditions according to the comparative example, Fig. 5 is a diagram illustrating example operational waveforms of each part during turn-on control according to the comparative example, Fig. 6 is a diagram illustrating example operational waveforms of each part during turn-on control according to the first embodiment, Fig. 7 is a diagram illustrating a specific configuration example of a gate driver according to a modified example, and Fig. 8 is a diagram illustrating a gate driver according to a second embodiment. FIG. 10 is a diagram showing a specific configuration example of such a gate drive device; FIG. 9 is a diagram showing an example of the operating waveforms of each part during turn-on control in the second embodiment; FIG. 10 is a diagram showing a specific configuration example of a gate drive device in the third embodiment; FIG. 11 is a diagram showing an example of the operating waveforms of each part during turn-on control in the third embodiment; FIG. 12 is a diagram for explaining two methods for determining the short-circuit behavior of drain current in the modified example; FIG. 13 is a diagram for explaining the method for detecting drain current when the first method is adopted as the short-circuit behavior determination method in the modified example; and FIG. 14 is a diagram for explaining the method for detecting drain current when the second method is adopted as the short-circuit behavior determination method in the modified example.

[0015] Hereinafter, several embodiments will be described with reference to the drawings. Note that substantially the same components in each embodiment will be denoted by the same reference numerals and the description thereof will be omitted. (First Embodiment) Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 7.

[0016] 1, the gate drive device 1 of this embodiment drives a gate drive type semiconductor switching element 3 that constitutes the lower arm of a half-bridge circuit 2 connected between a pair of DC power supply lines L1 and L2. In other words, the gate drive device 1 of this embodiment drives one of two semiconductor switching elements 3 and 4 that are connected in series between the pair of DC power supply lines L1 and L2.

[0017] The gate-driven semiconductor switching element 4 that constitutes the upper arm of the half-bridge circuit 2 is driven by a gate driving device (not shown) that is configured in the same manner as the gate driving device 1 of this embodiment. In this specification, of the two semiconductor switching elements 3, 4, the semiconductor switching element 3 that is the driving target of the gate driving device 1 may be referred to as the driven element, and of the two semiconductor switching elements 3, 4, the semiconductor switching element 4 that is not the driving target of the gate driving device 1 may be referred to as the non-driven element.

[0018] The semiconductor switching elements 3 and 4 are both power elements, and in this case, each includes an N-channel MOSFET and a freewheeling diode connected between the drain and source of the MOSFET with the source side as the anode, i.e., connected in anti-parallel to the MOSFET. In this case, the semiconductor switching elements 3 and 4 are SiC elements made of silicon carbide.

[0019] The drain of the semiconductor switching element 4 is connected to a high-potential side DC power supply line L1. The DC power supply line L1 is connected to a high-potential side terminal of a DC power supply 5 such as a battery. The source of the semiconductor switching element 4 is connected to the drain of the semiconductor switching element 3. The source of the semiconductor switching element 3 is connected to a low-potential side DC power supply line L2. The DC power supply line L2 is connected to a low-potential side terminal of the DC power supply 5. In this case, the potential of the DC power supply line L2 serves as the ground, which is the reference potential of the circuit. A node N1, which is the interconnection node of the two semiconductor switching elements 3 and 4, is connected to a load 6 such as a motor winding. As a result, the output current of the half-bridge circuit 2 is supplied to the load 6.

[0020] <Specific Configuration of Gate Drive Device> As a specific configuration of the gate drive device 1 of this embodiment, for example, a configuration example as shown in Fig. 2 can be adopted. The gate drive device 1 of this embodiment has the same basic configuration as a gate drive device 100 of a comparative example to which a general short-circuit protection technique is applied, as shown in Fig. 3. Therefore, hereinafter, the configuration of the gate drive device 100 of the comparative example will first be described, and then the configuration of the gate drive device 1 of this embodiment will be described.

[0021] As shown in FIG. 3 , the gate drive device 100 of the comparative example includes an ON drive unit 11, an OFF drive unit 12, a control unit 113, and a Desat detection circuit 14, and is configured as an IC. The ON drive unit 11 turns on the drive target element based on a drive command signal Sa generated by the control unit 113. The ON drive unit 11 includes a buffer 15, a MOSFET transistor Q1, and a resistor R1. The buffer 15 receives the drive command signal Sa and outputs a signal corresponding to the input signal. As shown in FIG. 5 and other figures, the drive command signal Sa is a binary signal that commands the ON drive of the semiconductor switching element 3 when it is at a high level. In other words, in this case, a high-level drive command signal Sa corresponds to an ON drive command that commands the ON drive of the drive target element.

[0022] The output terminal of the buffer 15 is connected to the gate of the transistor Q1. The transistor Q1 is turned on when the output signal of the buffer 15 is at a high level, and turned off when the output signal of the buffer 15 is at a low level. In other words, the transistor Q1 is turned on when an ON drive command is input, and turned off when no ON drive command is input. The drain of the transistor Q1 is connected to a power supply line 16 to which a first voltage V1 is supplied. The first voltage V1 is a voltage that is sufficiently higher than the gate threshold voltage of the semiconductor switching element 3.

[0023] The source of transistor Q1 is connected to node N2 via resistor R1. Node N2 is connected to the gate of semiconductor switching element 3. Resistor R1 has a fixed resistance value and functions as a gate resistor when semiconductor switching element 3 is turned on. When an on drive command is input to on driver 11 configured as described above, transistor Q1 is turned on, causing a charging current to flow that charges the gate capacitance of semiconductor switching element 3.

[0024] In this case, the charging current that charges the gate capacitance of the semiconductor switching element 3 corresponds to the ON drive signal. In this way, when an ON drive command instructing to turn on the semiconductor switching element 3 is input, the ON drive unit 11 is configured to supply the ON drive signal to the gate of the semiconductor switching element 3, thereby turning on the semiconductor switching element 3. The supply path of the charging current that corresponds to the ON drive signal is "power supply line 16 → transistor Q1 → resistor R1 → gate of the semiconductor switching element 3."

[0025] The off-drive unit 12 includes a buffer 17, a MOSFET transistor Q2, and a resistor R2. The buffer 17 receives a drive command signal Sb and outputs a signal corresponding to the input signal. As shown in FIG. 5 and other figures, the drive command signal Sb is a binary signal, and when it is at a high level, it commands the semiconductor switching element 3 to be driven off. In other words, in this case, a high-level drive command signal Sb corresponds to an off-drive command that commands the element to be driven to be driven off.

[0026] The output terminal of the buffer 17 is connected to the gate of the transistor Q2. The transistor Q2 is turned on when the output signal of the buffer 17 is at a high level, and turned off when the output signal of the buffer 17 is at a low level. In other words, the transistor Q2 is turned on when an OFF drive command is input, and turned off when an OFF drive command is not input. The source of the transistor Q2 is connected to the ground, which is the reference potential of the circuit. The ground in this case is different from the ground in the half-bridge circuit 2.

[0027] The drain of transistor Q2 is connected to node N2 via resistor R2. Resistor R2 has a fixed resistance value and functions as a gate resistor when semiconductor switching element 3 is turned off. When an off drive command is input to off driver 12 configured as described above, transistor Q2 is turned on, causing a discharge current to flow that discharges the gate capacitance of semiconductor switching element 3.

[0028] In this case, the discharge current that discharges the gate capacitance of semiconductor switching element 3 corresponds to the OFF drive signal. In this way, when an OFF drive command instructing to drive semiconductor switching element 3 OFF is input, OFF drive unit 12 supplies the OFF drive signal to the gate of semiconductor switching element 3, thereby driving semiconductor switching element 3 OFF. The supply path of the discharge current that corresponds to the OFF drive signal is "gate of semiconductor switching element 3 → resistor R2 → transistor Q2 → ground."

[0029] The control unit 113 is configured with logic circuits and the like, and includes functional blocks such as a drive control unit 118 and a short-circuit determination unit 19. The drive control unit 118 generates a drive command signal Sa and provides the generated drive command signal Sa to the ON drive unit 11. The drive control unit 118 generates a drive command signal Sb and provides the generated drive command signal Sb to the OFF drive unit 12. In other words, the drive control unit 118 controls the ON / OFF of the element to be driven by generating an ON drive command and outputting it to the ON drive unit 11 and generating an OFF drive command and outputting it to the OFF drive unit 12.

[0030] The short-circuit determination unit 19 determines whether the semiconductor switching element 4, which is the non-drive target element, is in a short-circuited state based on the voltage Vd of the drain, which is the main terminal of the semiconductor switching element 3, which is the drive target element. As shown in Fig. 4, the gate voltage Vg of the drive target element, the current flowing through the drive target element, i.e., the drain current Id of the drive target element, and the drain voltage Vd of the drive target element behave differently in a normal state in which the non-drive target element is not in a short-circuited state and in a short-circuited state in which the non-drive target element is in a short-circuited state.

[0031] 4, the waveforms under normal conditions are indicated by dashed lines, and the waveforms under short-circuit conditions are indicated by solid lines. Of these voltages and currents, the drain voltage Vd is relatively low under normal conditions in the latter half of the turn-on period, but is relatively high under short-circuit conditions. The short-circuit determination unit 19 determines whether the non-driven element is in a short-circuit state based on such changes in the behavior of the drain voltage Vd.

[0032] In this case, the short-circuit determination unit 19 is configured to determine a short-circuit state using the Desat method. That is, the short-circuit determination unit 19 determines a short-circuit state based on the detection signal Sc output from the Desat detection circuit 14. The Desat detection circuit 14 includes a diode D1 and a capacitor C1. The cathode of the diode D1 is connected to a node N1, and the anode is connected to the DC power supply line L2 via the capacitor C1. The node N3, which is the interconnection node between the diode D1 and the capacitor C1, serves as the output node for the detection signal Sc. With this configuration, the detection signal Sc is at a relatively low level, such as 0 V, when the non-driven element is in a non-short-circuit state, and is at a relatively high level, such as 5 V, when the non-driven element is in a short-circuit state.

[0033] The short-circuit determination unit 19 determines whether the element to be driven is in a short-circuit state based on such a change in the level of the detection signal Sc. More specifically, the short-circuit determination unit 19 determines that the element to be driven is in a short-circuit state when it determines that the drain voltage Vd exceeds a predetermined threshold voltage Va based on the level of the detection signal Sc. When the short-circuit determination unit 19 determines that the non-drive element is in a short-circuit state, the drive control unit 118 outputs an off-drive command to the off-drive unit 12. As a result, in the above configuration, the element to be driven is cut off after the short-circuit determination unit 19 determines that it is in a short-circuit state.

[0034] The gate driver 1 of this embodiment shown in Fig. 2 has added configuration and control for realizing the two-stage ON technique to the gate driver 100 of the comparative example shown in Fig. 3. As will be described in detail later, during turn-on control, the gate driver 1 temporarily clamps, or limits, the gate voltage Vg of the element to be driven to the second voltage V2, and then determines whether or not a short circuit has occurred within a predetermined time limit Ta. If no short circuit is determined to have occurred, the gate driver 1 determines that the element is normal, releases the clamp, and raises the gate voltage Vg to the first voltage V1.

[0035] 2, the gate driving device 1 of this embodiment differs from the gate driving device 100 of the comparative example in that it includes a control unit 13 instead of the control unit 113, and in that it additionally includes a gate voltage detection unit 21 and a gate voltage limiting unit 22. The control unit 13 differs from the control unit 113 of the comparative example in that it includes a drive control unit 18 instead of the drive control unit 118, and in that it additionally includes a limit command generating unit 23.

[0036] The gate voltage detection unit 21 includes a voltage source 24 and a comparator 25. The voltage source 24 is a constant voltage source that outputs a second voltage V2. The second voltage V2 corresponds to a predetermined limit voltage, and is higher than the gate threshold voltage and mirror voltage of the semiconductor switching element 3, but lower than the first voltage V1. The second voltage V2 is applied to an inverting input terminal of the comparator 25. A non-inverting input terminal of the comparator 25 is connected to the gate of the semiconductor switching element 3.

[0037] According to the above configuration, the detection signal Sd output from the comparator 25 is a binary signal that changes depending on the gate voltage Vg of the semiconductor switching element 3. Specifically, the detection signal Sd is at a high level when the gate voltage Vg is higher than the second voltage V2, and is at a low level when the semiconductor gate voltage Vg is lower than the second voltage V2. The detection signal Sd is provided to the control unit 13.

[0038] The limit command generating unit 23 of the control unit 13 generates and outputs the limit command signal Se based on the detection signal Sd. As shown in Fig. 6 and other figures, the limit command signal Se is a binary signal, and when it is at a high level, it commands the limiting of the gate voltage Vg of the semiconductor switching element 3. That is, in this case, the high-level limit command signal Se corresponds to a limit command that commands the limiting of the gate voltage of the element to be driven.

[0039] The limit command generator 23 starts outputting the limit command when the gate voltage Vg of the element to be driven reaches the second voltage V2, which is a predetermined limit voltage, and ends outputting the limit command when a predetermined limit time Ta has elapsed from the time when output of the limit command started. Therefore, the limit command signal Se generated by the limit command generator 23 becomes a signal that changes from low level to high level when the detection signal Sd changes from low level to high level, that is, when the gate voltage Vg reaches the second voltage V2, and changes from high level to low level when the limit time Ta has elapsed from that point.

[0040] The gate voltage limiting unit 22 is composed of an AND circuit. The drive command signal Sa is input to the non-inverting input terminal of the AND circuit, and the limit command signal Se is input to the inverting input terminal of the AND circuit. In this case, the output signal of the gate voltage limiting unit 22 is input to the buffer 15 of the ON driver 11. The output signal of the gate voltage limiting unit 22 becomes a signal that represents the same logic as the drive command signal Sa while the limit command signal Se is at a low level, that is, while no limit command is being issued. Therefore, the ON driver 11 can execute an operation of driving the semiconductor switching element 3 ON based on the drive command signal Sa while no limit command is being issued.

[0041] The output signal of the gate voltage limiting unit 22 is at a low level while the limiting command signal Se is at a high level, i.e., while the limiting command is being given, regardless of the level of the drive command signal Sa. Therefore, the ON driver 11 cannot perform the operation of turning on the semiconductor switching element 3 based on the drive command signal Sa while the limiting command is being given. In other words, the operation of the ON driver 11 is stopped while the limiting command is being given. Therefore, while the limiting command is being given, the supply path of the ON drive signal from the ON driver 11 to the gate of the element to be driven is interrupted.

[0042] With this configuration, when a limit command is given to the ON drive unit 11 during a period in which an ON drive command is input, the gate voltage limiting unit 22 can limit the gate voltage Vg of the driven element to the second voltage V2 by cutting off the supply path of the ON drive signal from the ON drive unit 11 to the gate of the driven element. In this case, the limit command signal Se is a signal that remains high for only the limit time Ta. In other words, the limit command is given only for the limit time Ta. Therefore, when the limit command is no longer given after cutting off the supply path of the ON drive signal, the gate voltage limiting unit 22 can raise the gate voltage Vg of the driven element to the first voltage V1 by canceling the cutoff of the supply path of the ON drive signal.

[0043] Next, the operation of the above-described configuration regarding turn-on control during normal operation and during a short circuit will be described with reference to Figures 5 and 6. [1] Operation with the configuration of the comparative example The operating waveforms of each part during turn-on control in the configuration of the comparative example are as shown in Figure 5. In the configuration of the comparative example, during normal operation, the gate voltage Vg starts to rise from the time ta when the drive command signal Sa changes to a high level, and then passes through a mirror region in which the gate voltage Vg is maintained at the mirror voltage Vm, i.e., a mirror period Tm, before rising to the first voltage V1.

[0044] In the comparative example, in the event of a short circuit, the gate voltage Vg starts to rise from time ta when the drive command signal Sa goes high and rises to the first voltage V1. In this case, the short-circuit determination unit 19 determines that a short circuit has occurred at time tb, a predetermined time after the gate voltage Vg reaches the first voltage V1. Then, at time t2, the drive command signal Sa goes low and the drive command signal Sb goes high, thereby cutting off the element to be driven.

[0045] In the configuration of the comparative example, the gate voltage Vg is set to a relatively high first voltage V1 during a short circuit, which inevitably results in large short-circuit energy. As shown in the bottom part of Figure 4, the area of ​​the waveform representing the product of the drain current Id and the drain voltage Vd corresponds to the short-circuit energy. In the configuration of the comparative example, in order to reduce the short-circuit energy during a short circuit, the first voltage V1 needs to be reduced.

[0046] However, when the first voltage V1 is reduced, the on-resistance of the element to be driven during normal operation increases, resulting in a problem of increased conduction loss during normal operation. As such, with the configuration of the comparative example, it is difficult to simultaneously reduce the short-circuit energy during a short circuit and prevent an increase in conduction loss during normal operation.

[0047] [2] Operation of the Configuration of this Embodiment The operating waveforms of each part during turn-on control in the configuration of this embodiment are as shown in Figure 6. In the configuration of this embodiment, under normal conditions, the gate voltage Vg starts to rise from time t1 when the drive command signal Sa goes high, and then passes through a mirror region in which the gate voltage Vg is maintained at the mirror voltage Vm, i.e., a mirror period Tm, before reaching the second voltage V2 at time t2. Then, at time t2, the limit command signal Se goes high, and the gate voltage Vg is clamped to the second voltage V2.

[0048] This clamping of the gate voltage Vg continues until time t4, when the limit time Ta has elapsed. During the period in which the gate voltage Vg is being clamped, the short-circuit determination unit 19 determines whether a short circuit has occurred. At time t4, the limit command signal Se goes low, thereby releasing the clamping of the gate voltage Vg and causing the gate voltage Vg to start rising again, up to the first voltage V1.

[0049] In the configuration of this embodiment, in the event of a short circuit, the gate voltage Vg starts to rise from time t1 when the drive command signal Sa goes high, and rises to the second voltage V2 at time t2. Then, at time t2, the limit command signal Se goes high, clamping the gate voltage Vg to the second voltage V2. This clamping of the gate voltage Vg continues until time t4 when the limit time Ta has elapsed. During the period in which the gate voltage Vg is being clamped, the short-circuit determination unit 19 determines whether a short circuit exists.

[0050] In this case, the short-circuit determination unit 19 determines that a short circuit has occurred at time t3, which is before time t4. Then, at time t3, the drive command signal Sa goes low and the drive command signal Sb goes high, thereby cutting off the element to be driven. In the configuration of this embodiment, the gate voltage Vg is kept at the relatively low second voltage V2 during a short circuit, so that the short-circuit energy can be kept small compared to the comparative example.

[0051] Furthermore, in the configuration of this embodiment, since it is not necessary to reduce the first voltage V1, an increase in the on-resistance of the driven element during normal operation is suppressed, and as a result, an increase in conduction loss during normal operation can be suppressed. In this way, with the configuration of this embodiment, it is possible to both reduce the short-circuit energy during a short circuit and suppress an increase in conduction loss during normal operation.

[0052] According to the present embodiment described above, when controlling the turn-on of the semiconductor switching element 3, which is the element to be driven, the gate voltage Vg of the element to be driven can be limited by the action of the gate voltage limiting unit 22. In this case, the gate voltage limiting unit 22 only needs to be configured to be able to block the supply path of the on-drive signal, and therefore its size can be kept smaller than that of conventional configurations. Therefore, according to this embodiment, the excellent effects of being able to keep short-circuit energy small in the event of a short circuit and to suppress an increase in conduction loss during normal operation can be obtained without increasing the size of the configuration.

[0053] In this embodiment, when the gate voltage limiting unit 22 no longer receives a limiting command after cutting off the supply path of the ON drive signal, the gate voltage limiting unit 22 releases the cutoff of the supply path of the ON drive signal. Also, in this embodiment, when the short-circuit determining unit 19 determines that the non-driven element is in a short-circuit state, the drive control unit 18 outputs an OFF drive command to the OFF drive unit 12. This configuration makes it possible to realize a two-stage ON technique, thereby effectively improving the trade-off between short-circuit energy and conduction loss.

[0054] In this embodiment, the limit command generator 23 starts outputting the limit command when the gate voltage Vg of the drive target element reaches the second voltage V2, which is a predetermined limit voltage, and ends outputting the limit command when a predetermined limit time Ta has elapsed since the start of outputting the limit command. With this configuration, it is possible to perform a clamp operation with high accuracy so that the gate voltage Vg becomes the desired limit voltage.

[0055] <Modifications of Gate Voltage Limiting Unit> The gate voltage limiting unit may have any configuration as long as it can limit the gate voltage Vg of the element to be driven by cutting off the supply path of the on-drive signal, and may be modified, for example, to the configuration shown in Fig. 7. A gate voltage limiting unit 22A provided in a gate drive device 1A of the modified example shown in Fig. 7 includes a transistor Q3 and an inverter circuit 27.

[0056] Transistor Q3 is a MOSFET similar to transistor Q1. In this case, the drain of transistor Q3 is connected to power supply line 16, and the drain of transistor Q1 is connected to the source of transistor Q3. That is, transistors Q1 and Q3 are connected in series between power supply line 16 and the gate of semiconductor switching element 3. In this case, buffer 15 receives drive command signal Sa and outputs a signal corresponding to the input signal, similar to the configuration of the comparative example shown in FIG.

[0057] The inverter circuit 27 receives the limiting command signal Se and outputs an inverted signal of the input signal. The output terminal of the inverter circuit 27 is connected to the gate of the transistor Q3. The transistor Q3 is turned on when the output signal of the inverter circuit 27 is high, i.e., when the limiting command signal Se is low, and is turned off when the output signal of the inverter circuit 27 is low, i.e., when the limiting command signal Se is high.

[0058] According to the configuration of the above-described modified example, during the period when the restriction command signal Se is at a low level, i.e., during the period when no restriction command is given, the transistor Q3 is on, which enables the on-drive unit 11 to perform the operation of driving the semiconductor switching element 3 on based on the drive command signal Sa. Also, according to the configuration of the above-described modified example, during the period when the restriction command signal Se is at a high level, i.e., during the period when a restriction command is given, the transistor Q3 is off, which blocks the supply path of the on-drive signal from the on-drive unit 11 to the gate of the element to be driven.

[0059] Therefore, according to the configuration of the above-described modified example, while the limit command is being given, the ON drive unit 11 cannot perform the operation of driving the semiconductor switching element 3 ON regardless of the level of the drive command signal Sa. In other words, while the limit command is being given, the operation of the ON drive unit 11 is stopped. Therefore, even with the configuration of this modified example, when a limit command is given during the period when the ON drive command is input to the ON drive unit 11, the supply path of the ON drive signal from the ON drive unit 11 to the gate of the driven element can be cut off, thereby limiting the gate voltage Vg of the driven element to the second voltage V2.

[0060] Second Embodiment A second embodiment will be described below with reference to Fig. 8 and Fig. 9. As shown in Fig. 8, in this embodiment, a resistor R31, which is a pull-down resistor, is added and connected between the gate and source of a semiconductor switching element 3, which is an element to be driven. SiC elements are generally provided with such a pull-down resistor to prevent false turn-on.

[0061] In this configuration, when the supply path of the ON drive signal is interrupted, that is, when the execution of ON drive by the ON drive unit 11 is stopped, the following behavior is repeated. That is, when the execution of ON drive is stopped, the gate capacitance is discharged via the resistor R31, causing the gate voltage Vg to drop from the second voltage V2. Then, the restriction of the gate voltage Vg by the gate voltage limiting unit 22, i.e., the clamping, is released, and the execution of ON drive is resumed.

[0062] As a result, the gate voltage Vg starts to rise and reaches the second voltage V2, after which the execution of the ON drive is stopped and the gate voltage Vg is clamped. Then, when the execution of the ON drive is stopped, the gate voltage Vg drops from the second voltage V2. As this behavior is repeated, the gate voltage Vg is not maintained at the second voltage V2 during the time limit Ta, but instead rises and drops alternately, as shown by the dashed-dotted waveform in Figure 9 . The presence of this period in which the gate voltage Vg drops may result in an increase in conduction loss during normal operation.

[0063] Therefore, in order to prevent such a drop in gate voltage Vg, gate drive device 31 of this embodiment includes a drop suppression unit 32. Drop suppression unit 32 includes transistor Q31, voltage source 33, and operational amplifier 34. Transistor Q31 is a MOSFET similar to transistor Q1. The drain of transistor Q31 is connected to power supply line 16 to which first voltage V1 is supplied. The source of transistor Q31 is connected to node N2, i.e., the gate of semiconductor switching element 3.

[0064] The voltage source 33 is a constant voltage source that outputs a second voltage V2. The second voltage V2 is provided to a non-inverting input terminal of an operational amplifier 34. The non-inverting input terminal of the comparator 25 is connected to the gate of the semiconductor switching element 3. The inverting input terminal of the operational amplifier 34 is connected to a node N2, i.e., the gate of the semiconductor switching element 3. A drive command signal Sa is provided to the operational amplifier 34.

[0065] The OP amplifier 34 is configured to operate when the drive command signal Sa is at a high level and to stop operating when the drive command signal Sa is at a low level. As a result, when the drive command signal Sa is at a high level, that is, when an ON drive command is input, the OP amplifier 34 operates, thereby performing feedback control so that the gate voltage Vg becomes the second voltage V2. With the decrease suppression unit 32 configured in this way, it is possible to suppress a decrease in the gate voltage Vg of the element to be driven during a period when the supply path of the ON drive signal is blocked by the gate voltage limiting unit 22 under normal circumstances, as shown by the solid line waveform in Figure 9.

[0066] According to the present embodiment described above, by providing the decrease suppression unit 32 that suppresses a decrease in the gate voltage Vg of the semiconductor switching element 3 during the period when the supply path of the ON drive signal is blocked by the gate voltage limiting unit 22, it is possible to maintain the gate voltage Vg at the second voltage V2 during the period when the execution of ON drive is stopped. Therefore, according to the present embodiment, even in a configuration in which the resistor R31, which is a pull-down resistor, is connected to the gate of the semiconductor switching element 3, an increase in conduction loss during normal operation can be suppressed.

[0067] Third Embodiment A third embodiment will now be described with reference to Figures 10 to 14. As shown in Figure 10, a gate drive device 41 of this embodiment differs from the gate drive device 1 of the first embodiment in that it includes a control unit 42 instead of the control unit 13, and a current detection unit 43 instead of the gate voltage detection unit 21.

[0068] The control unit 42 differs from the control unit 13 in that it includes a limit command generation unit 44 instead of the limit command generation unit 23. The current detection unit 43 detects the drain current Id of the semiconductor switching element 3, i.e., the current flowing through the element to be driven, and includes a resistor R41, a voltage source 45, and a comparator 46. The resistor R41 is a shunt resistor, and is connected between the source of the semiconductor switching element 3 and the DC power supply line L2.

[0069] The voltage at node N41, which is the interconnection node between the source of semiconductor switching element 3 and resistor R41, corresponds to the drain current Id. Node N41 is connected to the non-inverting input terminal of comparator 46. Voltage source 45 is a constant voltage source that outputs a threshold voltage Vb. The threshold voltage Vb is provided to the inverting input terminal of comparator 46. The threshold voltage Vb is a voltage corresponding to the threshold current Ith for determining whether the drain current Id exhibits short-circuit behavior. Short-circuit behavior refers to the behavior of a non-driven element when it changes from a non-short-circuit state to a short-circuit state.

[0070] 11, the magnitude of the drain current Id differs between the normal state in which the non-driven element is not short-circuited and the short-circuit state in which the non-driven element is short-circuited. That is, the short-circuit behavior of the drain current Id is that the current increases. The threshold voltage Vb is set to a voltage value that can determine the difference in the magnitude of the drain current Id.

[0071] According to the above configuration, the detection signal Sf output from the comparator 46 is a binary signal that changes depending on whether the drain current Id indicates a short circuit. Specifically, the detection signal Sf goes high when the drain current Id indicates a short circuit, and goes low when the drain current Id does not indicate a short circuit. The detection signal Sf is provided to the control unit 42.

[0072] The limit command generator 44 of the control unit 42 generates and outputs a limit command signal Sg based on the detection signal Sf. The limit command signal Sg is a binary signal similar to the limit command signal Se, and commands limiting of the gate voltage Vg of the semiconductor switching element 3 when it is at a high level. In other words, in this case, a high-level limit command signal Sg corresponds to a limit command that commands limiting of the gate voltage of the element to be driven. With this configuration, the limit command generator 44 can output a limit command when the current flowing through the element to be driven exhibits short-circuit behavior.

[0073] Next, the operation of the above-described configuration regarding turn-on control during a short circuit will be described with reference to Fig. 11. The operational waveforms of each part during turn-on control in the configuration of this embodiment are as shown in Fig. 11. In Fig. 11, the waveforms during a short circuit in this embodiment are shown by solid lines, the waveforms during normal operation in this embodiment are shown by dotted lines, and the waveforms during a short circuit in the first embodiment are shown by dashed lines.

[0074] In the configuration of this embodiment, when a short circuit occurs and the drain current Id reaches the threshold voltage Vb, the limit command signal Sg transitions to a high level, clamping the gate voltage Vg to the voltage at that time. Therefore, the predetermined limit voltage in this embodiment is higher than the mirror voltage but lower than the second voltage V2. The short-circuit determination unit 19 then determines whether a short circuit exists, and determines that a short circuit exists at time t41. Then, at time t41, the drive command signal Sa transitions to a low level and the drive command signal Sb transitions to a high level, thereby shutting off the device to be driven.

[0075] According to the present embodiment described above, the limit command generator 44 is configured to output a limit command when the drain current Id exhibits short-circuit behavior. Therefore, according to the present embodiment, the gate voltage Vg is immediately clamped when the drain current Id exhibits short-circuit behavior. Therefore, the voltage at the time of clamping, i.e., the limit voltage, is kept low compared to when the gate voltage Vg is clamped when it reaches the second voltage V2. As a result, according to the present embodiment, the short-circuit energy can be reduced by the area indicated by the hatching in FIG. 11 compared to when the gate voltage Vg is clamped when it reaches the second voltage V2.

[0076] Furthermore, according to this embodiment, during normal turn-on control, the gate voltage Vg is no longer clamped to the second voltage V2, which allows the gate voltage Vg to rise to the first voltage V1 more quickly, resulting in the effect of keeping conduction loss low during normal operation.

[0077] <Variations on the method for determining the short-circuit behavior of the drain current Id> As shown in Figure 12, methods for determining the short-circuit behavior of the drain current Id include a first method that determines the behavior based on the difference in the magnitude of the drain current Id, and a second method that measures the time over which the drain current Id is changing, in other words, the time it takes to reach a peak value from zero, and determines the behavior based on the difference in that time.

[0078] In the above embodiment, the first method is used to determine the short-circuit behavior of the drain current Id, but when the first method is used, any of the three methods shown in Fig. 13 can be used to detect the drain current Id. Note that, in the waveforms shown in the bottom row of Fig. 13, the waveform during a short circuit is indicated by a solid line, and the waveform during normal operation is indicated by a dashed dotted line.

[0079] The shunt resistor method is the method adopted in the above embodiment, and outputs a voltage according to the drain current Id using a resistor R41, which is a shunt resistor connected in series to the semiconductor switching element 3. The output voltage Vo using the shunt resistor method can be expressed by the following equation (1), where the resistance value of the resistor R41 is Ra: Vo = Ra × drain current Id (1)

[0080] In the sense MOS method, a sense MOS 51 with a predetermined MOS ratio is connected in parallel to the semiconductor switching element 3, and a voltage corresponding to the drain current Id is output by a resistor R51 connected in series to the sense MOS 51. The output voltage Vo in the sense MOS method can be expressed by the following equation (2), where the resistance value of the resistor R51 is Rb. Vo = Rb × drain current Id × MOS ratio (2)

[0081] The parasitic L + integration method utilizes a parasitic inductor L51, such as a wiring between the source of the semiconductor switching element 3 and the DC power supply line L2, and outputs a voltage corresponding to the drain current Id by integrating the parasitic L voltage, which is the voltage between the terminals of the parasitic inductor L51, using an integrator 52. The output voltage Vo using the parasitic L + integration method can be expressed by the following equation (3), where La is the inductance value of the parasitic inductor L51 and di / dt is the gradient of the drain current Id. Vo = ∫ (La × di / dt) dt = La × drain current (3)

[0082] In the above embodiment, the first method is used to determine the short-circuit behavior of the drain current Id, but the second method can also be used. When the second method is used, the method for detecting the drain current Id can be a parasitic L+ timer circuit method as shown in Fig. 14. Note that, in the waveforms shown in the lower part of Fig. 14, the waveform during a short circuit is indicated by a solid line, and the waveform during normal operation is indicated by a dashed dotted line.

[0083] The parasitic L + timer circuit method utilizes a parasitic inductor L51, such as a wiring between the source of the semiconductor switching element 3 and the DC power supply line L2, and inputs the parasitic L voltage, which is the voltage between the terminals of the parasitic inductor L51, to a timer circuit 53, measures the time that the parasitic L voltage is at a high level, and outputs a signal corresponding to the time over which the drain current Id is changing.

[0084] <Modifications of the Limit Command Generator> The limit command generator may be configured to output a limit command when at least one of the voltage at the main terminal of the driven element, the gate voltage of the driven element, and the current flowing through the driven element exhibits short-circuit behavior. As shown in Fig. 4, the gate voltage Vg of the driven element, the drain current Id of the driven element, and the drain voltage Vd of the driven element exhibit different behaviors in the normal state and in the short-circuit state.

[0085] The gate voltage Vg normally increases stepwise to reach the first voltage V1, whereas it linearly increases to reach the first voltage V1 when a short circuit occurs. The drain voltage Vd normally changes from a relatively high voltage value to a relatively low voltage value, whereas it maintains a relatively high voltage value when a short circuit occurs. Therefore, the limit command generation unit can be modified to output a limit command when the gate voltage Vg of the device to be driven exhibits the short circuit behavior described above. The limit command generation unit can also be modified to output a limit command when the drain voltage Vd of the device to be driven exhibits the short circuit behavior described above.

[0086] (Other Embodiments) The present disclosure is not limited to the embodiments described above and illustrated in the drawings, and can be modified, combined, or expanded as desired without departing from the spirit of the present disclosure. The numerical values ​​shown in the above embodiments are merely examples, and the present disclosure is not limited to these.

[0087] The gate-driven semiconductor switching elements 3 and 4 are not limited to MOSFETs and may be, for example, IGBTs. The gate-driven semiconductor switching elements 3 and 4 may also be Si elements using silicon or GaN elements using gallium nitride as the material for forming the elements.

[0088] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0089] In addition to the inventions described in the claims, the present disclosure also includes the following inventions: [1] A gate drive device for driving one of two gate-driven semiconductor switching elements (3, 4) connected in series between a pair of DC power supply lines (L1, L2), comprising: an on drive unit (11) that, when an on drive command commanding on-drive of a drive target element (3) that is the semiconductor switching element to be driven of the two semiconductor switching elements is input, supplies an on drive signal to the gate of the drive target element to turn on the drive target element; an off drive unit (12) that, when an off drive command commanding off-drive of the drive target element is input, supplies an off drive signal to the gate of the drive target element to turn off the drive target element; a drive control unit (18) that generates and outputs the on drive command to the on drive unit and generates and outputs the off drive command to the off drive unit to control on / off of the drive target element; and a limit command generation unit (23, 44) that generates and outputs a limit command commanding a limit on the gate voltage of the drive target element. a gate voltage limiting unit (22, 22A) that, when the limiting command is given during a period in which the ON drive command is input to the ON drive unit, limits the gate voltage of the driven element to a predetermined limiting voltage higher than a mirror voltage by cutting off a supply path of the ON drive signal from the ON drive unit to the gate of the driven element. [2] The gate drive device according to [1], wherein the gate voltage limiting unit releases the cutoff of the ON drive signal supply path when the limiting command is no longer given after cutting off the supply path of the ON drive signal. [3] The gate drive device according to [1] or [2], further comprising a short-circuit determination unit (19) that determines whether a non-driven element (4), which is the semiconductor switching element that is not the driven element and is one of the two semiconductor switching elements, is in a short-circuit state based on a voltage of a main terminal of the driven element, and the drive control unit outputs the OFF drive command to the OFF drive unit when the short-circuit determination unit determines that the non-driven element is in a short-circuit state.[4] The gate drive device according to any one of [1] to [3], wherein the limit command generation unit (23) starts outputting the limit command when the gate voltage of the drive target element reaches the limit voltage and ends outputting the limit command when a predetermined limit time has elapsed since the start of outputting the limit command. [5] The gate drive device according to [1], further comprising: a short-circuit determination unit (19) that determines whether a non-drive target element (4), which is the semiconductor switching element that is not the drive target of one of the two semiconductor switching elements, is in a short-circuit state based on a voltage of a main terminal of the drive target element, wherein the limit command generation unit (44) outputs the limit command when at least one of the voltage of the main terminal of the drive target element, the gate voltage of the drive target element, and the current flowing through the drive target element exhibits a short-circuit behavior that is a behavior of the non-drive target element when it changes from a non-short-circuit state to a short-circuit state, and wherein the drive control unit outputs the off-drive command to the off-drive unit when the short-circuit determination unit determines that the non-drive target element is in a short-circuit state. [6] The gate drive device according to any one of [1] to [5], further comprising a decrease suppression unit (32) that suppresses a decrease in the gate voltage of the element to be driven during a period in which the supply path of the on-drive signal is blocked by the gate voltage limiting unit.

Claims

1. A gate drive device for driving one of two gate-driven semiconductor switching elements (3, 4) connected in series between a pair of DC power supply lines (L1, L2), comprising: an on drive unit (11) that, when an on drive command is input to command on drive of a drive target element (3), which is the semiconductor switching element to be driven among the two semiconductor switching elements, supplies an on drive signal to the gate of the drive target element to turn on the drive target element; an off drive unit (12) that, when an off drive command is input to command off drive of the drive target element, supplies an off drive signal to the gate of the drive target element to turn off the drive target element; a drive control unit (18) that generates the on drive command and outputs it to the on drive unit, and also generates the off drive command and outputs it to the off drive unit, thereby controlling on / off of the drive target element; and a limit command generation unit (23, 44) that generates and outputs a limit command that commands a limit on the gate voltage of the drive target element. a gate voltage limiting unit (22, 22A) that, when the limiting command is given during a period in which the ON drive command is input to the ON drive unit, limits the gate voltage of the element to be driven to a predetermined limiting voltage higher than a mirror voltage by cutting off a supply path of the ON drive signal from the ON drive unit to the gate of the element to be driven.

2. The gate drive device according to claim 1, wherein the gate voltage limiting unit releases the interruption of the supply path of the ON drive signal when the limiting command is no longer given after the supply path of the ON drive signal is interrupted.

3. A gate drive device as described in claim 1 or 2, further comprising a short-circuit determination unit (19) that determines whether or not a non-driven element (4), which is one of the two semiconductor switching elements and is not a driven element, is in a short-circuit state based on the voltage of the main terminal of the driven element, and when the short-circuit determination unit determines that the non-driven element is in a short-circuit state, the drive control unit outputs the off drive command to the off drive unit.

4. A gate drive device as described in claim 1 or 2, wherein the limit command generation unit (23) starts outputting the limit command when the gate voltage of the element to be driven reaches the limit voltage, and ends outputting the limit command when a predetermined limit time has elapsed since the start of outputting the limit command.

5. The gate drive device according to claim 1 further comprises a short-circuit determination unit (19) for determining whether or not a non-driven element (4), which is the semiconductor switching element that is not the driven element of the two semiconductor switching elements, is in a short-circuit state based on the voltage of the main terminal of the driven element, wherein the limit command generation unit (44) outputs the limit command when at least one of the voltage of the main terminal of the driven element, the gate voltage of the driven element, and the current flowing through the driven element exhibits short-circuit behavior, which is the behavior of the non-driven element when it changes from a non-short-circuit state to a short-circuit state, and wherein the drive control unit outputs the off drive command to the off drive unit when the short-circuit determination unit determines that the non-driven element is in a short-circuit state.

6. A gate drive device according to claim 1 or 2, further comprising a drop suppression section (32) that suppresses a drop in the gate voltage of the element to be driven during the period when the supply path of the on-drive signal is blocked by the gate voltage limiting section.

Images