Semiconductor device

Abstract

A semiconductor device according to some embodiments of the present invention comprises: a gate electrode; a channel pattern spaced apart from the gate electrode; a gate dielectric layer between the channel pattern and the gate electrode; a first interfacial film between the gate dielectric layer and the channel pattern; and a second interfacial film in contact with the first interfacial film and the channel pattern, wherein the channel pattern includes an alloy film and an oxide film on the alloy film, the alloy film including a first metal and a second metal, which are different from each other, and the oxide film including a metal oxide that contains the first metal, the first interfacial film includes a material different from that of the gate dielectric layer, and the alloy film includes an upper portion disposed at the same level as the oxide film and a lower portion disposed at a level lower than that of the oxide film.

Description

semiconductor devices

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including an alloy film and an oxide film of a channel pattern.

[0002] Oxide semiconductors generally possess a wider bandgap than silicon-based semiconductors. Therefore, using oxide semiconductors to construct electronic devices allows for transparent circuits with an average visible light transmittance of over 50%. Furthermore, electronic devices can be manufactured at relatively low temperatures, utilizing inexpensive, large-area substrates like glass or plastic.

[0003] Research on n-type oxide semiconductors is actively underway, and n-type oxide semiconductors with excellent properties are known. However, transistors using p-type oxides have limited use due to low mobility and on / off current ratio. Accordingly, various studies are being conducted to fabricate p-type transistors with improved electrical characteristics.

[0004] Embodiments of the present invention aim to provide a semiconductor device with improved electrical characteristics and reliability and a method for manufacturing the same.

[0005] A semiconductor device according to some embodiments includes a gate electrode; a channel pattern spaced apart from the gate electrode; a gate insulating film between the channel pattern and the gate electrode; a first interface film between the gate insulating film and the channel pattern; and a second interface film in contact with the first interface film and the channel pattern, wherein the channel pattern includes an alloy film and an oxide film on the alloy film, the alloy film includes different first and second metals, the oxide film includes a metal oxide including the first metal, the first interface film includes a different material from the gate insulating film, and the alloy film may include an upper portion disposed at the same level as the oxide film and a lower portion disposed at a level lower than the oxide film.

[0006] A semiconductor device according to some embodiments may include a gate electrode; a channel pattern spaced apart from the gate electrode; a gate insulating film between the channel pattern and the gate electrode; and the channel pattern may include an alloy film and an oxide film on the alloy film, wherein the alloy film may include tellurium and selenium, and the oxide film may include tellurium oxide.

[0007] A semiconductor device according to some embodiments includes a gate electrode; a channel pattern spaced apart from the gate electrode; a gate insulating film between the channel pattern and the gate electrode; a first interface film between the gate insulating film and the channel pattern; a source electrode spaced apart from the channel pattern; a drain electrode spaced apart from the channel pattern; and a second interface film between the channel pattern and the source electrode and between the channel pattern and the drain electrode, wherein a sidewall of the source electrode may be coplanar with a first sidewall of the second interface film, and a sidewall of the drain electrode may be coplanar with a second sidewall of the second interface film.

[0008] A semiconductor device according to embodiments of the present invention can form an oxide film including an oxide on an alloy film of a channel pattern, thereby reducing the phenomenon of vaporization and evaporation of a material of the alloy film during the crystallization process of the alloy film.

[0009] A semiconductor device according to embodiments of the present invention can reduce the Fermi-level pinning phenomenon that may occur between a channel and a source electrode or between a channel and a drain electrode by including an interface film.

[0010] FIG. 1A is a cross-sectional view of a semiconductor device according to some embodiments.

[0011] Figure 1b is an enlarged view of area A of Figure 1a.

[0012] FIGS. 2a, 2b, 2c, 2d, 2e, 2f and 2g are drawings for explaining a method of manufacturing a semiconductor device according to some embodiments.

[0013] Figure 3 is a table showing the electrical characteristics of semiconductor devices according to Table Examples 1 to 6 and Comparative Examples 1 to 3.

[0014] Figure 4a is a graph showing the output characteristics of semiconductor devices according to Comparative Example 1 and Examples 1 to 3.

[0015] FIG. 4b is a graph showing the XRD pattern of the channel pattern of each of the semiconductor devices according to Comparative Example 2, Comparative Example 3, Example 4, Example 5, and Example 6.

[0016] FIGS. 5a, 5b, 5c, 5d, and 5e are drawings showing SEM images of channel patterns of each of the semiconductor devices according to Comparative Example 2, Comparative Example 3, Example 4, Example 5, and Example 6.

[0017] FIGS. 6a, 6b, 6c, and 6d are XPS graphs of channel patterns of each of the semiconductor devices according to Comparative Example 2, Comparative Example 3, Example 4, Example 5, and Example 6.

[0018] Figure 7 is a graph showing the optical band gap of the channel pattern of a semiconductor device according to Example 6 before and after heat treatment.

[0019] FIG. 8 is a drawing showing an HRTEM image of a channel pattern of a semiconductor device according to Example 6.

[0020] FIG. 9a is a drawing showing the EDS mapping results of the channel pattern of a semiconductor device according to Example 6.

[0021] Figure 9b is a graph showing the EDS spectrum and element ratio obtained in area A of Figure 9a.

[0022] Figure 10a is a graph showing the output characteristics of semiconductor devices according to Comparative Example 2, Example 4, Example 5, and Example 6.

[0023] Figure 10b is a graph showing the transfer characteristics of semiconductor devices according to Example 6.

[0024] A drawing showing the best mode for carrying out the present invention is Fig. 1a.

[0025] Hereinafter, semiconductor devices according to embodiments of the present invention will be described in detail with reference to the drawings.

[0026]

[0027] FIG. 1A is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 1B is an enlarged view of region A of FIG. 1A.

[0028] Referring to FIGS. 1A and 1B, a semiconductor device may include a substrate (100). In some embodiments, the substrate (100) may be a semiconductor, glass, or polymer substrate. For example, the semiconductor substrate may include silicon, germanium, silicon-germanium, GaP, or GaAs. The substrate (100) may have a plate shape extending along a plane extending in a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be horizontal directions that are orthogonal to each other.

[0029] A gate electrode (110) may be provided on a substrate (100). The gate electrode (110) may be in contact with the upper surface of the substrate (100). The gate electrode (110) may include a conductive material.

[0030] A gate insulating film (111) may be provided on the gate electrode (110). The gate insulating film (111) may cover the gate electrode (110). The gate insulating film (111) may be in contact with the upper surface of the substrate (100). The gate electrode (110) may be disposed between the substrate (100) and the gate insulating film (111). The gate insulating film (111) may include an insulating material. For example, the gate insulating film (111) may include an oxide or a nitride.

[0031] A first interface film (121) may be provided on the gate insulating film (111). The thickness of the first interface film (121) in the third direction (D3) may be smaller than the thickness of the gate insulating film (111) in the third direction (D3). The third direction (D3) may intersect the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be a vertical direction orthogonal to the first direction (D1) and the second direction (D2). In some embodiments, the thickness of the first interface film (121) in the third direction (D3) may be 1 nm or more and 100 nm or less.

[0032] A channel pattern (CP) may be provided on the first interface film (121). The channel pattern (CP) may be spaced apart from the gate electrode (110). A gate insulating film (111) may be disposed between the gate electrode (110) and the channel pattern (CP). The first interface film (121) may be disposed between the gate insulating film (111) and the channel pattern (CP). The channel pattern (CP) may overlap the gate electrode (110) in a third direction (D3).

[0033] The channel pattern (CP) may include an oxide film (OL) and an alloy film (AL). The oxide film (OL) may be provided on the alloy film (AL).

[0034] The oxide film (OL) can be in contact with the upper surface of the alloy film (AL). The oxide film (OL) can be arranged at a higher level than the alloy film (AL).

[0035] The alloy film (AL) may include an upper portion (AL_U) disposed at the same level as the oxide film (OL) and a lower portion (AL_L) disposed at a lower level than the oxide film (OL).

[0036] The alloy film (AL) may include an outer wall (AL_OS) in contact with the second interface film (122) and an inner wall (AL_IS) in contact with the oxide film (OL). The inner wall (AL_IS) of the alloy film (AL) may be a side wall of the upper portion (AL_U) of the alloy film (AL).

[0037] The outer wall (AL_OS) of the alloy film (AL) may be spaced apart from the oxide film (OL) in the first direction. The upper portion (AL_U) of the alloy film (AL) may surround the oxide film (OL). The lower portion (AL_L) of the alloy film (AL) may be in contact with the lower surface of the oxide film (OL).

[0038] The upper surface of the alloy film (AL) may include a first portion (AL_T1) in contact with the second interfacial film (122) and a second portion (AL_T2) in contact with the oxide film (OL). The first portion (AL_T1) of the upper surface of the alloy film (AL) may be arranged at a higher level than the second portion (AL_T2) of the upper surface of the alloy film (AL). The first portion (AL_T1) and the second portion (AL_T2) of the upper surface of the alloy film (AL) may be spaced apart from each other in a third direction (D3).

[0039] The width (L1) of the upper surface (OL_T) of the oxide film (OL) in the first direction (D1) may be smaller than the width (L2) of the upper surface of the alloy film (AL) in the first direction (D1).

[0040] The thickness of the channel pattern (CP) in the third direction (D3) may be 4 nm or more and 100 nm or less.

[0041] The alloy film (AL) may include different first and second metals. For example, the alloy film (AL) may include tellurium (Te) and selenium (Se). The alloy film (AL) may include alloy crystals of the first and second metals. The concentration of selenium in the alloy film (AL) may be greater than 32 at.% and less than 100 at.%. The concentration of tellurium in the alloy film (AL) may be greater than or equal to 0.1 at.% and less than 68 at.%. In some embodiments, the alloy film (AL) may include oxygen. The concentration of oxygen in the alloy film (AL) may be greater than or equal to 0.1 at.% and less than 1 at.%.

[0042] The oxide film (OL) may include a metal oxide. The oxide film (OL) may include a metal oxide including a first metal. For example, the oxide film (OL) may include tellurium oxide.

[0043] The first interface film (121) may include a material different from the gate insulating film (111). For example, the first interface film (121) may include hBN, TiO2, Al2O3, HfO2, ZrO2, SAM, CYTOP, PVP, PMMA, PS, or PI.

[0044] A second interface film (122) may be provided on the first interface film (121). The second interface film (122) may include a first portion (122_1) and a second portion (122_2) spaced apart in the first direction (D1).

[0045] The second interfacial film (122) may include a first side wall (122_S1) and a second side wall (122_S2). The first side wall (122_S1) of the second interfacial film (122) may be a side wall of the first portion (122_1) of the second interfacial film (122). The second side wall (122_S2) of the second interfacial film (122) may be a side wall of the second portion (122_2) of the second interfacial film (122).

[0046] The second interfacial film (122) can be in contact with the upper surface of the first interfacial film (121). A first portion (122_1) of the second interfacial film (122) can be in contact with the side wall (AL_S) of the alloy film (AL) and the side wall (OL_S) of the oxide film (OL). A second portion (122_2) of the second interfacial film (122) can be in contact with the side wall (AL_S) of the alloy film (AL) and the side wall (OL_S) of the oxide film (OL). The second interfacial film (122) can be in contact with the upper surface (OL_T) of the oxide film (OL). The second interfacial film (122) can cover a portion of the upper surface (OL_T) of the oxide film (OL). The channel pattern (CP) may be placed between the first portion (122_1) and the second portion (122_2) of the second interface film (122).

[0047] The thickness of the second interface film (122) in the third direction (D3) may be smaller than the thickness of the channel pattern (CP) in the third direction (D3). The thickness of the second interface film (122) in the third direction (D3) may be 1 nm or more and 10 nm or less.

[0048] The second interfacial film (122) may include a different material than the source electrode (131). The second interfacial film (122) may include a different material than the drain electrode (132). For example, the second interfacial film (122) may include tellurium (Te), graphene, hBN, TiO2, Al2O3, HfO2, or ZrO2. In some embodiments, the first interfacial film (121) and the second interfacial film (122) may include the same material.

[0049] A source electrode (131) may be provided on a first portion (122_1) of the second interface film (122). A drain electrode (132) may be provided on a second portion (122_2) of the second interface film (122). The source electrode (131) and the drain electrode (132) may be spaced apart from each other. The source electrode (131) and the channel pattern (CP) may be spaced apart from each other. The drain electrode (132) and the channel pattern (CP) may be spaced apart from each other. The second interface film (122) may be disposed between the source electrode (131) and the channel pattern (CP). The first portion (122_1) of the second interface film (122) may be disposed between the source electrode (131) and the channel pattern (CP). The second interface film (122) may be disposed between the drain electrode (132) and the channel pattern (CP). A second portion (122_2) of the second interface film (122) may be placed between the drain electrode (132) and the channel pattern (CP).

[0050] The side wall (131_S) of the source electrode (131) and the first side wall (122_S1) of the second interface film (122) may form a coplanar surface. The side wall (131_S) of the source electrode (131) and the first side wall (122_S1) of the second interface film (122) may be inclined with respect to the upper surface of the first interface film (121).

[0051] The side wall (132_S) of the drain electrode (132) and the second side wall (122_S2) of the second interface film (122) may be coplanar. The side wall (132_S) of the drain electrode (132) and the second side wall (122_S2) of the second interface film (122) may be inclined with respect to the upper surface of the first interface film (121).

[0052] A passivation film (140) may be provided in contact with the source electrode (131), the drain electrode (132), the first sidewall (122_S1) of the second interface film (122), the second sidewall (122_S2) of the second interface film (122), and the upper surface (OL_T) of the oxide film (OL). The passivation film (140) may cover the upper surface and the sidewall (131_S) of the source electrode (131) and the upper surface and the sidewall (132_S) of the drain electrode (132). The passivation film (140) may include an insulating material. For example, the passivation film (140) may include an oxide or a nitride.

[0053] The first portion (122_1) of the second interface film (122) may include an upper portion (122_1U), a middle portion (122_1M), and a lower portion (122_1L). The first side wall (122_S1) of the second interface film (122) may be a side wall of the upper portion (122_1U) of the first portion (122_1) of the second interface film (122).

[0054] The middle portion (122_1M) of the first portion (122_1) of the second interfacial film (122) may be disposed at a higher level than the lower portion (122_1L). The upper portion (122_1U) of the first portion (122_1) of the second interfacial film (122) may be disposed at a higher level than the middle portion (122_1M). The lower portion (122_1L) and the middle portion (122_1M) of the first portion (122_1) of the second interfacial film (122) may be disposed at a higher level than the lower surface (OL_T) of the alloy film (AL). The lower portion (122_1L) and the middle portion (122_1M) of the first portion (122_1) of the second interfacial film (122) may be disposed at a lower level than the upper surface (OL_T) of the oxide film (OL). The upper portion (122_1U) of the first portion (122_1) of the second interface film (122) may be placed at a higher level than the channel pattern (CP).

[0055] The lower portion (122_1L) and the middle portion (122_1M) of the first portion (122_1) of the second interfacial film (122) can be in contact with the sidewall of the channel pattern (CP). The lower portion (122_1L) of the first portion (122_1) of the second interfacial film (122) can be in contact with the sidewall of the alloy film (AL). The middle portion (122_1M) of the first portion (122_1) of the second interfacial film (122) can be in contact with the sidewalls of the alloy film (AL) and the oxide film (OL).

[0056] The upper portion (122_1U) of the first portion (122_1) of the second interface film (122) may be in contact with the upper surface (OL_T) of the oxide film (OL). The upper portion (122_1U) of the first portion (122_1) of the second interface film (122) may cover a portion of the oxide film (OL).

[0057] The source electrode (131) may include a first portion (131_1) and a second portion (131_2) on the first portion (131_1). The side wall (131_S) of the source electrode (131) may be a side wall of the second portion (131_2) of the source electrode (131).

[0058] The first part (131_1) of the source electrode (131) may be placed at the same level as the channel pattern (CP). The first part (131_1) of the source electrode (131) may be placed at a level higher than the lower surface of the alloy film (AL).

[0059] The second portion (131_2) of the source electrode (131) may be positioned at a level higher than the channel pattern (CP). The second portion (131_2) of the source electrode (131) may be positioned at a level higher than the upper surface (OL_T) of the oxide film (OL).

[0060] The structure of the second portion (122_2) of the second interface film (122) may be similar to the structure of the first portion (122_1) of the second interface film (122). The structure of the drain electrode (132) may be similar to the structure of the source electrode (131).

[0061] In some embodiments, the semiconductor device may include a bottom gate / top contact structure. In some embodiments, the semiconductor device may include a bottom gate / bottom contact, an top gate / top contact, or an top gate / bottom contact structure.

[0062] According to some embodiments, a semiconductor device can improve electrical characteristics by disposing an oxide film (OL) on an alloy film (AL), so that the oxide film (OL) prevents vaporization and evaporation of the alloy film (AL) during the crystallization process of the alloy film (AL).

[0063] A semiconductor device according to some embodiments may include a first interfacial film (121) to change surface energy. Accordingly, the crystallinity of the alloy film (AL) may be changed, or the adhesion between the first interfacial film (121) and the alloy film (AL) may be improved. In addition, as the surface energy is changed, the adhesion between the first interfacial film (121) and the source electrode (131) and the adhesion between the first interfacial film (121) and the drain electrode (132) may be improved.

[0064] A semiconductor device according to some embodiments can include a second interfacial film (122) to relatively reduce the Fermi-level pinning phenomenon that may occur between an alloy film (AL) and a source electrode (131).

[0065] A semiconductor device according to some embodiments may include a second interfacial film (122) to relatively reduce a Fermi-level pinning phenomenon that may occur between an alloy film (AL) and a drain electrode (132).

[0066] In some embodiments, a semiconductor device includes a channel pattern (CP) including an alloy of tellurium and selenium, so that even if the channel pattern (CP) has a relatively large thickness, the band gap can be relatively large, and thus the on / off current ratio can be relatively large.

[0067]

[0068] FIGS. 2a, 2b, 2c, 2d, 2e, 2f and 2g are drawings for explaining a method of manufacturing a semiconductor device according to some embodiments.

[0069] Referring to FIG. 2a, a substrate (100) may be provided. A gate electrode (110) may be formed on the substrate (100). A gate insulating film (111) covering the gate electrode (110) may be formed.

[0070] Referring to FIG. 2b, a first interface film (121) can be formed on the gate insulating film (111).

[0071] Referring to FIG. 2c, a preliminary channel pattern (CPa) can be formed on the first interface film (121). Forming the preliminary channel pattern (CPa) may include forming a mask pattern including an opening, depositing the preliminary channel pattern (CPa) within the opening of the mask pattern, and removing the mask pattern.

[0072] Depositing the preliminary channel pattern (CPa) may include, for example, sputtering, chemical vapor deposition, or atomic layer deposition. The preliminary channel pattern (CPa) may include an amorphous material. The preliminary channel pattern (CPa) may include a first metal and a second metal. For example, the preliminary channel pattern (CPa) may include tellurium (Te) and selenium (Se).

[0073] Referring to FIG. 2d, a second interface film (122) covering the first interface film (121) and the preliminary channel pattern (CPa) can be formed.

[0074] Referring to FIG. 2e, a conductive film (130) covering the second interface film (122) can be formed.

[0075] Referring to FIG. 2f, a through hole (H1) penetrating the second interface film (122) and the conductive film (130) can be formed. In some embodiments, the through hole (H1) may be in the form of a trench extending in the second direction (D2).

[0076] The second interface film (122) can be separated into a first portion (122_1) and a second portion (122_2) by a through hole (H1). In some embodiments, the first portion (122_1) and the second portion (122_2) of the second interface film (122) can be connected on the first interface film (121).

[0077] The conductive film (130) can be separated into a source electrode (131) and a drain electrode (132) by a through hole (H1).

[0078] The upper surface of the preliminary channel pattern (CPa), the side wall of the second interface film (122), the side wall of the source electrode (131), and the side wall of the drain electrode (132) can be exposed through the through hole (H1).

[0079] Referring to Fig. 2g, a preliminary channel pattern (CPa) may be heat-treated to form an alloy film (AL) and an oxide film (OL) on the alloy film (AL). The heat-treated preliminary channel pattern (CPa) may be defined as a channel pattern (CP). An alloy crystal including a first metal and a second metal may be formed by the heat treatment, and an alloy film (AL) may be formed.

[0080] The heat treatment may be performed, for example, in an air atmosphere, an oxygen atmosphere, or a nitrogen atmosphere. In some embodiments, the temperature of the heat treatment may be 100° C. or higher and 400° C. or lower. Referring to FIG. 1A, a passivation film (140) may be formed on the source electrode (131), the drain electrode (132), and the oxide film (OL). In some embodiments, the heat treatment may be performed after forming the passivation film (140), and the oxide film (OL) may not be formed on the alloy film (AL).

[0081] A method for manufacturing a semiconductor device according to some embodiments may perform heat treatment on a preliminary channel pattern (CPa) to form metals included in the channel pattern (CP) into an alloy crystal structure.

[0082] A method for manufacturing a semiconductor device according to some embodiments performs heat treatment on a preliminary channel pattern (CPa) before forming a through hole (H1) or after forming a passivation film (140), thereby forming metals included in the channel pattern (CP) into an alloy crystal structure without forming an oxide film (OL).

[0083] A method for manufacturing a semiconductor device according to some embodiments can reduce the phenomenon of vaporization or evaporation of metals included in the preliminary channel pattern (CPa) when performing heat treatment on the preliminary channel pattern (CPa) by forming a passivation film (140) on the preliminary channel pattern (CPa).

[0084]

[0085] Below, the results of evaluating the electrical and chemical characteristics of semiconductor devices are described with reference to experimental examples.

[0086]

[0087] [Manufacture of Examples and Comparative Examples]

[0088] [Example 1]

[0089] A 100 nm thick gate insulator (SiO2) was grown on a doped n-type Si substrate by thermal oxidation. A mask pattern was formed on the gate insulator. While injecting argon gas, a pulsed KrF laser (248 nm) was irradiated at 5 Hz on a sintered target with a ratio of Se and Te atoms of 0.25:0.75. Se and Te atoms emitted from the target were deposited to form a 20 nm thick Se0.25Te0.75 channel pattern. A second shadow mask was placed on the Se0.25Te0.75, and a nickel pattern was formed by electron beam deposition to form source and drain electrodes on both sides of the Se0.25Te0.75 pattern. After forming the source and drain electrodes, the Se0.25Te0.75 was heat-treated at 250°C for 2 hours in an oxygen atmosphere.

[0090] [Example 2]

[0091] Example 2 was prepared similarly to Example 1, but with the Se and Te atomic ratio set to 0.5:0.5.

[0092] [Example 3]

[0093] Example 3 was prepared similarly to Example 1, but with the Se and Te atomic ratio set to 0.75:0.25.

[0094] [Example 4]

[0095] Example 4 was manufactured similarly to Example 2, but with a channel pattern thickness of 60 nm and a heat treatment temperature of 150°C.

[0096] [Example 5]

[0097] Example 5 was prepared similarly to Example 4, but with the heat treatment temperature set to 200°C.

[0098] [Example 6]

[0099] Example 6 was prepared similarly to Example 4, but with the heat treatment temperature set to 250°C.

[0100] [Comparative Example 1]

[0101] Comparative Example 1 was prepared similarly to Example 1, but with the atomic ratio of Se and Te set to 0:1.

[0102] [Comparative Example 2]

[0103] Comparative Example 2 was prepared similarly to Example 4, but without performing heat treatment.

[0104] [Comparative Example 3]

[0105] Comparative Example 3 was prepared similarly to Example 4, but with a heat treatment temperature of 300°C.

[0106]

[0107] Figure 3 is a table showing the electrical characteristics of semiconductor devices according to Examples 1 to 6 and Comparative Examples 1 to 3. Comparative Example 2 did not undergo heat treatment. It was confirmed that Comparative Example 3 did not have TFT characteristics.

[0108]

[0109] Figure 4a is a graph showing the electrical characteristics of semiconductor devices. The x-axis represents the potential difference between the gate electrode and the source electrode, and the y-axis represents the amount of current flowing in the channel.

[0110] Referring to FIGS. 3 and 4a, the semiconductor devices according to Examples 1 to 3 and Comparative Example 1 exhibited the characteristics of a p-type TFT, and it was confirmed that the characteristics of mobility and on / off current ratio changed depending on the atomic ratio of Te and Se.

[0111]

[0112] Figure 4b is a graph showing an XRD (X-ray diffraction) pattern of a channel pattern of semiconductor devices. The x-axis represents the diffraction angle of the X-ray, and the y-axis represents the intensity of the received X-ray.

[0113] Referring to Fig. 4b, it was confirmed that the channel pattern including Te and Se was in an amorphous state during the deposition step and crystallized into a polycrystalline state after heat treatment at 150°C, 200°C, and 250°C. It was confirmed that a phase change to Te or TeO2 oxide occurred after heat treatment at 300°C.

[0114]

[0115] Figures 5a, 5b, 5c, 5d and 5e are drawings showing SEM (Scanning electron microscope) images of a channel pattern of a semiconductor device.

[0116] Referring to FIGS. 3, 5a, 5b, 5c, 5d, and 5e, it was confirmed that the Se0.5Te0.5 channel pattern was in an amorphous state during the deposition step, and that the crystal size increased as it crystallized into a polycrystalline state after heat treatment at 150°C, 200°C, and 250°C.

[0117]

[0118] Figures 6a, 6b, 6c and 6d are XPS (X-ray photoelectron spectroscopy) graphs of the channel pattern of the semiconductor device.

[0119] Figures 6a and 6b are XPS graphs measuring the top surface of the Se0.5Te0.5 channel pattern. Figures 6c and 6d are XPS graphs measuring the top surface of the Se0.5Te0.5 channel pattern after etching 10 nm from the top surface.

[0120] Referring to FIG. 3, FIG. 6a, 6b, 6c and 6d, as the heat treatment temperature increases, metallic Te (Te) is formed on the upper surface of the Se0.5Te0.5 channel pattern. 0 ) ratio decreases, and Te 4+It was confirmed that the ratio of Se3d increases. It was confirmed that as the heat treatment temperature increases, the ratio of Se3d also decreases. When heat treated at 300℃, most of Te 0 Go Te 4+ It was confirmed that Se3d was changed to , and disappeared.

[0121]

[0122] Figure 7 is a Tauc plot graph showing the optical band gap before and after heat treatment of the channel pattern of a semiconductor device.

[0123] Referring to Fig. 7, it was confirmed that the band gap of the Se0.5Te0.5 channel pattern before heat treatment was 1.30 eV, and the band gap of the channel pattern after heat treatment was 1.13 eV.

[0124]

[0125] Figure 8 is a drawing showing a high-resolution transmission electron microscopy (HRTEM) image of a channel pattern of a semiconductor device.

[0126] Referring to Fig. 8, it was confirmed that the (100) plane of the Se0.5Te0.5 channel pattern was crystallized so that it was parallel to the upper surface of the substrate.

[0127]

[0128] Fig. 9a is a diagram showing the results of EDS (Energy-dispersive X-ray spectroscopy) mapping of the Se0.5Te0.5 channel pattern of a semiconductor device. Fig. 9b is a graph showing the EDS spectrum and element ratio obtained in area A of Fig. 9a.

[0129] Referring to Figures 9a and 9b, it was confirmed that the element ratio of Se and Te inside the alloy film was approximately 50:50, and that almost no selenium existed on the upper surface of the alloy film.

[0130]

[0131] Figure 10a is a graph showing the output characteristics of semiconductor devices.

[0132] The x-axis of Fig. 10a represents the potential difference between the gate electrode and the source electrode, and the y-axis represents the amount of current flowing in the channel.

[0133] Referring to Fig. 10a, it was confirmed that the semiconductor devices according to Examples 4 to 6 and Comparative Example 2 all exhibited the characteristics of a p-type transistor. In addition, it was confirmed that as the heat treatment temperature increased, the on / off current ratio significantly increased.

[0134]

[0135] Figure 10b is a graph showing the transfer characteristics of semiconductor devices according to Example 6.

[0136] It was confirmed that the electrical characteristics, such as the on / off current ratio and mobility, of the semiconductor device according to some embodiments can be improved by controlling the composition ratio of Te and Se and controlling the temperature at which the channel pattern is heat-treated.

[0137]

[0138] While the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical concept or essential features thereof. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0139] The present invention relates to a semiconductor device. More specifically, it can be used in a semiconductor device including an alloy film and an oxide film of a channel pattern.

Claims

gate electrode; A channel pattern spaced apart from the gate electrode; A gate insulating film between the channel pattern and the gate electrode; a first interface film between the gate insulating film and the channel pattern; and Including the first interface film and the second interface film in contact with the channel pattern, The above channel pattern includes an alloy film and an oxide film on the alloy film, The above alloy film comprises different first and second metals, The above oxide film comprises a metal oxide including a first metal, The first interface film comprises a material different from the gate insulating film, A semiconductor device wherein the alloy film includes an upper portion disposed at the same level as the oxide film and a lower portion disposed at a lower level than the oxide film. In the first paragraph, The first metal comprises tellurium, The second metal comprises selenium, A semiconductor device wherein the concentration of the second metal in the alloy film is greater than 32 at.% and less than 100 at.%. In the first paragraph, A semiconductor device in which the alloy film includes an inner wall in contact with the oxide film and an outer wall spaced apart from the oxide film. In the third paragraph, Further comprising a source electrode and a drain electrode disposed on the second interface film and including a material different from the second interface film, The first interface film and the second interface film are disposed between the source electrode and the gate insulating film, A semiconductor device in which the first interface film and the second interface film are disposed between the drain electrode and the gate insulating film. In paragraph 4, The second interface film includes a first portion in contact with the source electrode and a second portion in contact with the drain electrode, The side wall of the first part and the side wall of the source electrode form a coplanar surface, A semiconductor device in which the side wall of the second portion and the side wall of the drain electrode form a common plane. In paragraph 5, are arranged on the source electrode, the drain electrode and the channel pattern, A semiconductor device further comprising a passivation film in contact with the sidewall of the first portion of the second interface film, the sidewall of the second portion of the second interface film, the sidewall of the source electrode, and the sidewall of the drain electrode. In the first paragraph, The upper portion of the alloy film is in contact with the side wall of the oxide film, A semiconductor device in which the lower portion of the alloy film is in contact with the lower surface of the oxide film. gate electrode; A channel pattern spaced apart from the gate electrode; a gate insulating film between the channel pattern and the gate electrode; and The above channel pattern includes an alloy film and an oxide film on the alloy film, The above alloy film contains tellurium and selenium, The above oxide film is a semiconductor device including tellurium oxide. In paragraph 8, A semiconductor device wherein the concentration of selenium in the alloy film is greater than 32 at.% and less than 100 at.%. In paragraph 8, Further comprising a first interface film between the gate insulating film and the channel pattern and a second interface film on the first interface film, A semiconductor device wherein the thickness of the above channel pattern is 4 nm or more and 100 nm or less. In paragraph 10, A semiconductor device wherein the thickness of the second interface film is greater than 0 nm and less than or equal to 10 nm. In paragraph 10, A semiconductor device in which the second interface film is in contact with the upper surface of the oxide film. In paragraph 10, The above second interfacial film is: A lower portion in contact with the upper surface of the first interfacial film; a middle portion in contact with the side wall of the above channel pattern; and Including the upper part that contacts the upper surface of the above channel pattern, A semiconductor device wherein the upper portion of the second interface film is spaced apart from the first interface film. In paragraph 13, Further comprising a source electrode and a drain electrode on the second interface film, The second interface film is disposed between the source electrode and the channel pattern, A semiconductor device in which the second interface film is disposed between the drain electrode and the channel pattern. In paragraph 8, The above alloy film contains oxygen, A semiconductor device wherein the concentration of oxygen in the alloy film is 0.01 at.% or more and less than 1 at.%. gate electrode; A channel pattern spaced apart from the gate electrode; A gate insulating film between the channel pattern and the gate electrode; A first interface film between the gate insulating film and the channel pattern; A source electrode spaced apart from the above channel pattern; A drain electrode spaced apart from the above channel pattern; A second interface film is included between the channel pattern and the source electrode and between the channel pattern and the drain electrode, The side wall of the above source electrode is coplanar with the first side wall of the second interface film, A semiconductor device in which the side wall of the above drain electrode forms a coplanar surface with the second side wall of the above second interface film. In paragraph 16, A semiconductor device in which the second interface film is in contact with the upper surface of the channel pattern. In paragraph 17, Further comprising a passivation film on the second interface film and the channel pattern, A semiconductor device in which the above passivation film is in contact with the upper surface of the above channel pattern. In paragraph 18, A semiconductor device in which the passivation film is in contact with the sidewall of the source electrode, the sidewall of the drain electrode, the first sidewall of the second interface film, and the second sidewall of the second interface pattern. In paragraph 16, The above channel pattern comprises an alloy of tellurium and selenium, A semiconductor device wherein the concentration of the cellulosic material within the channel pattern is greater than 32 at.% and less than 100 at.%.

Images