Light emitting diode arrays of different wavelength emitters with overgrown p-type layer and associated methods of manufacture

Abstract

In a general aspect, a microLED display includes a doped semiconductor member having a red microLED disposed on the doped semiconductor member. The red microLED has a top surface opposite the doped semiconductor member. The display also includes a green microLED disposed on the doped semiconductor member. The green microLED having a top surface opposite the doped semiconductor member. The display also includes a blue microLED formed on the doped semiconductor member and having a third top surface opposite the doped semiconductor member. The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are substantially coplanar.

Description

Aty Docket No.: 0120-952BW01LIGHT EMITTING DIODE ARRAYS OF DIFFERENT WAVELENGTH EMITTERS WITH OVERGROWN P-TYPE LAYER AND ASSOCIATED METHODS OF MANUFACTUREBACKGROUND

[0001] Some electronic device applications, such as augmented reality devices, include RGB micro-displays with a fine pixel pitch, e.g. pixel to pixel distance. However, forming a such RGB displays is challenging. For instance achieving displays with desired pixel pitch, image quality, and operating efficiency may not be possible using prior approaches. For instance, display produced using nanowire epitaxy may suffer from, at least, low operating efficiency, and difficulties in forming practical devices, e.g., with pixel to pixel pitch.SUMMARY

[0002] In a general aspect, a microLED display includes a doped semiconductor member having a red microLED disposed on the doped semiconductor member. The red microLED has a top surface opposite the doped semiconductor member. The display also includes a green microLED disposed on the doped semiconductor member. The green microLED having a top surface opposite the doped semiconductor member. The display also includes a blue microLED formed on the doped semiconductor member and having a third top surface opposite the doped semiconductor member. The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are substantially coplanar.

[0003] In another general aspect, a method includes growing, on a substrate: a red microLED having a top surface opposite the substrate, a green microLED having a top surface opposite the substrate, and a blue microLED having a third top surface opposite the substrate. The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are substantially coplanar.

[0004] In another general aspect, a display includes a substrate, and a first LED mesa including a first active region configured to emit light of a first wavelength. The first LED mesa is disposed on a first lateral region of the substrate. The display also includes a second LED mesa including a second active region configured to emit light of a second wavelengthAty Docket No.: 0120-952BW01 different than the first wavelength. The second LED mesa is disposed on a second lateral region of the substrate distinct from the first lateral region. The display further includes a first p-doped region contacting a sidewall of the first LED mesa, and a second p-doped region contacting a sidewall of the second LED mesa. The first p-doped region and the second p- doped region have respective top surfaces opposite the substrate that are substantially coplanar.

[0005] In another general aspect, a device includes a substrate; and a first semiconductor stack disposed on the substrate and having a first active region. The first semiconductor stack has a first lateral boundary that is non-parallel with the substrate. The device further includes a second semiconductor stack disposed on a portion of the first semiconductor stack and having a second active region. A first p-doped semiconductor material contacts the first lateral boundary and is configured to laterally inject holes into the first active region.

[0006] In another general aspect, a method of forming a display includes growing, on a planar surface of a substrate, a first semiconductor stack having a first active region. The method further includes growing, on the first semiconductor stack, a second semiconductor stack having a second active region. The method also includes forming, in the first semiconductor stack, a first lateral boundary that is non-parallel with the planar surface. The method still further includes growing a first p-doped semiconductor material contacting the first lateral boundary.

[0007] In another general aspect, a method of forming a device includes, in a single growth operation, successively growing, on a substrate, a first semiconductor stack having a first active region, a second semiconductor stack having a second active region, and a third semiconductor stack having a third active region. The method further includes etching the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack to respectively define a first etched sidewall, a second etched sidewall, and a third etched sidewall. The method also includes regrowing a p-doped material that contacts the first etched sidewall, the second etched sidewall, and the third etched sidewall. The method further includes etching the p-doped material to define a first p-doped region, a second p- doped region, and a third p-doped region that, respectively, contact the first etched sidewall, the second etched sidewall, and the third etched sidewall.Aty Docket No.: 0120-952BW01BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIGs. 1 A to ID are diagrams schematically illustrating an example light emitting diode (LED) regions.

[0009] FIGs. 2A to 2E are diagrams schematically illustrating an example process for forming a regrown conductive layer on an array of LED regions.

[0010] FIGs. 3 A to 3D are diagrams schematically illustrating example implementations of a plurality of monolithically formed LED regions.

[0011] FIGs. 4A to 4C are diagrams schematically illustrating a process of forming a display including a plurality of monolithically formed LED regions.

[0012] FIG. 5 illustrates an example of a quantum well-based LED structure.

[0013] FIG. 6 illustrates an example of a quantum well-based LED structure enhanced with sidewall hole injection of the quantum well layers, in accordance with aspects of this disclosure.

[0014] FIG. 7 illustrates an example of a quantum well-based LED structure enhanced with sidewall hole injection of the quantum well layers, in accordance with aspects of this disclosure.

[0015] FIG. 8 illustrates an example of a quantum well-based LED structure enhanced with sidewall hole injection of the quantum well layers, in accordance with aspects of this disclosure.

[0016] FIG. 9 illustrates an example of a quantum well-based LED structure enhanced with sidewall hole injection of the quantum well layers, in accordance with aspects of this disclosure.

[0017] FIG. 10 illustrates an example of multiple quantum well-based LED structure enhanced with sidewall hole injection of the quantum well layers and supported on a single semiconductor template, in accordance with aspects of this disclosure.

[0018] FIG. 11 illustrates a top view of multiple LED structures as part of an array, in accordance with aspects of this disclosure.

[0019] FIG. 12 illustrates an example of a quantum well-based LED structure enhanced with vertically stacked multi quantum well structures, in accordance with aspects of this disclosure.

[0020] FIG. 13 illustrates an example of a quantum well-based LED structure enhanced with vertically stacked multi-quantum well structures after additional processing, in accordance with aspects of this disclosure.Aty Docket No.: 0120-952BW01

[0021] FIG. 14 illustrates an example of a quantum well-based LED structure enhanced with vertically stacked multi quantum well structures after additional processing, in accordance with aspects of this disclosure.

[0022] FIG. 15 illustrates an example of a quantum well-based LED structure enhanced with vertically stacked multi quantum well structures after additional processing, in accordance with aspects of this disclosure.

[0023] FIG. 16 illustrates an example of a quantum well-based LED structure enhanced with vertically stacked multi quantum well structures after additional processing, in accordance with aspects of this disclosure.

[0024] FIGs. 17A to 17G illustrate a fabrication flow for producing a stack LED structure, in accordance with aspect of this disclosure.

[0025] FIG. 18 is a cross-sectional diagram illustrating operation of an example stacked LED device, such as the stacked device of FIGs. 17A-17G.

[0026] FIG. 19 is a cross-sectional diagram of an example stacked display including several stacked pixels 1810, such as a plurality of the stacked devices of FIGs. 17A-17G.

[0027] FIGs. 20A to 20J illustrate examples of specifically tailored dopant profiles within the n-type layers, in accordance with aspects of this disclosure.

[0028] In the drawings, which are not necessarily drawn to scale, like reference symbols may indicate like and / or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same, and / or similar elements in the same view, or in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated in a given view.DETAILED DESCRIPTION

[0029] This disclosure is directed to semiconductor devices including arrays of light emitting diodes (LEDs) with different emission wavelengths (e.g., red, green and blue light), and methods for making such semiconductor devices. Briefly, in some implementations, a semiconductor device can include an epitaxial substrate having, formed thereon, a first plurality of LED regions (LED regions) that emit light with a spectrum characterized by a first wavelength. For instance, light emitted by the first plurality of LED regions can have aAty Docket No.: 0120-952BW01 spectrum (distribution) of wavelengths that are centered around a target wavelength for a desired emission color, e.g., red, green or blue. In this example, the semiconductor device can also have, formed thereon, a second plurality of LED regions that emit light with a spectrum characterized by a second wavelength different than the first wavelength. That is, light emitted by the second plurality of LED regions can have a distribution of wavelengths that are centered around a target wavelength for a desired emission color, e.g., red, green or blue, that is different than the target wavelength of the first plurality of LED regions.

[0030] In example implementations, LED regions can operate with a peak light emission wavelength that may be in a range of 390-430 nanometers (nm), e.g., violet, in a range of 430-480 nm (blue), in a range or 480-510 nm (cyan), in a range of 510-550 nm (green), in a range of 550-600 nm (yellow / orange), or in a range of 600-660 nm (red). A respective spectrum of a LED region can have a full-width at half maximum of e.g. about 20 nm, 30 nm, 40 nm, or 50 nm.

[0031] In some implementations, a semiconductor device can include at least one layer of p-type conductivity that is grown (e.g., epitaxially regrown) on at least one LED region. Epitaxy can be performed using a number of deposition techniques, e.g., metalorganic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), sputtering, among other deposition techniques.

[0032] In some implementations, a semiconductor device can further include a third plurality of LED regions that emit light characterized by a third wavelength that is different than the first wavelength and the second wavelength (e.g., centered at a target wavelength for a different color than the first wavelength and the second wavelength).

[0033] An example method for producing a semiconductor device can be performed using an epitaxial substrate. The substrate can include at least one group-III Nitride semiconductor layer on which LED regions are grown. The substrate can be a bulk wafer with a composition belonging to an aluminum indium gallium nitride (AlInGaN) material system. In some implementations, the substrate can be a template wafer that includes one or more group-III Nitride template layers overlaying a heteroepitaxial substrate formed from a non-group-III Nitride material. Such template wafers can include gallium nitride (GaN) template layers grown on sapphire, silicon, silicon carbide, gallium oxide (GaO), spinel gemstone, and so forth.

[0034] In some implementations, template wafers can include GaN template layers grown on engineered substrates, such as silicon on insulator (SOI) wafers where the group-III Nitride template layers are grown on a relatively thin seed layer including one or moreAty Docket No.: 0120-952BW01 materials appropriate for group-III Nitride epitaxial growth, such as sapphire, silicon, silicon carbide (SiC), or the like. In some implementations, a seed layer can be attached to, or disposed on a handle wafer using a non-epitaxial process such as direct bonding, oxide-oxide bonding, or other such processes. In some implementations, group III-Nitride template layers can be grown on a substrate wafer such as silicon (Si), sapphire, SiC, etc., as part of a same epitaxial process used to grow or form the first plurality of LED regions. In some implementations, a template substrate can be fabricated using a separate epitaxial process than an epitaxial process used form layers of the LED regions.

[0035] In example implementations described herein, LED devices can be formed monolithically. That is, in some implementations, a first plurality of LED region, a second plurality of LED regions, and a third plurality of LED regions can be formed, by epitaxial processes, on a same epitaxial substrate. Formation of such LED regions can occur during one or multiple epitaxial operations. For instance, a first epitaxial process can be used to form the first plurality of LED regions, one a second epitaxial process can be used to form the second plurality of LED regions, a third epitaxial process can be used to form the third plurality of LED regions.

[0036] For purposes of this disclosure, whenever a surface (or interface) is referred to as being planar, or a plurality of surfaces are referred to as being coplanar, it is to be understood that the surface does not have to be an ideally planar surface, or the plurality of surfaces do not have to be ideally coplanar. Instead, it is sufficient if the surface (or interface) is substantially planar, or the plurality of surfaces are substantially coplanar. That is, a substantially planar surface, or a plurality of substantially coplanar surfaces can have a total height variation consistent with what is obtained from a planar epitaxial step. Quantitatively, for example, the surface or surfaces can have a total height variation (THV), relative to a common reference, of less than 100 nm, less than 50 nm, less than 20 nm, or less than 10 nm. In some implementations, a THV can be measured across an area of at least 10 micrometers (pm) x 10 pm, at least 100 pm x 100 pm). As noted above, such a THV can apply to a discontinuous surface (e.g., a plurality of substantially coplanar surfaces. For instance, a plurality of LED regions (e.g. LED mesas) can have respective top regions which have respective top surfaces that are substantially coplanar, e.g., having a small THV across the respective top regions.

[0037] In some implementations, two surfaces (or interfaces) can be substantially parallel. That is, the surfaces may have a local angle that is less than 5 degrees, or less than 1Aty Docket No.: 0120-952BW01 degree. Such a local angle can be measured across an area of at least 10 gm x 10 gm, or an area of at least 100 gm xlOO gm.

[0038] In some implementations, a thickness can be substantially uniform, e.g., a thickness of a layer or a plurality of layers. That is, a substantially uniform thickness can have a total thickness variation (TTV) of less than 100 nm, less than 50 nm, less than 20 nm, or less than 10 nm. In some implementations, a TTV can be measured across an area of at least 10 pm x 10 pm, or an area of at least 100 gm xlOO gm.

[0039] LEDs, such as those described herein, can be formed by various techniques and / or processes. For instance, in some implementations, LEDs can be formed by planar growth of epitaxy and lithography / etch processes, e.g. to form LED mesas. In some implementations, LEDs can be formed by selective area growth (SAG), e.g., where a selective mask is deposited on a substrate and selective growth of LED mesas in openings of the mask is performed. With such processes, several pluralities of LEDs (configured to emit different colors of light) can be formed on a substrate, e.g. a first plurality emitting at a first wavelength, a second plurality emitting at a second wavelength, and / or a third plurality emitting at a third wavelength.

[0040] For purposes of this disclosure, the term at least one layer can refer to a plurality of layers, such as plurality of layers having varying doping levels (e.g. heavily doped, lightly doped, and / or unintentionally doped) and / or varying composition (e.g. GaN, InGaN, AlGaN, AlInGaN). For instance, an active region may include several InGaN (or AlInGaN) quantum wells separated by several GaN quantum barriers, A p-type region can include one or more p-doped GaN layers, such as an electron blocking layer (p-doped AlGaN), and / or a highly doped p+ type GaN contact layer. An n-type layer can include one or more n-doped GaN layers, such an indium-containing underlayer (e.g., a bulk indium gallium nitride (InGaN) layer, a bulk aluminum indium nitride (AllnN) layer, a GaN / InGaN superlattice, and / or other variations). Quantum wells can include In with a concentration in a range of 10-20%, 15-25%, 20-30%, or 25-50%), where the In concentration can be based, at least, on a desired emission spectrum. An epitaxial stack can further include an etch- selective region (or etch-stop region), as discussed herein.

[0041] FIGs. 1 A to ID are diagrams schematically illustrating side, cross-sectional views of example light emitting diode (LED) regions. FIG. 1 A illustrates a plurality of LED regions 110 that are disposed on a substrate 101. As shown in FIG. 1A, the LED regions 100 can include (e.g., be formed from) LED device layers 100. In some implementations, the device layers 100 are grown on the substrate 101 using one or more epitaxial processes.Aty Docket No.: 0120-952BW01

[0042] In this example, the LED device layers 100 of each of the LED regions 110 include a light emitting region 103. The light emitting regions 103, which can include at least one active quantum well (QW) layer, are configured, during operation, to emit photons with a spectrum characterized by a first wavelength. In some implementations, the respective light emitting regions 103 of the LED regions 110 can be configured to emit light of different wavelengths (e.g., selected from red, green and / or blue wavelengths).

[0043] Further in this example, the LED device layers 100 include at least one n-type layer 104, where the at least one n-type layer 104 is grown before the light emitting regions 103. Also in this example, the LED device layers 100 include at least one cladding layer 102, which can be either n-type conductive layers or p-type conductive layers. In some implementations, the at least one n-type layer 104 can also be referred to as a cladding layer or cladding layers.

[0044] While the LED regions 110 shown in FIG. 1 A have rectangular cross-sections, mesas of various shapes can be produced using the approaches described herein. For instance, FIG. IB illustrates an example LED mesa 110a with non-vertical sidewalls 111, e.g., the mesa is trapezoidal in shape. Using the example approaches described herein, the LED mesa 110a can be grown on a template (the epitaxial substrate 101). The growth surface 101 includes at least one n-type layer 104, an active region (e.g., light emitting region 103), p- layers (e.g., at least one cladding layer 102), and sidewall material defining the non-vertical sidewalls 111. In some implementations, the active region and the sidewall material can be n- doped, p-doped, or undoped.

[0045] FIG. 1C illustrates another mesa 110b, where the active region 103 includes a slanted active region portion 103a. In some implementations, the slanted active region portion 103 a can have a different thickness and composition than a planar section 103b of the active region 103, e.g., the slanted active region portion 103a can be thinner than the planar section 103b). In some implementations, the light emitting region 103 may not emit light under electrical injection. In some implementations, material of the non-vertical sidewalls 111 of the 110b can be p-doped and, during electrical injection to the light emitting region 103, holes are injected from the sidewall material, through the slanted active region portion 103a, and into the planar section 103b of the light emitting region 103. Slanted regions of a mesa can have a complex structure, with epitaxial layers growing at an angle, and having varying thickness, composition, doping level, and so forth.

[0046] In example implementations, such as the example of FIG. ID, after forming a first plurality of LED regions 110c that are configured to emit light at a first wavelength, aAty Docket No.: 0120-952BW01 second plurality of LED regions 120 can be formed on a growth surface of a corresponding substrate, e.g., an epitaxial substrate wafer, using a second epitaxial process. The second plurality of LED regions 120, as shown in FIG. ID, include a second set of LED device layers 100a. For purposes of illustration only a single LED region of the first plurality of LED regions 110c, and a single LED region of the second plurality of LED regions 120 is shown in FIG. ID.

[0047] In this example, the second set of LED device layers 100a includes a light emitting region 108, which can include at least one light emitting layer, e.g., one or more quantum well layers, configured to emit light of a second spectrum characterized by a second wavelength. In this example, the second spectrum is different than the first spectrum, e.g., is of a different color. In this example, the second set of LED device layers 100a includes a cladding layer 107 and a cladding layer 109, respectively above and below the light emitting region 108. The cladding layer 107 and the cladding layer 109 can each include one or more layers, which can be n-type layers and / or p-type layers.

[0048] FIG. 2 is a diagram illustrating an example array of LED regions. In this example, the array of LED regions includes a first plurality of LED regions 210 and a second plurality of LED regions 220, which are disposed on a growth surface 201a of a substrate. For purposes of illustration, only a single LED region of the first plurality of LED regions 210, and a single LED region of the second plurality of LED regions 220 are shown. In some implementations, additional pluralities of LED regions can be included on the growth surface 201a. For instance, in some implementations, a plurality of red LED regions, a plurality of green LED regions, and a plurality of blue LED regions can be included on a growth surface of a corresponding substrate. For instance, the LED regions 210 and 220 can be included in an array of LED regions that form pixels of a corresponding display device including LED regions 210 and LED regions 220.

[0049] As shown in FIG. 2, LED regions 210 include first LED layers 211a and conductive layer 250a overlying the LED layers 21 la. As also shown in FIG. 2, LED regions 210 include second LED layers 211b and conductive layers 250b overlying second LED layers 211b.

[0050] In this example, the conductive layers 250a and 250b respectively include sidewall conductive layer 251a and 251b. The sidewall conductive layer 251a and 251b can respectively promote lateral injection into first LED layers 211a and second LED layers 211b. Conductive layers 250a and 250b (and the corresponding sidewall conductive layersAty Docket No.: 0120-952BW01251a and 251b) can be formed by one or more process operations, such as selective area growth, regrowth over an etched sidewall, etching, and / or other process operations.

[0051] In some implementation, the plurality of LED regions 210 and the second plurality of LED regions 220 can be configured to emit at respective, distinct wavelengths. For instance, the plurality of LED regions 210 and the second plurality of LED regions 220 at two distinct colors selected from red, green, and blue. In some implementations, LED regions 210 and 220 are formed monolithically by epitaxial steps on the growth surface 201a of the substrate 201.

[0052] A fabrication process can be performed to produce sidewalls 251a and 251b with a desired width or thickness. For instance, the sidewalls 251a and 251b can have respective remaining widths or thickness that are at least 10 nm (at least 50 nm, at least 100 nm, or at least 200 nm), and / or less than lum (less than 500 nm, or less than 200 nm). Such widths or thicknesses can facilitate lateral current flow while limiting surface area occupied by the sidewalls 251a and 251b.

[0053] In some implementations, there can be height differences of greater than 100 nm between top surfaces of the first plurality of LED regions 210 and the second plurality of LED regions 220. In contrast, in some implementations, upper surfaces of LED regions 210 and 220 are substantially coplanar. Quantitatively, a total height variation (THV) across the upper surfaces of conductive layers 250a and 250b can be less than 100 nm, less than 50 nm, less than 20 nm, or less than 10 nm. This THV can be measured across an area of at least 10 pm x 10 pm; or at least 100 pm x 100pm; or an area that is at least 10 pm x 10 pm and less than 100 pm x 100pm. Such coplanar (substantially coplanar) configurations can be advantageous for further processing, e.g., by providing coplanar surfaces for subsequent processing operations, such as lithography, forming contacts, performing CMP, bonding to a backplane, and so forth.

[0054] As illustrated in FIG. 2, the conductive layers 250a and the conductive layers 250b have vertical sidewalls, respectively the sidewalls 251a and the sidewalls 251b. In other implementations, the sidewalls 251a and 251b can have a variety of geometries, such as slanted or curved sidewalls. Such geometries can be obtained via etch processing (e.g. dry etch, and / or wet etch), which can produce a non-vertical shape for the sidewalls 251a and 251b. In some implementations, the sidewalls 251a and 251b can be slanted, with an angle from vertical that is between 5 degrees and 45 degrees. In some implementations, the sidewalls 251a and 251b can have a varying local angle, with an average angle from vertical that is between 5 degrees and 45 degrees.Aty Docket No.: 0120-952BW01

[0055] In example implementations, the sidewalls 251a and 251b can have a well- controlled thickness. In some implementations, it can be advantageous to limit this thickness, since the sidewalls occupy contribute to a total footprint a respective LED mesa and do not contribute to the active area of the LEDs. In some implementations, a width of the sidewalls 251a and 251b can be less than 1 pm (less than 500 nm, less than 200 nm, or less than 100 nm).

[0056] In FIG. 2, widths of sidewalls 251a and 251b is shown as being equal. In some implementations, mesas configured to emit different colors (such as red, green, blue) can have different sidewall widths. For instance, in some implementations, sidewall 251a could be thinner than sidewall 251b. In some implementations, some mesas can have a sidewall width of zero, e.g., have no conductive material on the sidewall. In this example, some mesas have a sidewall width of zero (no conductive material on the sidewall). For instance, as shown in this example, LED regions 210 can have conductive layers 250a only on top of the mesa and not on its sidewalls (differing from the example shown in FIG. 2), whereas LED regions 220 can have conductive layers 250b overlying the mesa (as shown in the example of FIG. 2).

[0057] Conductive layers 250a and 250b can include a plurality of layers. For instance, the conductive layers 250a and 250b can include p-doped GaN, p-doped AlGaN (acting, e.g., as an electron blocking layer), and / or p-doped InGaN. The conductive layers 250a and 250b can have various geometries. For instance the geometry can be planar, conformal with corresponding LED mesas, or partially conformal with corresponding LED mesas. In some implementations, a topmost layer of the conductive layers 250a and / or 250b can be a highly-doped p-type layer, which can facilitate formation of low resistance p- contacts (e.g., Ohmic contacts). In some implementations, the highly-doped, p-type layer can be doped with magnesium (Mg) or germanium (Ge), with a doping concentration of greater than 5 x 1019 / cm3(greater than 1 x 1020 / cm3, greater than 2 x 1020 / cm3, or greater than 5 x 1020 / cm3).

[0058] In some implementations, conductive layers 250a and 250b can include at least one p-doped layer, and at least one n-doped layer formed on the p-doped layer. A tunnel junction can be formed at an interface between the n-doped layer and the p-doped layer, which can facilitate injection of holes into the active (quantum well) regions during operation. A top surface of the n-doped layer can be planar, leading to coplanar LEDs with an n-doped surface. The tunnel junction can be produced using high n-type and p-type doping, and / or by insertion of a heterostructure (e.g., an InGaN layer) at the interface. The n-dopedAty Docket No.: 0120-952BW01 layer can be conformal around or over the p-doped layer. For instance, the n-doped layer can be formed around the structures of FIG. 2, such that n-doped material surrounds a shell of p- doped material, forming a second shell around the LED mesas.

[0059] In some implementations, a p-contact material is formed on a portion of the conductive layers 250a and 250b. The p-contact material forms p-contacts that enable electrical operation of LED regions 210 and 220. The p-contact material may comprise a metal (e.g. Ti, Al, Ni, Au, Ag, Pt, W, etc.), and / or a transparent oxide (ITO, ZnO).

[0060] FIG. 3 A is a diagram illustrating an implementation of a plurality of LEDs formed on an epitaxial substrate 301. As shown in FIG. 3B, three LED mesas (an LED mesa 310, an LED mesa 320, and an LED mesa 330) are formed on the epitaxial substrate 301. The LED mesas 310, 320 and 330 can be configured to respectively emit blue light, green light, and red light during operation. Respective p-doped materials 302cl, 302c2 and 302c3 overlie each respective LED mesa. The respective p-doped materials 302cl, 302c2 and 302c3 can include a plurality of layers. In this example, each of the p-doped materials 302cl, 302c2 and 302c3 includes two respective regions. Regions 304cl, 304c2 and 304c2 are conformal around the respective LED mesas 310, 320 and 330 with a uniform thickness. Regions 303cl, 303c2, 303c3 respectively surround regions 304cl, 304c2 and 343c2, and respective thicknesse3s of upper portions differ, such that their top surfaces are coplanar. In this example, the upper portion of region 303cl is the thinnest and the upper portion of region 3030c3 is the thickest, to compensate for the fact that the LED mesa 310 is the tallest of the illustrated LED mesas, and the LED mesa 330 is the shortest of the illustrated LED mesas). In this example, the p-doped materials 302cl, 302c2 and 302c3 have a same layer structure; in other examples, the structures and layer configurations of the p-doped materials 302cl, 302c2 and 302c3 may differ. Regardless of the particular arrangement, p-doped materials may be configured to provide a coplanar top surface on top of LED mesas having unequal heights. In some implementations, the p-doped layers 302cl, 302c2 and 302c3 can have respective various compositions and doping levels, such as described herein.

[0061] In the example of FIG. 3B, respective p-doped materials 302cl, 302c2 and 302c3 overlies the respective mesa sidewalls. This arrangement can enable lateral injection of holes into respective active regions (e.g., quantum wells) of the LED mesas 310, 320, and 330.

[0062] In this example, surface 302s, which corresponds with upper surfaces of p- doped materials 302cl, 302c2 and 302c3, is substantially coplanar, as described and below with respect to FIGs. 3B. For instance, as illustrated in FIG. 3B, coplanar regions or surfacesAty Docket No.: 0120-952BW01(e.g., substantially coplanar regions of surfaces), can be defined in the context of surface roughness of respective regions or surfaces.

[0063] For instance, FIG. 3B is a cross-sectional diagram schematically illustrating LED mesas 310 and 320, such as discussed above, with respective top surfaces of epitaxial layers having intrinsic epitaxial roughness. In example implementations, growth of some materials, such as p-doped III-Nitride layers with high doping levels, can result in a local surface roughness, e.g. with a local height variation at least 10 nm (at least 20 nm, or at least 50 nm), or a local height variation in a range 10-100 nm. In some implementations, a THV between two neighboring mesas, such as the LED mesa 310 and the LED mesa 320, can be dominated by this local roughness. For instance, FIG. 3B illustrates a cross-section of the LED mesas 310 and 320 with overlying p-doped regions The LED mesa 310 has an average height of 3 lOah and the LED mesa 320 has an average height of 320ah, where the LED mesas 310 and 320 have coplanar (substantially coplanar) upper surfaces, respectively 302sl and 302s2, of their corresponding p-GaN regions. As shown in FIG. 3D, a difference 302d between the average height 3 lOah of the LED mesa 310 and the average height 320ah of the LED mesa 320 is smaller than the THV 302v due to the epitaxial surface roughness.

[0064] Accordingly, in some examples, a THV between several mesas (or, more generally, several lateral regions) can be defined as a height variation between respective average heights of those mesas or regions. In some examples, two LED mesas are compared (e.g. two mesas having different active regions and configured to emit light at different wavelengths). A difference between an average height of the first and an average height of the second mesa (e.g., respectively averaging over local surface roughness within each mesa) can be less than 100 nm (less than 50 nm, less than 20 nm, less than 10 nm, or less than 5 nm). In some examples, a test region can be examined (e.g., a region with an area of at least 10 pm x 10 pm, or at least 100 pm xlOO pm), where a plurality of mesas are present within the test region (e.g., having at least two different active regions). A largest difference between respective average heights of all the mesas in the test region can be less than 100 nm (less than 50 nm, less than 20 nm, less than 10 nm, or less than 5 nm).

[0065] In this example, bottom surfaces of the LED mesas 310, 320, and 330 are also shown as being substantially coplanar. In some implementations, those bottom surfaces can have other arrangements, e.g., may not be substantially coplanar.

[0066] In the example implementation described herein, mesas of LEDs can be microLED mesas. An LED mesa can include at least one InGaN-containing active region, where the at least one active region can be substantially planar. In some implementations, anAty Docket No.: 0120-952BW01LED mesa can have a lateral dimension (e.g., parallel to a corresponding substrate and / or template) that is less than 20 pm (less than 10 pm, less than 5 pm, less than 3 pm, or less than 1 pm), and / or more than 100 nm (more than 500nm, more than 1 pm). An LED mesa can have vertical sidewalls or non-vertical sidewalls (e.g. slanted sidewalls).

[0067] In some implementations, such as those described herein, a regrown p-doped material can be in contact (e.g., in direct contact) with an n-doped material underlying an active region (e.g. an n-doped template). In some implementations, this junction is configured to avoid parasitic electron-hole recombination at the junction, as such recombination can compete with recombination (e.g., light emitting recombination) in the active region, which can reduce quantum efficiency of the corresponding LEDs. For instance, this junction can have a higher bandgap than the active region of the LED. The active region can be InGaN with a bandgap less than 3 electron-volts (eV), and the junction can have a bandgap greater than 3.3eV, such as a GaN homojunction, or a GaN / AlGaN or AlGaN / AlGaN heterojunction.

[0068] Example implementations include displays, e.g. microLED displays. A display can have an array of pixels, characterized by a pitch. The pitch can be less than 1 millimeter (mm) (less than 100 pm, less than 10 pm, or less than 5 pm). Each pixel can have a plurality of subpixels, e.g. a red subpixel, a green subpixel, and a blue subpixel. Each subpixel can have a fill factor (e.g., a fraction of a total area of a corresponding pixel that is occupied by the subpixel). In some implementations, a fill factor can be in a range 10-50%, 10-20%, 10- 30%, or 20-30%. In some implementations, red subpixels can be larger than green subpixels and blue subpixels. In some implementations, a red subpixel area of a pixel can be at least 1.5 times that of an area of a blue subpixel of the pixel and / or an area of a green subpixel of the pixel.

[0069] In some implementations, subpixels are substantially planar. That is, subpixels of a pixel can have substantially co-planar p-doped layer top surfaces. In some implementations, p-contacts can be formed on top regions (surfaces) of the subpixels, and interfaces between the p-contacts and semiconductor material of the subpixels can be substantially co-planar.

[0070] FIGs. 4A to 4C are cross-sectional views schematically illustrating an example processing flow for forming a display. FIG 4A illustrates a cross-sectional view where epitaxial processing operations and LED processing operations have been performed. For instance, as shown in FIG. 4A, epitaxial processing operations and LED processing operations are used to produce a pixel 410, a pixel 420, and a pixel 430 on an epitaxial substrate 401, e.g., a growth substrate with at least one template layer formed thereon. In thisAty Docket No.: 0120-952BW01 example, each of the pixels 410, 420, 430 respectively includes, at least, three LED mesas. For instance, the pixel 410 include an LED mesa 410b (blue), an LED mesa 410g (green), and an LED mesa 41 Or (red). In this example, each of the LED mesas has p-doped material 402 surrounding the mesa, where top surfaces of the p-doped material are substantially coplanar, as indicated by coplanar surface 402s.

[0071] As shown in FIG. 4B, respective p-type electrical contacts 460 are respectively formed on the material p-doped material 402 of the LED mesas, e.g., 410b, 410g, and 410r. Dielectric material 455 is formed in spaces between the LED mesas. As further shown in FIG. 4B, a CMOS driver 450 is coupled with the respective p-type electrical contacts 460, such that the CMOS driver 450 can drive corresponding LED regions through the respective p-type electrical contacts 460. In this example, for purpose of clarity, various elements of the display are not shown. Such various elements can include n-type contacts, and reflective materials in-between the LED mesas (e.g., metal reflectors disposed in the dielectric material). The structure of FIG. 4B can be obtained by various process operations, e.g. by a copper damascene process and a hybrid bonding process to couple an LED wafer or die with a CMOS wafer or die.

[0072] In FIG. 4C, a growth substrate of the epitaxial substrate 401 is removed, a template portion 401b (e.g. GaN) of the epitaxial substrate 401 is thinned and etched to form a texture. Such a texture can be formed as a two-dimensional pattern of trenches 40 It and / or holes that can facilitate light extraction during operation of the pixels 410, 420 and 430. The display emits light through the etched template in a direction 470.

[0073] Example implementations of semiconductor light emitters that enable light emission with improved efficiency are described herein. The aspects presented herein enable use of LED technology that maintains high efficiency at reduced light emitting device sizes. In some implementations, light emitters may have a size on a micron scale or even a submicron scale.

[0074] As one example, Ill-nitride LEDs can be incorporated into a lighting or display system to cover a wide portion of the visible spectrum of light. However, the efficiency of the light emitters may drop for the emission of longer wavelengths (e.g., red wavelengths) and / or for smaller sizes of individual light emitters due to, for example, sidewall surface degradation, epitaxial growth issues, reduced volume of light-emitting materials which are more susceptible to non-radiative processes with high carrier concentrations at desired brightness, and / or non-uniform distribution of holes throughout anAty Docket No.: 0120-952BW01LED’s quantum well structure, leading to asymmetric carrier concentrations across the active quantum well region of the light emitter.

[0075] FIG. 5 illustrates a portion of an LED structure 500, which includes an active quantum well (QW) structure to produce light emission. As shown in FIG. 5, LED structure 500 is formed on a substrate 510. In an example, a preparation layer 520 is formed, deposited, or grown on a top surface 519 of substrate 510 to prepare for the formation of an active QW structure 530 thereon. A p-type layer (p-type layers 540) is formed on top of (disposed on) active QW structure 530 to provide a protective layer as well as a conductive contact layer.

[0076] While preparation layer 520, active QW structure 530, and p-type layer 540 are shown in FIG. 5 as single layers, in some implementations each one of these layers may include multiple layers of different materials to provide the functionality described above. For instance, active QW structure 530 may include one or more QW and quantum barrier (QB) layer pairs. It is also noted that, in some implementations, preparation layer 520 may be excluded.

[0077] Substrate 510 may be, for example, a semiconductor substrate, a nonsemiconductor substrate prepared with one or more semiconductor layers, such as a sapphire substrate coated with a gallium nitride layer, or a semiconductor template formed using semiconductor epitaxy. Preparation layer 520, for example, may include one or more layers and act as a transitional layer providing surface step and / or morphology to improve the material characteristics of active QW structure 530 grown on preparation layer 520, as compared to an LED structure where active QW structure 530 is grown directly on substrate 510.

[0078] As shown in FIG. 5, the LED structure 500 includes both n- and p-doped regions surrounding the active QW structure 530. For instance, substrate 510 may be, or may include an n-doped layer (such as an n-doped GaN layer or GaN template). Likewise, preparation layer 520 may be n-doped. Active QW structure 530 may be n-doped, p-doped, or undoped.

[0079] In some implementations, a substrate may be n-doped, a preparation layer may be undoped or n-doped, and / or an active QW structure may be n-doped, p-doped or undoped.

[0080] In some implementations, light emission characteristics of active QW structure 530 depends on injection of holes from p-type layer 540 into active QW structure 530 through a c-plane surface 539 in a c-plane direction 550 for a Ill-nitride light emitter. In example implementations, c-plane direction 550 is parallel to a surface normal 560 defined with respect to a plane of the surface of substrate 510. As shown in FIG. 5, surface normalAty Docket No.: 0120-952BW01560 is parallel to c-plane direction 550 (e.g., a layer stacking axis on which preparation layer 520, active QW structure 530, and p-type layer 540 are grown) such that hole injection into active QW structure 530 takes place in a c-plane direction 550 from p-type layers 540 into active QW structure 530. However, this method of hole injection leads to a higher concentration of holes in active QW structure 530 near p-type layer 540 and lower concentration of holes in active QW structure 530 near preparation layer 520, thus resulting in uneven distribution of holes throughout active QW structure 530 (e.g., along c-plane direction 550). More specifically, such hole concentration problems occur when the hole mobility is lower than the electron mobility, which is the case for most semiconductor materials used for light-emitting devices and is especially prevalent in the case of a Ill-nitride material system. Such asymmetric carrier concentrations throughout active QW structure 530 can lead to reduced overall radiative recombination and efficiency in light emission from LED structure 500.

[0081] Aspects of a microLED and / or nano-LED structure are described herein that enable higher efficiencies at a broader range of wavelengths, as well as a broader range of current densities as additional quantum wells can be incorporated into the active light emitting region, through a light emitting structure configured for sidewall hole injection of one or more quantum well layers. For example, the aspects described herein may improve efficiency at longer wavelengths of light emission. It is noted that the device configurations and techniques disclosed herein may be applicable to any semiconductor QW structures and devices.

[0082] FIG. 6 illustrates an example QW-based LED structure 600 enhanced by sidewall hole injection, as described herein. As shown in FIG. 6, LED structure 600 is formed on substrate 510, which may be one of the options described above such as a GaN template or an epitaxial layer formed on a semiconductor substrate. In some implementations, substrate 510 has a planar top surface (e.g., a top surface of a planar wafer). In some examples, techniques such as epitaxial growth and dry etch, or selective area growth may be used to define the position, shape, and size of the elements of LED structure 600.

[0083] In the example implementation shown in FIG. 6, LED structure 600 includes a preparation layer 620 formed on top surface 519 of substrate 510. Substrate 510 and preparation layer 620 may be n-doped. Preparation layer 620 may include one or more layers of materials to improve surface conditions for formation of an active QW structure 630 thereon. Active QW structure 630 includes one or more sets of a QW layer sandwiched between QB layers formed, grown, or deposited on preparation layer 620. Active QWAty Docket No.: 0120-952BW01 structure 630 acts as a source of light emission for LED structure 600. An electron blocking layer (EBL) 640 may be formed around preparation layer 620 and active QW structure 630 to reduce current leakage from preparation layer 620 and active QW structure 630. In some implementations, the electron blocking layer 640 may be omitted.

[0084] In some implementations, preparation layer 620 may be formed on substrate 510 such that one or more surfaces of preparation layer 620 are parallel to top surface 519, as shown in FIG. 6. In an example implementation, five or more sets of QW / QB layers are included within active QW structure 630. In some implementations, fifty or more sets of QW / QB layers may be included within active QW structure 630, depending on an intended emitted wavelength and operating brightness of active QW structure 630. A variety of materials, such as InGaN, can be used to implement active QW structure 630, depending on desired performance characteristics.

[0085] In this example, because InGaN alloys have a lower bandgap than GaN, with a higher In concentration corresponding to a lower bandgap, a desired wavelength may be achieved by selecting a desired In% concentration. For instance, an In % concentration may be at least 10% (or at least 15%, or at least 20%, or at least 25%, or at least 30%). In some implementations, In% concentration may be in a range of 10-20% (or in a range of 15-25%, or in a range of 20-30%, or in a range of 25-35%, or in a range of 30-40%). In some examples, InGaN may also be used in the preparation layers. In such implementations, an In % concentration in the preparation layers may be lower than an In% concentration in the QWs. For instance, In% concentration in the preparation layers may be in a range 0-5%, or in a range of 0-10%, or in a range of 2-8%, or in a range of 1-10%.

[0086] Still referring to FIG. 6, a p-type layer 650 is formed around electron blocking layer 640 to provide hole injection through sidewalls 652 of active QW structure 630 in directions indicated by arrows 654, in addition to c-plane hole migration through a top surface 639 of active QW structure 630 in c-plane direction 550. The sidewall hole injection for active QW structure 630 achieves a more uniform hole distribution across active QW structure 630, which facilitates improvement in external quantum efficiency (EQE) of LED structure 600.

[0087] In the example of FIG. 6, P-contact 660, P-type layer 650 and electron blocking layer 640 may be p-doped. Therefore, the structure of FIG. 6 may include a p-n junction located at a boundary between p-doped and n-doped layers, where this boundary may include tan interface between substrate 510 and some p-doped layers (e.g., p-type layer 250 and / or electron blocking layer 640), and / or an interface between preparation layer 620Aty Docket No.: 0120-952BW01 and some p-doped layers. If active QW structure 630 is n-doped, a p-n junction is present at its interface with p-doped layers (e.g., with electron blocking layer 640, or with p-type layer 650 if electron blocking layer 640 is omitted). If active QW structure 630 is undoped, a p- intrinsic- n (p-i-n) region may be formed, with the intrinsic region corresponding to active QW structure 630.

[0088] In the LED structure 600 of FIG. 6, injection of holes may occur both into active QW structure 630 and in some n-doped layers (including substrate 510 and preparation layer 620). However, injection of holes in these n-doped layers (other than active QW structure 630) may not be desirable. Accordingly, in some implementations, the LED structure 600 of FIG. 6 may be configured to inject holes into active QW structure 630 without significantly injecting holes into these n-doped layers. This may be achieved by achieve by selection of respective bandgaps of the materials (e.g., through design and / or processing), as well as selection of operating parameters of the LED structure 600. For instance, if the substrate 500 is n-GaN and the active QW structure 630 is InGaN (with a lower bandgap than GaN), the LED structure 600 may be operated at a voltage sufficient for hole injection in InGaN (which may be less than 3 V) but lower than a voltage necessary for hole injection into GaN (which may be on the order of 3.4V). For instance, the operating voltage may be less than 3V (or less than 2.7V, or less than 2.5V, or less than 2.2V).

[0089] In some implementations, preparation layer 620 may include InGaN layers with a lower In% composition than active QW structure 630, such that hole injection into preparation layer 620 is not significant. For instance, a voltage necessary for hole injection into preparation layer 620 may be at least 3 V, and the LED structure 600 may be operated a voltage below 3 V (or below 2.7V, or below 2.5V, or below 2.2V).

[0090] In some examples, at least 80% (or at least 90%, or at least 99%) of a hole current may be injected into active QW structure 630. This injection may be lateral, vertical, or both lateral and vertical. That is, in example implementations described herein, there may be direct contact between p-type regions and n-type regions surrounding an active QW structure, but preferential current injection in the active QW structure.

[0091] Sidewall hole injection also allows for an increased number of QW / QB pairs within active QW structure 630 (or other active QW structures described herein), as well as an increase in a thickness of each corresponding QB layer (e.g., of a QW layer and QB layer pair), as is discussed in further detail below. That is, sidewall hole injection allows more uniform distribution of holes throughout an entire set of QW layers within active QW structure 630, even with increased numbers of QW / QB layers and thicker QB layers, leadingAty Docket No.: 0120-952BW01 to improved LED light emission performance as well as additional device design and epitaxial growth structure flexibility. For instance, with sidewall hole injection, tens of QW / QB combination layers (pairs) can be incorporated into LED structure 600, thus providing extended design options for emission of light over a wider range of wavelengths than previously possible. Also, each QB layer can have a thickness of 50 nm or greater (or 30 nm or greater, or 20 nm or greater, or 10 nm or greater, or 8 nm or greater, or 6 nm or greater), with more uniform distribution of holes throughout active QW structure 630 and without a reduction in EQE characteristics of LED structure 600. Increased thickness of each QB layer may help to improve, for example, strain balance and growth morphology for the overall active QW structure 630. A QB may include several layers, including layers of GaN, layers of InGaN, and layers of Al GaN (with an Al% composition of at least 10% (e.g., at least 20%, 30%, 40%, 50%)) or even AIN. A p-contact 660 is formed on p-type layer 650 to provide electrical contact to LED structure 600. P-contact 660 is formed, for example, of a metal, metal alloy, a transparent conductor, and / or other conductive material compatible with p-type layer 650.

[0092] Active QW regions may be characterized by one or more of following aspects, alone or in combination, which may be facilitated by lateral injection. For instance an active QW region (active QW structure) can have a plurality of quantum wells (e.g., at least 4, or at least 6, or at least 8, or at least 10, or at least 12, or at least 14, or at least 16, or at least 18, or at least 20). An active QW region can operation with efficient lateral injection of holes into a plurality of QWs, with at least 4 (e.g., at least 6, or at least 8, or at least 10, or at least 12, or at least 14, or at least 16, or at least 18, or at least 20) QWs being laterally injected with holes. An active QW region can include thick barrier layers (e.g., quantum barrier (QB) layers) between respective quantum wells. These barrier layers can have a thickness of at least 6 nm (e.g., at least 8 nm, or at least 10 nm, or at least 15 nm, or at least 20 nm). Such barrier layers may include at least one GaN layer, and / or at least one Al GaN layer, where the Al% concentration is at least 10% (e.g., at least 20%, at least 30%, at least 40%, at least 50%). QWs of an active QW region can operate (emit light at a desired wavelength) at an operating voltage less than V0 + 1 V (e.g., less than V0 + 0.5 V, less than V0 + 0.3 V) where V0=1240 / lambda (where lambda is a peak emission wavelength), measured at a current density of at least lA / cm2 (e.g., at least 10A / cm2, at least 100A / cm2). A peak emission wavelength (lambda) may be at least 590 nm (e.g., at least 600 nm, at least 610 nm, at least 620 nm, or at least 630 nm) at a current density of at least lA / cm2 (e.g., at least 10A / cm2, at least 100A / cm2).Aty Docket No.: 0120-952BW01

[0093] In some implementations, an LED structure can have six or more quantum wells each emitting light at a wavelength lambda, at a current density of at least lA / cm2, where lambda is at least 600 nm. The six or more quantum wells may be separated by quantum barriers (QBs) having a thickness of at least 6 nm. The LED structure can also include p-layers disposed on the sidewalls of the LED structure, where the p-layers and the QWs are arranged to facilitate sidewall injection of holes into the quantum wells from the p- layers, thus facilitating an operating voltage lower than V0+0.5 V (where V0=1240 / lambda) and an operating current density of at least lA / cm2.

[0094] Further modifications to LED 600 are possible. For example, EBL 640 may be omitted in some implementations. Additionally, p-contact layer 660 may be conformally wrapped over the vertical sides of p-type layer 650, as is discussed further below. Still further, preparation layer 620 or equivalent materials promoting favorable growth conditions for active QW structure 630 (e.g., lattice matching, adhesion, and / or defect control) may be incorporated into substrate 510.

[0095] In some implementations, one or more additional hole blocking layers can be incorporated into an LED structure for prevention of hole migration into the preparation layer, which may improve hole injection efficiency into a corresponding active QW structure. Two examples of LED structures including hole blocking layers are respectively illustrated in FIGs. 8 and 8.

[0096] As shown in FIG. 7, in addition to the various components of LED structure 600, LED structure 700 includes a hole blocking layer 710 disposed between substrate 510 and preparation layer 620 to prevent migration of holes into preparation layer through substrate 510. Similarly, in FIG. 8, an LED structure 800 includes a hole blocking layer 810 surrounding (e.g., at least partially surrounding) preparation layer 620 to prevent sidewall hole injection into preparation layer 620, which may isolate sidewall hole injection effect to active QW structure 630. Example materials for the hole blocking layers include, but are not limited to, an n-doped layer, such as an n-doped AlInGaN or AlGaN material. In some implementations, hole blocking layer 810 may be incorporated into substrate 510, or disposed below preparation 620, such as hole blocking layer 1610 of FIG. 16. In such implementations, such as the example of FIG. 16, a hole blocking layer may extend between p-type layer 650 and substrate 510 so as to reduce electrical leakage from LED structure 800.

[0097] FIG. 9 illustrates an exemplary implementation of a QW -based LED structure 900 enhanced by sidewall hole injection. LED structure 900 includes a preparation layer 920 formed on substrate 510. Dimensions of preparation layer 920 can be defined using, forAty Docket No.: 0120-952BW01 example, epitaxial growth and dry etch, or selective area growth techniques. In some implementations, preparation layer 920 may be omitted. As with the LED structure 800 of FIG. 8, preparation layer 920 of the LED structure 900 is surrounded (e.g., at least partially surrounded) by a hole blocking layer 925 to reduce hole migration (injection) into preparation layer 920.

[0098] In the example of FIG. 9, an active QW structure 930 is created by forming alternating stacks of QB layers 932 and QW layers 934 on hole blocking layer 925 in a pyramidal shape. In the LED structure 900, active QW structure 830 is surrounded (e.g., at least partially surrounded) by an electron blocking layer 940, and a p-type layer 950 is formed on electron blocking layer 940. P-type layer 950 promotes injection of holes specifically into QW layers 934 as indicated by arrows 954, which denote directions that are perpendicular, or has a component perpendicular, to c-plane direction 550. A p-contact 960 is formed at least partially over p-type layer 950 to provide electrical contact to LED structure 900, e.g., to p-type layer 950. In the example of FIG. 9, LED structure 900 further includes a dielectric layer 980, which may be disposed on substrate 510 and may abut, or contact hole blocking layer 925. In some implementations, dielectric layer 980 blocks contact between electron blocking layer 940, p-type layer 950, and substrate 510, further preventing hole migration into preparation layer 920. For example, dielectric layer 980 may prevent unwanted current flow between p-type layer 950 and substrate 510.

[0099] As with other implementations described herein, p-type layer 950 facilitates hole injection into QW layers 934 in a direction other than c-plane direction 550, thus leading to greater uniformity in hole injection into, and hole migration through active QW structure 930. Consequently, implementations of LED structure 900 may exhibit improved EQE and light emission improvement over LED devices without a device architecture which enables sidewall hole injection.

[0100] FIG. 10 illustrates an LED array 1000 including QW -based LED structures enhanced with sidewall hole injection, in accordance with an example implementation. As shown in FIG. 10, LED array 1000 includes LED structure 600 (as described in reference to FIG. 6). A second LED structure 600' is also included in LED array 1000. As shown, LED structure 600' includes a preparation layer 620', an active QW structure 630', an electron blocking layer 640', a p-type layer 650', and a p-contact 660'. LED structure 600' may be structurally identical to LED structure 600 such that they exhibit similar light emission characteristics at a similar wavelength. As discussed previously with respect to LED structure 600, in some implementations, preparation layer 620' may be omitted. Alternatively, LEDAty Docket No.: 0120-952BW01 structure 600' may include different material compositions (e.g., different materials used in the preparation layer 650', active QW structure 630', etc.) such that LED structure 600' exhibits different light emission characteristics from LED structure 600 while still taking advantage of the same sidewall hole injection mechanism as LED structure 600.

[0101] A top view of exemplary LED array 1100, including an array of LED structures 1110, 1120, and 1130 emitting at red, green, and blue wavelengths, respectively, is shown in FIG. 11.

[0102] FIG. 12 illustrates an example of a vertically stacked layer structure 1200 from which microLED devices can be produced. For instance, FIG. 12 illustrates an arrangement (e.g., a stack) of layers that can be used to emit different colors of light from within a same device. In this example, an n-type preparation layer 1205 is disposed above and / or disposed on a substrate 1201. In some implementations, the preparation layer 1205 may include n-type GaN layers, n-type InGaN layers, n-type AlGaN layers, or combinations thereof. As shown in FIG. 12, an n-type layer, e.g., hole blocking layer (HBL) 1210, can be disposed above and / or on preparation layer 1205. In some implementations, HBL 1210 can have various compositions (e.g. AlGaN, InAlGaN, InGaN, Si-doping, etc.). The properties of HBL 1210 can preclude the flow of holes through the layer, for instance if layer 1210 is AlGaN.

[0103] Multi quantum well (MQW) structures 1215 are disposed above and / or disposed on HBL 1210. MQW layers 1215 can emit light of one of a plurality of colors (e.g., red, green or blue). In this example, the MQW layers 1215, in operation, emit blue light. An n-type layer 1220 can be disposed above and / or disposed on MQW layers 1215. For instance, layer 1220 may serve as a second HBL. In some implementations, N-type layer 1220 can have various compositions (e.g. AlGaN, InAlGaN, InGaN, doped , etc.).

[0104] MQW layers 1225, e.g., second MQW layers, are disposed above and / or disposed on n-type layer 1220. As with MQW layers 1215, MQW layers 1225 can emit light of one or a plurality of colors, e.g., a different color than MQW layers 1215. In this example, the MQW layers 1225, emit green light. An n-type layer 1230, e.g., a third n-type layer, may be disposed above and / or disposed on MQW layers 1225. Layer 1230 may serve as a third HBL. In some implementations, n-type layer 1230 can have various compositions (e.g. AlGaN, InAlGaN, InGaN, Si-doping, etc.).

[0105] MQW layers 1235, e.g., third MQW layers, are disposed above and / or disposed on n-type layer 1230. As with MQW layers 1215 and 1225, MQW layers 1235 can emit light of one of a plurality of colors, e.g., a different color than the respective colors of MQW layers 1215 and MQW layers 1225. In this example, MQW layers, in operation, emitAty Docket No.: 0120-952BW01 red light. An n-type layer 1240, e.g., fourth -n-type layer, can be disposed above and / or disposed on MQW layers 1235. In some implementations, n-type layer 1240 can have various compositions (e.g. AlGaN, InAlGaN, InGaN, Si-doping, etc.). In example implementations, vertically stacked layer structure 1200 can be patterned to produce emitters of different colors integrated into single pixels.

[0106] In some implementations, the vertically stacked layer structure 1200 shown in FIG. 12 is grown by planar epitaxy. In some implementations, the vertically stacked layer structure 1200 contains n-doped layers and undoped layers, but does not contain any p-doped layers, e.g., excludes p-doped layer. This is in contrast with other possible implementations where p-type and n-type layers are interspersed (and, in some implementations, can form tunnel junctions between active regions of different colors). In some implementations, the vertically stacked layer structure 1200 may contain p-doped layers formed above MQW layers 1235, but exclude p-doped layers below layers 1235 (that is, the layers between the first MQW layers 1215 and the third MQW layers 1235 may be n-doped and / or undoped, but exclude p-doped layers).

[0107] FIG. 13 illustrates a vertically stacked layer structure 1300, which can be produced by subjecting vertically stacked layer structure 1200 subjected to additional processing, e.g., semiconductor fabrication operations. In region 1305 of vertically stacked layer structure 1300, layers of vertically stacked layer structure 1200 have been patterned and etched to expose n-type layer 1210 (e.g., the first HBL). These process operations also defines a periphery of the device. As shown in FIG. 13, these process operations also expose sidewalls of MQW layers 1215 in region 1305. In region 1310 of vertically stacked layer structure 1300, layers of vertically stacked layer structure 1200 have been patterned and etched to expose n-type layer 1220 (e.g., the second HBL). As shown in FIG. 13, these process operations also expose sidewalls of MQW layers 1225 in region 1310. In region 1315 of vertically stacked layer structure 1300, layers of vertically stacked layer structure 1200 have been patterned and etched to expose n-type layer 1330 (e.g., the third HBL). These process operations also expose the sidewalls of MQW 1235 in region 1315. In region 1300 of this example, none of the layers of vertically stacked layer structure 1200 are patterned and / or etched. Etch steps for producing vertically stacked layer structure 1300 from vertically stacked layer structure 1200 can include dry etch processes, wet etch processes, or combinations thereof.

[0108] Subsequent to the patterning and etch processes discussed above, p-type layer 1325, e.g., an AlGaN layer, is then formed above (e.g., on) the resulting patterned and etchedAty Docket No.: 0120-952BW01 structure. Various processes, such as patterning and etch processes, may be used to prepare the exposed surfaces (e.g., surfaces of the three HBL layers as well as the sidewalls of the three MQW layer structures). These processes may include lithography, etching, material deposition (e.g. thin-film deposition), surface treatments (e.g. chemical clean), epitaxy. In some implementation, p-type layer 1325 may be formed in a conformal manner (e.g., as shown in FIG. 23) or may have a sloped profile with respect to the sidewalls of the three MQW structures.

[0109] The p-type layer 1325, during operation of an LED produced from the vertically stacked layer structure 2300, is configured to inject carriers into the sidewalls of the MQW layer structures 1215, 1225 and 1235. As described herein, this carrier injection can improve the performance of a corresponding LED (e.g., improve quantum efficiency). A p+ layer 1330, e.g., a GaN layer, is formed above (e.g., on) p-type layer 1325. The p+ layer 1330 serves as an electrical conduction path and can be conformal with the underlying structure of the vertically stacked layer structure 2300. The combination of the p-type layer 1325 and the p+ layer 1330 enhances both hole injection in the c-plane direction (e.g., from an upper surface of the device) as well as sidewall hole injection into the three MQW layer structures. In some examples, the 2300 is configured such that carrier injection occurs preferentially (or only) from, through, or at the sidewalls.

[0110] FIG. 14 illustrates a vertically stacked layer structure 1400, .e.g., after the vertically stacked structure 1300 has been subjected to additional processing. In this example, in region 1305, vertically stacked layer structure 1300 has been patterned and etched to form void 1405 by removing p+ layer 1330 and a portion of p-type layer 1325 from void 1405. This operation effectively isolates a corresponding LED device from adjacent LED devices.

[0111] As shown in FIG. 14, in region 1310, the vertically stacked layer structure 1300 has been patterned and etched to remove p+ layer 1330 to form void 1410 by removing a portion of p-type layer 1325. This operation effectively isolates the MQW layer structure 1215 from the MQW layer structure 1225 on a p-side (upper side) of the vertically stacked layer structure 1400. In region 1315, the vertically stacked layer structure 1300 has been patterned and etched to form void 1415 by removing p+ layer 1330 and a portion of p-type layer 1325. This operation effectively isolates the MQW layer structure 1225 from the MQW layer structure 1235 on the p-side (upper side) of the vertically stacked layer structure 1400. The patterning of vertically stacked layer structure 1400 can include one or more etch operations, which can be dry etch processes, wet etch processes, or combinations thereof.Aty Docket No.: 0120-952BW01

[0112] After the patterning, e.g., etch processes, contact pad 1420 is formed within region 1310. This allows for MQW layer structure 1215 to be independently addressed during operation a device including the vertically stacked layer structure 1400. Additionally, contact pad 1425 is formed within region 1315. This allows for MQW layer structure 1225 to be independently addressed during operation of the device. Additionally, contact pad 1430 is formed within region 1320. This allows for MQW layer structure 1235 to be independently addressed during operation of the device. In this example, voids 1405, 1410, and 1415 define respective peripheries of the resultant three emitter regions (e.g., MQW layer structures 1215, 1225, and 1235). Therefore, the contact pads 1420, 1425, and 1430 make electrical contact along the perimeter of the three emitters. The vertically stacked layer structure 1400 can then be subjected to further processing to form fully functional LED devices.

[0113] Although the etch operations described above with respect to FIG. 14 are shown as terminating at, or within, p-doped AlGaN layers, variations are possible. For instance, in some implementations, etch steps can etch entirely through p-layers, e.g., p- doped AlGaN layers, and into an underlying n-doped layer. Therefore, in such implementations, corresponding void regions (e.g., voids 1405, 1410, 1415) can terminate at, or within an n-GaN layer.

[0114] FIG. 15 illustrates a vertically stacked layer structure 1500 after the vertically stacked structure 1200 has been subjected to additional processing operations. In region 1505 of the vertically stacked layer structure 1500, layers of vertically stacked layer structure 1200 have been patterned and etched to expose n-type layer 1220 (e.g., the second HBL). In region 1510 of vertically stacked layer structure 1500, layers of vertically stacked layer structure 1200 have been patterned and etched to expose n-type layer 1230 (e.g., the third HBL). In region 1515 of vertically stacked layer structure 1500 layers 1200 are not patterned and etched. In region 1505, void 1520 is formed through MQW layer structure 1215 (e.g., the first MQW). In region 1510, void 1525 is been formed through MQW layer structure 1225 (e.g. , the second MQW). In region 1515, void 1530 is been formed through MQW layer structure 1235 (e.g., the first MQW). After forming voids, 1520, 1525, and 1530, p-type layer 1540 (e.g., an AlGaN layer) is formed above the patterned and etched structure. Various etch processes may be used to prepare the exposed surfaces of prior to formation of p-type layer 1540 (e.g. surfaces of the three HBL layers as well as the sidewalls of the three MQW structures). The etch steps may include dry etch processes, wet etch processes, or combinations thereof.Aty Docket No.: 0120-952BW01

[0115] The p-type layer 1540 of the vertically stacked layer structure 1500 can be formed in a conformal manner with respect to the sidewalls of the three MQW structures. The p-type layer 1540 is configured, during operation an LED device including the vertically stacked layer structure 1500, to inject carriers (e.g., holes) into sidewalls of the three MQW structures (1215, 1225, and 1235). As described here, this carrier injection may improve the performance of the device, such as increasing quantum efficiency.

[0116] A p+ layer 1545 (e.g., a p+ GaN layer) is disposed above and / or on p-type layer 1540. The p+ layer 1545 can be conformal with the underlying structure of the vertically stacked layer structure 1500, and serves as an electrical conduction path. The combination of the p-type layer 1540 and the p+ layer 1545 can enhance both hole injection in the c-plane direction (e.g., from the top, or an upper surface of the device) as well as sidewall hole injection into the three MQW structures.

[0117] FIG. 16 illustrates a vertically stacked layer structure 1600 after the vertically stacked structure 1500 has been subjected to additional processing operations. In region 1505 of vertically stacked layer structure 1600, the device has been patterned and etched to form void 1602 by removing p+ layer 1545 and a portion of p-type layer 1540. This operation effectively isolates the first MQW layer structure 1215 from the MQW layer structure 1225. In region 1510 of vertically stacked layer structure 1600, the device has been patterned and etched form void 1610 by removing p+ layer 1545 and a portion of p-type layer 1540. In region 1515 of vertically stacked layer structure 1600, the device has been patterned and etched to form void 1615 by removing p+ layer 1545 and a portion of p-type layer 1540. This step effectively isolates the MQW layer structure 1225 from the MQW layer structure 1235. The etch operations may include dry etch processes, wet etch processes, or combinations thereof.

[0118] After the etch operations, contact pad 1630 is formed in region 1505 and centered above void 1520. This allows MQW layer structure 1215 to be independently addressed during operation of the device. Additionally, contact pad 1635 is formed in region 1510 and centered above void 1525. This allows MQW layer structure 1225 to be independently addressed during operation of the device. Additionally, contact pad 1640 is formed in region 1515 and centered above void 1530. This allows MQW structure 1235 to be independently addressed during operation of the device. In this example, voids 1520, 1525, and 1530 penetrate respective centers of the three illustrate emitter regions (e.g., MQW layer structures 1215, 1225, and 1235). The vertically stacked layer structure 1600 of FIG. 16 can be subjected to further processing to form fully functional LED devices.Aty Docket No.: 0120-952BW01

[0119] An example implementation of a method of forming or producing a stacked device, such as example stacked devices described herein, includes producing or providing a substrate with a growth surface, such a substrate with a GaN-based template (e.g., growth surface). The example method further includes, growing an epitaxial stack having, in order of epitaxial growth, a first active region (emitter, MQW, etc.), an n-type spacing region, a second active region, and a top layer. The first active region and the second active region to respectively emit blue, green, or red active light. The first active region and the second active region may be n-doped, undoped, p-doped. The top layer may include a p-doped layer, an AlGaN layer (e.g., an EBL and / or an HBL). The epitaxial stack may be planar, e.g., all the epitaxial regions are disposed in respective planes that are parallel with the growth surface.

[0120] The example method further includes, etching a first region to expose a first sidewall of the first active region, and etching a second region to expose a second sidewall of the second active region. The example method also includes, forming p-doped material (e.g., by epitaxial regrowth) that overlies the first and second sidewalls. The example method further includes, etching the p-doped material to form (1) a first p-doped region that contacts the first sidewall and can inject holes laterally into the first active region, e.g., forming a first LED, and (2) a second p-doped region that contacts the second sidewall and can inject holes laterally into the second active region, e.g., forming a second LED.

[0121] The example method also includes, forming a first p-contact and second p- contact to, respectively, the first p-doped region and the second p-doped regions, such that the first LED and the second LEDs can be operated, e.g., operated independently. The first LED and the second LED may be configured to form subpixels of a pixel of a display device. The example method can also include producing a third LED with a third active region, thus enabling three-color operation (e.g. for a red-green-blue display) with a single vertically stacked epitaxial layer structure.

[0122] FIGs. 17A to 17G are cross-sectional diagrams illustrating an example fabrication flow for producing a stacked LED device. As shown in FIG. 17 A, an epitaxial stack 1700 is grown. The epitaxial stack 1700 can be grown in a single epitaxial process operation (epitaxial run), or can be grown using multiple epitaxial process operations. In this example, the epitaxial stack 1700 includes, in order of epitaxial growth, a template / substrate 1701, an n-doped base layer 1702, a first active region 1703 (configured to emit light at a first wavelength), a first n-doped spacing region 1704, a second active region 1705 (configured to emit light at a second wavelength), a second n-doped spacing region 1706, a third active region 1708 (configured to emit light at a third wavelength), and a top layer 1708 (which mayAty Docket No.: 0120-952BW01 include p-layers and / or n-layers). Each layer or region of the epitaxial stack 1700 can include one or more semiconductor layers, including III-V semiconductors, III-Nitrides, GaN, InGaN, AlGaN, AllnN, and / or AlInGaN of various compositions. In particular, the active regions 1703, 1705 and 1707 may include In-containing quantum wells that are configured to emit one of blue, green and red light. In examples, any ordering of colors for the active regions 1703, 1705 and 1707 is possible, e.g., first / second / third active regions may be, blue / green / red, red / green / blue, and so forth.

[0123] As shown in FIG. 17B, layers of the epitaxial stack 1700 are etched (e.g., by three successive etch operations combined with corresponding lithography operations) to expose a first sidewall 1703w of the first active region 1703, a second sidewall 1705w of the second active region 1705, and a third sidewall 1707w of the third active region 1707. In this example, the etch operations terminate, respectively, at or within the tempi ate / substrate 1701, the first n-doped spacing region 1704, and the second spacing region second n-doped spacing region 1706.

[0124] As shown in FIG. 17C, a p-doped material 1710 is regrown on the etched stack of FIG. 17B. In some implementations, regrowth of the p-doped material 1710 can be performed epitaxially, with the p-doped material 1710 being a crystal epitaxially registered to a crystal of the etched stack. In some implementations, regrowth of the p-doped material 1710 can be achieved using metal-organic chemical vapor deposition (MOCVD), molecular- beam epitaxy (MBE), sputtering, atomic-layer deposition (ALD), and / or other epitaxial methods. In this example, the p-doped material 1710 is planar (substantially planar) after its growth. Planarization of the p-doped material 1710 can be obtained through selection of growth conditions that facilitate a planarizing growth mode (e.g., by selecting pressure, precursor flows, carrier gas flows, temperature, and / or doping level used during the growth operation).

[0125] As shown in FIG. 17D, etched portions 1720 are formed in the p-doped material 1710 to separate it into a first p-doped region 1710a, a second p-doped region 1710b, and a third p-doped region 1710c. In this example, the first p-doped region 1710a, the second p-doped region 1710b, and the third p-doped region 1710c respectively contact the first sidewall 1703w, the second sidewall 1705w, and the 1707w. In some implementations, upper surfaces of the first p-doped region 1710a, the second p-doped region 1710b, and the 1710c can be coplanar or substantially coplanar.

[0126] FIG. 17E illustrates formation of p-contacts 1730 on portions of the first, second and third p-doped regions 1710a, 1710b, and 1710c. FIG. 17 F illustrates formation ofAty Docket No.: 0120-952BW01 trench material in the etched portions 1720, which can be referred to as trenches, between the first, second and third p-doped regions 1710a, 1710b, and 1710c. In some implementations, the trench material 1740 can include dielectrics and / or metals. The first, second and third p- doped regions 1710a, 1710b and 1710c are electrically isolated from each other after the trench material 1740 is disposed in the etched portions 1720. As further shown in FIG. 17F, a CMOS driver 1750 is coupled with an LED wafer including the stacked LED device of this example. For instance, the CMOS driver 1750 is coupled with the LED wafer (e.g., via the p- contacts 1730) using a bonding material 1760. For instance, hybrid bonding (such as wafer- to-wafer bonding, die-to-wafer bonding, and / or die-to-die bonding) can be performed to couple the CMOS driver 1750 with the LED device produced from the epitaxial stack 1700.

[0127] FIG. 17G illustrates removal of a growth substrate of the tempi ate / substrate 1701 from the structure of FIG. 17F. In some implementations, removal of the growth substrate can include thinning the tempi ate / substrate 1701, and forming textured regions 1770 (e.g., openings in the substrate 1701), which can facilitate light extraction during operation of the corresponding LED device. The resulting device includes three LEDs (stacked) that can be operated independently using the CMOS driver 1750, such that the three LEDs emit light at their respective wavelengths. In some implementations, the three LED may be included in a subpixel of a display pixel.

[0128] In some implementations, N-contacts can be formed at various positions of the device of the example of FIGs. 17A-17G. For instance, an n-contact may contact a portion of the tempi ate / substrate 1701, or a portion of the n-doped base layer 1702 (e.g., a base layer). In some implementations, a same n-contact can be used as an n-contact for the three LEDs of the stacked device of FIGs. 17A-17G.

[0129] FIG. 18 is a cross-sectional diagram that illustrates operation of a stacked LED device, such as the stacked device of FIGs. 17G, with the CMOS driver 1750 and the bonding material 1760 omitted. In this example, voltages are referenced to a voltage potential at the n- contact (e.g., where the n-contact is at 0 V, or electrical ground). Voltages VI, V2, V3 are applied to respective p-contacts 1730a, 1730b, and 1730c, which induces first, second and third flows of holes that are laterally injected, respectively, in the first, second and third active regions 1703, 1705, and 1707, and first, second, and third flows of electrons that are injected from the n-contact to, respectively the first, second, and third active regions 1703, 1705, and 1707. The electron and hole flows (e.g., currents) result in respective light emissions in the respective active regions.Aty Docket No.: 0120-952BW01

[0130] FIG. 19 is a cross-sectional diagram of a stacked display 1900 having several stacked pixels 1810, such as a plurality of the stacked devices of FIGs. 17A-17G. Each stacked pixel 1810 has three subpixels, such as described herein. The stacked pixels 1810 are separated by a pixel pitch 181 Op. In some implementations, the pixel pitch 181 Op can be less than 200 pm (less than 100 pm, less than 20 pm, less than 10 pm, or less than 5 pm). An area of a stacked pixel 1810 can be less than 200 pm2(less than 100 pm2, less than 20 pm2, less than 10 pm2, 5 pm2).

[0131] In some examples of stacked LEDs, the area of each active region is maximized. The area of each color may be at least 30% (or 40%, 50%, 60%, 70%, 80%) of the total area of a pixel. In some examples, a stacked LED display includes a red LED, and the area of the red LED is at least 30% (or 40%, 50%, 60%, 70%, 80%) of the total area of a pixel.

[0132] In some examples, the staked LED does not contain any tunnel junction, i.e. the spacing regions between active regions are of a single doping type (e.g. n-doped).

[0133] In some examples, a stacked LED is driven to avoid unwanted emission from a subpixel due to reabsorption of light from another subpixel. For instance, if a pixel is nominally-off, a voltage V or current I (e.g. V=0 or V<0 or 1=0 or I<0) may be imposed on the device to sweep out any carriers created by absorption, so that the device emits no light in the nominally-off state.

[0134] In a variation, a stacked LED includes tunnel junctions. In this approach, the first and second spacing regions become first and second tunnel junctions, e.g. having (in order of epi growth) an n+ region, a tunnel junction region, a p+ region. The tunnel junction may be a homojunction e.g. between n+ GaN and p+ GaN), or a heterojunction (e.g. with a InGaN layer). Here the sign + indicated a highly-doped region, as these are beneficial to tunnel junctions. In this case, the regrown material may be n-doped material rather than p- doped material, and n-contacts are formed on the n-doped material.

[0135] FIGs. 20A to 20J illustrate examples of example dopant concentration profiles within n-type layers (e.g., HBLs). The distribution of the n-type dopant within HBL layers can influence the movement and transport of carriers through the layers. Such HBLs effectively isolate the MQW structures from each other while still allowing them to be individually addressed during operation of a corresponding stacked LED device. The HBLs also allow electrical operation of each MQW structure (e.g., a color of a respective emitter) to be adjusted, e.g., to improve display characteristics. The dopant concentration profiles discussed with respect to FIGs. 20A to 20J can be applied to any or all of the HBL layers ofAty Docket No.: 0120-952BW01 the example implementations described herein. That is, each HBL layer of a device (e.g., a stacked device) can have a unique dopant profile or all of the HBL layers may have a similar dopant profile.

[0136] FIG. 20A illustrates a dopant concentration profile 2000-a of an example HBL, where a dopant concentration varies linearly from a bottom of the HBL to a top of the HBL, the bottom being closer to a corresponding growth surface than the top. As shown by the dopant concentration profile 2000-a in FIG. 20A, the dopant concentration of the HBL increases as the layer is formed (e.g., as its thickness increases), such that the dopant concentration of the HBL is higher at the top of the layer with respect to the bottom of the layer.

[0137] FIG. 20B illustrates a dopant concentration profile 2000-b of an example HBL, where a dopant concentration varies linearly from a bottom of the HBL to a top of the HBL. As shown by the dopant concentration profile in FIG. 20B, the dopant concentration decreases as the HBL is formed, such that a dopant concentration of the HBL is higher at the bottom of the layer with respect to the top of the layer.

[0138] FIG. 20C illustrates a dopant concentration profile 2000-c within an example HBL, where a dopant concentration varies nonlinearly from a bottom of the HBL to a top of the HBL. As shown by the dopant concentration profile 2000-c in FIG. 20C, the dopant concentration of the HBL increases as the HBL is formed, such that the dopant concentration rises sharply at the bottom of the layer with respect to the top of the layer. In some implementations, such as the example of FIG. 20C, the dopant concentration profile 2000-c (e.g., of an HBL) varies parabolically from the bottom to the top of the layer.

[0139] FIG. 20D illustrates a dopant concentration profile 2000-d of an example HBL, where a dopant concentration varies nonlinearly from a bottom of the HBL to a top of the HBL. As shown by the dopant concentration profile 2000-d in FIG. 20D, a dopant concentration of the HBL increases as the layer is formed, such that the dopant concentration rises sharply at the top of the layer with respect to the bottom of the layer. In some implementations, such as the example of FIG. 20D, the dopant concentration profile 2000-d (e.g., of an HBL) varies parabolically from the bottom to the top of the layer.

[0140] FIG. 20E illustrates a dopant concentration profile 2000-e of an example HBL, where a dopant concentration varies nonlinearly from a bottom of the HBL to a top of the HBL. As shown by the dopant concentration profile 2000-e in FIG. 20E, the dopant concentration of the HBL decreases as the layer is formed, such that the dopant concentration decreases sharply at the top of the layer with respect to the bottom of the layer. In someAty Docket No.: 0120-952BW01 implementations, such as the example of FIG. 20E, the dopant concentration profile 2000-e (e.g., of an HBL) varies parabolically from the bottom to the top of the layer.

[0141] FIG. 20F illustrates a dopant concentration profile of an example HBL, where a dopant concentration varies nonlinearly from a bottom of the HBL to the top of the HBL. As shown by the dopant concentration profile 2000-f in FIG. 20F, As shown by the dopant concentration profile 2000-f in FIG. 20F, the dopant concentration of the HBL decreases as the layer is formed, such that the dopant concentration decreases sharply at the bottom of the layer with respect to the top of the layer. In some implementations, such as the example of FIG. 20F, the dopant concentration profile 2000-f (e.g., of an HBL) varies parabolically from the bottom to the top of the layer.

[0142] FIG. 20G illustrates a dopant concentration profile 2000-g of an example HBL, where a dopant concentration varies in a stepwise manner from a bottom of the HBL to a top of the HBL. As shown by the dopant concentration profile 2000-g in FIG. 20G, the dopant concentration of the HBL increases as the layer is formed, such that the dopant concentration is higher at the top of the layer with respect to the bottom of the layer. The dopant concentration transition, as illustrated by the dopant concentration profile 2000-g, occurs approximately at a center of the layer, e.g., a center between the bottom of the layer and the top of the layer. In some implementations, doping of the HBL can be engineered such that the dopant concentration transition occurs close to the bottom of the layer, or close to the top of the layer.

[0143] FIG. 20H illustrates a dopant concentration profile 2000-h of an example HBL, where a dopant concentration varies in a stepwise manner from a bottom of the HBL a top of the HBL. As shown by the dopant concentration profile 2000-h in FIG. 20H, the dopant concentration of the HBL decreases as the layer is formed, such that the dopant concentration is higher at the bottom of the layer with respect to the top of the layer. The dopant concentration transition, as illustrated by the dopant concentration profile 2000-h, occurs approximately at a center of the layer, e.g., a center between the bottom of the layer and the top of the layer. In some implementations, doping of the HBL can be engineered such that the dopant concentration transition occurs close to the bottom of the layer, or close to the top of the layer.

[0144] FIG. 201 illustrates a dopant concentration profile 2000-i of an example HBL, where a dopant concentration varies from a bottom of the HBL toto a top of the HBL. As shown by the dopant concentration profile 2000-i in FIG. 201, the dopant concentration, in at least a portion of the HBL, increases as the HBL is formed. For instance, as shown in FIG.Aty Docket No.: 0120-952BW01201, the dopant concentration profile 2000-1 has a peak). The dopant concentration peak, in this example, occurs approximately at a center of the layer. In some implementations, doping of the HBL can be engineered such that the dopant concentration peak can occur close to the bottom of the layer or close to the top of the layer.

[0145] FIG. 20J illustrates a dopant concentration profile 2000-j of an example HBL, where a dopant concentration varies from a bottom of the HBL toa top of the HBL. As shown by the dopant concentration profile 2000-1 in FIG. 201, the dopant concentration, in at least a portion of the HBL, decreases as the HBL is formed. For instance, as shown in FIG. 20J, the dopant concentration profiled 2000-J has an inverted peak (e.g., as compared to FIG. 201). A smallest value of the dopant concentration, in this example, occurs approximately at a center of the layer. In some implementations, doping of the HBL can be engineered such that the smallest dopant concentration value can occur close to the bottom of the layer or close to the top of the layer.

[0146] In a general aspect, a micro LED display includes a doped semiconductor member having a red microLED disposed on the doped semiconductor member. The red microLED has a top surface opposite the doped semiconductor member. The display also includes a green microLED disposed on the doped semiconductor member. The green microLED having a top surface opposite the doped semiconductor member. The display also includes a blue microLED formed on the doped semiconductor member and having a third top surface opposite the doped semiconductor member. The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are substantially coplanar.

[0147] Implementations can include one or more of the following features or aspects, alone or in combination. For example, the red microLED, the green microLED, and the blue microLED can include epitaxial layers disposed on the doped semiconductor member.

[0148] The red microLED, the green microLED and the blue microLED can be monolithically formed on the semiconductor member.

[0149] The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are p-doped.

[0150] The display can include a first p-contact disposed on the top surface of the red microLED, a second p-contact disposed on the top surface of the green microLED, and a third p- contact disposed on the top surface of the blue microLED. The first p-contact, the second p-contact, and the third p-contact can be substantially coplanar.

[0151] The display can include a display driver. The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED can be electrically coupled to the display driver.Aty Docket No.: 0120-952BW01

[0152] The red microLED, the green microLED, and blue microLED can be respective gallium nitride (GaN) based microLEDs.

[0153] The red microLED, the green microLED, and blue microLED can be included in a pixel of the microLED display.

[0154] The red microLED, the green microLED, and the blue microLED, respectively, can have a lateral dimension less than 10 micrometers (pm).

[0155] Respective heights of the top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED can have a total height variation less than 100 nanometers.

[0156] At least two microLEDs of the red microLED, the green microLED, and the blue microLED can have respective sidewalls including a first p-doped material and a second p-doped material overlying the respective sidewalls and configured to inject holes laterally into respective active regions of the at least two microLEDs through the respective sidewalls.

[0157] The top surfaces of the red microLED, the green microLED, and the blue microLED can be, respectively, top surfaces of the first p-doped material, the second p-doped material, and the third p-doped material.

[0158] The red microLED, the green microLED, and the blue microLED can have respective n-type regions that are electrically coupled to the doped semiconductor member, and configured such that, during electrical operation, electrons are injected from the doped semiconductor member into the red microLED, the green microLED, and the blue microLED.

[0159] In another general aspect, a method includes growing, on a substrate: a red microLED having a top surface opposite the substrate, a green microLED having a top surface opposite the substrate, and a blue microLED having a third top surface opposite the substrate. The top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are substantially coplanar.

[0160] In another general aspect, a display includes a substrate, and a first LED mesa including a first active region configured to emit light of a first wavelength. The first LED mesa is disposed on a first lateral region of the substrate. The display also includes a second LED mesa including a second active region configured to emit light of a second wavelength different than the first wavelength. The second LED mesa is disposed on a second lateral region of the substrate distinct from the first lateral region. The display further includes a first p-doped region contacting a sidewall of the first LED mesa, and a second p-doped region contacting a sidewall of the second LED mesa. The first p-doped region and the second p-doped region have respective top surfaces opposite the substrate that are substantially coplanar.

[0161] In another general aspect, a device includes a substrate; and a first semiconductor stack disposed on the substrate and having a first active region. The first semiconductor stack has aAty Docket No.: 0120-952BW01 first lateral boundary that is non-parallel with the substrate. The device further includes a second semiconductor stack disposed on a portion of the first semiconductor stack and having a second active region. A first p-doped semiconductor material contacts the first lateral boundary and is configured to laterally inject holes into the first active region.

[0162] Implementations can include one or more of the following features or aspects, alone or in combination. For example, the second semiconductor stack can have a second lateral boundary that is non-parallel with the substrate. The display can include a second p-doped semiconductor material contacting the second lateral boundary and configured to laterally inject holes into the second active region.

[0163] The device can include a third semiconductor stack formed on a portion of the second semiconductor stack and having a third active region. The third semiconductor stack can have a third lateral boundary that is non-parallel with the substrate, and a third p-doped semiconductor material contacting the third lateral boundary and configured to laterally inject holes into the third active region.

[0164] The device can include a first n-contact electrically coupled to the first semiconductor stack and the second semiconductor stack, a first p-contact electrically coupled to the first p-doped semiconductor material, and a second p-contact electrically coupled to the second p-doped semiconductor material.

[0165] The first semiconductor stack and the second semiconductor stack can be entirely n- doped.

[0166] The first semiconductor stack and the second semiconductor stack can be separated by an n-doped spacing semiconductor region.

[0167] The first semiconductor stack can include a first planar boundary. The first p-doped semiconductor material can contact the first planar boundary.

[0168] The first p-doped semiconductor material can be epitaxially registered with the first semiconductor stack.

[0169] The device can include a third semiconductor stack disposed on the substrate and having a third active region. The third semiconductor stack can be laterally separated from the first semiconductor stack and the second semiconductor stack.

[0170] The first semiconductor stack can be epitaxially registered with the substrate, and the second semiconductor stack can be epitaxially registered with the first semiconductor stack.

[0171] The device can include a template disposed on the substrate, The first semiconductor stack can be disposed on the template. The template can be n-doped. The display can include an n- contact disposed on the template.

[0172] The first active region and the second active region can emit light at different wavelengths.Aty Docket No.: 0120-952BW01

[0173] The first active region and the second active region can be included in respective subpixels of a pixel of a display.

[0174] In another general aspect, a method of forming a display includes growing, on a planar surface of a substrate, a first semiconductor stack having a first active region. The method further includes growing, on the first semiconductor stack, a second semiconductor stack having a second active region. The method also includes forming, in the first semiconductor stack, a first lateral boundary that is non-parallel with the planar surface. The method still further includes growing a first p-doped semiconductor material contacting the first lateral boundary.

[0175] Implementations can include one or more of the following features or aspects, alone or in combination. For example, the first p-doped semiconductor material can be configured to laterally inject holes into the first active region.

[0176] Forming the first lateral boundary can include etching the first semiconductor stack to define a first etched sidewall that is non-parallel with the planar surface.

[0177] The first p-doped semiconductor material can include re-growing the first p-doped semiconductor material on the first etched sidewall.

[0178] The method can include etching the second semiconductor stack to define a second etched sidewall that is non-parallel with the planar surface. The method can include re-growing a p- doped layer contacting the first etched sidewall and the second etched sidewall. The method can include etching the p-doped layer to define the first p-doped semiconductor material, and a second p- doped semiconductor material contacting the second etched sidewall.

[0179] The first active region and the second active region can be parallel with the planar surface.

[0180] In another general aspect, a method of forming a device includes, in a single growth operation, successively growing, on a substrate, a first semiconductor stack having a first active region, a second semiconductor stack having a second active region, and a third semiconductor stack having a third active region. The method further includes etching the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack to respectively define a first etched sidewall, a second etched sidewall, and a third etched sidewall. The method also includes regrowing a p-doped material that contacts the first etched sidewall, the second etched sidewall, and the third etched sidewall. The method further includes etching the p-doped material to define a first p-doped region, a second p-doped region, and a third p-doped region that, respectively, contact the first etched sidewall, the second etched sidewall, and the third etched sidewall.

[0181] Implementations can include one or more of the following features or aspects, alone or in combination. For example, the first active region, the active region second, and the third active region can emit light of different colors.Aty Docket No.: 0120-952BW01

[0182] The first p-doped region, the second p-doped region, and the third p-doped region are configured, under electrical operation, to promote hole injection, respectively, into the first active region, the second active region, and the third active region.

[0183] The first LED, the second LED, and the third LED are respective subpixels of a pixel of a display.

[0184] The method can include bonding the device to a driver that electrically contacts the first active region, the second active region, and the third active region, and is configured to control electrical operation of the first LED, the second LED, and the third LED.

[0185] The p-doped material can be epitaxially registered with the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack.

[0186] A surface of the p-doped material can be substantially planar after growth.

[0187] Respective surfaces of the first p-doped region, the second p-doped region and the third p-doped region can be substantially coplanar.

[0188] The first spacer region and the second spacer region can be n-doped.

[0189] The first active region, the second active region, and the third active region can be n- doped.

[0190] The single growth operation can exclude growth of p-doped material.

[0191] It will be understood, for purposes of this disclosure, that when an element, such as a layer, a region, or a substrate, is referred to as being on, disposed on, disposed in, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly disposed on, directly disposed in, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, direct in, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0192] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to, vertically adjacent to, or horizontally adjacent to.Aty Docket No.: 0120-952BW01

[0193] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques, such as epitaxial growth processes, associated with semiconductor substrates and materials including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or so forth.

[0194] While certain features of various example implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

Claims

Aty Docket No.: 0120-952BW01WHAT IS CLAIMED IS:

1. A microLED display comprising: a doped semiconductor member; a red microLED disposed on the doped semiconductor member, the red microLED having a top surface opposite the doped semiconductor member; a green microLED disposed on the doped semiconductor member, the green microLED having a top surface opposite the doped semiconductor member; and a blue microLED formed on the doped semiconductor member and having a third top surface opposite the doped semiconductor member; the top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED being coplanar.

2. The microLED display of claim 1, wherein the red microLED, the green microLED, and the blue microLED include epitaxial layers disposed on the doped semiconductor member.

3. The microLED display of claims 1 and 2, wherein the red microLED, the green microLED and the blue microLED are monolithically formed on the semiconductor member.

4. The microLED display of any of the preceding claims, wherein the top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED are p-doped.

5. The microLED display of claim 4, further comprising: a first p-contact disposed on the top surface of the red microLED; a second p-contact disposed on the top surface of the green microLED; and a third p-contact disposed on the top surface of the blue microLED, the first p-contact, the second p-contact, and the third p-contact being coplanar.

6. The microLED display of any of the preceding claims, further comprising a display driver,Aty Docket No.: 0120-952BW01 the top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED being electrically coupled to the display driver.

7. The microLED display of any of the preceding claims, wherein the red microLED, the green microLED, and the blue microLED are respective gallium nitride (GaN) based microLEDs.

8. The microLED display of any of the preceding claims, wherein the red microLED, the green microLED, and the blue microLED are included in a pixel of the microLED display.

9. The microLED display of any of the preceding claims, wherein the red microLED, the green microLED, and the blue microLED, respectively, have a lateral dimension less than 10 micrometers (pm).

10. The microLED display of any of the preceding claims, wherein respective heights of the top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED have a total height variation less than 100 nanometers.

11. The microLED display of any of the preceding claims, wherein at least two microLEDs of the red microLED, the green microLED, and the blue microLED have respective sidewalls including a first p-doped material and a second p-doped material overlying the respective sidewalls and configured to inject holes laterally into respective active regions of the at least two microLEDs through the respective sidewalls.

12. The microLED display of claim 11, wherein the top surfaces of the red microLED, the green microLED, and the blue microLED are, respectively, top surfaces of the first p-doped material, the second p-doped material, and the third p-doped material.

13. The microLED display of any of the preceding claims, wherein the red microLED, the green microLED, and the blue microLED have respective n-type regions that are electrically coupled to the doped semiconductor member, and configured such that,Aty Docket No.: 0120-952BW01 during electrical operation, electrons are injected from the doped semiconductor member into the red microLED, the green microLED, and the blue microLED.

14. A method of forming a microLED display, the method comprising: growing, on a doped semiconductor member: a red microLED having a top surface opposite the substrate; a green microLED having a top surface opposite the substrate; and a blue microLED having a third top surface opposite the substrate, the top surface of the red microLED, the top surface of the green microLED and the top surface of the blue microLED being coplanar.

15. A display comprising: a substrate; a first LED mesa including a first active region configured to emit light of a first wavelength, the first LED mesa being disposed on a first lateral region of the substrate; a second LED mesa including a second active region configured to emit light of a second wavelength different than the first wavelength, the second LED mesa being disposed on a second lateral region of the substrate distinct from the first lateral region; a first p-doped region contacting a sidewall of the first LED mesa; and a second p-doped region contacting a sidewall of the second LED mesa, the first p-doped region and the second p-doped region having respective top surfaces opposite the substrate that are coplanar.

16. A device comprising: a substrate; a first semiconductor stack disposed on the substrate and having a first active region, the first semiconductor stack having a first lateral boundary that is non-parallel with the substrate; a second semiconductor stack disposed on a portion of the first semiconductor stack and having a second active region; and a first p-doped semiconductor material contacting the first lateral boundary and configured to laterally inject holes into the first active region.Aty Docket No.: 0120-952BW0117. The device of claim 16, wherein the second semiconductor stack has a second lateral boundary that is non-parallel with the substrate, the display further comprising a second p-doped semiconductor material contacting the second lateral boundary and configured to laterally inject holes into the second active region.

18. The device of claim 17, further comprising: a third semiconductor stack formed on a portion of the second semiconductor stack and having a third active region, the third semiconductor stack having a third lateral boundary that is non-parallel with the substrate; and a third p-doped semiconductor material contacting the third lateral boundary and configured to laterally inject holes into the third active region.

19. The device of claim 17 or claim 18, further comprising: a first n-contact electrically coupled to the first semiconductor stack and the second semiconductor stack; a first p-contact electrically coupled to the first p-doped semiconductor material; and a second p-contact electrically coupled to the second p-doped semiconductor material.

20. The device of any of claims 16 to 19, wherein the first semiconductor stack and the second semiconductor stack are entirely n-doped.

21. The device of any of claims 16 to 20, wherein the first semiconductor stack and the second semiconductor stack are separated by an n-doped spacing semiconductor region.

22. The device of any of claims 16 to 21, wherein the first semiconductor stack includes a first planar boundary, and the first p-doped semiconductor material contacts the first planar boundary.

23. The device of any of claims 16 to 22, wherein the first p-doped semiconductor material is epitaxially registered with the first semiconductor stack.Aty Docket No.: 0120-952BW0124. The device of any of claims 16 to 23, further comprising a third semiconductor stack disposed on the substrate and having a third active region, the third semiconductor stack being laterally separated from the first semiconductor stack and the second semiconductor stack.

25. The device of any of claims 16 to 24, where the first semiconductor stack is epitaxially registered with the substrate and the second semiconductor stack is epitaxially registered with the first semiconductor stack.

26. The device of any of claims 16 to 25, further comprising a template disposed on the substrate, the first semiconductor stack being disposed on the template.

27. The device of claim 26, wherein the template is n-doped, the display further comprising an n-contact disposed on the template.

28. The device of any of claims 16 to 27, wherein the first active region and the second active region emit light at different wavelengths.

29. The device of any of claims 16 to 28, wherein the first active region and the second active region are included in respective subpixels of a pixel of a display.

30. A method of forming a display comprising: growing, on a planar surface of a substrate, a first semiconductor stack having a first active region; growing, on the first semiconductor stack, a second semiconductor stack having a second active region; forming, in the first semiconductor stack, a first lateral boundary that is non-parallel with the planar surface; and growing a first p-doped semiconductor material contacting the first lateral boundary.

31. The method of claim 30, wherein the first p-doped semiconductor material is configured to laterally inject holes into the first active region.Aty Docket No.: 0120-952BW0132. The method of any of claims 30 and 31, wherein forming the first lateral boundary includes etching the first semiconductor stack to define a first etched sidewall that is non-parallel with the planar surface.

33. The method of claim 32, wherein growing the first p-doped semiconductor material includes re-growing the first p-doped semiconductor material on the first etched sidewall.

34. The method of any of claims 32 and 33, further comprising: etching the second semiconductor stack to define a second etched sidewall that is nonparallel with the planar surface; re-growing a p-doped layer contacting the first etched sidewall and the second etched sidewall; and etching the p-doped layer to define the first p-doped semiconductor material, and a second p-doped semiconductor material contacting the second etched sidewall.

35. The method of any of claims 30 to 34, wherein the first active region and the second active region are parallel with the planar surface.

36. A method of forming a device, the method comprising: in a single growth operation, successively growing, on a substrate: a first semiconductor stack having a first active region; a second semiconductor stack having a second active region; and a third semiconductor stack having a third active region; etching the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack to respectively define a first etched sidewall, a second etched sidewall, and a third etched sidewall; regrowing a p-doped material that contacts the first etched sidewall, the second etched sidewall, and the third etched sidewall; and etching the p-doped material to define a first p-doped region, a second p-doped region, and a third p-doped region that, respectively, contact the first etched sidewall, the second etched sidewall, and the third etched sidewall.Aty Docket No.: 0120-952BW0137. The method of claim 36, wherein the first active region, the active region second, and the third active region emit light of different colors.

38. The method of any of claims 36 and 37, wherein the first p-doped region, the second p-doped region, and the third p-doped region are configured, under electrical operation, to promote hole injection, respectively, into the first active region, the second active region, and the third active region.

39. The method of any of claims 36 to 38, wherein the first LED, the second LED, and the third LED are respective subpixels of a pixel of a display.

40. The method of any of claims 36 to 39, further comprising bonding the device to a driver that electrically contacts the first active region, the second active region, and the third active region, and is configured to control electrical operation of the first LED, the second LED, and the third LED.

41. The method of any of claims 36 to 40, wherein the p-doped material is epitaxially registered with the first semiconductor stack, the second semiconductor stack, and the third semiconductor stack.

42. The method of any of claims 36 to 41, wherein a surface of the p-doped material is planar after growth.

43. The method of any of claims 36 to 42, wherein respective surfaces of the first p-doped region, the second p-doped region and the third p-doped region are coplanar.

44. The method of any of claims 36 to 43, further comprising: growing a first spacing region between the first semiconductor stack and the second semiconductor stack, the first spacing region being n-doped; and growing a second spacing region between the second semiconductor stack and the third semiconductor stack, the second spacing region being n-doped.

45. The method of any of claims 36 to 44, wherein the first active region, the second active region, and the third active region are n-doped.Aty Docket No.: 0120-952BW0146. The method of any of claims 36 to 45, wherein the single growth operation excludes growth of p-doped material.

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