Data block state acquisition method and apparatus, and electronic device

Abstract

The present disclosure relates to the technical field of data processing. Provided are a data block state acquisition method and apparatus, and an electronic device. The method comprises: in response to a first read request encountering read misses in a first-level private cache and a second-level private cache, acquiring, by means of a shared cache, a first data block returned for the first read request; and acquiring a first count value of the first data block, and on the basis of the first count value, acquiring a first data block state of the first data block.

Description

State acquisition method, device and electronic equipment of data block

[0001] Cross-reference to related applications

[0002] The present disclosure is based on and claims priority from Chinese Patent Application No. 202411096640.7, filed on August 12, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of data processing, and in particular to a state acquisition method, device and electronic equipment of data block. BACKGROUND

[0004] With the development of technology, the number of processor cores integrated on a chip is increasing. In order to enable a multi-level cache storage system on the chip to provide data for multiple processor cores at the same time, the multi-level cache system needs to be maintained for consistency.

[0005] However, maintaining the consistency of the storage information of the private cache and the shared cache and other related areas on multiple processor cores is a large amount of work, which may lead to waste of part of the storage resources in the multi-level cache system. SUMMARY

[0006] The present disclosure aims to at least partially solve one of the technical problems in the related art.

[0007] To this end, a first aspect of the present disclosure provides a state acquisition method of data block.

[0008] A second aspect of the present disclosure provides a state acquisition device of data block.

[0009] A third aspect of the present disclosure provides a data storage device of a multi-level cache system.

[0010] A fourth aspect of the present disclosure provides an electronic device.

[0011] A fifth aspect of the present disclosure provides a computer-readable storage medium.

[0012] The first aspect of the present disclosure provides a state acquisition method of data block, the method comprising: in response to a first read request reading invalid in a first private cache and a second private cache, acquiring a first data block returned by the first read request through a shared cache; acquiring a first count value of the first data block, and acquiring a first data block state of the first data block according to the first count value.

[0013] The second aspect of the present disclosure provides a state obtaining device of a data block, which comprises: a first obtaining module, configured to obtain a first data block returned by a first read request through a shared cache in response to a read miss of the first read request in a first private cache and a second private cache; and a second obtaining module, configured to obtain a first count value of the first data block, and obtain a first data block state of the first data block according to the first count value.

[0014] The third aspect of the present disclosure provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the state obtaining method of the data block according to the first aspect when executing the program.

[0015] To achieve the above object, the fourth aspect of the present disclosure provides a computer readable storage medium, which stores a computer program, and the program is executable on a processor to implement the state obtaining method of the data block according to the first aspect.

[0016] The state obtaining method, device and electronic device of the data block according to the embodiments of the present disclosure obtain a first data block of a first read request through a shared cache in response to a read miss of the first read request in a first private cache and a second private cache, and obtain a first data block state of the first data block according to a first count value of the first data block. In the present disclosure, the first data block of the first read request is obtained through the shared cache in response to a read miss of the first read request in the first private cache and the second private cache, and the first data block state of the first data block is determined according to the first count value of the first data block, which reduces the workload of consistency maintenance of the multi-level cache system, thereby reducing the waste degree of cache capacity and improving the hit rate of memory access request in the multi-level cache.

[0017] It should be understood that the description of the present disclosure is not intended to identify key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above-mentioned and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0019] FIG. 1 is a flowchart of a state obtaining method of a data block according to an embodiment of the present disclosure;

[0020] FIG. 2 is a flowchart of a state obtaining method of a data block according to another embodiment of the present disclosure;

[0021] FIG. 3 is a flowchart of a state obtaining method of a data block according to another embodiment of the present disclosure;

[0022] FIG. 4 is a structural schematic diagram of a state acquisition device of a data block according to an embodiment of the present disclosure;

[0023] FIG. 5 is a structural schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, in which the same or similar components have the same or similar designations and functions throughout. The embodiments described below are exemplary and are intended to explain the present disclosure, and are not to be understood as limiting the present disclosure.

[0025] FIG. 1 is a flowchart of a state acquisition method of a data block according to an embodiment of the present disclosure. As shown in FIG. 1, the method comprises:

[0026] S101, in response to reading invalidation in the first private cache and the second private cache in response to a first read request, acquiring first data blocks returned by the shared cache in response to the first read request.

[0027] In an embodiment of the present disclosure, the multi-level cache system can include a plurality of processor cores, wherein a plurality of private caches can be provided on each processor core.

[0028] As an example, in the multi-level cache storage system shown in FIG. 2, a first private cache, a second private cache and a shared cache shown in FIG. 2 are provided, wherein the first private cache and the second private cache shown in FIG. 2 are two private caches on the processor core 1 shown in FIG. 2.

[0029] It should be noted that the scenario shown in FIG. 2 also includes a routing node, and data interaction between the first private cache, the second private cache on each processor core and the shared cache shown in FIG. 2 can be achieved through the routing node shown in FIG. 2, thereby constructing the multi-level cache storage system shown in FIG. 2.

[0030] In this example, the second private cache and the first private cache can be inclusive, non-inclusive or exclusive.

[0031] Inclusive can be understood as that the data blocks in the first private cache all exist in the second private cache, non-inclusive can be understood as that the data blocks in the first private cache can exist or can not exist in the second private cache, and exclusive can be understood as that the data blocks in the first private cache do not exist in the second private cache.

[0032] It should be noted that the first private cache and the second private cache on any processor core in the multi-level cache system proposed in the embodiments of the present disclosure do not maintain a containing relationship.

[0033] It can be understood that the data block in the first private cache on any processor core in the multi-level cache system proposed in the embodiments of the present disclosure may or may not exist in the second private cache on the processor core.

[0034] In the embodiments of the present disclosure, the access request for reading the data block in the multi-level cache system can be marked as a first read request of the multi-level cache system.

[0035] Optionally, the multi-level cache system can be constructed based on the first private cache, the second private cache and the shared cache, the first read request can access the first private cache, and the first read request may not hit in the first private cache, and thus it can be determined that the first read request is read invalid in the first private cache.

[0036] In this scenario, the first private cache can send an access request corresponding to the first read request to the second private cache, wherein the access request may not hit in the second private cache, and thus it can be determined that the first read request is read invalid in the second private cache.

[0037] It can be understood that when the first read request does not hit in the first private cache and the second private cache, it can be determined that the first read request is read invalid in the first private cache and the second private cache.

[0038] In the embodiments of the present disclosure, when the first read request is read invalid in the first private cache and the second private cache, the shared cache in the multi-level cache system can be accessed and / or the private cache on other processor cores can be accessed through the shared cache and / or the memory can be accessed through the shared cache, so as to obtain the access data block of the first read request in the multi-level cache system.

[0039] The data block can be marked as a first data block accessed by the first read request in the multi-level cache system.

[0040] S102, obtaining a first count value of the first data block, and obtaining a first data block state of the first data block according to the first count value.

[0041] In the embodiments of the present disclosure, the first data block has a corresponding storage state in the multi-level cache system, wherein the storage state of the first data block in the multi-level cache system can be marked as the first data block state of the first data block.

[0042] Optionally, the first data block has a count value, which can be marked as a first count value, wherein the first count value can be understood as a record value of the number of times the first data block is modified.

[0043] In this scenario, a preset count value analysis strategy can be acquired, and the first count value is analyzed based on the strategy, so as to determine the first data block state of the first data block according to the analysis result.

[0044] It should be noted that the first data block state can be a shared state or an exclusive state.

[0045] In the scenario where the first data block state of the first data block is in the shared state, when the read request on the other processor core is not hit, the read request on the processor core that is not hit can be effectively responded through the first data block, so as to achieve the purpose of reducing the workload of consistency maintenance of the multi-level cache system to a certain extent.

[0046] In addition, when the first data block state of the first data block is in the exclusive state, the processing core to which the first data block belongs can perform a write operation on the first data block, and when the processing core receives a write request of the first data block, the write request can be directly hit, so as to achieve the purpose of reducing the workload of consistency maintenance of the multi-level cache system to a certain extent.

[0047] The state acquisition method of the data block provided in the disclosure, when the first read request is read invalid in the first private cache and the second private cache, the first data block of the first read request is acquired through the shared cache, and the first data block state of the first data block is acquired according to the first count value of the first data block. In the disclosure, when the first read request is read invalid in the first private cache and the second private cache, the first data block is acquired through the shared cache, and the first data block state of the first data block is determined according to the first count value of the first data block, which reduces the workload of consistency maintenance of the multi-level cache system, thereby reducing the waste degree of cache capacity and improving the hit rate of memory request in the multi-level cache.

[0048] In the above embodiment, regarding the acquisition of the first data block state of the first data block according to the first count value, it can be further understood in combination with FIG. 3, which is a flowchart of a state acquisition method of a data block according to another embodiment of the disclosure. As shown in FIG. 3, the method comprises:

[0049] S301, in response to the read invalid of the first read request in the first private cache and the second private cache, the first data block returned by the first read request is acquired through the shared cache.

[0050] Optionally, in response to the read invalid of the first read request in the first private cache and the second private cache, a second read request is generated and sent to the shared cache.

[0051] In the embodiments of the present disclosure, a preset invalidation determination strategy can be acquired, and it is determined whether the first read request is read invalid in the first private cache according to the access state of the first read request in the first private cache.

[0052] In response to the first read request not being hit in the first private cache, it is determined that the first read request is read invalid in the first private cache.

[0053] It can be understood that the invalidation determination strategy of determining whether the first read request is hit in the first private cache as whether the first read request is read invalid in the first private cache, wherein when the first read request is not hit in the first private cache, it is determined that the first read request is read invalid in the first private cache.

[0054] Optionally, in response to the second data block existing in the first private cache and the second data block not being in the invalid state in the first private cache, it is determined that the first read request is hit in the first private cache.

[0055] It can be understood that when the second data block that the first read request wants to access exists and is valid in the first private cache, it is determined that the first read request can obtain the information of the second data block, and in this case, it is determined that the first read request is hit in the first private cache.

[0056] In the embodiments of the present disclosure, the data blocks in the multi-level cache system have multiple data block states, wherein the state of the data block in the multi-level cache system can be identified according to the identification information on the state bit of the data block.

[0057] As an example, the identification information on the state bit of the data block is set as one of an invalid state (INV) identification, a shared state (SHD) identification and an exclusive state (EXC) identification.

[0058] In this example, when the identification information on the state bit of the second data block is the INV identification information, it is determined that the second data block is in the invalid state in the first private cache.

[0059] When the identification information on the state bit of the second data block is the SHD identification information, it is determined that the second data block is in the shared state in the first private cache.

[0060] When the identification information on the state bit of the second data block is the EXC identification information, it is determined that the second data block is in the exclusive state in the first private cache.

[0061] It can be understood that when the second data block that the first read request wants to access in the level-1 private cache is in a state other than the invalid state in the level-1 private cache, it is determined that the first read request can obtain the information of the second data block, and in this case, it is determined that the first read request hits in the level-1 private cache.

[0062] In this case, the second data block can be taken as the first data block of the first read request.

[0063] It should be noted that in the case where the data block is in the shared state, the processor core directly hits when reading the block and write invalidation occurs when writing the block, and in the case where the data block is in the exclusive state, the processor directly hits when reading and writing the data block.

[0064] Therefore, it is determined that the first read request misses in the level-1 private cache in response to the second data block that the first read request accesses in the level-1 private cache not existing in the level-1 private cache or the second data block being in the invalid state in the level-1 private cache.

[0065] Among them, the data block that the first read request wants to access in the level-1 private cache can be marked as the second data block, and in this case, when the second data block does not exist in the level-1 private cache, it is determined that the first read request misses in the level-1 private cache.

[0066] And when the second data block of the first read request is in the invalid state in the level-1 private cache, it is determined that the first read request misses in the level-1 private cache.

[0067] In the embodiments of the present disclosure, when the first read request is read invalid in the level-1 private cache, a third read request corresponding to the first read request can be generated based on the access request generation method in the related art and sent to the level-2 private cache.

[0068] It can be understood that the third read request is an access request generated by the level-1 private cache to convey the access demand of the first read request to the level-2 private cache.

[0069] Optionally, in response to the third read request corresponding to the first read request missing in the level-2 private cache, it is determined that the first read request corresponding to the third read request is read invalid in the level-2 private cache.

[0070] Among them, in response to the third data block that the third read request accesses in the level-2 private cache not existing in the level-2 private cache, or the third data block not being in the exclusive state or not being in the shared state in the level-2 private cache, it is determined that the first read request corresponding to the third read request misses in the level-2 private cache.

[0071] In the embodiments of the present disclosure, the third read request can be marked as a third data block in the data block that the second read request wants to access in the second private cache. In this case, when the third data block does not exist in the second private cache, it can be determined that the third read request corresponding to the first read request is read invalid in the second private cache.

[0072] Correspondingly, the data block state of the third data block in the second private cache can be obtained. When the state of the third data block in the second private cache cannot support the access of the third read request, it can be determined that the third read request corresponding to the first read request is read invalid in the second private cache.

[0073] The state of the third data block in the second private cache that cannot support the access of the third read request can include other data block states in addition to the shared state and the exclusive state.

[0074] Optionally, in response to the third data block being in the shared state or the exclusive state in the second private cache, it is determined that the first read request corresponding to the third read request hits in the second private cache.

[0075] In this case, it can be determined that the third read request can read the required data block in the second private cache.

[0076] Further, it can be determined that the first read request corresponding to the third read request hits in the second private cache. In this case, the data block can be taken as the first data block of the first read request corresponding to the third read request.

[0077] Therefore, when the third data block is not in the exclusive state or the shared state in the second private cache, it can be determined that the data block cannot be read by other private caches, and the data block cannot be taken as the first data block of the first read request. Further, it can be determined that the first read request does not hit in the second private cache.

[0078] Optionally, the second data block corresponding to the second read request is obtained as the first data block corresponding to the first read request through the shared cache.

[0079] In the embodiments of the present disclosure, after the first read request is read invalid in the first private cache and the second private cache, the first data block of the first read request can be queried and obtained from the shared cache, the private cache on other processor cores, or the memory through the shared cache of the multi-level cache system.

[0080] It should be noted that in the embodiments of the present disclosure, before the first read request is read invalid in the first private cache and the second private cache, and the second read request is generated and sent to the shared cache, the detailed information of the first data block required by the first read request in the multi-level cache system can be determined by accessing the cache directory of the multi-level cache system.

[0081] In the embodiments of the present disclosure, there is a cache directory in the multi-level cache system, wherein the cache directory and the shared cache of the multi-level cache system do not maintain a containing relationship.

[0082] Optionally, in response to the read invalidation in the first private cache and the second private cache, a fourth read request is generated and sent to the cache directory of the multi-level cache system, and in response to the fourth read request missing in the cache directory, a second read request is generated according to the fourth read request and sent to the shared cache.

[0083] In the embodiments of the present disclosure, the read request of the cache directory of the multi-level cache system generated after the read invalidation of the first private cache and the second private cache can be marked as a fourth read request, wherein the fourth read request can be sent to the cache directory of the multi-level cache system to obtain detailed information of the first data block.

[0084] In this scenario, the directory information accessed by the fourth read request in the cache directory can be marked as access target information of the fourth read request, wherein in response to the data block record state in the access target information indicating valid-dirty or valid-clean, it is determined that the fourth read request hits in the cache directory, and a write-back request is sent to the second private cache to which the corresponding data block of the data block record state belongs.

[0085] In the embodiments of the present disclosure, when the fourth read request corresponds to access target information in the cache directory indicating that the data block accessed by the first read request is in a valid-dirty or valid-clean state in the multi-level cache system, it can be understood that the access target information of the fourth read request exists in the cache directory, and thus it is known that the fourth read request hits in the cache directory.

[0086] In this scenario, when the data block record state in the access target information is valid-dirty or valid-clean, it can be determined that the data block can be used as the first data block returned to the first read request, and further, a write-back request can be sent to the second private cache to which the data block belongs to obtain the first data block of the first read request through the shared cache.

[0087] Correspondingly, in response to the access target information of the fourth read request not existing in the cache directory, or the fourth data block corresponding to the fourth read request being recorded as invalid in the cache directory, it is determined that the fourth read request misses in the cache directory.

[0088] It can be understood that when the access target information of the fourth read request does not exist in the cache directory, it can be determined that the fourth read request does not obtain the target information required by the fourth read request, and thus it can be determined that the fourth read request does not hit in the cache directory.

[0089] Correspondingly, when the corresponding operation data block of the fourth read request in the multi-level cache storage system is recorded as an invalid state in the corresponding directory record information in the cache directory, it can also be determined that the fourth read request does not hit in the cache directory, wherein the corresponding operation data block of the fourth read request in the multi-level cache storage system can be marked as the fourth data block.

[0090] Optionally, the first data block is obtained from the shared cache and / or memory, wherein in response to the existence of the unique backup data block of the first data block, the second data block state of the first data block is determined as the shared state.

[0091] In the embodiment of the disclosure, after the fourth read request does not hit in the cache directory, the corresponding data block can be obtained from the shared cache and / or memory of the multi-level cache storage system as the first data block.

[0092] Optionally, the first data block can be stored in the first-level private cache accessed by the first read request, and / or the first-level private cache and the corresponding second-level private cache, and in this case, the storage state of the first data block needs to be determined, wherein the storage state of the first data block in this case can be marked as the second data block state.

[0093] The related state of the first data block can be identified, wherein when it is identified that the first data block has a unique backup data block in the multi-level cache storage system, the second data block state of the first data block can be marked as the shared state.

[0094] Optionally, in response to the writing of the first data block, a second count value of the writing of the first data block is obtained, and when the second count value is greater than or equal to a preset count value threshold, the second data block state of the first data block is adjusted to the exclusive state.

[0095] It can be understood that when the first data block in the shared state subsequently has a write operation, the number of write operations can be recorded as a second count value, and the second data block state of the first data block is determined according to the second count value.

[0096] When the second count value is less than the preset count value threshold, it can be determined that the second data block state can remain in the shared state without adjustment.

[0097] Correspondingly, when the second count value is greater than or equal to a preset count value threshold, it can be determined that the second data block state needs to be adjusted, and then the second data block state of the first data block can be adjusted from the shared state to the exclusive state.

[0098] In S302, a first count value of the first data block is obtained, and a first data block state of the first data block is obtained according to the first count value.

[0099] In the embodiments of the present disclosure, the first count value of the first data block can be obtained by a counter, and a threshold value of the counter can be configured by software or set as a fixed value.

[0100] As an example, the counter can be further understood in combination with the following table.

[0101] In the above table, the storage location of the data block counted by the counter in the multi-level cache system can be determined by the data block address shown in the table, the number of times the corresponding data block is modified can be determined by the count value shown in the table, and whether the corresponding data block is in an effective state can be determined by the valid identification bit shown in the table.

[0102] Taking the first data block as an example, the data block located in the fourth row in the above table is set as the first data block, and it can be known from the above table that the first data block is in an effective state, the address information of the first data block in the multi-level cache system is “0x1f75da00”, and the number of times the first data block is currently modified is “0xf”. In this scenario, it can be determined that the first count value of the first data block is the corresponding value of “0xf”.

[0103] Optionally, in response to the first count value being greater than or equal to the preset count value threshold, the first data block state of the first data block is determined as the exclusive state.

[0104] For the first data block on any processor core, when the first count value of the first data block is greater than or equal to the count value threshold, it can be determined that the number of write request accesses of the first data block on the processor core within a set historical time range may be greater than the number of accesses of other types of requests, and in this scenario, the first data block state of the first data block can be determined as the exclusive state.

[0105] It should be noted that in the scenario where the first data block state is adjusted to the exclusive state, when the processor core receives the access instruction of the write request of the first data block again, the instruction can be directly hit on the processor core.

[0106] Optionally, in response to the first count value being less than the count value threshold, the first data block state of the first data block is determined as the shared state.

[0107] When the first count value is less than the count value threshold, the information in the first data block does not satisfy the state adjustment condition of the processor core exclusive data block, and the state of the first data block can be adjusted to the shared state.

[0108] It can be understood that when the first data block on the processor core receives a write request access less frequently within a set historical time range, the first data block state of the first data block can be marked as a shared state.

[0109] It should be noted that in the scenario where the first data block state is marked as a shared state, when a read request of the first data block received by another processor core is not hit, the first data block can be obtained from the processor core.

[0110] It should be noted that the first count value has a preset zero clearing strategy. In response to identifying that the first count value satisfies the preset zero clearing strategy, it is determined that the value of the first count value is 0, and in response to the value of the first count value being 0, it is determined that the state of the first data block is unchanged.

[0111] It can be understood that when the first count value satisfies the preset zero clearing strategy, the value of the first count value can be adjusted to 0. In this scenario, when the first data block state of the first data block is an exclusive state, the exclusive state remains unchanged, or when the first data block state of the first data block is a shared state, the exclusive state remains unchanged.

[0112] The state acquisition method of the data block provided by the present disclosure reduces the workload of maintaining consistency of the multi-level cache system when the first read request is read invalid in the first private cache and the second private cache, thereby reducing the waste degree of cache capacity and improving the hit rate of memory access requests in the multi-level cache.

[0113] Corresponding to the state acquisition method of the data block proposed in the above several embodiments, one embodiment of the present disclosure also proposes a state acquisition device of a data block. Since the state acquisition device of the data block proposed in the embodiment of the present disclosure corresponds to the state acquisition method of the data block proposed in the above several embodiments, the implementation manner of the above state acquisition method is also applicable to the state acquisition device of the data block proposed in the embodiment of the present disclosure, which will not be described in detail in the following embodiments.

[0114] FIG. 4 is a structural schematic diagram of a state acquisition device of a data block according to an embodiment of the present disclosure. As shown in FIG. 4, the state acquisition device 400 of the data block includes a first acquisition module 41 and a second acquisition module 42, wherein:

[0115] The first obtaining module 41 is configured to obtain, in response to a read miss of a first read request in a first private cache and a second private cache, a first data block returned by the shared cache in response to the first read request.

[0116] The second obtaining module 42 is configured to obtain a first count value of the first data block, and obtain a first data block state of the first data block according to the first count value.

[0117] In the embodiments of the present disclosure, the second obtaining module 42 is further configured to: in response to the first count value being greater than or equal to a preset count value threshold, determine that the first data block state of the first data block is an exclusive state; and in response to the first count value being less than the count value threshold, determine that the first data block state of the first data block is a shared state.

[0118] In the embodiments of the present disclosure, the second obtaining module 42 is further configured to: in response to identifying that the first count value satisfies a preset zero-clearing policy, determine that the value of the first count value is 0.

[0119] In the embodiments of the present disclosure, the second obtaining module 42 is further configured to: in response to the value of the first count value being 0, determine that the state of the first data block is unchanged.

[0120] In the embodiments of the present disclosure, the first obtaining module 41 is further configured to: in response to a read miss of a first read request in a first private cache and a second private cache, generate a second read request and send the second read request to the shared cache; and obtain, as a first data block corresponding to the first read request, a second data block corresponding to the second read request from the shared cache.

[0121] In the embodiments of the present disclosure, the first obtaining module 41 is further configured to: in response to a miss of the first read request in the first private cache, determine that the first read request is a read miss in the first private cache; and in response to a miss of a third read request corresponding to the first read request in the second private cache, determine that the first read request corresponding to the third read request is a read miss in the second private cache.

[0122] In the embodiments of the present disclosure, the first obtaining module 41 is further configured to: in response to a second data block accessed by the first read request in the first private cache not existing in the first private cache, or the second data block being in an invalid state in the first private cache, determine that the first read request is a miss in the first private cache.

[0123] In the embodiments of the present disclosure, the first obtaining module 41 is further configured to: in response to a third data block accessed by the third read request in the second private cache not existing in the second private cache, or the third data block not being in an exclusive state or a shared state in the second private cache, determine that the first read request corresponding to the third read request is a miss in the second private cache.

[0124] In the embodiment of the present disclosure, the first obtaining module 41 is further configured to: in response to the first read request missing in the first private cache and the second private cache, generate a fourth read request and send the fourth read request to a cache directory of the multi-level cache system. In response to the fourth read request missing in the cache directory, generate a second read request according to the fourth read request and send the second read request to the shared cache.

[0125] In the embodiment of the present disclosure, the first obtaining module 41 is further configured to: in response to the second data block existing in the first private cache and the second data block not being in an invalid state in the first private cache, determine that the first read request hits in the first private cache.

[0126] In the embodiment of the present disclosure, the first obtaining module 41 is further configured to: in response to the third data block being in a shared state or an exclusive state in the second private cache, determine that the first read request corresponding to the third read request hits in the second private cache.

[0127] In the embodiment of the present disclosure, the first obtaining module 41 is further configured to: in response to the access target information of the fourth read request not existing in the cache directory or the fourth data block corresponding to the fourth read request being recorded as an invalid state in the cache directory, determine that the fourth read request misses in the cache directory.

[0128] In the embodiment of the present disclosure, the first obtaining module 41 is further configured to: obtain the first data block from the shared cache and / or the memory; in response to the first data block existing a unique backup data block, determine that the second data block state of the first data block is a shared state; in response to the first data block being written, obtain a second count value of the first data block being written, and when the second count value is greater than or equal to a preset count value threshold, adjust the second data block state of the first data block to an exclusive state.

[0129] In the embodiment of the present disclosure, the first obtaining module 41 is further configured to: in response to the data block record state in the access target information of the fourth read request in the cache directory being valid-dirty or valid-clean, determine that the fourth read request hits in the cache directory, and send a write-back request to the second private cache to which the data block corresponding to the data block record state belongs.

[0130] In the embodiment of the present disclosure, the second private cache and the first private cache do not maintain a containing relationship.

[0131] The state acquisition device of the data block provided in the present disclosure, when the first read request is read invalid in the first private cache and the second private cache, acquires the first data block of the first read request through the shared cache, and acquires the first data block state of the first data block according to the first count value of the first data block. In the present disclosure, when the first read request is read invalid in the first private cache and the second private cache, the first data block is acquired through the shared cache, and the first data block state of the first data block is determined according to the first count value of the first data block, thereby reducing the workload of consistency maintenance of the multi-level cache system, reducing the waste degree of cache capacity, and improving the hit rate of memory access requests in the multi-level cache.

[0132] To implement the above-mentioned embodiments, the present disclosure further provides an electronic device 500, as shown in FIG. 5, which can specifically include a memory 51, a processor 52, and a computer program stored on the memory 51 and executable on the processor 52. When the processor 52 executes the program, the data block state acquisition method shown in the above-mentioned embodiments is implemented.

[0133] To implement the above-mentioned embodiments, the present disclosure further provides a computer readable storage medium, which stores a computer program. The program is executed by a processor to implement the data block state acquisition method shown in the above-mentioned embodiments.

[0134] In addition, the terms "first", "second", "third" and the like are used only to describe various features, and are not to be construed as indicating or implying relative importance or a specific number of the features indicated. Therefore, features defined with "first", "second", "third" and the like can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0135] In the description of the present disclosure, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the skilled in the art can combine and combine the different embodiments or examples described in the present disclosure and the features of the different embodiments or examples without contradiction.

[0136] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above-described embodiments are exemplary, and it is not construed that the present disclosure is limited to the above-described embodiments, and a person of ordinary skill in the art can make changes, modifications, replacements, and variations to the above-described embodiments within the scope of the present disclosure.

Claims

1. A method for obtaining a state of a data block, the method comprising: obtaining, in response to a first read request being read invalid in a first private cache and a second private cache, a first data block returned by a shared cache for the first read request; obtaining a first count value of the first data block, and obtaining a first data block state of the first data block according to the first count value. The obtaining the first count value of the first data block, and obtaining the first data block state of the first data block according to the first count value comprises: determining that the first data block state of the first data block is an exclusive state, in response to the first count value being greater than or equal to a preset count value threshold; determining that the first data block state of the first data block is a shared state, in response to the first count value being less than the count value threshold. The method further comprises: determining that the first count value is 0, in response to identifying that the first count value meets a preset zeroing policy.

2. The method of claim 1, wherein, The method further comprises: determining that the state of the first data block is unchanged, in response to the first count value being 0. The obtaining, in response to the first read request being read invalid in the first private cache and the second private cache, the first data block returned by the shared cache for the first read request comprises: generating a second read request and sending the second read request to the shared cache, in response to the first read request being read invalid in the first private cache and the second private cache; obtaining, by the shared cache, a second data block corresponding to the second read request as the first data block corresponding to the first read request. The method further comprises: determining that the first read request is read invalid in the first private cache, in response to the first read request being missed in the first private cache; determining that the first read request corresponding to a third read request is read invalid in the second private cache, in response to the third read request being missed in the second private cache.

3. The method of claim 2, wherein, The determining that the first read request is read invalid in the first private cache, in response to the first read request being missed in the first private cache, comprises: determining that the first read request is missed in the first private cache, in response to a second data block accessed by the first read request not existing in the first private cache, or the second data block being in an invalid state in the first private cache. The determining that the first read request corresponding to the third read request is read invalid in the second private cache, in response to the third read request being missed in the second private cache, comprises: determining that the first read request corresponding to the third read request is missed in the second private cache, in response to a third data block accessed by the third read request not existing in the second private cache, or the third data block not being in an exclusive state or a shared state in the second private cache.

4. The method of claim 3, wherein, ​ ​ 5. The method of any one of claims 1 to 4, wherein, ​ ​ ​ 6. The method of claim 5, wherein, ​ ​ ​ 7. The method of claim 6, wherein, ​ ​ 8. The method of claim 6, wherein, ​ ​ 9. The method of claim 5, wherein, The method further comprises: generating a fourth read request and sending the fourth read request to a cache directory of the multi-level cache system in response to the first read request missing in the primary private cache and the secondary private cache; generating the second read request according to the fourth read request and sending the second read request to the shared cache in response to the fourth read request missing in the cache directory.

10. The method of claim 7, wherein, The method further comprises: determining that the first read request hits in the primary private cache in response to the second data block existing in the primary private cache and the second data block not being in an invalid state in the primary private cache.

11. The method of claim 8, wherein, The method further comprises: determining that the first read request corresponding to the third read request hits in the secondary private cache in response to the third data block being in a shared state or an exclusive state in the secondary private cache.

12. The method of claim 9, wherein, The method further comprises: determining that the fourth read request misses in the cache directory in response to the access target information in the cache directory not existing or a fourth data block corresponding to the fourth read request being recorded as an invalid state in the cache directory.

13. The method of claim 12, wherein, The method further comprises, after determining that the fourth read request misses in the cache directory: obtaining the first data block from a shared cache and / or memory; determining that a second data block state of the first data block is in a shared state in response to the first data block existing a unique backup data block; obtaining a second count value of the first data block being written and adjusting the second data block state of the first data block to an exclusive state when the second count value is greater than or equal to a preset count value threshold.

14. The method of claim 12, wherein, The method further comprises: determining that the fourth read request hits in the cache directory and sending a write-back request to a secondary private cache to which a data block corresponding to the data block record state in the access target information in the cache directory belongs in response to the data block record state in the access target information in the cache directory indicating a valid-dirty or valid-clean state.

15. The method of any one of claims 1-14, wherein, The secondary private cache and the primary private cache do not maintain an inclusion relationship.

16. A data block state obtaining apparatus, the apparatus comprising: a first obtaining module configured to obtain a first data block returned by a first read request in response to the first read request missing in a primary private cache and a secondary private cache through a shared cache; a second obtaining module configured to obtain a first count value of the first data block and obtain a first data block state of the first data block according to the first count value.

17. An electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1-15 when executing the program.

18. A computer readable storage medium having stored thereon a computer program, the program, when executed by a processor, implementing the method of any of claims 1-15.

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