Access method and apparatus for multi-level cache storage system, device, and medium

Abstract

The present disclosure relates to the technical field of data processing, and provides an access method and apparatus for a multi-level cache storage system, a device, and a medium. The method comprises: acquiring a target request operation of a multi-level cache storage system; in response to the target request operation being a first replacement request operation, acquiring a replacement area of the first replacement request operation in the multi-level cache storage system, so as to determine a target write-back area of the first replacement request operation in the multi-level cache storage system; and acquiring a first data block of the first replacement request operation in the replacement area, and replacing and writing back the first data block to the target write-back area.

Description

Access method, device, equipment and medium of multi-level cache storage system

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on and claims priority from Chinese Patent Application No. 202411096643.0 filed on August 12, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of data processing, and in particular to an access method, device, equipment and medium of a multi-level cache storage system. BACKGROUND

[0004] With the development of technology, the number of processor cores integrated on a chip is increasing, and the amount of data stored in the multi-level cache storage system on the chip is also increasing.

[0005] When data in a data block in the multi-level cache storage system is modified, the data block can be marked for modification, and the data block can be replaced and written back to the upper level cache when certain conditions are met, to maintain the data consistency of the multi-level cache storage system, but the flexibility is poor. SUMMARY

[0006] The present disclosure aims to at least partially solve one of the technical problems in the related art.

[0007] To this end, the first aspect of the present disclosure provides an access method of a multi-level cache storage system.

[0008] The second aspect of the present disclosure provides an access device of a multi-level cache storage system.

[0009] The third aspect of the present disclosure provides an electronic device.

[0010] The fourth aspect of the present disclosure provides a computer-readable storage medium.

[0011] The first aspect of the present disclosure provides an access method of a multi-level cache storage system, the method comprising: obtaining a target request operation of the multi-level cache storage system; in response to the target request operation being a first replacement request operation, obtaining a replacement area of the first replacement request operation in the multi-level cache storage system to determine a target write-back area of the first replacement request operation in the multi-level cache storage system; obtaining a first data block of the first replacement request operation in the replacement area, and replacing and writing back the first data block to the target write-back area.

[0012] The second aspect of the present disclosure provides an access device of a multi-level cache storage system, the device comprising: an acquisition module configured to acquire a target request operation of the multi-level cache storage system; a determination module configured to, in response to the target request operation being a first replacement request operation, acquire a replacement area of the first replacement request operation in the multi-level cache storage system, so as to determine a target write-back area of the first replacement request operation in the multi-level cache storage system; and a replacement write-back module configured to acquire a first data block of the first replacement request operation in the replacement area, and replace and write back the first data block to the target write-back area.

[0013] The third aspect of the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the access method of the multi-level cache storage system according to the first aspect is implemented.

[0014] To achieve the above-mentioned purposes, the fourth aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the access method of the multi-level cache storage system according to the first aspect is implemented.

[0015] The access method, device, equipment and medium of the multi-level cache storage system according to the embodiments of the present disclosure, when the target request operation is the first replacement request operation, the replacement area and the target write-back area corresponding to the first replacement request operation are acquired, the first data block in the replacement area is replaced, and the first data block is written back to the target write-back area. In the present disclosure, the target write-back area is determined according to the replacement area, so as to replace and write back the first data block, the consistency of the multi-level cache storage system is maintained, the replacement write-back of the first data block is implemented based on the first replacement request operation, the data block can be replaced and written back to different target write-back areas without waiting for specific conditions to be met, the flexibility of the replacement write-back of the data block is improved, and the access method of the multi-level cache storage system is optimized.

[0016] It should be understood that the content described in the present disclosure is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent through the following description of the embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above-mentioned and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] FIG. 1 is a flowchart of an access method of a multi-level cache storage system according to an embodiment of the present disclosure;

[0019] FIG. 2 is a schematic diagram of a multi-level cache storage system according to an embodiment of the present disclosure;

[0020] FIG. 3 is a flowchart of an access method of a multi-level cache storage system according to another embodiment of the present disclosure;

[0021] FIG. 4 is a structural diagram of an access device of a multi-level cache storage system according to an embodiment of the present disclosure;

[0022] FIG. 5 is a structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, in which the same or similar components have the same or similar reference numbers throughout the drawings and a detailed description of the same or similar components is not repeated. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be understood as limiting the present disclosure.

[0024] FIG. 1 is a flowchart of an access method of a multi-level cache storage system according to an embodiment of the present disclosure, as shown in FIG. 1, the method comprises:

[0025] S101, obtaining a target request operation of a multi-level cache storage system.

[0026] In the embodiments of the present disclosure, the request operation of accessing the multi-level cache storage system can be marked as a target request operation, wherein the target request operation can include a read access request operation, a write access request operation, a replacement request operation, an invalidation request operation, and an invalidation and write-back request operation, etc.

[0027] S102, in response to the target request operation being a first replacement request operation, obtaining a replacement area of the first replacement request operation in the multi-level cache storage system to determine a target write-back area of the first replacement request operation in the multi-level cache storage system.

[0028] In the embodiments of the present disclosure, the target request operation can also include a replacement request operation of a data block in the multi-level cache storage system, and the replacement request operation currently to be executed in the multi-level cache storage system can be marked as a first replacement request operation.

[0029] Optionally, the first replacement request operation has an access area in the multi-level cache storage system, and the area can be marked as a replacement area of the first replacement request operation in the multi-level cache storage system. The replacement area can be understood as an area where the data block to be replaced in the multi-level cache storage request operation of the first replacement request operation is located.

[0030] As an example, as shown in FIG. 2, the processor core 1 includes a first private cache, the multi-level cache storage system further includes a second private cache and a shared cache, and the data interaction between the first private cache, the second private cache on each processor core and the shared cache shown in FIG. 2 is implemented through the routing nodes shown in FIG. 2, so as to build the multi-level cache storage system shown in FIG. 2.

[0031] In the scenario shown in FIG. 2, the replacement region of the first replacement request operation can be the first private cache shown in FIG. 2, can be the second private cache shown in FIG. 2, or can be the shared cache shown in FIG. 2, which is not limited here.

[0032] In the embodiment of the present disclosure, after the data block in the replacement region is replaced, the data in the data block needs to be written back, and the region when the data block is written back can be marked as the target write-back region of the first replacement request operation in the multi-level cache storage system.

[0033] As an example, if the replacement region of the first replacement request operation in the multi-level cache storage system is set as the first private cache shown in FIG. 2, then in the multi-level cache storage system shown in FIG. 2, the second private cache which is the upper level of the first private cache shown in FIG. 2 can be determined as the target write-back region of the first replacement request operation.

[0034] As another example, if the replacement region of the first replacement request operation is set as the second private cache shown in FIG. 2, then in this example, the shared cache shown in FIG. 2 is the target write-back region corresponding to the second private cache.

[0035] In S103, the first data block in the replacement region of the first replacement request operation is obtained, and the first data block is replaced and written back to the target write-back region.

[0036] In the embodiment of the present disclosure, the data block replaced by the first replacement request operation in the replacement region can be marked as the first data block.

[0037] Optionally, based on the execution of the first replacement request operation, the first data block in the replacement region can be replaced, and the data in the first data block is written back to the corresponding target write-back region.

[0038] As an example, if the replacement region is set as the first private cache shown in FIG. 2 and the target write-back region is set as the second private cache shown in FIG. 2, then in this example, after the first data block in the first private cache is replaced by the first replacement request operation, the data in the first data block can be written back to the second private cache shown in FIG. 2, so as to complete the execution of the first replacement request operation.

[0039] The method of the multi-level cache storage system provided in the disclosure, when the target request operation is the first replacement request operation, the replacement region corresponding to the first replacement request operation and the target write-back region are obtained, the first data block in the replacement region is replaced, and the first data block is written back to the target write-back region. In the disclosure, the target write-back region is determined according to the replacement region to replace and write back the first data block, which realizes the consistency maintenance of the multi-level cache storage system, realizes the replacement and write back of the first data block based on the first replacement request operation, and does not need to wait for a specific condition to be met, that is, the data block can be replaced and written back to different target write-back regions, thereby improving the flexibility of the replacement and write back of the data block and optimizing the access method of the multi-level cache storage system.

[0040] In the above embodiment, regarding the execution of the first replacement request operation, it can also be understood in combination with FIG. 3. FIG. 3 is a flowchart of an access method of a multi-level cache storage system according to another embodiment of the disclosure. As shown in FIG. 3, the method comprises:

[0041] S301, in response to the first access request operation being the first replacement request operation, obtaining the replacement region of the first replacement request operation in the multi-level cache storage system to determine the target write-back region of the replacement request operation in the multi-level cache storage system.

[0042] Optionally, in response to the replacement region being a private cache of a first level in the multi-level cache storage system, the private cache of a second level corresponding to the private cache of the first level is determined as the target write-back region of the first replacement request operation in the multi-level cache storage system.

[0043] As an example, as shown in FIG. 2, in the multi-level cache storage system shown in FIG. 2, the cache of the upper level of the private cache of the first level is the private cache of the second level, wherein the data block in the private cache of the first level can be written back to the private cache of the second level.

[0044] In this scenario, when the replacement region of the first replacement request operation in the multi-level cache storage system is the private cache of the first level, the private cache of the second level can be determined as the target write-back region corresponding to the first replacement request operation.

[0045] Optionally, in response to the replacement region being a private cache of a second level in the multi-level cache storage system, the shared cache and / or the memory are determined as the target write-back region of the first replacement request operation in the multi-level cache storage system.

[0046] As an example, in the multi-level cache storage system shown in FIG. 2, the data block in the private cache of the second level can be written back to the shared cache, or directly written back to the memory.

[0047] In this example, when the replacement region of the first replacement request operation is the two-level private cache shown in FIG. 2, the shared cache and / or the memory shown in FIG. 2 can be determined as the target write-back region of the first replacement request operation in the multi-level cache storage system.

[0048] S302, obtaining a first data block of the first replacement request operation in the replacement region, and performing replacement write-back of the first data block to the target write-back region.

[0049] Optionally, in response to the replacement region being the one-level private cache and the target write-back region being the two-level private cache, a second data block of the first replacement request operation in the one-level private cache is obtained, and the second data block is taken as the first data block, a second replacement request operation of the two-level private cache is generated, and the first data block is replaced and written back to the two-level private cache based on the second replacement request operation.

[0050] In the scenario where the replacement region is the one-level private cache and the target write-back region is the two-level private cache, a data block in the one-level private cache that needs to be replaced by the first replacement request operation can be marked as a second data block, which is the first data block of the first replacement request operation in the replacement region.

[0051] Optionally, the second data block as the first data block needs to be replaced and written back, and in this scenario, the one-level private cache can generate a request operation corresponding to the second data block and send the request operation to the two-level private cache to replace and write back the second data block from the one-level private cache to the two-level private cache.

[0052] The request operation generated by the one-level private cache to replace and write back the second data block to the two-level private cache can be marked as a second replacement request operation.

[0053] In the embodiments of the present disclosure, each data block in the two-level private cache is provided with a containing bit vector bit and a write state bit (w bit), wherein for any data block, the value on the containing bit vector bit of the data block can identify whether a corresponding data block exists in the corresponding one-level private cache, and the value on the write state bit of the data block can identify whether the data block has been written.

[0054] In this scenario, the write state bit and the containing bit vector bit of the first data block in the two-level private cache are modified, and a replacement write-back response is sent to the processor core corresponding to the first replacement request operation.

[0055] In the embodiments of the present disclosure, when the first data block is replaced and written back from the one-level private cache to the two-level private cache, the state of the first data block in the two-level private cache changes.

[0056] In this scenario, the first data block in the secondary private cache is a data block that has been written, and the value of the write state bit of the first data block in the secondary private cache can be modified to the corresponding value of the written state, such as 1.

[0057] Correspondingly, when the second data block in the primary private cache is replaced and the first data block is written back to the secondary private cache, it can be determined that the first data block in the secondary private cache does not have a corresponding associated data block in the primary private cache. In this scenario, the containing relationship corresponding to the first data block can be determined according to the containing relationship determination method in the related art, and the containing bit vector bit corresponding to the first data block can be modified according to the determination result.

[0058] It should be noted that the containing relationship between each data block can be maintained or not maintained, or can be a non-containing relationship, which is not limited here.

[0059] Optionally, in response to the replacement region being the secondary private cache, a third data block in the secondary private cache is obtained as the first data block for which the first replacement request operation is performed, and a first data block state of the first data block in the secondary private cache is obtained.

[0060] In the scenario where the replacement region is the secondary private cache, the data block in the secondary private cache that the first replacement request operation wants to replace can be marked as the third data block, which is the first data block in the replacement region for which the first replacement request operation is performed.

[0061] The third data block as the first data block can be in a shared state or an exclusive state. In this scenario, the first data block can be replaced and written back to the target write-back region according to the first data block state.

[0062] As a possible implementation manner, in response to the shared cache not having a fourth data block associated with the first data block, and the first data block state indicating that the first data block is in a shared state, the shared cache is determined as the target write-back region, and the first data block is replaced and written back to the shared cache.

[0063] In the embodiments of the present disclosure, the state of the first data block in the replacement region can be marked as the first data block state, and the current state of the first data block can be identified according to the specific information carried by the first data block state.

[0064] Optionally, the levels of caches in the multi-level cache storage system maintain a non-containing relationship. In this scenario, the first data block in the secondary private cache can or can not have an associated data block in the shared cache. The data block associated with the first data block in the secondary private cache in the shared cache can be marked as the fourth data block.

[0065] When the fourth data block does not exist in the shared cache and the first data block in the second private cache is in the shared state, it can be determined that the data in the first data block can be shared data of each cache in the multi-level cache storage system, and it can be determined that the target write-back area of the first data block is the shared cache.

[0066] Further, the first data block can be replaced from the second private cache and written back to the shared cache.

[0067] As another possible implementation, in response to the fourth data block associated with the first data block not existing in the shared cache and the first data block being in the exclusive state, the memory is determined as the target write-back area, and the first data block is replaced and written back to the memory.

[0068] In the embodiments of the present disclosure, when the fourth data block does not exist in the shared cache and the first data block is in the exclusive state, it can be understood that the data in the first data block is not shared data of each cache in the multi-level cache storage system, in this scenario, the first data block is not written back to the shared cache, and it can be determined that the memory can be used as the target write-back area of the first data block.

[0069] Further, based on the execution of the first replacement request operation, the first data block is replaced from the second private cache and written back to the memory.

[0070] It should be noted that the fourth data block associated with the first data block can exist in the shared cache, wherein in response to the first data block existing in the shared cache and the fourth data block associated with the first data block, the first data block is replaced and written back to the shared cache.

[0071] In the embodiments of the present disclosure, the fourth data block associated with the first data block can exist in the shared cache, in this scenario, it can be determined that the data in the first data block can be written back to the shared cache.

[0072] Further, the shared cache can be used as the target write-back area of the first data block, and the first data block can be replaced from the second private cache and written back to the shared cache.

[0073] As another possible implementation, in response to the first data block existing in the cache directory of the multi-level cache storage system and the fourth data block not existing in the shared cache, the first data block is replaced and written back to the target write-back area according to the state of the first data block.

[0074] In the embodiment of the present disclosure, the multi-level cache storage system has a corresponding cache directory. In this scenario, the first data block may have corresponding directory information in the cache directory. The directory information can be marked as the data block directory information corresponding to the first data block in the cache directory.

[0075] In the scenario where the data block directory information exists in the cache directory and the fourth data block does not exist in the shared cache, the state of the first data block can be shared or exclusive. In response to the state of the first data block being shared, the first data block is replaced and written back to the shared cache.

[0076] It can be understood that when the state of the first data block is shared, the data in the first data block can be shared by each level of cache of the multi-level cache storage system. In this scenario, the first data block can be replaced and written back from the second private cache to the shared cache.

[0077] Correspondingly, the first data block can be in an exclusive state. In response to the state of the first data block being exclusive, the first data block is replaced and written back to the memory. It can be understood that when the state of the first data block is exclusive, the data in the first data block does not need to be shared by each level of cache of the multi-level cache storage system in the shared cache. In this scenario, the first data block can be directly replaced and written back from the second private cache to the memory.

[0078] It should be noted that after the first data block is replaced and written back from the second private cache to the corresponding target write-back area, the data block directory information corresponding to the first data block in the cache directory needs to be modified. In response to the first data block being replaced and written back to the shared cache, the state information and the identification bit information of the data block directory information are modified.

[0079] In the embodiment of the present disclosure, the modification of the data block directory information can be achieved by modifying the state information and the identification bit information of the data block directory information. The state information can be used to obtain the state of the first data block. The identification bit information can be understood as the w bit in the data block directory information, which is used to indicate whether the corresponding data block is written.

[0080] Optionally, after the first data block is replaced and written back to the target write-back area, the target write-back area sends a replacement write-back response to the second private cache. It can be understood that after the first data block is replaced and written back to the corresponding target write-back area, the target write-back area can generate corresponding response information. The response information is the replacement write-back response sent to the second private cache as the replacement area.

[0081] It should be noted that during the replacement write-back process, the data block that is replaced and written back may need to be invalidated. The invalidation of the data block can be understood in combination with the following content:

[0082] Optionally, in response to the target request operation being an invalid request operation, the invalid request operation acquires a second data block state of a fifth data block in the secondary private cache, and acquires a sixth data block in the secondary private cache corresponding to a primary private cache.

[0083] In the embodiments of the present disclosure, part of the data blocks in the multi-level cache storage system need to be invalidated, for example, for any data block, when the directory information of the data block in the cache directory indicates that the data block is in an invalid state, and the data block is currently in a non-invalid state, in order to maintain the data consistency of the multi-level cache storage system, the data block needs to be invalidated in this scenario.

[0084] Optionally, the cache directory can send related request operations to the cache to which the data block belongs, so as to invalidate the data block.

[0085] As an example, assuming that the cache to which the data block needs to be invalidated belongs to the secondary private cache shown in FIG. 2, the related request operation sent by the cache directory to the secondary private cache can be marked as an invalid request operation, and the data block in the secondary private cache that needs to be invalidated can be marked as a fifth data block, and the data block in the primary private cache shown in FIG. 2 that needs to be invalidated can be marked as a sixth data block.

[0086] In this scenario, the invalid request operation can be executed according to the state of the fifth data block and the state of the sixth data block, wherein the state of the fifth data block can be marked as a second data block state.

[0087] Optionally, in response to the second data block state being a shared state and the sixth data block being identified to exist in the primary private cache, the sixth data block is invalidated.

[0088] In the embodiments of the present disclosure, when the second data block state indicates that the fifth data block is in a shared state, and the sixth data block in the primary private cache exists, the sixth data block needs to be invalidated after the fifth data block in the secondary private cache is invalidated.

[0089] It should be noted that the sixth data block in the primary private cache can be in a shared state, in which case, in response to the target request operation being an invalid request operation, and the sixth data block being in a shared state in the primary private cache, and the fifth data block and the sixth data block being in a maintenance containing relationship, the sixth data block is invalidated.

[0090] In the embodiments of the present disclosure, when the fifth data block and the sixth data block are in a maintenance containing relationship, it can be understood that the fifth data block contains all the data in the sixth data block, and in this case, the invalidation processing of the sixth data block needs to be performed first, and then the invalidation processing of the fifth data block is performed to realize the corresponding invalidation request operation.

[0091] Optionally, in response to the target request operation being an invalidation request operation and the sixth data block being in a shared state, the invalidation processing is performed on the sixth data block.

[0092] In the embodiments of the present disclosure, when the sixth data block is in a shared state, it can be understood that the data content in the sixth data block may exist in a backup in a private cache on another processor core, or may exist in a backup in a shared cache, and in this case, in order to realize the execution of the invalidation request operation, the invalidation processing of the sixth data block is performed first, and a corresponding invalidation processing response is generated and transmitted to the secondary private cache.

[0093] It should be noted that after the secondary private cache receives the invalidation processing response, the fifth data block stored in the secondary private cache can be invalidated, or other data blocks in other caches can be invalidated based on other preset invalidation strategies, which is not limited here.

[0094] Optionally, the sixth data block can be processed based on a data block invalidation processing method in the related art, and then the invalidation processing of the sixth data block is realized.

[0095] Optionally, in response to the first invalidation response of the sixth data block of the secondary private cache to the primary private cache, the invalidation processing of the fifth data block is performed, and the second invalidation response of the fifth data block and the sixth data block to the cache directory is performed.

[0096] In the embodiments of the present disclosure, after the sixth data block in the primary private cache is invalidated, a corresponding processing response can be generated and sent to the secondary private cache, and the processing response can be marked as a first invalidation response. Further, after the secondary private cache receives the first invalidation response sent by the primary private cache, the invalidation processing of the fifth data block in the secondary private cache can be performed.

[0097] Optionally, after the invalidation processing of the fifth data block in the secondary private cache is performed, a corresponding processing response can be returned to the cache directory sending the invalidation request operation, and the processing response can be marked as a second invalidation response. Based on the reception of the second invalidation response by the cache directory, the invalidation processing of the fifth data block and the sixth data block is realized.

[0098] In the embodiments of the present disclosure, the write-back of the data block in the replacement write-back process can be further understood in combination with the following content:

[0099] In some implementations, in response to the target request operation being a write-back request operation, it is identified whether the seventh data block of the write-back request operation in the second-level private cache is in an exclusive state, and whether the write-back request operation has an associated eighth data block in the first-level private cache corresponding to the second-level private cache, wherein the write-back request operation is a request operation sent by the cache directory to the second-level private cache.

[0100] In the embodiments of the present disclosure, the cache directory can send a write-back request operation to each level of cache on the corresponding processor core, wherein the data block in the second-level private cache of the processor core that needs to be processed by the write-back request operation can be marked as a seventh data block, and the data block in the first-level private cache that needs to be processed by the write-back request operation can be marked as an eighth data block.

[0101] In this scenario, the states of the seventh data block and the eighth data block can be identified respectively, wherein whether the seventh data block is in an exclusive state and whether the eighth data block exists in the first-level private cache can be identified according to the attribute information of the seventh data block and the eighth data block respectively.

[0102] Optionally, in response to the write-back request operation having an associated eighth data block in the first-level private cache, the eighth data block is written back to the second-level private cache, and the eighth data block is adjusted to a shared state, and in response to the seventh data block being identified as an exclusive state, the seventh data block is adjusted to a shared state after the eighth data block is written back to the second-level private cache, and a write-back response corresponding to the write-back request operation is sent to the cache directory.

[0103] It can be understood that when the eighth data block exists in the first-level private cache, the eighth data block needs to be written back to the second-level private cache and adjusted to a shared state, and in this scenario, whether the seventh data block is in an exclusive state can be identified, wherein when the seventh data block is identified as being in an exclusive state, it needs to be adjusted in state.

[0104] The seventh data block needs to be adjusted to a shared state, and a corresponding response is generated and returned to the cache directory sending the write-back request operation, wherein the response is a write-back response.

[0105] It should be noted that after the seventh data block is adjusted to a shared state, the second-level private cache can be marked as an owner node of the seventh data block, wherein the second-level private cache can be set and processed according to the owner node setting method in the related art, so as to be marked as the owner node of the seventh data block.

[0106] In some implementations, in response to the target request operation being a write-back request operation and the eighth data block being in an exclusive state in the primary private cache, the secondary private cache sends a write-back response to the first exclusive processor core, where the first exclusive processor core is a processor core that exclusively processes the backup data block corresponding to the eighth data block.

[0107] In the embodiments of the present disclosure, when the eighth data block in the primary private cache can be in an exclusive state, in order to implement write-back of the eighth data block to the secondary private cache, a corresponding write-back request can be sent to a processor core that exclusively has a backup data block corresponding to the eighth data block in the multi-level cache storage system, where the processor core that exclusively processes the backup data block corresponding to the eighth data block can be marked as the first exclusive processor core.

[0108] Further, the secondary private cache can send a corresponding write-back request to the first exclusive processor core to write back the backup data block corresponding to the eighth data block exclusively on the first exclusive processor core to the secondary private cache.

[0109] In some other implementations, in response to the target request operation being a write-back request operation and the eighth data block being in an exclusive state in the primary private cache, the eighth data block is adjusted to a shared state, and the eighth data block is written back to the secondary private cache.

[0110] In the embodiments of the present disclosure, when the eighth data block is in an exclusive state in the primary private cache, in order to implement write-back of the eighth data block to the secondary private cache, the data block state of the eighth data block can be adjusted, so that the eighth data block after state adjustment can implement the write-back operation of the data block.

[0111] The eighth data block can be adjusted to a shared state, which can be understood as that the eighth data block in the shared state satisfies the preset data block write-back condition, and in this scenario, the eighth data block adjusted to the shared state can be written back to the secondary private cache.

[0112] In the embodiments of the present disclosure, in the process of replacement write-back, invalidation and write-back of the data block can also be required, which can be understood in combination with the following content:

[0113] In response to the target request operation being an invalidation and write-back request operation, whether the ninth data block in the secondary private cache is in an exclusive state is identified, and whether there is an associated tenth data block in the primary private cache corresponding to the secondary private cache is identified, where the invalidation and write-back request operation is a request operation sent by the cache directory to the secondary private cache.

[0114] In the embodiments of the present disclosure, when the target request operation is an invalidation and write-back request operation sent to the secondary private cache for the cache directory, the data block in the secondary private cache which needs to be processed by write-back and invalidation can be marked as a ninth data block, and the data block in the primary private cache which needs to be processed by write-back and invalidation can be marked as a tenth data block.

[0115] Optionally, the state of the ninth data block in the secondary private cache and whether the tenth data block exists in the primary private cache need to be identified. When it is identified that the tenth data block exists in the primary private cache, in response to the invalidation and write-back request operation, the tenth data block associated in the primary private cache is processed by invalidation, and the tenth data block is written back to the secondary private cache.

[0116] In this scenario, the tenth data block in the primary private cache needs to be written back to the secondary private cache, and the tenth data block in the primary private cache needs to be invalidated, so as to complete the invalidation and write-back processing of the tenth data block.

[0117] Optionally, in response to identifying that the ninth data block is in the exclusive state, after the tenth data block is written back to the secondary private cache, the ninth data block is processed by invalidation and write-back, and an invalidation and write-back response corresponding to the invalidation and write-back request operation is sent to the cache directory.

[0118] It can be understood that, after the tenth data block is written back to the secondary private cache, the ninth data block in the exclusive state is processed by write-back. When the ninth data block is in the exclusive state, the data in the ninth data block can be directly written back to the memory, and after the data is written back, the ninth data block is placed in an invalid state, so as to realize the invalidation and write-back processing of the ninth data block.

[0119] Further, a processing response corresponding to the invalidation and write-back processing of the ninth data block is generated, and the response is sent to the cache directory as an invalidation and write-back response corresponding to the invalidation and write-back request operation.

[0120] In some implementations, in response to the target request operation being an invalidation and write-back request operation and the tenth data block being in the exclusive state, the secondary private cache sends the invalidation and write-back request operation to a corresponding second exclusive processor core. The second exclusive processor core is a processor core of a backup data block of the exclusive tenth data block. The ninth data block is obtained based on replacement of the tenth data block in the secondary private cache. The ninth data block and the tenth data block are in a containment relationship.

[0121] In the embodiments of the present disclosure, when the ninth data block is obtained by the replacement operation of the tenth data block in a maintenance containing relationship, it can be understood that the data in the ninth data block is the same as the data in the tenth data block. In this case, when the tenth data block is in an exclusive state, the backup data block on the processor core corresponding to the exclusive tenth data block in the multi-level cache storage system can be invalidated, and the processor core can be marked as a second exclusive processor core.

[0122] Further, the tenth data block on the second exclusive processor core and the corresponding backup data block are invalidated.

[0123] In other implementations, in response to the target request operation being invalid and the write-back request operation, and the tenth data block being in an exclusive state, the tenth data block is invalidated, and a corresponding write-back response is sent to the secondary private cache to write the tenth data block back to the secondary private cache.

[0124] In the embodiments of the present disclosure, when the tenth data block is in an exclusive state, the tenth data block can be invalidated, and a corresponding write-back response can be sent to the corresponding secondary private cache to implement invalidation and write-back of the tenth data block to the secondary private cache.

[0125] In the embodiments of the present disclosure, the first replacement request operation can also be implemented through a cache directory, which can be understood in combination with the following content:

[0126] The directory state of the eleventh data block corresponding to the first replacement request operation in the cache directory is obtained, and in response to the directory state being valid and clean, the backup data block in the secondary private cache that owns the backup of the eleventh data block is invalidated.

[0127] In the embodiments of the present disclosure, the operation data block corresponding to the first replacement request operation in the multi-level cache storage system can be marked as the eleventh data block. In this case, the state recorded in the cache directory of the eleventh data block can be obtained, and the state is marked as the target state of the eleventh data block.

[0128] In some implementations, the directory state of the eleventh data block in the cache directory can be a valid and clean state. In this case, the secondary private cache of the processor core that owns the backup data block of the eleventh data block in the multi-level cache storage system can be obtained, and the backup data block stored in each of the secondary private caches is invalidated.

[0129] Optionally, in response to the directory state being valid and dirty, the backup data block in the secondary private cache that owns the backup of the eleventh data block and is not the owner node is invalidated.

[0130] In the embodiment of the present disclosure, when the directory state indicates that the eleventh data block is in a valid-dirty state, a non-owner node's partial secondary private cache needs to be obtained from a partial secondary private cache that owns a backup of the eleventh data block, and invalidation processing is performed on the backup data block in the partial secondary private cache.

[0131] Optionally, in response to the directory state being valid-dirty, an invalidation and write-back request is sent to the third exclusive processor core or the owner node of the eleventh data block.

[0132] In the embodiment of the present disclosure, the processor core that exclusively owns the eleventh data block can be marked as the third exclusive processor core, and optionally, when the directory state indicates that the eleventh data block is in a valid-dirty state, an invalidation and write-back request can be sent to the third exclusive processor core or the owner node of the eleventh data block to invalidate and write back the corresponding data block.

[0133] The method of the multi-level cache storage system provided by the present disclosure determines a target write-back area according to a replacement area to perform replacement write-back on the first data block, thereby achieving consistency maintenance of the multi-level cache storage system, performing replacement write-back on the first data block based on a first replacement request operation, and not needing to wait for a specific condition to be met to replace and write back the data block to a different target write-back area, thereby improving the flexibility of the replacement write-back of the data block and optimizing the access method of the multi-level cache storage system.

[0134] Corresponding to the access method of the multi-level cache storage system proposed in the above several embodiments, one embodiment of the present disclosure also proposes an access device of a multi-level cache storage system. Since the access device of the multi-level cache storage system proposed in the embodiment of the present disclosure corresponds to the access method of the multi-level cache storage system proposed in the above several embodiments, the implementation manners of the access method of the multi-level cache storage system are also applicable to the access device of the multi-level cache storage system proposed in the embodiment of the present disclosure, which will not be described in detail in the following embodiments.

[0135] FIG. 4 is a structural schematic diagram of an access device of a multi-level cache storage system according to an embodiment of the present disclosure. As shown in FIG. 4, the access device 400 of the multi-level cache storage system includes an obtaining module 41, a determining module 42, and a replacement write-back module 43, wherein:

[0136] The obtaining module 41 is configured to obtain a target request operation of the multi-level cache storage system.

[0137] The determining module 42 is configured to, in response to the target request operation being a first replacement request operation, obtain a replacement area of the first replacement request operation in the multi-level cache storage system to determine a target write-back area of the first replacement request operation in the multi-level cache storage system.

[0138] The replacement write-back module 43 is configured to obtain a first data block in the replacement region for the first replacement request operation, and replace the first data block and write it back to the target write-back region.

[0139] In the embodiments of the present disclosure, the replacement write-back module 43 is further configured to: in response to the replacement region being a private cache at a first level in the multi-level cache storage system, determine that a private cache at a second level corresponding to the private cache at the first level is the target write-back region for the first replacement request operation in the multi-level cache storage system; and in response to the replacement region being the private cache at the second level in the multi-level cache storage system, determine that the shared cache and / or the memory is the target write-back region for the first replacement request operation in the multi-level cache storage system.

[0140] In the embodiments of the present disclosure, the replacement write-back module 43 is further configured to: in response to the replacement region being the private cache at the first level and the target write-back region being the private cache at the second level, obtain a second data block in the private cache at the first level for the first replacement request operation, and take the second data block as the first data block; generate a second replacement request operation for the private cache at the second level, and replace and write back the first data block to the private cache at the second level based on the second replacement request operation.

[0141] In the embodiments of the present disclosure, the replacement write-back module 43 is further configured to: modify the write state bit and the containing bit vector bit of the first data block in the private cache at the second level, and send a replacement write-back response to the processor core corresponding to the first replacement request operation.

[0142] In the embodiments of the present disclosure, the replacement write-back module 43 is further configured to: in response to the replacement region being the private cache at the second level, obtain a third data block in the private cache at the second level for the first replacement request operation, and take the third data block as the first data block; obtain a first data block state of the first data block in the private cache at the second level; and replace and write back the first data block to the target write-back region according to the first data block state.

[0143] In the embodiments of the present disclosure, the replacement write-back module 43 is further configured to: in response to the fourth data block associated with the first data block not existing in the shared cache and the first data block state indicating that the first data block is in a shared state, determine that the shared cache is the target write-back region, and replace and write back the first data block to the shared cache; and in response to the fourth data block associated with the first data block not existing in the shared cache and the first data block state indicating that the first data block is in an exclusive state, determine that the memory is the target write-back region, and replace and write back the first data block to the memory.

[0144] In the embodiments of the present disclosure, the replacement write-back module 43 is further configured to: in response to the first data block having the associated fourth data block in the shared cache, replace and write back the first data block to the shared cache.

[0145] In the embodiment of the present disclosure, the replacement write-back module 43 is further configured to: in response to the first data block corresponding data block directory information existing in the cache directory of the multi-level cache storage system and the fourth data block not existing in the shared cache, replace and write back the first data block to the target write-back area according to the first data block state; in response to the first data block state being the shared state, replace and write back the first data block to the shared cache; and in response to the first data block state being the exclusive state, replace and write back the first data block to the memory.

[0146] In the embodiment of the present disclosure, the replacement write-back module 43 is further configured to: in response to the first data block being replaced and written back to the shared cache, modify the state information and the identification bit information of the data block directory information.

[0147] In the embodiment of the present disclosure, the replacement write-back module 43 is further configured to: the target write-back area responds to the replacement write-back of the two-level private cache.

[0148] In the embodiment of the present disclosure, the device further comprises an invalidation module configured to: in response to the target request operation being an invalidation request operation, acquire a second data block state of a fifth data block of the invalidation request operation in the two-level private cache and acquire a sixth data block in a one-level private cache corresponding to the two-level private cache, wherein the invalidation request operation is a request operation sent by the cache directory to the two-level private cache; in response to the second data block state being the shared state and the sixth data block being identified as existing in the one-level private cache, perform invalidation processing on the sixth data block; and in response to the one-level private cache performing a first invalidation response of the sixth data block to the two-level private cache, perform invalidation processing on the fifth data block and perform a second invalidation response of the fifth data block and the sixth data block to the cache directory.

[0149] In the embodiment of the present disclosure, the invalidation module is further configured to: in response to the target request operation being the invalidation request operation and the sixth data block being in the shared state in the one-level private cache and the fifth data block and the sixth data block being in the maintenance containing relationship, perform invalidation processing on the sixth data block.

[0150] In the embodiment of the present disclosure, the invalidation module is further configured to: in response to the target request operation being the invalidation request operation and the sixth data block being in the shared state, perform invalidation processing on the sixth data block.

[0151] In the embodiments of the present disclosure, the device further comprises a write-back module, configured to: in response to the target request operation being a write-back request operation, identify whether a seventh data block of the write-back request operation in the secondary private cache is in an exclusive state, and identify whether an associated eighth data block of the write-back request operation exists in a primary private cache corresponding to the secondary private cache, wherein the write-back request operation is a request operation sent by a cache directory to the secondary private cache; in response to the associated eighth data block existing in the primary private cache, write the eighth data block back to the secondary private cache, and adjust the eighth data block to a shared state; and in response to identifying that the seventh data block is in the exclusive state, after writing the eighth data block back to the secondary private cache, adjust the seventh data block to the shared state, and send a write-back response corresponding to the write-back request operation to the cache directory.

[0152] In the embodiments of the present disclosure, the write-back module is further configured to: in response to the target request operation being the write-back request operation and the eighth data block being in the exclusive state in the primary private cache, send a write-back response to a first exclusive processor core by the secondary private cache, wherein the first exclusive processor core is a processor core that exclusively processes a backup data block corresponding to the eighth data block.

[0153] In the embodiments of the present disclosure, the write-back module is further configured to: in response to the target request operation being the write-back request operation and the eighth data block being in the exclusive state in the primary private cache, adjust the eighth data block to the shared state, and write the eighth data block back to the secondary private cache.

[0154] In the embodiments of the present disclosure, the write-back module is further configured to: mark the secondary private cache as an owner node of the seventh data block.

[0155] In the embodiments of the present disclosure, the device further comprises an invalidation and write-back module, configured to: in response to the target request operation being an invalidation and write-back request operation, identify whether a ninth data block of the invalidation and write-back request operation in the secondary private cache is in an exclusive state, and identify whether an associated tenth data block of the invalidation and write-back request operation exists in a primary private cache corresponding to the secondary private cache, wherein the invalidation and write-back request operation is a request operation sent by a cache directory to the secondary private cache; in response to the associated tenth data block existing in the primary private cache, perform invalidation processing on the tenth data block, and write the tenth data block back to the secondary private cache; and in response to identifying that the ninth data block is in the exclusive state, after writing the tenth data block back to the secondary private cache, perform invalidation and write-back processing on the ninth data block, and send an invalidation and write-back response corresponding to the invalidation and write-back request operation to the cache directory.

[0156] In the embodiment of the present disclosure, the invalidation and write-back module is further configured to: in response to the target request operation being an invalidation and write-back request operation and the tenth data block being in the exclusive state, send the invalidation and write-back request operation to a corresponding second exclusive processor core of the second private cache, wherein the second exclusive processor core is a processor core that exclusively backs up the tenth data block, and the ninth data block is obtained based on replacement of the tenth data block in the second private cache, and the ninth data block and the tenth data block are in a maintenance containing relationship.

[0157] In the embodiment of the present disclosure, the invalidation and write-back module is further configured to: in response to the target request operation being an invalidation and write-back request operation and the tenth data block being in the exclusive state, invalidate the tenth data block, and send a corresponding write-back response to the second private cache to write the tenth data block back to the second private cache.

[0158] In the embodiment of the present disclosure, the invalidation and write-back module is further configured to: obtain a first directory state of an eleventh data block corresponding to the first replacement request operation in a cache directory; in response to the directory state being valid and clean, perform invalidation processing on a backup data block in the second private cache that owns a backup of the eleventh data block; and in response to the directory state being valid and dirty, perform invalidation processing on a backup data block in the second private cache that owns a backup of the eleventh data block and is a non-owner node.

[0159] In the embodiment of the present disclosure, the invalidation and write-back module is further configured to: in response to the directory state being valid and dirty, send an invalidation and write-back request to a third exclusive processor core or an owner node of the eleventh data block.

[0160] The device of the multi-level cache storage system provided by the present disclosure, when the target request operation is the first replacement request operation, obtains a replacement region and a target write-back region corresponding to the first replacement request operation, performs replacement processing on a first data block in the replacement region, and writes the first data block back to the target write-back region. In the present disclosure, the target write-back region is determined according to the replacement region to perform replacement write-back on the first data block, which realizes consistency maintenance of the multi-level cache storage system, realizes replacement write-back of the first data block based on the first replacement request operation, and does not need to wait for a specific condition to be met to replace and write back the data block to different target write-back regions, thereby improving the flexibility of replacement write-back of the data block and optimizing the access method of the multi-level cache storage system.

[0161] In order to implement the above-mentioned embodiments, an electronic device 500 is provided in the embodiment of the present disclosure, as shown in FIG. 5, which specifically can include a memory 51, a processor 52, and a computer program stored on the memory 51 and executable on the processor 52, and when the processor 52 executes the program, the access method of the multi-level cache storage system as shown in the above-mentioned embodiments is implemented.

[0162] To achieve the above-mentioned embodiments, the embodiments of the present disclosure further propose a computer readable storage medium, having stored thereon a computer program, which is executed by a processor to implement the access method of the multi-level cache storage system as shown in the above-mentioned embodiments.

[0163] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated order of limiting the indicated technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0164] In the description of the present disclosure, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, a person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0165] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present disclosure, and those of ordinary skill in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present disclosure.

Claims

1. An access method of a multi-level cache storage system, the method comprising: obtaining a target request operation of a multi-level cache storage system; in response to the target request operation being a first replacement request operation, obtaining a replacement region of the first replacement request operation in the multi-level cache storage system to determine a target write-back region of the first replacement request operation in the multi-level cache storage system; obtaining a first data block of the first replacement request operation in the replacement region and replacing the first data block to the target write-back region.

2. The method of claim 1, wherein, The response to the target request operation being a first replacement request operation, obtaining a replacement region of the first replacement request operation in the multi-level cache storage system to determine a target write-back region of the first replacement request operation in the multi-level cache storage system, comprises: in response to the replacement region being a first level private cache in the multi-level cache storage system, determining a second level private cache corresponding to the first level private cache as the target write-back region of the first replacement request operation in the multi-level cache storage system; in response to the replacement region being the second level private cache in the multi-level cache storage system, determining a shared cache and / or memory as the target write-back region of the first replacement request operation in the multi-level cache storage system.

3. The method of claim 2, wherein, The obtaining a first data block of the first replacement request operation in the replacement region and replacing the first data block to the target write-back region, comprises: in response to the replacement region being the first level private cache and the target write-back region being the second level private cache, obtaining a second data block of the first replacement request operation in the first level private cache and taking the second data block as the first data block; generating a second replacement request operation of the second level private cache and replacing the first data block to the second level private cache based on the second replacement request operation.

4. The method of claim 3, wherein, The method further comprises: modifying a write state bit and a containing bit vector bit of the first data block in the second level private cache and performing a replacement write-back response to a processor core corresponding to the first replacement request operation.

5. The method of claim 2, wherein, The obtaining a first data block of the first replacement request operation in the replacement region and replacing the first data block to the target write-back region, comprises: in response to the replacement region being the second level private cache, obtaining a third data block of the first replacement request operation in the second level private cache and taking the third data block as the first data block; obtaining a first data block state of the first data block in the second level private cache; replacing the first data block to the target write-back region according to the first data block state.

6. The method of claim 5, wherein, The replacing the first data block to the target write-back region according to the first data block state, comprises: in response to the fourth data block associated with the first data block not existing in the shared cache and the first data block state indicating that the first data block is in the shared state, determining that the shared cache is the target write-back area, and replacing and writing back the first data block to the shared cache; in response to the fourth data block associated with the first data block not existing in the shared cache and the first data block state indicating that the first data block is in the exclusive state, determining that the memory is the target write-back area, and replacing and writing back the first data block to the memory.

7. The method of claim 6, wherein, The method further comprises: in response to the first data block having the associated fourth data block in the shared cache, replacing and writing back the first data block to the shared cache.

8. The method of claim 5, wherein, The replacing and writing back of the first data block to the target write-back area according to the first data block state comprises: in response to the first data block having corresponding data block directory information in the cache directory of the multi-level cache storage system and the fourth data block not existing in the shared cache, replacing and writing back the first data block to the target write-back area according to the first data block state; in response to the first data block state being the shared state, replacing and writing back the first data block to the shared cache; in response to the first data block state being the exclusive state, replacing and writing back the first data block to the memory.

9. The method of claim 8, wherein, The method further comprises: in response to the replacing and writing back of the first data block to the shared cache, modifying the state information and the identification bit information of the data block directory information.

10. The method of claim 8, wherein, After the replacing and writing back of the first data block to the target write-back area according to the first data block state, the target write-back area comprises: the target write-back area responding to the replacement write-back of the two-level private cache.

11. The method of any one of claims 1-10, wherein, The method further comprises: in response to the target request operation being an invalid request operation, obtaining a second data block state of a fifth data block of the invalid request operation in a two-level private cache, and obtaining a sixth data block in a one-level private cache corresponding to the two-level private cache, wherein the invalid request operation is a request operation sent by a cache directory to the two-level private cache; in response to the second data block state being the shared state and the sixth data block being identified as existing in the one-level private cache, invalidating the sixth data block; in response to the one-level private cache responding to the two-level private cache with a first invalidation response of the sixth data block, invalidating the fifth data block and sending a second invalidation response of the fifth data block and the sixth data block to the cache directory.

12. The method of any one of claims 1-11, wherein, The method further comprises: in response to the target request operation being an invalid request operation, the sixth data block being in the shared state in the one-level private cache, and the fifth data block and the sixth data block being in a maintenance containing relationship, invalidating the sixth data block.

13. The method of any one of claims 1-12, wherein, The method further comprises: in response to the target request operation being an invalid request operation and the sixth data block being in the shared state, invalidating the sixth data block.

14. The method of any one of claims 1-13, wherein, The method further comprises: In response to the target request operation being a write-back request operation, it is identified whether a seventh data block of the write-back request operation in a second-level private cache is in an exclusive state, and whether an eighth data block associated with the write-back request operation in a first-level private cache corresponding to the second-level private cache exists, wherein the write-back request operation is a request operation sent by a cache directory to the second-level private cache; In response to the eighth data block associated with the write-back request operation existing in the first-level private cache, the eighth data block is written back to the second-level private cache, and the eighth data block is adjusted to a shared state; In response to the seventh data block being identified as the exclusive state, after the eighth data block is written back to the second-level private cache, the seventh data block is adjusted to the shared state, and a write-back response corresponding to the write-back request operation is sent to the cache directory.

15. The method of any one of claims 1-14, wherein, The method further comprises: In response to the target request operation being a write-back request operation and the eighth data block being in an exclusive state in the first-level private cache, the second-level private cache sends a write-back response to a first exclusive processor core, wherein the first exclusive processor core is a processor core that exclusively occupies a backup data block corresponding to the eighth data block.

16. The method of any one of claims 1-15, wherein, The method further comprises: In response to the target request operation being a write-back request operation and the eighth data block being in an exclusive state in the first-level private cache, the eighth data block is adjusted to a shared state, and the eighth data block is written back to the second-level private cache.

17. The method of claim 14, wherein, The method further comprises: The second-level private cache is marked as an owner node of the seventh data block.

18. The method of any one of claims 1-17, wherein, The method further comprises: In response to the target request operation being an invalidation and write-back request operation, it is identified whether a ninth data block of the invalidation and write-back request operation in a second-level private cache is in an exclusive state, and whether a tenth data block associated with the invalidation and write-back request operation in a first-level private cache corresponding to the second-level private cache exists, wherein the invalidation and write-back request operation is a request operation sent by a cache directory to the second-level private cache; In response to the tenth data block associated with the invalidation and write-back request operation existing in the first-level private cache, the tenth data block is invalidated and written back to the second-level private cache; In response to the ninth data block being identified as the exclusive state, after the tenth data block is written back to the second-level private cache, the ninth data block is invalidated and written back, and an invalidation and write-back response corresponding to the invalidation and write-back request operation is sent to the cache directory.

19. The method of any one of claims 1-18, wherein, The method further comprises: In response to the target request operation being an invalidation and write-back request operation and the tenth data block being in an exclusive state, the second-level private cache sends an invalidation and write-back request operation to a corresponding second exclusive processor core, wherein the second exclusive processor core is a processor core that exclusively occupies a backup data block of the tenth data block, a ninth data block is obtained based on replacement of the tenth data block in the second-level private cache, and the ninth data block and the tenth data block are in a containment relationship.

20. The method of any one of claims 1-19, wherein, The method further comprises: In response to the target request operation being invalid and a write-back request operation, and the tenth data block being in an exclusive state, invalidating the tenth data block, and sending a corresponding write-back response to a secondary private cache to write the tenth data block back to the secondary private cache.

21. The method of any one of claims 1-20, wherein, The method further includes: obtaining a directory state of an eleventh data block corresponding to the first replacement request operation in a cache directory; in response to the directory state being valid and clean, invalidating a backup data block in a secondary private cache that owns a backup of the eleventh data block; in response to the directory state being valid and dirty, invalidating a backup data block in a secondary private cache that owns a backup of the eleventh data block and is a non-owner node.

22. The method of claim 21, wherein, The method further includes: in response to the directory state being valid and dirty, sending an invalidation and write-back request to a third exclusive processor core or an owner node of the eleventh data block.

23. An access device of a multi-level cache storage system, the device comprising: an obtaining module configured to obtain a target request operation of a multi-level cache storage system; a determining module configured to, in response to the target request operation being a first replacement request operation, obtain a replacement area of the first replacement request operation in the multi-level cache storage system to determine a target write-back area of the first replacement request operation in the multi-level cache storage system; a replacement write-back module configured to obtain a first data block of the first replacement request operation in the replacement area, and replace and write back the first data block to the target write-back area.

24. An electronic device, comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1-22 when executing the program.

25. A computer readable storage medium having stored thereon a computer program, wherein the program is executable by a processor to implement the method of any one of claims 1-22.

Images