Processing method and apparatus for write request, and device and medium

Abstract

The present disclosure relates to the technical field of data processing. Provided are a processing method and apparatus for a write request, and a device and a medium. The method comprises: acquiring a data block state of a first candidate data block in a first-level private cache for a first write request, wherein the first-level private cache belongs to a first processor core; on the basis of the data block state, identifying whether the first write request encounters a write miss in the first-level private cache; and in response to identifying that the first write request encounters a write miss in the first-level private cache, acquiring a target write data block for the first write request by means of a second-level private cache of the first processor core.

Description

Method, device, equipment and medium for processing write request

[0001] Cross-reference to related applications

[0002] The present disclosure is based on and claims priority from Chinese Patent Application No. 202411096641.1 filed on August 12, 2024, the content of which is hereby incorporated by reference in its entirety into the present disclosure. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of data processing, and in particular to a method, device, equipment and medium for processing write request. BACKGROUND

[0004] With the development of technology, the number of processor cores integrated on a chip is increasing, and when accessing a multi-level cache storage system on the chip, an access request may not hit, resulting in a decrease in the performance of a multi-core processor.

[0005] Therefore, how to improve the hit rate of an access request in a multi-level cache storage system is very important. SUMMARY

[0006] The present disclosure aims to at least partially solve one of the technical problems in the related art.

[0007] To this end, a first aspect of the present disclosure provides a method for processing write request.

[0008] A second aspect of the present disclosure provides a device for processing write request.

[0009] A third aspect of the present disclosure provides an electronic device.

[0010] A fourth aspect of the present disclosure provides a computer-readable storage medium.

[0011] The first aspect of the present disclosure provides a method for processing write request, the method comprising: obtaining a data block state of a first candidate data block of a first write request in a first private cache, wherein the first private cache belongs to a first processor core; identifying whether the first write request is write-invalidation in the first private cache according to the data block state; and in response to identifying that the first write request is write-invalidation in the first private cache, obtaining a target write data block of the first write request through a second private cache on the first processor core.

[0012] The second aspect of the present disclosure provides a processing device of a write request, which comprises: a first obtaining module, configured to obtain a data block state of a first candidate data block of a first write request in a first private cache, wherein the first private cache belongs to a first processor core; an identifying module, configured to identify whether the first write request is write invalid in the first private cache according to the data block state; and a second obtaining module, configured to obtain a target write data block of the first write request through a second private cache on the first processor core in response to identifying that the first write request is write invalid in the first private cache.

[0013] The third aspect of the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the processing method of the write request according to the first aspect.

[0014] To achieve the above object, the fourth aspect of the present disclosure provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the program is executable on a processor to implement the processing method of the write request according to the first aspect.

[0015] The processing method, device, equipment and medium of the write request according to the embodiments of the present disclosure obtain the data block state of the first candidate data block of the first write request in the first private cache, and when it is identified according to the data block state that the first write request is write invalid in the first private cache, the target write data block of the first write request can be obtained through the second private cache corresponding to the first private cache. In the present disclosure, whether the first write request is write invalid in the first private cache is identified through the data block state, which simplifies the identification and determination method of write invalidity. In the scenario that the first write request is write invalid in the first private cache, the target write data block of the first write request is obtained through the second private cache, which improves the hit rate of the write request in the multi-level cache storage system, optimizes the processing method of the write request, adopts different write allocation strategies for write data in different cache levels, improves the utilization rate of cache storage resources at each level, and thus improves the performance of the multi-core processor.

[0016] It should be understood that the content described in the present disclosure is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent through the following description of the embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present disclosure will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0018] FIG. 1 is a flowchart of a processing method of a write request according to an embodiment of the present disclosure;

[0019] FIG. 2 is a schematic diagram of a multi-level cache storage system according to an embodiment of the present disclosure;

[0020] FIG. 3 is a flowchart of a method for processing a write request according to another embodiment of the present disclosure;

[0021] FIG. 4 is a schematic diagram of a processing device for processing a write request according to an embodiment of the present disclosure;

[0022] FIG. 5 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, in which like or similar elements are denoted by the same or similar reference numerals, and therefore the same or similar elements are not described in detail again. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be understood as limiting the present disclosure.

[0024] FIG. 1 is a flowchart of a method for processing a write request according to an embodiment of the present disclosure, as shown in FIG. 1, the method comprises:

[0025] S101, obtaining a data block state of a first candidate data block of a first write request in a first private cache, wherein the first private cache belongs to a first processor core.

[0026] In the embodiments of the present disclosure, the multi-level cache storage system can include a private cache and a shared cache. As an example, as shown in FIG. 2, in the multi-level cache storage system shown in FIG. 2, a first private cache and a second private cache on a processor core 1 shown in FIG. 2, and a shared cache shown in FIG. 2 are included.

[0027] The first private cache and the second private cache on each processor core can realize data interaction through the routing node shown in FIG. 2, and data coordination between the caches can be realized through the routing node shown in FIG. 2, thereby realizing the composition of the multi-level cache storage system.

[0028] Optionally, the write request received by the multi-level cache storage system can be marked as a first write request, and the data block accessed by the first write request in the first private cache receiving the first write request can be marked as a first candidate data block in the first private cache.

[0029] In the embodiments of the present disclosure, the first candidate data block has a corresponding state, and the state information can be marked as the data block state of the first candidate data block. The data block state can be a shared state, an exclusive state, or an invalid state, which is not limited here.

[0030] It should be noted that the first private cache receiving the first write request can mark the processor core to which the first private cache belongs as the first processor core.

[0031] As an example, as shown in FIG. 2, it is assumed that the first private cache shown in FIG. 2 is the first private cache receiving the first write request, and the processor core to which the first private cache belongs is the processor core 1 shown in FIG. 2. In this example, the processor core 1 shown in FIG. 2 can be marked as the first processor core.

[0032] S102, according to the data block state, identifying whether the first write request is write invalid in the first private cache.

[0033] In the embodiment of the present disclosure, for the data block accessed by the write request in the first private cache, when the data block is in the exclusive state, the write request can implement the write operation on the data block, and the write request can hit in the first private cache.

[0034] In this scenario, the data block state of the first candidate data block needs to be analyzed to identify whether the first write request hits in the first private cache, wherein the miss state can be marked as a write invalid state.

[0035] It can be understood that when it is identified according to the data block state that the first candidate data block is not in the exclusive state in the first private cache, it is determined that the first write request misses in the first private cache, that is, the first write request is write invalid in the first private cache in this scenario.

[0036] S103, in response to identifying that the first write request is write invalid in the first private cache, obtaining the target write data block of the first write request through the second private cache on the first processor core.

[0037] In the embodiment of the present disclosure, the levels of caches in the multi-level cache storage system can be Non-Inclusive, that is, the data blocks existing in the upper level cache can exist in the lower level cache, or can not exist in the lower level cache.

[0038] In this scenario, when the first write request is write invalid in the first private cache, the corresponding second private cache of the first private cache in the multi-level cache storage system can be obtained, and the data block that can hit the first write request can be obtained from the levels of caches in the multi-level cache storage system through the second private cache, and the data block is the target write data block of the first write request.

[0039] It can be understood that when the data block that can hit the first write request exists in the second private cache, the data block can be determined as the target write data block of the first write request.

[0040] When the data block that can be hit by the first write request does not exist in the secondary private cache, the data block that can be hit by the first write request is obtained from the shared cache or the memory in the multi-level cache storage system through the secondary private cache, as the target write data block of the first write request.

[0041] The processing method of the write request provided in the disclosure obtains the data block state of the first candidate data block of the first write request in the primary private cache. When it is identified that the first write request is write-invalidation in the primary private cache according to the data block state, the target write data block of the first write request can be obtained through the secondary private cache corresponding to the primary private cache. In the disclosure, whether the first write request is write-invalidation in the primary private cache is identified through the data block state, which simplifies the identification and determination method of write-invalidation. In the scenario that the first write request is write-invalidation in the primary private cache, the target write data block of the first write request is obtained through the secondary private cache, which improves the hit rate of the write request in the multi-level cache storage system and optimizes the processing method of the write request.

[0042] In the above embodiment, the processing method of the write request can be further understood in combination with FIG. 3. FIG. 3 is a flowchart of the processing method of the write request according to another embodiment of the disclosure. As shown in FIG. 3, the method comprises the following steps.

[0043] S301, identifying whether the first write request is write-invalidation in the primary private cache according to the data block state.

[0044] Optionally, in response to the data block state indicating that the first candidate data block does not exist in the primary private cache, it is determined that the first write request is write-invalidation in the primary private cache.

[0045] In the embodiment of the disclosure, the first candidate data block that the first write request wants to access in the primary private cache may not exist in the primary private cache.

[0046] In this scenario, when it is identified that the first candidate data block does not exist in the primary private cache according to the data block state, it can be determined that the first write request is not hit in the primary private cache, and thus it can be determined that the first write request is write-invalidation in the primary private cache.

[0047] Optionally, in response to the data block state indicating that the first candidate data block is in a non-writable state in the primary private cache, it is determined that the first write request is write-invalidation in the primary private cache, wherein the non-writable state includes one of a shared state and an invalid state.

[0048] In the embodiments of the present disclosure, when the data block is in an exclusive state, it can be determined that the data block is writable. In this scenario, when it is identified according to the data block state that the first candidate data block is in an invalid state or a shared state or other non-exclusive state in the level-1 private cache, it can be determined that the first candidate data block is in a non-writable state in the level-1 private cache.

[0049] Further, when it is identified that the first candidate data block is in a non-writable state in the level-1 private cache, it can be determined that the first write request is not hit in the level-1 private cache, so it can be determined that the first write request is identified as write invalidation in the level-1 private cache.

[0050] Optionally, in response to the data block state indicating that the first candidate data block is in a non-writable state, the amount of buffered data corresponding to the first write request is obtained. In response to the amount of buffered data being less than a preset amount of buffered data threshold, it is determined that the first write request is write invalidation in the level-1 private cache.

[0051] In the embodiments of the present disclosure, the level-1 private cache has a corresponding write invalidation request buffer area, which can be marked as a write buffer area. When the data in the write request fills one data row in the write buffer area, the data in the data row can be written into the corresponding data block.

[0052] In this scenario, when the data block state indicates that the first candidate data block is in a non-writable state, and the data of the write operation corresponding to the first write request cannot fill one data row in the write buffer area, it can be determined that the first write request is write invalidation.

[0053] In this scenario, the amount of data corresponding to the first write request can be obtained to obtain the amount of buffered data required when the first write request is written to the write buffer area, and the upper limit value of the amount of data that can be buffered in one data row in the write buffer area is obtained, and the upper limit value is marked as the amount of buffered data threshold. In this scenario, the amount of buffered data of the first write request and the amount of buffered data threshold can be compared. When the amount of buffered data is less than the amount of buffered data threshold, it can be determined that the write data corresponding to the first write request cannot fill one data row in the write buffer area, and it can be further determined that the first write request is write invalidation in the level-1 private cache.

[0054] In response to the amount of buffered data being equal to the amount of buffered data threshold, a data row write-back request of the first write request is generated and transmitted to the shared cache to write the write data in the first write request in the shared cache. The write data is not allocated for writing on the level-1 private cache and the level-2 private cache of the first processor core, and is not directly written to the memory. In the embodiments of the present disclosure, the amount of buffered data corresponding to the first write request can be equal to the amount of buffered data threshold of one data row in the write buffer area. In this scenario, the data carried in the first write request can be cached in one data row in the write buffer area, and the data row can be written into the multi-level cache storage system.

[0055] Optionally, a write back request corresponding to the data row can be generated and marked as a data row write back request of the first write request, and the data row write back request can be directly sent to the shared cache of the multi-level cache storage system to directly write the data in the data row into the shared cache.

[0056] It can be understood that, through the execution of the data row write back request, the write data in the first write request can be directly written into the shared cache, and at the same time, no write allocation is performed in the first-level private cache and the second-level private cache that receive the first write request.

[0057] In the present disclosure, different write allocation strategies are adopted for write data in different cache levels, which improves the utilization of cache storage resources at each level and thus improves the performance of the multi-core processor.

[0058] Optionally, in response to the cache directory receiving the data row write back request transmitted by the second-level private cache and the write data in the first write request being written into the shared cache, the cache directory returns a data row write back response to the second-level private cache.

[0059] In the embodiments of the present disclosure, when processing the data row write back request corresponding to the first write request, the multi-level cache storage system also transmits the corresponding data row request to the cache directory to maintain data consistency of the multi-level cache storage system.

[0060] Optionally, the corresponding data row write back request can be sent to the cache directory by the second-level private cache corresponding to the first-level private cache corresponding to the first write request.

[0061] In this scenario, the write data in the first write request can be directly written back to the shared cache, and then the cache directory can return corresponding response information to the second-level private cache after the write data in the first write request is written into the shared cache. The response information can be marked as a data row write back response corresponding to the data row write back request.

[0062] Optionally, in response to the data block state indicating that the first candidate data block is in the exclusive state, the first candidate data block is determined to be in the writable state, and it is determined that the first write request hits in the first-level private cache, the first candidate data block is determined as the target write data block of the first write request.

[0063] In the embodiments of the present disclosure, when the state of the data block accessed by any write request in the first-level private cache is in the exclusive state, the data block can realize the writing of the write data carried in the write request. The exclusive state can be understood as the writable state.

[0064] In this scenario, when the data block state indicates that the first candidate data block is in the exclusive state, it is determined that the first candidate data block is in the writable state, and then it is determined that the first write request hits in the level-1 private cache.

[0065] Further, the first candidate data block hit by the first write request can be determined as the target write data block of the first write request.

[0066] S302, in response to identifying that the first write request is write-missed in the level-1 private cache, obtaining, by the second private cache on the first processor core, the target write data block of the first write request.

[0067] Optionally, in response to the first write request being write-missed in the level-1 private cache, a second write request is generated.

[0068] In the embodiments of the present disclosure, when the first write request is write-missed in the level-1 private cache, a corresponding write request can be generated and transmitted to the second private cache corresponding to the level-1 private cache, so as to achieve the purpose of obtaining the target write data block through the second private cache.

[0069] Optionally, in response to the first write request being write-missed in the level-1 private cache, a second write request is generated.

[0070] Optionally, it is identified whether the second write request hits in the second private cache.

[0071] Optionally, in response to the second candidate data block in the second private cache being in the non-writable state, it is determined that the second write request is identified as not hitting in the second private cache, wherein the non-writable state includes one of the shared state and the invalid state.

[0072] In the present disclosure, the data block accessed by the second write request in the second private cache can be marked as the second candidate data block, wherein when the second candidate data block is in the non-writable state such as the shared state or the invalid state, it is determined that the second candidate data block cannot implement the writing of the data corresponding to the second write request.

[0073] Further, it is determined that the second write request does not hit in the second private cache.

[0074] Optionally, in response to the second candidate data block not existing in the second private cache, it is determined that the second write request is identified as not hitting in the second private cache.

[0075] In the embodiments of the present disclosure, the second candidate data block accessed by the second write request in the second private cache can also not exist in the second private cache, and then it is determined that the second write request does not hit in the second private cache in this scenario.

[0076] Optionally, in response to the second candidate data block corresponding to the second write request being in the exclusive state, it is determined that the second candidate data block is in the writable state, and it is determined that the first write request hits in the secondary private cache, and the second candidate data block is taken as the target write data block of the first write request.

[0077] In the embodiment of the present disclosure, when the second candidate data block is in the exclusive state, it can be determined that the second candidate data block is in the writable state, and the data in the second write request can be written into the second candidate data block.

[0078] In this scenario, it can be determined that the second write request hits in the secondary private cache, and further, it can be understood that the first write request hits in the secondary private cache, and further, the second candidate data block in the secondary private cache can be taken as the target write data block of the first write request.

[0079] Optionally, in response to identifying that the second write request does not hit in the secondary private cache, a third write request is generated.

[0080] In the embodiment of the present disclosure, when the second write request does not hit in the secondary private cache, the target write data block of the first write request can be obtained from the shared cache or the memory through the secondary private cache.

[0081] The second private cache can generate a write request mark based on the second write request as the third write request. It should be noted that the third write request can be sent to the shared cache, or can be sent to the cache directory of the multi-level cache storage system, which is not limited here.

[0082] Optionally, the target write data block of the first write request is obtained according to the third write request.

[0083] The third write request can be transmitted to the cache directory, and in this scenario, the directory information of the third write request in the cache directory of the multi-level cache storage system can be obtained, and the target write data block of the first write request can be obtained according to the directory information.

[0084] In the embodiment of the present disclosure, the request information carried in the third write request can be obtained, and the request information is compared with the information already stored in the cache directory of the multi-level cache storage system, and the information associated with the request information is filtered from all the information as the directory information of the third write request in the cache according to the comparison result.

[0085] Optionally, in response to the directory information indicating that the third candidate data block corresponding to the third write request is in the valid clean state, the third candidate data block is obtained from the second processor core as the target write data block, and invalid processing is performed on the third candidate data block on the second processor core, wherein the second processor core is a processor core that owns a backup of the third candidate data block among the remaining processor cores except the first processor core.

[0086] In the embodiment of the present disclosure, the directory information associated with the third write request in the cache directory exists in the associated data block in the multi-level cache storage system, and the data block can be marked as a third candidate data block corresponding to the third write request.

[0087] In this scenario, the related information of the third candidate data block can be obtained through the directory information, and when the directory information indicates that the third candidate data block is in a valid and clean state (valid-clean), the third candidate data block can be used as the target write data block of the first write request.

[0088] Among them, the processor core currently storing the third candidate data block and the processor core used for the backup data block of the third candidate data block in the multi-level cache storage system can be marked as a second processor core.

[0089] In order to enable the third candidate data block to be used as the target write data block of the first write request, when the third candidate data block is transmitted to the first processor core, invalidation processing needs to be performed on the third candidate data block on all second processor cores, so that the third candidate data block on the first processor core can be the exclusive data block of the first processor core.

[0090] Optionally, regarding the invalidation processing on the third candidate data block on the second processor core, the following can be understood in combination:

[0091] In some implementations, in response to the third candidate data block being in a shared state in the second-level private cache on the second processor core, and the third candidate data block existing in the first-level private cache on the second processor core, after invalidation processing is performed on the third candidate data block in the first-level private cache on the second processor core, invalidation processing is performed on the third candidate data block in the second-level private cache on the second processor core.

[0092] In the embodiment of the present disclosure, for any second processor core, when the third candidate data block on the second processor core is in a shared state in the second-level private cache on the second processor core, and the third candidate data block exists in the first-level private cache on the second processor core, invalidation processing can be performed on the third candidate data block in the first-level private cache, and then invalidation processing is performed on the third candidate data block in the second-level private cache on the second processor core.

[0093] In other implementations, in response to the third candidate data block being in a shared state in the second-level private cache on the second processor core, and the third candidate data block not existing in the first-level private cache on the second processor core, invalidation processing is performed on the third candidate data block in the second-level private cache on the second processor core.

[0094] In the embodiments of the present disclosure, for any second processor core, when the third candidate data block in the second-level private cache on the second processor core is in a shared state, and the first-level private cache on the second processor core does not exist the third candidate data block, the invalidation processing can be directly performed on the third candidate data block in the second-level private cache on the second processor core.

[0095] It should be noted that the data block state of the third candidate data block on the second processor core can be adjusted to an invalid state according to the data block state adjustment method in the related art, so as to realize the invalidation processing of the third candidate data block. The invalidation processing of the third candidate data block can also be realized according to other data block invalidation processing methods, which is not limited here.

[0096] Optionally, in response to the directory information indicating that the third candidate data block is in a valid-dirty state, the third candidate data block is obtained from the second processor core as a target write data block, and invalidation and write-back processing is performed on the third candidate data block on the second processor core, wherein the second processor core is a processor core that exclusively occupies the backup of the third candidate data block among the remaining processor cores except the first processor core, or is a processor core to which the owner node of the third candidate data block belongs.

[0097] In the embodiments of the present disclosure, when the specific information in the directory information records that the third candidate data block is in a valid-dirty state, it can be determined that the data in the third candidate data block needs to be written back.

[0098] In this scenario, the processor core can exclusively occupy the third candidate data block or serve as the owner node of the third candidate data block. The processor core that exclusively occupies the third candidate data block or serves as the owner node of the third candidate data block can be marked as the second processor core.

[0099] Optionally, the third candidate data block on the second processor core can be taken as a target write data block of the first write request, and the third candidate data block on the second processor core can be subjected to invalidation and write-back processing.

[0100] It can be understood that, in order to enable the third candidate data block to serve as an exclusively occupied data block on the first processor core, when the first processor core obtains the third candidate data block, the third candidate data block on the second processor core needs to be subjected to invalidation processing. Since the third candidate data block is in a valid-dirty state, the data in the third candidate data block needs to be subjected to write-back processing.

[0101] The invalidation and write-back processing of the third candidate data block can be understood in combination with the following content.

[0102] Optionally, in response to the third candidate data block being in an exclusive state in the second-level private cache on the second processor core and the third candidate data block existing in the first-level private cache on the second processor core, invalidating the third candidate data block in the first-level private cache on the second processor core and writing back to the second-level private cache on the second processor core, invalidating the third candidate data block in the second-level private cache on the second processor core, sending a write-back response to the cache directory, and writing back the third candidate data block.

[0103] In the embodiments of the present disclosure, when the third candidate data block exists in the first-level private cache on the second processor core and is in an exclusive state in the second-level private cache on the second processor core, the third candidate data block in the first-level private cache can be invalidated and written back.

[0104] The third candidate data block in the first-level private cache can be invalidated and written back, and the data stored in the third candidate data block in the first-level private cache can be written back to the third candidate data block in the second-level private cache on the second processor core, and then the third candidate data block in the second-level private cache can be written back and invalidated, thereby realizing invalidation and write-back of the third candidate data block on the second processor core.

[0105] It should be noted that the second processor core can send a write-back response to the cache directory, and the cache directory can send a corresponding write-back response to the second-level private cache that sent the third write request after receiving the write-back response from the second processor core, so as to take the third candidate data block as the target write data block of the first write request.

[0106] Optionally, in response to the directory information being empty or the directory information indicating that the third candidate data block is invalid, the target write data block corresponding to the third write request is obtained from the shared cache and / or the memory.

[0107] In the embodiments of the present disclosure, the third write request can not have corresponding target information in the cache directory, and this scenario can be marked as the directory information of the third write request being empty in the cache directory.

[0108] In addition, when the third write request has directory information in the cache directory, the data block state stored in the directory information can be in an invalid state.

[0109] In these two scenarios, it can be determined that the target write data block cannot be obtained through the cache directory, and in this scenario, the target write data block needs to be obtained through the shared cache and / or the memory in the multi-level cache storage system.

[0110] As a possible implementation manner, the second private cache can send the third write request to the memory, where a fourth candidate data block of the third write request in the memory can be obtained, and the fourth candidate data block is determined as the target write data block.

[0111] In the embodiments of the present disclosure, the data block accessed by the third write request in the memory can be marked as a fourth candidate data block, and the fourth candidate data block can be used as the target write data block of the first write request in the multi-level cache storage system.

[0112] It should be noted that writing the target write data block into only the second private cache can be understood as that, in the case of writing the target write data block into only the second private cache sending the third write request, the target write data block is the exclusive data block of the second private cache, and in this case, the second write request can hit in the second private cache, that is, the first write request corresponding to the second write request can hit in the first private cache corresponding to the second private cache.

[0113] Further, the target write data block is the target write data block of the first write request.

[0114] The processing method of the write request provided by the present disclosure obtains the data block state of the first candidate data block of the first write request in the first private cache, and when it is identified according to the data block state that the first write request is write invalid in the first private cache, the target write data block of the first write request can be obtained through the second private cache corresponding to the first private cache. In the present disclosure, whether the first write request is write invalid in the first private cache is identified through the data block state, which simplifies the identification and determination method of write invalidity. In the case that the first write request is write invalid in the first private cache, the target write data block of the first write request is obtained through the second private cache, which improves the hit rate of the write request in the multi-level cache storage system, optimizes the processing method of the write request, adopts different write allocation strategies for write data in different cache levels, improves the utilization rate of cache storage resources at each level, and thus improves the performance of the multi-core processor.

[0115] Corresponding to the processing method of the write request proposed in the above several embodiments, one embodiment of the present disclosure also proposes a processing device of a write request. Since the processing device of the write request proposed in the embodiments of the present disclosure corresponds to the processing method of the write request proposed in the above several embodiments, the implementation manners of the above processing method of the write request are also applicable to the processing device of the write request proposed in the embodiments of the present disclosure, which will not be described in detail in the following embodiments.

[0116] FIG. 4 is a structural schematic diagram of a processing device of a write request according to an embodiment of the present disclosure. As shown in FIG. 4, the processing device 400 of the write request includes a first obtaining module 41, an identification module 42, and a second obtaining module 43, where:

[0117] The first obtaining module 41 is configured to obtain a data block state of a first candidate data block of the first write request in a first private cache, wherein the first private cache belongs to the first processor core.

[0118] The identification module 42 is configured to identify whether the first write request is write-invalidation in the first private cache according to the data block state.

[0119] The second obtaining module 43 is configured to, in response to identifying that the first write request is write-invalidation in the first private cache, obtain the target write data block of the first write request through a second private cache on the first processor core.

[0120] In the embodiments of the present disclosure, the identification module 42 is further configured to: in response to the data block state indicating that the first candidate data block does not exist in the first private cache, determine that the first write request is write-invalidation in the first private cache; and in response to the data block state indicating that the first candidate data block is in a non-writable state in the first private cache, determine that the first write request is write-invalidation in the first private cache, wherein the non-writable state includes one of a shared state and an invalid state.

[0121] In the embodiments of the present disclosure, the identification module 42 is further configured to: in response to the data block state indicating that the first candidate data block is in a non-writable state, obtain a buffered data amount corresponding to the first write request; and in response to the buffered data amount being less than a pre-set buffered data amount threshold, determine that the first write request is write-invalidation in the first private cache.

[0122] In the embodiments of the present disclosure, the second obtaining module 43 is further configured to: in response to the first write request being write-invalidation in the first private cache, generate a second write request; identify whether the second write request hits in the second private cache; in response to identifying that the second write request does not hit in the second private cache, generate a third write request; and obtain the target write data block of the first write request according to the third write request.

[0123] In the embodiments of the present disclosure, the second obtaining module 43 is further configured to: in response to the second candidate data block of the second write request being in a non-writable state in the second private cache, determine that the second write request does not hit in the second private cache, wherein the non-writable state includes one of a shared state and an invalid state; and in response to the second candidate data block of the second write request not existing in the second private cache, determine that the second write request does not hit in the second private cache.

[0124] In the embodiments of the present disclosure, the second obtaining module 43 is further configured to: obtain directory information of the third write request in a cache directory of the multi-level cache storage system; and obtain the target write data block of the first write request according to the directory information.

[0125] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the directory information indicating that the third candidate data block corresponding to the third write request is in the valid clean state, obtaining the third candidate data block from the second processor core as the target write data block, and performing invalidation processing on the third candidate data block on the second processor core, wherein the second processor core is a processor core that owns the backup of the third candidate data block among the remaining processor cores except the first processor core; in response to the directory information indicating that the third candidate data block is in the valid dirty state, obtaining the third candidate data block from the second processor core as the target write data block, and performing invalidation and write-back processing on the third candidate data block on the second processor core, wherein the second processor core is a processor core that exclusively owns the backup of the third candidate data block among the remaining processor cores except the first processor core, or is a processor core to which the owner node of the third candidate data block belongs; and in response to the directory information being empty or the directory information indicating that the third candidate data block is invalid, obtaining the target write data block corresponding to the third write request from the shared cache and / or the memory.

[0126] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: obtaining the fourth candidate data block of the third write request in the memory, and determining the fourth candidate data block as the target write data block.

[0127] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: writing the target write data block only into the secondary private cache.

[0128] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the third candidate data block being in the shared state in the secondary private cache on the second processor core, and the third candidate data block existing in the primary private cache on the second processor core, performing invalidation processing on the third candidate data block in the primary private cache on the second processor core, and then performing invalidation processing on the third candidate data block in the secondary private cache on the second processor core; and in response to the third candidate data block being in the shared state in the secondary private cache on the second processor core, and the third candidate data block not existing in the primary private cache on the second processor core, performing invalidation processing on the third candidate data block in the secondary private cache on the second processor core.

[0129] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the third candidate data block being in the exclusive state in the secondary private cache on the second processor core, and the third candidate data block existing in the primary private cache on the second processor core, performing invalidation processing on the third candidate data block in the primary private cache on the second processor core and writing back to the secondary private cache on the second processor core, then performing invalidation processing on the third candidate data block in the secondary private cache on the second processor core, sending a write-back response to the cache directory, and writing back the third candidate data block.

[0130] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the buffer data amount being equal to the buffer data amount threshold, generate a data line write-back request of the first write request and transmit the data line write-back request to the shared cache to write the write data in the first write request in the shared cache, wherein the write data is not allocated in the first-level private cache and the second-level private cache on the first processor core, and is not directly written to the memory.

[0131] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the cache directory receiving the data line write-back request transmitted by the second-level private cache and the write data in the first write request being written in the shared cache, returning, by the cache directory, a data line write-back response to the second-level private cache.

[0132] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the data block state indicating that the first candidate data block is in the exclusive state, determining that the first candidate data block is in the writable state, and determining that the first write request hits in the first-level private cache; and taking the first candidate data block as the target write data block of the first write request.

[0133] In the embodiment of the present disclosure, the second obtaining module 43 is further configured to: in response to the second candidate data block corresponding to the second write request being in the exclusive state, determining that the second candidate data block is in the writable state, and determining that the first write request hits in the second-level private cache; and taking the second candidate data block as the target write data block of the first write request.

[0134] The processing device of the write request provided by the present disclosure obtains the data block state of the first candidate data block of the first write request in the first-level private cache. When it is identified according to the data block state that the first write request is write-missed in the first-level private cache, the target write data block of the first write request can be obtained through the second-level private cache corresponding to the first-level private cache. In the present disclosure, the write-missed identification and determination method is simplified by identifying whether the first write request is write-missed in the first-level private cache through the data block state. In the scenario that the first write request is write-missed in the first-level private cache, the target write data block of the first write request is obtained through the second-level private cache, the hit rate of the write request in the multi-level cache storage system is improved, and the processing method of the write request is optimized. Different write allocation strategies are adopted for write data in different cache levels, the utilization rate of the cache storage resources at each level is improved, and thus the performance of the multi-core processor is improved.

[0135] In order to implement the above-mentioned embodiments, the present disclosure further provides an electronic device 500, as shown in FIG. 5, which specifically can include a memory 51, a processor 52, and a computer program stored in the memory 51 and executable on the processor 52. When the processor 52 executes the program, the processing method of the write request shown in the above-mentioned embodiments is implemented.

[0136] To achieve the above-mentioned embodiments, the embodiments of the present disclosure further propose a computer readable storage medium, which stores a computer program. The program is executed by a processor to implement the processing method of the write request as shown in the above-mentioned embodiments.

[0137] In addition, the terms "first", "second", "third", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0138] In the description of the present disclosure, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0139] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present disclosure, and the person skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present disclosure.

Claims

1. A method for processing a write request, the method comprising: obtaining a data block state of a first candidate data block of a first write request in a first private cache, wherein the first private cache belongs to a first processor core; identifying whether the first write request is write-missed in the first private cache according to the data block state; in response to identifying that the first write request is write-missed in the first private cache, obtaining a target write data block of the first write request through a second private cache on the first processor core.

2. The method of claim 1, wherein, The identifying whether the first write request is write-missed in the first private cache according to the data block state comprises: in response to the data block state indicating that the first candidate data block does not exist in the first private cache, determining that the first write request is write-missed in the first private cache; in response to the data block state indicating that the first candidate data block is in a non-writable state in the first private cache, determining that the first write request is write-missed in the first private cache, wherein the non-writable state comprises one of a shared state and an invalid state.

3. The method of claim 2, wherein, The method further comprises: in response to the data block state indicating that the first candidate data block is in the non-writable state, obtaining a buffered data amount corresponding to the first write request; in response to the buffered data amount being less than a pre-set buffered data amount threshold, determining that the first write request is write-missed in the first private cache.

4. The method of any one of claims 1-3, wherein, The obtaining a target write data block of the first write request through a second private cache on the first processor core in response to identifying that the first write request is write-missed in the first private cache comprises: in response to the first write request being write-missed in the first private cache, generating a second write request; identifying whether the second write request hits in the second private cache; in response to identifying that the second write request does not hit in the second private cache, generating a third write request; obtaining the target write data block of the first write request according to the third write request.

5. The method of claim 4, wherein, The identifying whether the second write request hits in the second private cache comprises: in response to a second candidate data block of the second write request being in a non-writable state in the second private cache, determining that the second write request does not hit in the second private cache, wherein the non-writable state comprises one of a shared state and an invalid state; in response to the second candidate data block of the second write request not existing in the second private cache, determining that the second write request does not hit in the second private cache.

6. The method of claim 4, wherein, The obtaining the target write data block of the first write request according to the third write request comprises: obtaining directory information of the third write request in a cache directory of a multi-level cache storage system; obtaining the target write data block of the first write request according to the directory information.

7. The method of claim 6, wherein, The obtaining the target write data block of the first write request according to the directory information comprises: in response to the directory information indicating that the third candidate data block corresponding to the third write request is in a valid clean state, obtaining the third candidate data block from the second processor core as the target write data block, and invalidating the third candidate data block on the second processor core, wherein the second processor core is a processor core that owns a backup of the third candidate data block among the remaining processor cores except the first processor core; in response to the directory information indicating that the third candidate data block is in a valid dirty state, obtaining the third candidate data block from the second processor core as the target write data block, and invalidating and writing back the third candidate data block on the second processor core, wherein the second processor core is a processor core that exclusively owns a backup of the third candidate data block among the remaining processor cores except the first processor core, or is a processor core to which the owner node of the third candidate data block belongs; in response to the directory information being empty or the directory information indicating that the third candidate data block is invalid, obtaining the target write data block corresponding to the third write request from a shared cache and / or memory.

8. The method of claim 4, wherein, The target write data block of the first write request obtained according to the third write request comprises: obtaining a fourth candidate data block of the third write request in the memory, and determining the fourth candidate data block as the target write data block.

9. The method of claim 8, wherein, After the fourth candidate data block of the third write request in the memory is obtained, and the fourth candidate data block is determined as the target write data block, the method further comprises: writing the target write data block only into the second private cache.

10. The method of claim 7, wherein, The invalidating the third candidate data block on the second processor core comprises: in response to the third candidate data block being in a shared state in the second private cache on the second processor core, and the third candidate data block existing in the first private cache on the second processor core, invalidating the third candidate data block in the first private cache on the second processor core, and then invalidating the third candidate data block in the second private cache on the second processor core; in response to the third candidate data block being in a shared state in the second private cache on the second processor core, and the third candidate data block not existing in the first private cache on the second processor core, invalidating the third candidate data block in the second private cache on the second processor core.

11. The method of claim 7, wherein, The invalidating and writing back the third candidate data block on the second processor core comprises: in response to the third candidate data block being in an exclusive state in the second level private cache on the second processor core and the third candidate data block existing in a first level private cache on the second processor core, invalidating the third candidate data block in the first level private cache on the second processor core and writing back to the second level private cache on the second processor core, then invalidating the third candidate data block in the second level private cache on the second processor core, sending a write back acknowledgement to the cache directory, and writing back the third candidate data block.

12. The method of claim 3, wherein, The method further includes: in response to the buffer data amount being equal to the buffer data amount threshold, generating a data line write back request of the first write request and transmitting to a shared cache to write the write data in the first write request in the shared cache, wherein the write data is not allocated in the first level private cache and the second level private cache on the first processor core and is not directly written to a memory.

13. The method of claim 12, wherein, The method further includes: in response to the cache directory receiving the data line write back request transmitted by the second level private cache and the write data in the first write request being written in the shared cache, the cache directory returning a data line write back acknowledgement to the second level private cache.

14. The method of any one of claims 1-13, wherein, The method further includes: in response to the data block state indicating that the first candidate data block is in an exclusive state, determining that the first candidate data block is in a writable state, and determining that the first write request hits in the first level private cache; taking the first candidate data block as the target write data block of the first write request.

15. The method of claim 4, wherein, The method further includes: in response to the second candidate data block corresponding to the second write request being in an exclusive state, determining that the second candidate data block is in a writable state, and determining that the first write request hits in the second level private cache; taking the second candidate data block as the target write data block of the first write request.

16. An apparatus for processing a write request, the apparatus comprising: a first obtaining module configured to obtain a data block state of a first candidate data block of a first write request in a first level private cache, wherein the first level private cache belongs to a first processor core; an identifying module configured to identify whether the first write request is write-invalidate in the first level private cache according to the data block state; a second obtaining module configured to, in response to identifying that the first write request is write-invalidate in the first level private cache, obtain a target write data block of the first write request through a second level private cache on the first processor core.

17. An electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1-15 when executing the program.

18. A computer readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1-15.

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