Gate annealing method for ferroelectric transistor, gate structure, and ferroelectric transistor

Abstract

The present disclosure provides a gate annealing method for a ferroelectric transistor. The method comprises: forming an N / P-well layer, a source, and a drain on a substrate, wherein the source and the drain are formed at two ends of the N / P-well layer; forming a laser reflection layer by deposition in a source region and a drain region; depositing a ferroelectric material in a gate region by means of an atomic layer deposition process to form a ferroelectric layer, and performing a surface nitrogen enrichment treatment on the ferroelectric layer to form an interfacial nitrogen adsorption layer on the surface of the ferroelectric layer; depositing titanium nitride as a cap layer on the ferroelectric layer on which the interfacial nitrogen adsorption layer is formed, so as to ensure the phase stability of the ferroelectric layer, and by means of a laser annealing treatment, inducing the ferroelectric layer to generate a ferroelectric phase; and depositing a conductive metal on the cap layer to form a gate metal stack. The present disclosure further provides a gate structure obtained by the gate annealing method, and a ferroelectric transistor.

Description

Gate annealing method of ferroelectric transistor and gate structure and ferroelectric transistor TECHNICAL FIELD

[0001] The present disclosure belongs to the field of microelectronics, and in particular to a gate annealing method of ferroelectric transistor and gate structure and ferroelectric transistor. BACKGROUND

[0002] The rapid development of big data and artificial intelligence has put forward higher requirements for data storage, which has forced the development of new memory devices other than charge media, such as resistive random access memory (ReRAM), phase change memory (PCRAM) and ferroelectric memory (FeRAM), to become a research focus in the field of microelectronics, in order to meet the demand for low power consumption, high speed and high reliability in non-volatile storage, in-memory computing and brain-like computing.

[0003] In related technologies, doped HfO2 has been proven to be able to stimulate ferroelectric properties, so doped hafnium-based ferroelectric materials have been widely studied and attempted to be applied in 1T1C memory technology (Ferroelectric RAM, FeRAM) and 1T ferroelectric gate field effect transistor (ferroelectric field-effect transistors, FeFETs) to solve the problem of difficulty in miniaturization of classical perovskite ferroelectric materials.

[0004] However, there are still various problems in the current research of FeFET: first, the fatigue problem. In order to make doped hafnium-based oxides exhibit ferroelectric properties, a metal cap layer is needed to provide tensile stress to stabilize the ferroelectric orthorhombic phase (O phase) and tetragonal phase (T phase). Considering the compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process, titanium nitride is usually chosen as the top electrode, but the titanium element will absorb the oxygen element in the hafnium-based oxide, causing a large number of oxygen vacancies near the interface between the top electrode and the ferroelectric layer. These oxygen vacancies will gather under the action of field stress, forming a built-in field pinning effective ferroelectric flipping domain, causing fatigue of the ferroelectric. Second, the problem of thermal crosstalk. Hafnium-based ferroelectric materials need to be annealed at a high temperature (about 500℃) to activate the ferroelectric phase. This is a relatively high thermal budget requirement for the source and drain of small size devices and silicides, and the ferroelectric crystallization has an adverse effect on the source and drain impurity distribution and the silicide, changing the device performance. At the same time, long time high temperature annealing will also cause the aggregation of oxygen vacancies in the ferroelectric layer, causing fatigue.

[0005] In summary, interface oxygen vacancy regulation is needed to alleviate the fatigue problem, and low thermal budget, short holding time and large cooling rate annealing methods are used to regulate the oxygen vacancies in the body and alleviate the problem of thermal crosstalk.

[0006] Therefore, it has far-reaching practical significance to develop a method for activating ferroelectric phase of hafnium-based ferroelectric material with low thermal budget (annealing temperature less than 500 DEG C, annealing time less than seconds), and to improve the fatigue phenomenon of ferroelectric transistor. SUMMARY

[0007] Therefore, to solve the above and other problems in the related art, the present disclosure provides a gate annealing method of ferroelectric transistor, comprising:

[0008] forming an N / P well layer, a source and a drain on a substrate, wherein the source and the drain are formed at two ends of the N / P well layer;

[0009] depositing a laser reflection layer in the source region and the drain region;

[0010] depositing a ferroelectric material in the gate region by atomic layer deposition process to form a ferroelectric layer, and performing surface nitrogen enrichment treatment on the upper surface of the ferroelectric layer to form an interface nitrogen adsorption layer on the upper surface of the ferroelectric layer;

[0011] depositing titanium nitride as a cap layer on the ferroelectric layer with the interface nitrogen adsorption layer to ensure the phase stability of the ferroelectric layer, and inducing the ferroelectric layer to generate ferroelectric phase by laser annealing treatment;

[0012] depositing a conductive metal on the cap layer to form a gate metal stack.

[0013] According to the embodiment of the present disclosure, in the laser annealing treatment, the laser wavelength is 200-527 nm, the laser power is 3-5 W, and the laser current is 9.8-10.2 A.

[0014] According to the embodiment of the present disclosure, in the nitrogen enrichment treatment, the nitrogen enrichment atmosphere is ammonia, and the nitrogen enrichment treatment time is 1-15 min; the flow rate of ammonia is 200-300 sccm.

[0015] According to the embodiment of the present disclosure, the deposition of the laser reflection layer in the source region and the drain region in the aforementioned gate annealing method comprises:

[0016] depositing silicon nitride in the source region and the drain region respectively as gate isolation, and then sequentially depositing tungsten and silicon dioxide, and then removing the silicon dioxide and tungsten in the gate region, and the tungsten in the source region and the drain region as the laser reflection layer to protect the source and the drain.

[0017] According to the embodiment of the present disclosure, the conductive metal is tungsten.

[0018] According to the embodiment of the present disclosure, the aforementioned gate annealing method further comprises sequentially performing photolithography and etching on the gate metal stack to obtain a gate electrode with a target pattern.

[0019] According to an embodiment of the present disclosure, the etching process removes the laser reflection layer of the source region and the drain region.

[0020] According to an embodiment of the present disclosure, the ferroelectric material is hafnium oxide with a doping element, and the doping element includes one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.

[0021] In another aspect of the present disclosure, a gate structure of a ferroelectric transistor prepared according to the aforementioned gate annealing method is provided, which includes a gate oxide layer, a ferroelectric layer, a cap layer, and a gate metal stack. The gate oxide layer is adapted to form an insulating structure to reduce gate leakage, enhance the control of channel carriers by the gate voltage, and control the switching and working current of the ferroelectric transistor. The ferroelectric layer is formed on the gate oxide layer and has a ferroelectric phase to adjust the threshold voltage drift of the channel current according to the change of the polarization state of the ferroelectric layer in response to the gate voltage signal. The cap layer is formed on the ferroelectric layer and is adapted to stabilize the orthorhombic phase of the ferroelectric phase in the ferroelectric layer to enhance the ferroelectric properties of the ferroelectric layer. The gate metal stack is formed on the cap layer and is adapted to receive an external voltage.

[0022] In another aspect of the present disclosure, a ferroelectric transistor is provided, which includes a substrate, an N / P well layer, a source, a gate, and a drain. The N / P well layer is formed on the substrate and is adapted to isolate the channel carriers from the substrate to avoid the latch-up effect. The source is formed at one end of the N / P well layer. The gate has the aforementioned gate structure and is formed in the middle of the N / P well layer and serves as a gate. The gate metal stack of the gate stack structure polarizes the ferroelectric layer under the application of an external voltage, so that the gate structure outputs a gate voltage to control the carrier state of the channel structure and realize the switching of the ferroelectric transistor. The drain is formed at the other end of the N / P well layer.

[0023] According to an embodiment of the present disclosure, the gate annealing method proposed in the present disclosure alleviates the fatigue problem and the thermal crosstalk problem by regulating the oxygen vacancies in the body and on the surface of the ferroelectric phase. Specifically, after the atomic layer deposition (ALD) ferroelectric layer, an interface nitrogen enrichment treatment is performed in situ on the surface of the ferroelectric layer in a nitrogen-rich atmosphere of ammonia to obtain a ferroelectric layer with an interface nitrogen adsorption layer. The interface nitrogen adsorption layer inhibits the cap layer from absorbing oxygen from the ferroelectric layer, thereby reducing the generation of oxygen vacancies at the interface of the ferroelectric layer. Since the process of inhibiting titanium element from absorbing oxygen by NH3 treatment and the process of promoting titanium element from absorbing oxygen by high-temperature rapid thermal annealing are in a competitive relationship, the nitrogen enrichment treatment needs to be performed at a low thermal budget to be effective. Therefore, a nanosecond-level short-wave laser annealing scheme is designed in the present disclosure to activate the ferroelectric phase. The extremely fast temperature rising and falling rate of the laser annealing scheme does not allow the oxygen vacancies to have enough time to gather in the body of the ferroelectric layer, thereby achieving the purpose of regulating the oxygen vacancies in the body. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a preparation flow chart of a gate annealing method of a ferroelectric transistor in an embodiment of the present disclosure;

[0025] Figure 2 is a scanning electron microscope image of a ferroelectric phase material in Test Example 1 of the present disclosure;

[0026] Figure 3 is a scanning electron microscope image of a ferroelectric phase material in Test Example 2 of the present disclosure;

[0027] Figure 4 is a scanning electron microscope image of a ferroelectric phase material in Test Example 3 of the present disclosure;

[0028] Figure 5 is a polarization test graph of a ferroelectric material in Comparative Example 3 of the present disclosure subjected to 10 3 times of wake-up cycles;

[0029] Figure 6 is a polarization test graph of a ferroelectric material in Comparative Example 3 of the present disclosure subjected to 10 8 times of fatigue cycles;

[0030] Figure 7 is a cross-sectional schematic view of a well oxide layer in Embodiment 1 of the present disclosure;

[0031] Figure 8 is a cross-sectional schematic view of an N / P well layer formed on the basis of Figure 7 in Embodiment 1 of the present disclosure;

[0032] Figure 9 is a cross-sectional view of an isolation structure formed on the basis of Figure 8 in Embodiment 1 of the present disclosure;

[0033] Figure 10 is a cross-sectional schematic view of a gate oxide layer formed on the basis of Figure 9 in Embodiment 1 of the present disclosure;

[0034] Figure 11 is a cross-sectional schematic view of a pseudo-gate and hard mask stack formed on the basis of Figure 10 in Embodiment 1 of the present disclosure;

[0035] Figure 12 is a cross-sectional schematic view of a side wall formed on the basis of Figure 11 in Embodiment 1 of the present disclosure;

[0036] Figure 13 is a cross-sectional schematic view of a source / drain impurity distribution formed on the basis of Figure 12 in Embodiment 1 of the present disclosure;

[0037] Figure 14 is a cross-sectional schematic view of a source / drain silicide formed on the basis of Figure 13 in Embodiment 1 of the present disclosure;

[0038] Figure 15 is a cross-sectional schematic view of a laser reflection layer formed on the basis of Figure 14 in Embodiment 1 of the present disclosure;

[0039] Figure 16 is a cross-sectional schematic view of a gate position formed on the basis of Figure 15 in Embodiment 1 of the present disclosure;

[0040] Figure 17 is a cross-sectional schematic view of a nitrogen-rich treatment performed on the basis of Figure 16 in Embodiment 1 of the present disclosure;

[0041] FIG. 18 is a cross-sectional schematic view of laser annealing based on FIG. 17 in Embodiment 1 of the present disclosure;

[0042] FIG. 19 is a cross-sectional schematic view of forming a gate metal stack based on FIG. 18 in Embodiment 1 of the present disclosure;

[0043] FIG. 20 is a cross-sectional schematic view of forming a gate lithography based on FIG. 19 in Embodiment 1 of the present disclosure;

[0044] FIG. 21 is a cross-sectional schematic view of forming a ferroelectric transistor based on FIG. 20 in Embodiment 1 of the present disclosure.

[0045] In the drawings of the present disclosure, the meanings of the reference numerals are as follows: 1 - substrate; 101 - ion implantation layer; 2 - well oxygen layer, 21 - gate oxide layer; 31 - dummy gate; 32 - silicon dioxide layer; 33 - silicon nitride layer; 4 - side wall; 51 - source impurity region; 52 - drain impurity region; 61 - source silicide layer; 62 - drain silicide; 7 - laser reflection layer; 8 - gate position; 9 - ferroelectric layer; 10 - cap layer; 11 - gate metal stack; 12 - gate; 13 - spacer layer; 14 - via interconnection metal; 15 - electrode; 16 - source; 17 - drain. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below with reference to specific embodiments and drawings.

[0047] The endpoints of the ranges and any values disclosed in the present disclosure are not limited to the precise values stated. The ranges or values should be construed to be approximations that allow for significant figures to account for minor variations among the values. The endpoints of the ranges of values will preferentially be read to be not only the precise values stated, but also to also encompass values approximating the stated endpoints. The ranges of values will also preferably be construed as not limited to the precise values stated, but also to encompass values approximating the stated ranges.

[0048] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "includes" and tautological equivalents thereof, means that the claimed features, steps, operations, and / or components are among the various components that are specifically recited in the claims.

[0049] All terms used herein including technical and scientific terms have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein are not intended to have any ideologically or overly formal meanings, but should be interpreted in a manner consistent with the context of the present specification.

[0050] In the description of the present disclosure, it needs to be understood that the terms "longitudinal", "length", "circumferential", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and therefore cannot be understood as indicating or implying that the subsystems or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0051] Throughout the drawings, the same elements are denoted by the same or similar reference signs. When it can cause confusion in understanding the present disclosure, conventional structures or configurations will be omitted. Also, the shape, size, positional relationship of the components in the drawings do not reflect the true size, scale and actual positional relationship. In addition, in the present disclosure, any reference symbol located between parentheses should not be construed as limiting the present disclosure.

[0052] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure or description thereof. The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0053] In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present disclosure.

[0054] In the process of implementing the present disclosure, it is found that to alleviate the fatigue problem of ferroelectric transistors, it is necessary to reasonably regulate the interface oxygen vacancies of the ferroelectric layer to avoid the formation of built-in electric field pinning effective ferroelectric flipping domains due to the aggregation of oxygen vacancies, resulting in ferroelectric fatigue problems. For the problem of thermal crosstalk, a low thermal budget, short holding time and large cooling rate annealing method is needed to activate the ferroelectric phase.

[0055] Therefore, the present disclosure proposes a technical solution of "NH3 nitrogen-rich passivation + low thermal budget laser annealing" to reduce the oxygen vacancy defect concentration to simultaneously optimize the oxygen vacancies in the ferroelectric interface and the ferroelectric crystal. Among them, the NH3 nitrogen-rich passivation process optimizes the oxygen vacancies of the ferroelectric layer interface, and the low thermal budget laser annealing process optimizes the oxygen vacancies in the ferroelectric layer.

[0056] Figure 1 is a preparation flow chart of a gate annealing method of a ferroelectric transistor in an embodiment of the present disclosure.

[0057] The present disclosure proposes a gate annealing method of a ferroelectric transistor, as shown in Figure 1, comprising the following steps S101-S105:

[0058] Step S101: Forming an N / P well layer, a source 16 and a drain 17 on a substrate 1, wherein the source 16 and the drain 17 are formed at both ends of the N / P well layer;

[0059] Step S102: Depositing a laser reflection layer 7 in the source region and the drain region;

[0060] Step S103: Depositing a ferroelectric material in the gate region by an atomic layer deposition process to form a ferroelectric layer 9, and performing a surface nitrogen enrichment treatment on the upper surface of the ferroelectric layer 9 to form an interface nitrogen adsorption layer on the upper surface of the ferroelectric layer 9, the nitrogen enrichment treatment being as shown in Figure 17;

[0061] Step S104: Depositing titanium nitride as a cap layer 10 on the ferroelectric layer 9 with the interface nitrogen adsorption layer to ensure the phase stability of the ferroelectric layer 9, and inducing the ferroelectric layer 9 to generate a ferroelectric phase by laser annealing, the laser annealing being as shown in Figure 18;

[0062] Step S105: Depositing a conductive metal on the cap layer 10 to form a gate metal stack 11.

[0063] According to the embodiments of the present disclosure, the gate annealing method proposed by the present disclosure alleviates the fatigue problem and the thermal crosstalk problem by regulating the oxygen vacancies in the body and on the surface of the ferroelectric phase. Specifically, after the atomic layer deposition technology (ALD) ferroelectric layer 9, an interface nitrogen enrichment treatment is performed in situ on the surface of the ferroelectric layer 9 with ammonia as the nitrogen-enriched atmosphere, obtaining a ferroelectric layer 9 with an interface nitrogen adsorption layer, which will inhibit the cap layer from absorbing oxygen from the ferroelectric layer 9, reducing the generation of oxygen vacancies at the interface of the ferroelectric layer. Since the process of NH3 treatment inhibiting the oxygen absorption of titanium elements is in competition with the process of high-temperature rapid thermal annealing promoting the oxygen absorption of titanium elements, the advantage of ammonia treatment for improving fatigue needs to be manifested in low heat budget, therefore, a nanosecond (100-500 ns) short-wave laser annealing annealing scheme is designed in the present disclosure to activate the ferroelectric phase, and the extremely fast temperature rising and falling rate makes the oxygen vacancies not have enough time to gather in the body of the ferroelectric layer, thereby achieving the purpose of regulating the oxygen vacancies in the body. At the same time, it also meets the low heat budget requirement of ammonia passivation treatment, and can better highlight the advantage of NH3 interface passivation nitrogen enrichment treatment in improving fatigue.

[0064] In the present disclosure, the meaning of "in situ" is that after the ferroelectric layer is deposited by ALD, the nitrogen-rich passivation treatment is performed directly in the ALD chamber using the ammonia gas source of ALD.

[0065] According to an embodiment of the present disclosure, in the laser annealing process, the laser wavelength is 200-527 nm, for example, can be 200 nm, 300 nm, 400 nm, 500 nm, 527 nm, etc., the laser power is 3-5 W, for example, can be 3 W, 4 W, 5 W, etc., the corresponding current range is 9.8-10.2 A, preferably 10 A, and the corresponding laser power is 3.8 W.

[0066] According to an embodiment of the present disclosure, in the nitrogen-rich treatment, the nitrogen-rich atmosphere is ammonia, and the nitrogen-rich treatment time is 1-15 min, for example, can be 1 min, 5 min, 10 min, etc.; the flow rate of ammonia is 200-300 sccm, for example, can be 200 sccm, 250 sccm, 300 sccm, etc.

[0067] According to an embodiment of the present disclosure, the nitrogen element in the ammonia gas can be preferentially absorbed by the titanium element in the capping layer 10, thereby avoiding the absorption of the titanium element to the oxygen vacancies in the ferroelectric layer 9, and thereby achieving the regulation of the oxygen vacancies in the ferroelectric layer 9. After the ferroelectric layer 9 is deposited by ALD, some active attachment sites (usually some electrostatically suspended bonds) will appear at the interface of the ferroelectric layer 9. In situ NH3 treatment is performed in the ALD chamber, so that NH3 molecules can be adsorbed on the active sites due to electrostatic force, forming a nitrogen-rich interface. After subsequent deposition of TiN, the nitrogen-rich interface will preferentially react with Ti elements, preferentially occupying Ti elements, relieving the Ti elements from absorbing oxygen elements in the ferroelectric layer, and thereby achieving the regulation of the surface oxygen vacancies of the ferroelectric layer.

[0068] According to an embodiment of the present disclosure, in step S102, the deposition of the laser reflection layer 7 in the source region and the drain region in the aforementioned gate annealing method comprises: depositing silicon nitride in the source region and the drain region respectively as gate isolation, then depositing tungsten and silicon dioxide in turn, and then removing the silicon dioxide and the tungsten in the gate region, and the tungsten in the source region and the drain region as the laser reflection layer 7 to protect the source 16 and the drain 17.

[0069] According to an embodiment of the present disclosure, the silicon nitride can form isolation between the gate 12 and the source / drain on the one hand, and can be used as a pseudo gate to remove the stop layer of the previous CMP on the other hand.

[0070] According to an embodiment of the present disclosure, the use of tungsten as a cover layer can reflect most of the short-wave laser light, achieve precise regional selective laser irradiation, and only expose the ferroelectric material in the gate region to annealing, thereby avoiding the influence of the laser annealing heat budget of the ferroelectric crystallization on the source / drain impurity distribution and silicide.

[0071] According to an embodiment of the present disclosure, the conductive metal is tungsten.

[0072] According to an embodiment of the present disclosure, the aforementioned gate annealing method further comprises sequentially performing photolithography and etching on the gate metal stack 11 to obtain a gate 12 with a target pattern.

[0073] According to an embodiment of the present disclosure, the etching process removes the laser reflection layer in the source region and the drain region.

[0074] According to an embodiment of the present disclosure, the ferroelectric material is hafnium oxide with a doping element, and the doping element includes silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.

[0075] In another aspect of the present disclosure, a gate structure of a ferroelectric transistor prepared according to the aforementioned gate annealing method is provided, which includes a gate oxide layer 21, a ferroelectric layer 9, a cap layer 10, and a gate metal stack 11. The gate oxide layer 21 is adapted to form an insulating structure to reduce gate leakage, enhance the control of channel carriers by the gate voltage, and control the switching and working current of the ferroelectric transistor. The ferroelectric layer 9 is formed on the gate oxide layer 21, and has a ferroelectric phase to adjust the threshold voltage drift of the channel current according to the change of the polarization state of the gate voltage signal through the spontaneous polarization state. The cap layer 10 is formed on the ferroelectric layer 9, and is adapted to stabilize the orthorhombic phase of the ferroelectric phase crystallization of the ferroelectric layer 9 to enhance the ferroelectric properties of the ferroelectric layer 9. The gate metal stack 11 is formed on the cap layer 10, and is adapted to realize the interconnection of the gate electrode.

[0076] In another aspect of the present disclosure, a ferroelectric transistor is provided, which includes a substrate 1, an N / P well layer, a source 16, a gate 12, and a drain 17. The N / P well layer is formed on the substrate 1, and is adapted to isolate the channel carriers from the substrate to avoid the latch-up effect. The source 16 is formed at one end of the N / P well layer. The gate 12 has the aforementioned gate structure, and is formed in the middle of the N / P well layer and used as the gate 12. In the case of applying an external voltage, the ferroelectric layer 9 of the gate metal stack 11 of the gate structure is polarized, so that the gate structure outputs the gate voltage to control the carrier state of the channel structure and realize the switching of the ferroelectric transistor. The drain 17 is formed at the other end of the N / P well layer.

[0077] According to an embodiment of the present disclosure, when the gate structure obtained by applying the gate laser annealing method proposed in the present disclosure is used, the nitrogen element of the interface nitrogen adsorption layer of the ferroelectric transistor is preferentially absorbed by the titanium element in the cap layer 10 during operation, thereby ensuring the stability of the oxygen element in the ferroelectric layer 9, reducing the generation of oxygen vacancies, and ensuring the working stability of the ferroelectric transistor.

[0078] Test Example

[0079] In the implementation of the present disclosure, the feasibility of the "NH3 treatment + laser annealing" technical solution is verified on the ferroelectric capacitor, and the optimal condition is integrated in the FeFET.

[0080] FIGS. 2-4 are scanning electron micrographs of the ferroelectric phase material in Comparative Examples 1, 2, and 3, respectively, in the present test example.

[0081] In the present test example, three groups of controls were carried out respectively. The treatment of Comparative Example 1 was RTP annealing of the ferroelectric capacitor at 350°C for 60s, and the crystal structure is shown in FIG. 2; the treatment of Comparative Example 2 was 3-minute nitrogen-rich treatment in an ammonia atmosphere followed by RTP annealing of the ferroelectric capacitor at 350°C for 60s, and the crystal structure is shown in FIG. 3; the treatment of Comparative Example 3 was 3-minute nitrogen-rich treatment in an ammonia atmosphere followed by nanosecond laser annealing of the ferroelectric capacitor at 10A (corresponding to a laser power of 3.8W), and the crystal structure is shown in FIG. 3.

[0082] As can be seen from the comparison of Comparative Examples 1 and 2, the TiN and hafnium-zirconium-oxygen interface after 3-minute NH3 treatment is smoother and the interface oxide layer is thinner. As can be seen from the comparison of Comparative Examples 2 and 3, NLA (nanosecond laser annealing) does not deteriorate the smoothness of the TiN and hafnium-zirconium-oxygen interface, because the heating time is very short and the thermal damage is very small; at the same time, the ferroelectric grains activated by NLA are small, which may correspond to smaller ferroelectric remanent polarization, making it more suitable for small-size devices.

[0083] More specifically, the ferroelectric material obtained by different nitrogen-rich treatment time combined with nanosecond laser annealing was subjected to fatigue cycle treatment.

[0084] FIGS. 5 and 6 are polarization test graphs of the ferroelectric material in Comparative Example 3 of the present disclosure subjected to 10 3 times of wake-up cycle and 10 8 times of fatigue cycle, respectively, wherein p is the polarization value and V is the voltage value.

[0085] As shown in FIGS. 5 and 6, under NLA treatment, pure NH3 atmosphere can indeed effectively improve the remanent polarization (2Pr) of the ferroelectric phase material after wake-up cycle and fatigue cycle. Specifically, without nitrogen-rich treatment, the 2Pr after 10 3 times of wake-up cycle is 9.3, and the 2Pr after 10 8 times of fatigue cycle is 5.8. After 1, 2, and 3 minutes of NH3 treatment, respectively, the 2Pr after 10 3 times of wake-up cycle is increased by 25.8%, 29.0%, and 44.1%, respectively, and the 2Pr after 10 8The 2Pr after fatigue cycles is improved by 15.5%, 24.1% and 34.5% respectively. This result shows that the nanosecond laser annealing with low thermal budget can obtain good ferroelectric properties, and the nitrogen-rich treatment in NH3 atmosphere can further optimize the ferroelectric remanent polarization performance. And within a certain range, the longer the nitrogen-rich treatment time, the better the remanent polarization optimization performance.

[0086] Embodiment

[0087] In this embodiment, a ferroelectric transistor is completely prepared, wherein the gate is prepared according to the aforementioned gate annealing method, and FIGS. 7 to 21 are schematic diagrams of the preparation process in this embodiment.

[0088] Specifically:

[0089] As shown in FIG. 7, a thermal oxide silicon dioxide is grown on the surface of the silicon substrate 1 as a well oxide layer 2.

[0090] As shown in FIG. 8, then the substrate 1 is subjected to ion implantation and well pushing treatment, wherein the ion implantation layer 101 is a schematic structure after ion implantation and well pushing treatment.

[0091] As shown in FIG. 9, the well oxide layer 2 is completely removed, and then device isolation is achieved by using isolation technologies such as LOCOS or STI.

[0092] As shown in FIG. 10, a gate oxide layer 21 is regrown again.

[0093] As shown in FIG. 11, amorphous silicon, silicon dioxide, silicon nitride, silicon dioxide are sequentially deposited on the gate oxide layer 21 to form a pseudo gate 31, a first silicon dioxide layer 32, a silicon nitride layer 33 and a second silicon dioxide layer 34, respectively; wherein the first silicon dioxide layer 32, the silicon nitride layer 33 and the second silicon dioxide layer 34 are used as an ONO hard mask stack.

[0094] As shown in FIG. 12, the ONO hard mask stack on both sides is etched, and silicon nitride is deposited on both sides of the etched ONO hard mask stack and etched to obtain a side wall 4 as an isolation structure.

[0095] As shown in FIG. 13, source and drain ion implantation is performed on the surface of the substrate 1, and annealing is performed to activate the impurity distribution of the source impurity region 51 and the drain impurity region 52.

[0096] As shown in FIG. 14, Silicide process is performed on the source impurity region 51 and the drain impurity region 52 to form a source silicide layer 61 and a drain silicide layer 62 to reduce the source and drain contact resistance.

[0097] As shown in FIG. 15, SiN, W and SiO2 are sequentially deposited at the source and drain positions, respectively, and the SiO2 and part of the W at the gate position are polished away by a chemical mechanical polishing (CMP) process, and the remaining W serves as a laser reflection layer 7 to avoid adverse effects on the source impurity region 51, the drain impurity region 52, the source silicide layer 61 and the drain silicide layer 62 during subsequent ferroelectric laser annealing.

[0098] As shown in FIG. 16, the dummy gate 31 is removed to expose the gate position 8.

[0099] As shown in FIG. 17, a ferroelectric material is deposited as a ferroelectric layer 9 by an ALD process, and the thickness of the ferroelectric layer is 7 nm. The ferroelectric layer 9 is subjected to nitrogen enrichment treatment to enrich nitrogen at the interface of the ferroelectric layer 9 in an NH3 atmosphere, thereby forming an interface nitrogen adsorption layer.

[0100] Then, a 20-nm-thick TiN is deposited as a cap layer 10 by a physical vapor deposition (PVD) technique to assist ferroelectric crystallization. As shown in FIG. 18, nanosecond-level laser annealing is performed to induce a ferroelectric phase at a very fast temperature rise and fall, relieve the aggregation of oxygen vacancies in the body, avoid pinning of the ferroelectric switching domain, and improve the durability of the ferroelectric transistor. The parameters of the laser annealing are as follows: a Nd:YLF laser (Tolar527, 35K) with a laser wavelength of 527 nm, a laser pulse duration of 200 ns, a repetition rate of 500 Hz, and a laser power range of 3.1-4.9 W. At the same time, due to the shielding of the laser reflection layer 7, the laser has no adverse effects on the source impurity region 51, the drain impurity region 52, the source silicide layer 61 and the drain silicide layer 62.

[0101] As shown in FIG. 19, a 75-nm-thick conductive metal W is deposited as a gate metal stack 11.

[0102] As shown in FIG. 20, the gate region is subjected to photolithography, and then dry etching is performed to transfer the gate pattern, and at the same time, the laser reflection layer 7 is also etched away, thereby finally forming a gate 12.

[0103] As shown in FIG. 21, SiO2 is deposited as a spacer layer 13, and ON via etching is performed, and Ti, TiN and W are sequentially deposited at the via region, and the TiN is polished and deposited by a CMP process to etch the electrode, thereby obtaining a via interconnection metal 14 and an electrode 15. The structure of the ferroelectric transistor is shown in FIG. 21. In FIG. 21, the source 16 and the drain 17 are left-right symmetrical structures, and the positions of the source and the drain are only illustrative.

[0104] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present disclosure, and it should be understood that the above-described specific embodiments are merely specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A gate annealing method of a ferroelectric transistor, comprising: forming an N / P well layer, a source and a drain on a substrate, wherein the source and the drain are formed at two ends of the N / P well layer; depositing a laser reflection layer in the source region and the drain region; depositing a ferroelectric material in the gate region by an atomic layer deposition process to form a ferroelectric layer, and performing a surface nitrogen enrichment treatment on the upper surface of the ferroelectric layer to form an interface nitrogen adsorption layer on the upper surface of the ferroelectric layer; depositing titanium nitride as a cap layer on the ferroelectric layer with the interface nitrogen adsorption layer to ensure phase stability of the ferroelectric layer, and inducing the ferroelectric layer to generate a ferroelectric phase by a laser annealing process; depositing a conductive metal on the cap layer to form a gate metal stack.

2. The gate anneal method of claim 1, wherein, In the laser annealing process, the laser wavelength is 200-527 nm, the laser power is 3-5 W, and the laser current is 9.8-10.2 A.

3. The gate anneal method of claim 1, wherein, In the nitrogen enrichment treatment, the nitrogen enrichment atmosphere is ammonia, and the nitrogen enrichment treatment time is 1-15 min; the flow rate of the ammonia is 200-300 sccm. 4.The gate annealing method of claim 1, wherein depositing a laser reflection layer in the source region and the drain region comprises: depositing silicon nitride in the source region and the drain region respectively as gate isolation, and then sequentially depositing tungsten and silicon dioxide, and then removing the silicon dioxide and the tungsten in the gate region, the tungsten in the source region and the drain region serving as the laser reflection layer to protect the source and the drain.

5. The gate anneal method of claim 1, wherein, The conductive metal is tungsten. 6.The gate annealing method of claim 1, further comprising sequentially performing photolithography and etching on the gate metal stack to obtain a gate electrode with a target pattern.

7. The gate anneal method of claim 6, wherein, The etching process removes the laser reflection layer in the source region and the drain region.

8. The gate anneal method of claim 1, wherein, The ferroelectric material is hafnium oxide with a doping element, and the doping element includes silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium. 9.A gate structure of a ferroelectric transistor prepared by the gate annealing method of any one of claims 1-8, comprising: a gate oxide layer adapted to form an insulating structure to reduce gate leakage, enhance the control of gate voltage on channel carriers, and control the switching and working current of the ferroelectric transistor; a ferroelectric layer formed on the gate oxide layer, the ferroelectric layer having a ferroelectric phase to adjust the threshold voltage drift of channel current according to the change of polarization state of the gate voltage signal through a spontaneous polarization state; a cap layer formed on the ferroelectric layer, the cap layer being adapted to stabilize the orthorhombic phase of the ferroelectric phase crystal in the ferroelectric layer to enhance the ferroelectric properties of the ferroelectric layer; a gate metal stack formed on the cap layer, the gate metal stack being adapted to realize the interconnection of the gate electrode. 10.A ferroelectric transistor, comprising: a substrate; an N / P well layer formed on the substrate and adapted to isolate channel carriers from the substrate to avoid latch-up effect; a source formed at one end of the N / P well layer; and a gate having the gate structure as claimed in claim 9 formed in the middle of the N / P well layer, under the condition that an external voltage is applied to the gate metal stack of the gate, the gate structure outputs a gate voltage to control the carrier state of the N / P well layer, and realizes the on / off of the ferroelectric transistor; a drain formed at the other end of the N / P well layer.

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