Display device and electronic device comprising same

Abstract

A display device according to an embodiment may comprise: a circuit layer including a first transistor, a second transistor disposed on the first transistor, and a conductive pattern disposed between the first transistor and the second transistor; and a display layer disposed on the circuit layer and including a light-emitting element, wherein the first transistor includes a first semiconductor pattern and a first upper electrode, the second transistor includes a second semiconductor pattern, a second upper electrode disposed on the second semiconductor pattern, and a lower electrode disposed under the second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern overlap, and the conductive pattern is disposed so as to at least partially overlap each of the first semiconductor pattern and the second semiconductor pattern, thereby minimizing a dead space and exhibiting excellent driving characteristics.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device, and more particularly, to a display device including a plurality of transistors arranged on different layers and overlapping each other.

[0002] Display devices are used in various multimedia devices, such as televisions, mobile phones, tablet computers, and game consoles, to provide users with visual information. Display devices include light-emitting elements and pixel circuits for driving the light-emitting elements. Furthermore, display devices include gate driver circuits for providing signals to the pixel circuits. The light-emitting elements are controlled to emit light by signals output from the gate driver circuits.

[0003] In order to arrange these circuits, the area of ​​dead space corresponding to the non-display area may increase, and accordingly, it is necessary to develop a technology that maintains excellent electrical characteristics while reducing the dead space by adjusting the arrangement form of the circuits.

[0004] An object of the present invention is to provide a display device in which a plurality of transistors are arranged to overlap each other in different layers, thereby reducing a non-display area.

[0005] In addition, an object of the present invention is to provide a display device that exhibits excellent driving characteristics while minimizing the circuit layout area by arranging a conductive pattern between two transistors arranged to overlap on a plane.

[0006] One embodiment provides a display device including a base layer; a circuit layer disposed on the base layer and including a first transistor, a second transistor disposed on the first transistor, and a conductive pattern disposed between the first transistor and the second transistor; and a display layer disposed on the circuit layer and including a light-emitting element; wherein the first transistor includes a first semiconductor pattern and a first upper electrode disposed on the first semiconductor pattern, and the second transistor includes a second semiconductor pattern, a second upper electrode disposed on the second semiconductor pattern, and a lower electrode disposed under the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern overlap, and the conductive pattern overlaps at least a portion of each of the first semiconductor pattern and the second semiconductor pattern.

[0007] At least one of the first semiconductor pattern and the second semiconductor pattern may include an oxide semiconductor.

[0008] The above oxide semiconductor may have a mobility of 20㎠ / Vs or more.

[0009] The above oxide semiconductor is a metal oxide containing indium, gallium, and zinc, and the content of the indium in the metal oxide may be at least twice the content of the gallium.

[0010] At least one of the first semiconductor pattern and the second semiconductor pattern may include a plurality of layers stacked in the thickness direction and having different oxide semiconductor material compositions.

[0011] The above-mentioned conductive pattern may include a metal, a metal oxide, or a transparent conductive material.

[0012] The above-mentioned conductive pattern is electrically connected to a constant voltage line, and the lower electrode can be electrically connected to the second semiconductor pattern or the second upper electrode.

[0013] The above challenge pattern may include a grid pattern including a horizontal line portion extending in one direction on a plane and a vertical line portion intersecting the horizontal line portion.

[0014] At least one hole may be defined in the above challenge pattern.

[0015] The circuit layer may further include a first insulating layer covering the first semiconductor pattern, a second insulating layer disposed between the first insulating layer and the conductive pattern, a third insulating layer disposed between the conductive pattern and the lower electrode, a fourth insulating layer covering the lower electrode, a fifth insulating layer covering the second semiconductor pattern, and an upper insulating layer disposed on the fifth insulating layer.

[0016] A hole region is defined through one of the first to fourth insulating layers to the fifth insulating layer, and the upper insulating layer can be filled in the hole region.

[0017] At least one of the upper surface of the second insulating layer and the upper surface of the third insulating layer may be a flat surface.

[0018] The above-mentioned conductive patterns are a plurality of distinct ones, and the plurality of conductive patterns are arranged spaced apart from each other on a plane, and different constant voltage lines can be electrically connected to each of the conductive patterns.

[0019] A constant voltage is applied to the conductive pattern, and the conductive pattern can be electrically connected to at least one of the first semiconductor pattern and the second semiconductor pattern.

[0020] The circuit layer may further include a capacitor including a first sub-conductive pattern disposed on the same layer as the conductive pattern and including the same material as the conductive pattern, and a second sub-conductive pattern disposed above or below the first sub-conductive pattern, overlapping the first sub-conductive pattern.

[0021] One embodiment provides an electronic device, comprising: a display area; and a non-display area disposed on at least one side of the display area, the electronic device comprising: a base layer; a display layer disposed on the base layer and including a plurality of light-emitting elements disposed corresponding to the display area; and a circuit layer disposed between the base layer and the display layer and including a plurality of transistors and a plurality of insulating layers; wherein the circuit layer includes a pixel circuit electrically connected to the light-emitting elements; and a gate driving circuit disposed in the non-display area and including a lower transistor, an upper transistor disposed on the lower transistor, and a conductive pattern disposed between the lower transistor and the upper transistor; wherein the lower transistor includes a first semiconductor pattern and a first upper electrode disposed on the first semiconductor pattern, and the upper transistor includes a second semiconductor pattern, a second upper electrode disposed on the second semiconductor pattern, and a lower electrode disposed under the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern overlap, and the conductive pattern overlaps at least a portion of each of the first semiconductor pattern and the second semiconductor pattern.

[0022] At least one of the first semiconductor pattern and the second semiconductor pattern may include a metal oxide including at least one of indium, gallium, zinc, tin, and titanium.

[0023] The pixel circuit includes a driving transistor including a third semiconductor pattern, and a switching transistor including a fourth semiconductor pattern distinct from the third semiconductor pattern, wherein at least one of the third semiconductor pattern and the fourth semiconductor pattern may include a metal oxide including at least one of indium, gallium, zinc, tin, and titanium.

[0024] The third semiconductor pattern and the fourth semiconductor pattern may be arranged on the same layer as the first semiconductor pattern.

[0025] The third semiconductor pattern is disposed on the same layer as either the first semiconductor pattern or the second semiconductor pattern, the fourth semiconductor pattern is disposed on or below the third semiconductor pattern so as to overlap with the third semiconductor pattern, and the circuit layer may further include a pixel conductive pattern disposed between the third semiconductor pattern and the fourth semiconductor pattern.

[0026] In one embodiment, the display device can minimize dead space by reducing the area for arranging a plurality of transistors, including transistors arranged to overlap on a plane.

[0027] In addition, the display device of one embodiment includes transistors arranged so that semiconductor patterns overlap each other and conductive patterns arranged between the overlapping semiconductor patterns, thereby minimizing dead space and exhibiting high resolution characteristics while reducing coupling noise generation between the semiconductor patterns.

[0028] FIG. 1 is a perspective view of a display device according to one embodiment.

[0029] Figure 2 is a cross-sectional view of a display device according to one embodiment.

[0030] Figure 3 is a plan view of a display panel of one embodiment.

[0031] Figure 4 is an equivalent circuit diagram of a pixel according to one embodiment.

[0032] Fig. 5 is an equivalent circuit diagram of a gate driving circuit according to one embodiment.

[0033] Figure 6 is a cross-sectional view of a portion of a display panel of one embodiment.

[0034] Fig. 7 is a cross-sectional view showing a portion of a circuit layer according to one embodiment.

[0035] FIG. 8a is a plan view of a portion of a circuit layer according to one embodiment.

[0036] FIG. 8b is a plan view of a portion of a circuit layer according to one embodiment.

[0037] Fig. 9 is a cross-sectional view showing a portion of a circuit layer according to one embodiment.

[0038] FIG. 10a is a plan view of a challenge pattern according to one embodiment.

[0039] FIG. 10b is a plan view of a challenge pattern according to one embodiment.

[0040] Fig. 11a is a cross-sectional view showing a portion of a circuit layer according to one embodiment.

[0041] Fig. 11b is a cross-sectional view showing a portion of a circuit layer according to one embodiment.

[0042] FIG. 12a is a plan view of a portion of a circuit layer according to one embodiment.

[0043] FIG. 12b is a plan view of a portion of a circuit layer according to one embodiment.

[0044] Fig. 13 is a cross-sectional view showing a portion of a circuit layer according to one embodiment.

[0045] Fig. 14 is a cross-sectional view showing a portion of a display panel according to one embodiment.

[0046] Fig. 15 is a cross-sectional view showing a portion of a display panel according to one embodiment.

[0047] Fig. 16 is a cross-sectional view showing a portion of a display panel according to one embodiment.

[0048] Figure 17 is a block diagram of an electronic device according to one embodiment.

[0049] Figure 18 is a schematic diagram of an electronic device according to one embodiment.

[0050] The present invention is susceptible to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the present invention to specific disclosed forms, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

[0051] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0052] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0053] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0054] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0055] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0056] In this specification, "directly disposed" may mean that there are no additional layers, films, regions, plates, etc., between a portion of a layer, film, region, plate, etc. and another portion. For example, "directly disposed" may mean disposed between two layers or two members without using an additional member, such as an adhesive member.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0058] Hereinafter, a display device according to one embodiment and an electronic device according to one embodiment will be described with reference to the drawings.

[0059] FIG. 1 is a perspective view of an electronic device (DD) according to an embodiment of the present invention. As illustrated in FIG. 1, the electronic device (DD) may include a display device (DM) that displays an image through a display surface (DD-IS). The display surface (DD-IS) may have a rectangular shape having long sides extending in a first direction (DR1) on a plane and short sides extending in a second direction (DR2) intersecting the first direction (DR1). However, the present invention is not limited thereto, and the display surface (DD-IS) may have various shapes, such as a circle or a polygon.

[0060] In the present specification, the third direction (DR3) may be defined as a direction substantially perpendicular to a plane defined by the first direction (DR1) and the second direction (DR2). The front (or upper surface) and the rear (or lower surface) of each member constituting the electronic device (DD) may be opposed to each other in the third direction (DR3), and the normal directions of each of the front and rear surfaces may be substantially parallel to the third direction (DR3). A separation distance between the front and rear surfaces defined along the third direction (DR3) may correspond to a thickness of the member.

[0061] In this specification, "on a plane" may be defined as a state viewed from a third direction (DR3). That is, "on a plane" may be described based on a plane defined by the first direction (DR1) and the second direction (DR2). In this specification, "on a cross-section" may be defined as a state viewed from the first direction (DR1) or the second direction (DR2). Meanwhile, the directions indicated by the first to third directions (DR1, DR2, DR3) are relative concepts and may be converted into other directions.

[0062] In one embodiment of the present invention, an electronic device (DD) including a display device (DM) having a flat display surface is illustrated, but is not limited thereto. The electronic device (DD) may include a curved display surface or a three-dimensional display surface. For example, a three-dimensional display surface may include a plurality of display areas pointing in different directions and may include a bended display surface. The electronic device (DD) according to the present embodiment may be a flexible electronic device. The flexible electronic device may be a foldable electronic device.

[0063] In FIG. 1, a tablet terminal is illustrated as an example of an electronic device (DD). Electronic modules, a camera module, a power module, etc. mounted on a motherboard can be arranged in a bracket / case, etc., together with a display device (DM), to form a tablet terminal. However, the embodiment is not limited thereto, and the display device (DM) can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as cell phones, car navigation systems, game consoles, and smart watches.

[0064] As illustrated in FIG. 1, the display surface (DD-IS) includes an active area (DD-DA) where an image is displayed and a bezel area (DD-NDA) adjacent to the active area (DD-DA). The bezel area (DD-NDA) is an area where no image is displayed. Icon images are illustrated as examples of images in FIG. 1. The active area (DD-DA) may be referred to as a display area of ​​the display device (DM), and the bezel area (DD-NDA) may be referred to as a non-display area of ​​the display device (DM).

[0065] As illustrated in FIG. 1, the active region (DD-DA) may be substantially rectangular. The term "substantially rectangular" includes not only a rectangular shape in the mathematical sense, but also a rectangular shape in which no vertices are defined in the corner region (or corner region) but the boundary of the curve is defined.

[0066] The bezel area (DD-NDA) may surround the active area (DD-DA). However, this is not limited to this, and the shape of the bezel area (DD-NDA) may be modified. For example, the bezel area (DD-NDA) may be positioned on only one side of the active area (DD-DA).

[0067] FIG. 2 is a cross-sectional view of an electronic device (DD) according to one embodiment.

[0068] An electronic device (DD) may include a display device (DM) and a window (WM) disposed on the display device (DM). The display device (DM) and the window (WM) may be joined by an adhesive layer (PSA). However, the embodiment is not limited thereto, and in one embodiment, the adhesive layer (PSA) may be omitted. In one embodiment, the window (WM) may be formed by a coating method, and the window (WM) may be disposed directly on the display device (DM).

[0069] A display device (DM) may include a display panel (100), an input sensor (200), and a light control member (300). The display panel (100) may include a base layer (BS), a circuit layer (DP-CL), a display layer (DP-ED), and an encapsulation layer (TFE).

[0070] The display panel (100) according to one embodiment may be an emissive display panel, but is not particularly limited thereto. For example, the display panel (100) may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (100) is described as an organic light-emitting display panel. The display panel (100) will be described in more detail below.

[0071] The input sensor (200) may be disposed on the display panel (100). The input sensor (200) may detect a user's input using an electromagnetic induction method and / or a capacitive method. The input sensor (200) may be directly disposed on the display panel (100). Here, "directly disposed" may mean that no third component is disposed between the input sensor (200) and the display panel (100). For example, a separate adhesive layer may not be disposed between the input sensor (200) and the display panel (100). The display panel (100) and the input sensor (200) may be formed through a continuous process.

[0072] The light control member (300) may be a reflection reduction layer that reduces external light reflectance due to light incident from outside the electronic device (DD). However, the embodiment is not limited thereto, and the light control member (300) may include a configuration of various light control layers for improving the display quality of the electronic device (DD). For example, the light control member (300) according to one embodiment may include a polarizing layer, a phase retarder, a destructive interference structure, or a plurality of color filters. Meanwhile, the light control member (300) may be omitted in the electronic device (DD) according to one embodiment.

[0073] A window (WM) according to one embodiment may include a base substrate and a light-shielding pattern. The base substrate may include a glass substrate and / or a synthetic resin film, etc. The light-shielding pattern may partially overlap the base substrate. The light-shielding pattern may substantially correspond to a bezel area (DD-NDA, FIG. 1) of the electronic device (DD). An area where the light-shielding pattern is not arranged may correspond to an active area (DD-DA, FIG. 1) of the display device (DM). Meanwhile, in the present specification, "regions / portions correspond to each other" means "overlap each other" and is not limited to having the same area and / or the same shape. In addition, in the present specification, "regions / portions overlap" includes a case where regions / portions and regions / portions that are indicated to overlap when viewed on a plane overlap at least partly on the plane.

[0074] Fig. 3 is a plan view of a display panel according to one embodiment. Fig. 3 illustrates the planar arrangement relationship of signal lines (GL1 to GLm, DL1 to DLn) and pixels (PX11 to PXmn) among the components of the display panel (100). The signal lines (GL1 to GLm, DL1 to DLn) may include a plurality of gate lines (GL1 to GLm) and a plurality of data lines (DL1 to DLn).

[0075] The display panel (100) may include a display area (DA) and a non-display area (NDA). The non-display area (NDA) may be arranged on at least one side of the display area (DA). The pixels (PX11 to PXmn) may be arranged in the display area (DA), and some or all areas of the signal lines (GL1 to GLm, DL1 to DLn) may be arranged in the non-display area (NDA).

[0076] Each of the pixels (PX11 to PXmn) may be electrically connected to a corresponding gate line among a plurality of gate lines (GL1 to GLm) and a corresponding data line among a plurality of data lines (DL1 to DLn). Each of the pixels (PX11 to PXmn) may include a pixel driving circuit and a light-emitting element. Depending on the configuration of the pixel driving circuit of the pixels (PX11 to PXmn), more types of signal lines may be provided in the display panel (100). For example, each of the gate lines (GL1 to GLm) may include a corresponding scan line (SCLi, see FIG. 4) and a corresponding sensing line (SSLi, see FIG. 4).

[0077] The gate driving circuit (GDC) may be integrated into the display panel (100) through an oxide semiconductor gate driver circuit (OSG) process. In one embodiment, the gate driving circuit (GDC) may be formed directly on the base layer (BS, FIG. 2) and included in the display panel (DP). That is, the gate driving circuit (GDC) of one embodiment is different from connecting the gate driving circuit to the circuit layer (DP-CL, FIG. 2) as a separate member after mounting it on a circuit board or the like, and in one embodiment, the gate driving circuit (GDC) may be formed by directly patterning on the base layer (BS, FIG. 2). The gate driving circuit (GDC) connected to the gate lines (GL1 to GLm) may be arranged in a non-display area (NDA).

[0078] Referring to FIG. 3, in one embodiment, a gate driving circuit (GDC) may be arranged in a non-display area (NDA) located at one side of a display area (DA) in a first direction (DR1). In addition, in one embodiment, pads (PD) connected to ends of a plurality of data lines (DL1 to DLn) may be arranged in a non-display area (NDA) located at one side of a display area (DA) in a second direction (DR2). However, this is an example, and the embodiment is not limited thereto, and the arrangement positions of the gate driving circuit (GDC) and the pads (PD) may vary.

[0079] The gate driving circuit (GDC) may include a plurality of transistors formed through the same process as at least one of the pixel transistors included in the pixel circuit of the pixels (PXij) described below. At least one of the plurality of transistors included in the gate driving circuit (GDC) may include a semiconductor pattern including a metal oxide including at least one of indium, gallium, zinc, tin, and titanium.

[0080] Fig. 4 is an equivalent circuit diagram of a pixel according to one embodiment. Fig. 4 exemplarily illustrates a pixel (PXij) connected to an ith scan line (SCLi), an ith sensing line (SSLi), a jth data line (DLj), and a jth reference line (RLj). The pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (ED) connected to the pixel circuit (PC). The pixel circuit (PC) may include a plurality of pixel transistors (T1, T2, T3) and at least one capacitor (Cst). At least one of the plurality of pixel transistors (T1, T2, T3) may include a semiconductor pattern including a metal oxide including at least one of indium, gallium, zinc, tin, and titanium. For example, in one embodiment, all of the plurality of pixel transistors (T1, T2, T3) may include a semiconductor pattern including a metal oxide.

[0081] Hereinafter, the plurality of pixel transistors (T1, T2, T3) are described as N-type, but at least one transistor can be implemented as a P-type transistor.

[0082] In FIG. 4, a pixel circuit (PC) including a first pixel transistor (T1), a second pixel transistor (T2), a third pixel transistor (T3), and a pixel capacitor (Cst) is illustrated as an example, but the configuration of the pixel circuit (PC) is not limited thereto.

[0083] In one embodiment, the first pixel transistor (T1) may be a driving transistor, the second pixel transistor (T2) may be a switching transistor, and the third pixel transistor (T3) may be a sensing transistor. The pixel circuit (PC) may further include additional transistors in addition to the first to third pixel transistors (T1, T2, and T3), or may further include additional capacitors in addition to the pixel capacitor (Cst).

[0084] The light-emitting element (ED) may be an organic light-emitting element or an inorganic light-emitting element including an anode (a first electrode) and a cathode (a second electrode). The anode of the light-emitting element (ED) may receive a first voltage (ELVDD) through the first pixel transistor (T1), and the cathode of the light-emitting element (ED) may receive a second voltage (ELVSS). The light-emitting element (ED) may emit light by receiving the first voltage (ELVDD) and the second voltage (ELVSS).

[0085] A first pixel transistor (T1) may include a drain (D1) receiving a first voltage (ELVDD), a source (S1) connected to the anode of the light-emitting element (ED), and a gate (G1) connected to a pixel capacitor (Cst). The first pixel transistor (T1) may control a driving current flowing through the light-emitting element (ED) from the first voltage (ELVDD) in response to a voltage value stored in the pixel capacitor (Cst).

[0086] The second pixel transistor (T2) may include a drain (D2) connected to the j-th data line (DLj), a source (S2) connected to the pixel capacitor (Cst), and a gate (G2) receiving the ith first scan signal (SCi). The j-th data line (DLj) may receive the data voltage (Vd). The second pixel transistor (T2) may provide the data voltage (Vd) to the first pixel transistor (T1) in response to the ith first scan signal (SCi).

[0087] The third pixel transistor (T3) may include a source (S3) connected to the jth reference line (RLj), a drain (D3) connected to the anode of the light-emitting element (ED), and a gate (G3) receiving the ith second scan signal (SSi). The jth reference line (RLj) may receive a reference voltage (Vr). The third pixel transistor (T3) may initialize the capacitor (Cst) and the anode of the light-emitting element (ED).

[0088] The pixel capacitor (Cst) can store a voltage corresponding to the difference between the voltage received from the second pixel transistor (T2) and the first voltage (ELVDD). The pixel capacitor (Cst) can be connected to the gate (G1) of the first pixel transistor (T1) and the anode of the light-emitting element (ED).

[0089] Fig. 5 is an equivalent circuit diagram of a gate driving circuit (GDC) according to one embodiment. Fig. 5 illustrates a portion of a gate driving circuit (GDC) that outputs an ith first scan signal (SCi) and an ith second scan signal (SSj). Here, i is a natural number from 1 to m.

[0090] In one embodiment, the gate drive circuit (GDC) may include a plurality of stages. In one embodiment, the gate drive circuit (GDC) may include a plurality of stages connected to each of the gate lines (GL1 to GLm). In one embodiment, the plurality of stages may be arranged and positioned in the second direction (DR2).

[0091] A plurality of stages included in a gate drive circuit (GDC) can provide driving signals to pixels in a corresponding row, respectively. Each of the plurality of stages can include a plurality of transistors. Two or more transistors selected from among the plurality of transistors included in each stage can be arranged in a stacked manner so that their semiconductor patterns overlap each other. By arranging the transistors in a stacked manner so that they overlap each other on a plane, the area of ​​the non-display area (NDA, FIG. 3) can be minimized.

[0092] In addition, since some of the plurality of transistors included in each of the stages of the gate driving circuit (GDC) are arranged to overlap each other on a plane, the width of each of the stages in the second direction (DR2) is reduced, and accordingly, the arrangement interval of the pixels (PX11 to PXmn) can also be reduced. Therefore, it is possible to implement a high-resolution display device by arranging some of the plurality of transistors included in the gate driving circuit (GDC) to overlap each other.

[0093] Fig. 5 may be an equivalent circuit diagram of one stage among a plurality of stages. The gate drive circuit (GDC) may include all circuit configurations (e.g., m or more stages) for outputting first scan signals (SCi, where i is an integer from 1 to m) and second scan signals (SSi, where i is an integer from 1 to m).

[0094] Meanwhile, the circuit illustrated in FIG. 5 is only an example of a gate driving circuit (GDC), and the circuit configuration of the gate driving circuit (GDC) can be changed in various ways.

[0095] Referring to FIG. 5, the gate driving circuit (GDC) may receive clock signals (SC_CK, SS_CK, CR_CK), switching signals (SW1 to SW5), carry signals (CRi-3, CRi+4), a first low voltage (VSS1), a second low voltage (VSS2), and a third low voltage (VSS3), and output a first scan signal (SCi), a second scan signal (SSi), and a carry signal (CRi). The carry signals (CRi-3, CRi+4) may be signals generated within the gate driving circuit (GDC). That is, the i-3th carry signal (CRi-3) may be a signal related to the i-3rd first scan signal (SCi-3) and the i-3rd second scan signal (SSi-3), and the i+4th carry signal (CRi+4) may be a signal related to the i+4th first scan signal (SCi+4) and the i+4th second scan signal (SSi+4).

[0096] The gate drive circuit (GDC) may include transistors (M1-1, M1-2, M2-1, M2-2, M3-1, M3-2, M4-1, M4-2, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22-1, M22-2, M23-1, M23-2) and capacitors (C1, C2, C3).

[0097] The switching signals (SW1, SW4) transition to a high level at the start of a frame and then remain at a low level for the remainder of the frame. Each of the switching signals (SW1, SW4) may be a signal indicating the start of a frame. A frame may include an active period and a blank period.

[0098] The switching signal (SW2) is maintained at a low level (e.g., -9 V) during the active period and transitions to a high level (e.g., 25 V) at the start of the blank period. The switching signal (SW2) may be a signal indicating the start of the blank period.

[0099] The switching signal (SW3) is maintained at a high level (e.g., 25 V) or low level (e.g., -9 V) for one frame.

[0100] The switching signal (SW5) is a signal that is maintained at a high level (e.g., 25 V).

[0101] The gate drive circuit (GDC) illustrated in Fig. 5 operates as follows.

[0102] When the switching signal (SW4) transitions to a high level at the start of a frame, the transistors (M1-1, M1-2) are turned on, and the first node (Q) is initialized to the first low voltage (VSS1).

[0103] Since the transistors (M15, M16, M17) are turned on while the switching signal (SW3) is at a high level (e.g., 25 V), the second node (QB) can be set to a high level corresponding to the switching signal (SW3).

[0104] When the carry signal (CRi-3) transitions to a high level, the transistors (M4-1, M4-2) are turned on, and the first node (Q) can transition to a high level. When the first node (Q) transitions to a high level and the clock signals (SC_CK, SS_CK, CR_CK) are at a high level, the transistors (M5, M7, M9) are turned on, so that the first scan signal (SCi), the second scan signal (SSi), and the carry signal (CRi) can each transition to a high level. Meanwhile, when the carry signal (CRi-3) transitions to a high level, the transistor (M20) is turned on, so that the second node (QB) can be discharged to the first low voltage (VSS1).

[0105] Transistors (M5, M7, M9) are transistors that control the output of scan signals (SCi or SSi) provided to light-emitting elements (ED, FIG. 4) or carry signals (CRi) provided to the next stage, and may be referred to as switching transistors (M5, M7, M9). The channel widths of the switching transistors (M5, M7, M9) may be larger than the channel widths of the remaining transistors (M1-1, M1-2, M2-1, M2-2, M3-1, M3-2, M4-1, M4-2, M6, M8, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22-1, M22-2, M23-1, M23-2).

[0106] Meanwhile, since the transistor (M19) is turned on while the first node (Q) is at a high level, the second node (QB) can be maintained at the first low voltage (VSS1), i.e., at a low level. Therefore, the transistors (M6, M8, M10) can be maintained in a turned-off state.

[0107] When the clock signals (SC_CK, SS_CK, CR_CK) each change from a high level to a low level, the first scan signal (SCi), the second scan signal (SSi), and the carry signal (CRi) each transition from a high level to a low level.

[0108] Continuing, when the carry signal (CRi+4) transitions to a high level, the transistors (M2-1, M2-2) are turned on, and the first node (Q) can be discharged to the first low voltage (VSS1).

[0109] When the first node (Q) is the first low voltage (VSS1) and the carry signal (CRi-3) is at a low level, the transistors (M19, M20) are each turned off so that the second node (QB) can be maintained at a high level corresponding to the third switching signal (SW3). When the second node (QB) is at a high level, the transistors (M6, M8, M10) are turned on, so that the first scan signal (SCi) and the second scan signal (SSi) can be maintained at a voltage level of the third low voltage (VSS3), and the carry signal (CRi) can be maintained at a voltage level of the first low voltage (VSS1). That is, in a blank period within one frame, the first scan signal (SCi) and the second scan signal (SSi) can be maintained at the third low voltage (VSS3), and the carry signal (CRi) can be maintained at the first low voltage (VSS1).

[0110] At least one of the transistors included in the gate drive circuit (GDC) may include an oxide semiconductor pattern. The oxide semiconductor pattern may include a metal oxide including at least one of indium, gallium, zinc, tin, and titanium.

[0111] In one embodiment, a plurality of transistors included in a gate drive circuit (GDC) may include lower transistors and upper transistors arranged so that semiconductor patterns overlap each other on a plane, and may include a conductive pattern arranged between the lower transistors and the upper transistors. The conductive pattern may be connected to a voltage line to which a predetermined voltage is applied. A DC voltage may be applied to the conductive pattern through the voltage line.

[0112] For example, one of the switching transistors (M5, M7, M9) that control the output of the signal provided to the light-emitting elements may be arranged as a lower transistor, and one of the others may be arranged as an upper transistor overlapping the lower transistor. Additionally, a conductive pattern may be arranged between the lower transistor and the upper transistor.

[0113] A display device of one embodiment can exhibit a characteristic in which the area of ​​a non-display area (NDA) is reduced by arranging two or more transistors selected from among a plurality of transistors included in a gate driving circuit (GDC) so that their semiconductor patterns overlap each other, and including a conductive pattern arranged between the overlapping transistors to reduce the arrangement area of ​​the gate driving circuit (GDC).

[0114] Fig. 6 is a cross-sectional view of a display panel according to one embodiment. Fig. 6 illustrates the configuration of a display panel in a portion of a display area and a portion of a non-display area. Fig. 7 is an enlarged view of area AA of Fig. 6. Figs. 8a and 8b are plan views each illustrating a portion of a display panel. Figs. 8a and 8b may be plan views illustrating a portion of a part corresponding to area AA illustrated in Fig. 7.

[0115] The display panel (100) may include a base layer (BS), a circuit layer (DP-CL) disposed on the base layer (BS), and a display layer (DP-ED) disposed on the circuit layer (DP-CL). The circuit layer (DP-CL) may include a plurality of transistors, and the display layer (DP-ED) may include a light-emitting element (ED).

[0116] The base layer (BS) can provide a base surface on which the circuit layer (DP-CL) is placed. The base layer (BS) can include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite material substrate.

[0117] In one embodiment, the base layer (BS) may include at least one synthetic resin layer. The synthetic resin layer included in the base layer (BS) may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, a polyimide resin, and a perylene resin.

[0118] In one embodiment, the base layer (BS) may be a flexible substrate. When the base layer (BS) is a flexible substrate, the base layer (BS) may be capable of bending, folding, rolling, etc.

[0119] The circuit layer (DP-CL) may be disposed on the base layer (BS). The circuit layer (DP-CL) may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, a plurality of electrodes, signal lines, etc. The circuit layer (DP-CL) will be described in more detail below.

[0120] The display layer (DP-ED) may be disposed on the circuit layer (DP-CL). The display layer (DP-ED) may include a pixel defining layer (PDL) and a light-emitting element (ED). For example, the light-emitting element (ED) may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0121] A light emitting element (ED) may include a first electrode (AE), a second electrode (CE), and an emitting layer (EML). In one embodiment, the first electrode (AE) of the light emitting element (ED) may be an anode, and the second electrode (CE) may be a cathode.

[0122] A first electrode (AE) and a pixel defining layer (PDL) of a light emitting element (ED) may be disposed on an upper insulating layer (60). The first electrode (AE) may be connected to a connection electrode (CNE) at least through a contact hole penetrating the upper insulating layer (60). As the first electrode (AE) is connected to the connection electrode (CNE), the first electrode (AE) may be electrically connected to a first source (S1) of a first pixel transistor (T1) and a lower shielding pattern (BML), respectively, through the connection electrode (CNE) and the source electrode (SE2). That is, the first electrode (AE) of the light emitting element (ED) may be electrically connected to a semiconductor pattern (A1) of the first pixel transistor (T1) and a lower shielding pattern (BML), respectively.

[0123] A pixel defining layer (PDL) may define a light-emitting aperture that exposes at least a portion of a first electrode (AE). In the present embodiment, a portion of the first electrode (AE) exposed by the light-emitting aperture may correspond to a light-emitting area.

[0124] The pixel defining layer (PDL) may include a polymer resin and may further include an inorganic material contained within the polymer resin. In one embodiment, the pixel defining layer (PDL) may have a predetermined color. For example, the pixel defining layer (PDL) may include a base resin and a black pigment and / or black dye mixed into the base resin. However, embodiments of the pixel defining layer (PDL) are not limited thereto.

[0125] The second electrode (CE) may be arranged to face the first electrode (AE). The second electrode (CE) may be arranged in common to the pixels (PX11 to PXmn, FIG. 3) arranged in the display area (DA). That is, the second electrode (CE) may be a common electrode provided in common to a plurality of pixels (PX11 to PXmn, FIG. 3).

[0126] An emission layer (EML) may be disposed between a first electrode (AE) and a second electrode (CE). The emission layer (EML) may include an organic material and / or an inorganic material. The emission layer (EML) may be disposed in a pattern in an area corresponding to a light-emitting opening defined in a pixel defining layer (PDL). The emission layer (EML) may generate any one of red, green, and blue light. However, the present invention is not limited thereto, and the emission layer (EML) may be disposed in common across pixels and may generate blue light or white light. In FIG. 6, the emission element (ED) includes one emission layer (EML) as an example, but the present invention is not limited thereto, and the emission element (ED) may be a tandem-type emission element including a plurality of emission stacks.

[0127] The light emitting element (ED) may further include at least one functional layer provided between the first electrode (AE) and the light emitting layer (EML), and between the light emitting layer (EML) and the second electrode (CE). The light emitting element (ED) may further include, for example, a hole control layer provided between the first electrode (AE) and the light emitting layer (EML), and an electron control layer provided between the second electrode (CE) and the light emitting layer (EML). Each of the hole control layer and the electron control layer may be commonly arranged in pixels. The hole control layer may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. The electron control layer may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer.

[0128] An encapsulation layer (TFE) may be disposed on the display layer (DP-ED). The encapsulation layer (TFE) may protect the display layer (DP-ED), i.e., the light-emitting element, from foreign substances such as moisture, oxygen, and dust particles. The encapsulation layer (TFE) may include at least one encapsulation inorganic layer. The encapsulation layer (TFE) may include a laminated structure of a first encapsulation inorganic layer / encapsulation organic layer / second encapsulation inorganic layer.

[0129] After providing an insulating layer, a semiconductor layer, a conductive layer, etc. on a base layer (BS) through coating or deposition, a plurality of insulating layers and insulating patterns, a plurality of semiconductor patterns, a plurality of conductive patterns, a plurality of electrodes, and signal lines, etc. of a circuit layer (DP-CL) can be formed by patterning through multiple photolithography processes. The steps of the deposition, photo, and etching processes can be sequentially repeated depending on the stacking order of the patterns included in the circuit layer (DP-CL).

[0130] The circuit layer (DP-CL) may include a plurality of pixel transistors constituting a pixel circuit (PC, FIG. 4) of a pixel (PX11 to PXmn, FIG. 3), and a plurality of transistors constituting a gate driving circuit (GDC, FIG. 3).

[0131] Meanwhile, the cross-sectional structure of the circuit layer (DP-CL) illustrated in FIG. 6 and the like is exemplary and may vary depending on the manufacturing process of the circuit layer (DP-CL), the configuration of the pixel circuit, or the configuration of the gate driving circuit.

[0132] The circuit layer (DP-CL) may include a buffer layer (BFL), first to fifth insulating layers (10, 20, 30, 40, 50), and an upper insulating layer (60) as an insulating layer. The circuit layer (DP-CL) may include a lower shielding pattern (BML) and a conductive pattern (SMP). In addition, the circuit layer (DP-CL) may include a plurality of transistors (T1, T2, Tr-B, Tr-T), electrode patterns (CNE, SE1, SE2, DE1, DE2, SE-T, SE-B, DE-T, DE-B, UCL, USL), and signal lines (SL-P, SL-GU, SL-GB, SL-U, SL-L). The electrode patterns (CNE, SE1, SE2, DE1, DE2, SE-T, SE-B, DE-T, DE-B, UCL, USL) may be electrically connected to portions of transistors (T1, T2, Tr-B, Tr-T), lower shielding patterns (BML), or conductive patterns (SMP). In addition, the signal lines (SL-P, SL-GU, SL-GB, SL-U, SL-L) may be electrically connected to portions of the lower shielding patterns (BML), conductive patterns (SMP), or transistors (Tr-B, Tr-T).

[0133] A lower shielding pattern (BML) may be disposed on the base layer (BS). The lower shielding pattern (BML) may be formed of a metal material. The lower shielding pattern (BML) may be disposed to overlap with a transistor or the like to protect the semiconductor pattern of the transistor or the like. The lower shielding pattern (BML) may be disposed under the transistor to block an electric potential from affecting the transistor or to block external light from reaching the transistor.

[0134] Meanwhile, in one embodiment, the lower shielding pattern (BML) may be connected to an electrode or wiring to receive a predetermined constant voltage. Furthermore, in one embodiment, the lower shielding pattern (BML) may be a floating pattern that is isolated from other electrodes or wiring.

[0135] A buffer layer (BFL) may be disposed on a base layer (BS). The buffer layer (BFL) may improve bonding strength between the base layer (BS) and the semiconductor patterns (A1, A2, AB) and / or the lower shielding pattern (BML). The buffer layer (BFL) may cover the lower shielding pattern (BML). The buffer layer (BFL) may include at least one inorganic layer, and for example, the buffer layer (BFL) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0136] First to fifth insulating layers (10, 20, 30, 40, 50) may be disposed on a buffer layer (BFL). The first to fifth insulating layers (10, 20, 30, 40, 50) may be sequentially laminated and disposed in a third direction (DR3). An upper insulating layer (60) may be disposed on the fifth insulating layer (50). However, the embodiment is not limited thereto, and the number and laminated structure of insulating layers included in the circuit layer (DP-CL) are not limited to the illustrated embodiment.

[0137] The first insulating layer (10) may be disposed on a buffer layer (BFL). The first insulating layer (10) may be an inorganic layer. Contact holes exposing sources (S1, S2, SB) and drains (D1, D2, DB), etc., may be defined in the first insulating layer (10). In addition, contact holes in which connection electrodes, etc., connected to the lower shielding pattern (BML), are disposed may be defined in the first insulating layer (10).

[0138] A second insulating layer (20) may be disposed on the first insulating layer (10). The second insulating layer (20) may be an inorganic layer. Referring to FIG. 6 and the like, the second insulating layer (20) may cover electrode patterns or wires disposed on the first insulating layer (10). The upper surface of the second insulating layer (20) may be a flat surface.

[0139] A third insulating layer (30) may be disposed on the second insulating layer (20). The third insulating layer (30) may cover a conductive pattern (SMP) disposed on the second insulating layer (20). The third insulating layer (30) may be an inorganic layer. The upper surface of the third insulating layer (30) may be a flat surface. In one embodiment, at least one of the upper surface of the second insulating layer (20) and the upper surface of the third insulating layer (30) may be a flat surface.

[0140] The pixel transistors (T1, T2) and the first transistor (Tr-B) may be covered by the second insulating layer (20) and the third insulating layer (30). The second insulating layer (20) and the third insulating layer (30) may each be a layer including silicon nitride. In one embodiment, the second insulating layer (20) and the third insulating layer (30) may each have a laminated structure in which a plurality of layers are laminated. When the second insulating layer (20) or the third insulating layer (30) has a structure including a plurality of layers, at least one of the plurality of layers may be a planarization layer.

[0141] The fourth insulating layer (40) may be disposed on the third insulating layer (30). The second transistor (Tr-T) may be disposed on the third insulating layer (30), the fourth insulating layer (40) may cover the lower electrode (G-BP) disposed on the third insulating layer (30), and the second semiconductor pattern (AT) and the upper electrode (G-UP) of the second transistor (Tr-T) may be disposed on the fourth insulating layer (40). The fourth insulating layer (40) may be an inorganic layer. However, the embodiment is not limited thereto.

[0142] A fifth insulating layer (50) may be disposed on the fourth insulating layer (40). The fifth insulating layer (50) may cover the second transistor (Tr-T). In one embodiment, the fifth insulating layer (50) may be an inorganic layer.

[0143] An upper insulating layer (60) may be disposed on the fifth insulating layer (50). In one embodiment, the upper insulating layer (60) may be an organic layer. Referring to FIG. 6 and the like, the upper insulating layer (60) may cover electrode patterns or wires disposed on the fifth insulating layer (50). A contact hole may be defined in the upper insulating layer (60), and the light-emitting element (ED) and pixel transistors may be electrically connected through the contact hole of the upper insulating layer (60).

[0144] In addition, contact holes may be defined in the buffer layer (BFL) or the insulating layers (10, 20, 30, 40, 50). The contact holes may be formed by penetrating some of the stacked insulating layers, or may be defined only in a portion of the stack without penetrating any insulating layer. Through the contact holes, the lower shielding pattern and electrodes may be electrically connected, the semiconductor pattern and electrode pattern may be electrically connected, the semiconductor pattern and wiring may be electrically connected, the light-emitting element and transistor may be electrically connected, or the wiring and conductive patterns may be electrically connected.

[0145] For example, the connecting electrode (CNE) may be connected to a source electrode (SE1) connected to a source (S1) of the first pixel transistor through a contact hole formed by the second to fifth insulating layers (20, 30, 40, 50). The source electrode (SE1) of the first pixel transistor may be connected to the source (S1) through a contact hole defined in the first insulating layer (10), and may also be electrically connected to a lower shielding pattern (BML) through a contact hole defined in the first insulating layer (10) and a buffer layer (BFL).

[0146] Referring to FIGS. 6 and 7, a plurality of transistors (Tr-T, Tr-B, T1, T2) may be arranged on a buffer layer (BFL). In one embodiment, the first pixel transistor (T1) and the second pixel transistor (T2) may be arranged in a display area (DA), and the first transistor (Tr-B) and the second transistor (Tr-T) may be arranged in a non-display area (NDA).

[0147] Each of the plurality of transistors (Tr-T, Tr-B, T1, T2) may include a semiconductor pattern. Each of the semiconductor patterns may include a source region, a channel region, and a drain region. In the semiconductor pattern, the source region, the channel region, and the drain region may be regions that are distinguished according to doping concentration or conductivity.

[0148] In one embodiment, at least one of the plurality of transistors (Tr-T, Tr-B, T1, T2) may include an oxide semiconductor. That is, the semiconductor pattern of the transistors (Tr-T, Tr-B, T1, T2) may include an oxide semiconductor.

[0149] By including an oxide semiconductor material, the electron mobility in the transistors (Tr-T, Tr-B, T1, T2) may increase, and the leakage current may be reduced. Meanwhile, the oxide semiconductors included in each of the plurality of transistors (Tr-T, Tr-B, T1, T2) may all be the same. However, the present invention is not limited thereto, and at least one of the oxide semiconductors included in the semiconductor pattern of each of the plurality of transistors (Tr-T, Tr-B, T1, T2) may be a material different from the other materials.

[0150] An oxide semiconductor may also be referred to as a metal oxide semiconductor. The oxide semiconductor material may be a crystalline or amorphous oxide. For example, the semiconductor pattern may include a metal oxide, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. In one embodiment, the semiconductor pattern may include a transparent conductive oxide (TCO), such as indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), or zinc-tin oxide (ZTO).

[0151] An oxide semiconductor may include multiple regions that are distinguished by whether or not the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduced region) has greater conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduced region). The reduced region may substantially function as a source / drain or signal line of the transistor. The non-reduced region substantially corresponds to a channel region (or semiconductor region, active region) of the transistor. In other words, a part of the semiconductor pattern may be a channel region of the transistor, another part may be a source / drain region of the transistor, and still another part may be a signal transmission region.

[0152] Meanwhile, in this specification, the semiconductor pattern may also be referred to as an active layer. In addition, the non-reducing region may be referred to as a channel region, and the reducing region may be referred to as a source region or a drain region depending on the applied voltage.

[0153] A display panel (100) according to one embodiment may include a plurality of transistors arranged in a non-display area (NDA). In one embodiment, the display panel (100) may include a first transistor (Tr-B) and a second transistor (Tr-T) arranged in the non-display area (NDA) and overlapping in a third direction (DR3). Referring to FIGS. 6 to 8B , the overlapping of the transistors (Tr-B, Tr-T) corresponds to at least some of the semiconductor patterns (AB, AT) of the transistors overlapping in the third direction (DR3).

[0154] In one embodiment, the first transistor (Tr-B) may be disposed on a buffer layer (BFL), and the second transistor (Tr-T) may be disposed on the first transistor (Tr-B). The first transistor (Tr-B) may be referred to as a lower transistor, and the second transistor (Tr-T) may be referred to as an upper transistor. A conductive pattern (SMP) may be disposed between the first transistor (Tr-B) and the second transistor (Tr-T). Meanwhile, FIG. 8A is an exemplary plane showing a state in which the first transistor (Tr-B) and the conductive pattern (SMP) are disposed on the first transistor (Tr-B), and FIG. 8B is an exemplary plane showing a state in which the second transistor (Tr-T) is disposed on the stacked structure of the first transistor (Tr-B) and the conductive pattern (SMP) of FIG. 8A. In FIGS. 8a and 8b, some of the laminated structures are omitted and illustrated, and the overlapping relationship between the semiconductor pattern of the first transistor (Tr-B), the conductive pattern (SMP), and the semiconductor pattern of the second transistor (Tr-T) is emphasized.

[0155] Referring to FIGS. 6 to 8B, etc., the first transistor (Tr-B) may include a lower semiconductor pattern (or a first semiconductor pattern, AB) and a first upper electrode (GB). The first upper electrode (GB) may be referred to as a first gate electrode. The lower semiconductor pattern (AB) may be divided into a first source (or a first source region, SB), a first channel (or a first channel region, CB), and a first drain (or a first drain region, DB). A lower insulating pattern (GI-B) may be disposed between the lower semiconductor pattern (AB) and the first upper electrode (GB). The first upper electrode (GB) may be disposed on the lower insulating pattern (GI-B) and may be spaced apart from the lower semiconductor pattern (AB) in a third direction (DR3). The first upper electrode (GB) may overlap the first channel (CB). For example, the width of the first channel (CB) can be determined to correspond to the first upper electrode (GB).

[0156] The second transistor (Tr-T) may include an upper semiconductor pattern (or a second semiconductor pattern, AT), a second upper electrode (G-UP), and a lower electrode (G-BP). The second upper electrode (G-UP) may be referred to as a second upper gate electrode, and the lower electrode (G-BP) may be referred to as a second lower gate electrode. The second upper electrode (G-UP) and the lower electrode (G-BP) may each be electrically connected to the upper semiconductor pattern (AT).

[0157] The upper semiconductor pattern (AT) can be divided into a second source (or second source region, ST), a second channel (or second channel region, CT), and a second drain (or second drain region, DT). An upper insulating pattern (GI-T) can be arranged between the upper semiconductor pattern (AT) and the second upper electrode (G-UP). The second upper electrode (G-UP) can be arranged on the upper insulating pattern (GI-T) and spaced apart from the upper semiconductor pattern (AT) in a third direction (DR3). The second upper electrode (G-UP) can overlap the second channel (CT). For example, the width of the second channel (CT) can be determined to correspond to the second upper electrode (G-UP). The lower electrode (G-BP) can be arranged below the upper semiconductor pattern (AT) and spaced apart from the fourth insulating layer (40) in the third direction (DR3).

[0158] In one embodiment, at least one of the first transistor (Tr-B) and the second transistor (Tr-T) may include an oxide semiconductor. For example, in one embodiment, the lower semiconductor pattern (AB) of the first transistor (Tr-B) and the upper semiconductor pattern (AT) of the second transistor (Tr-T) may include an oxide semiconductor.

[0159] The lower semiconductor pattern (AB) and the upper semiconductor pattern (AT) may include oxide semiconductors having the same or different compositions or ratios. The mobility of at least one of the oxide semiconductors included in the lower semiconductor pattern (AB) and the upper semiconductor pattern (AT) may be 20㎠ / Vs or more.

[0160] For example, the lower semiconductor pattern (AB) and the upper semiconductor pattern (AT) may each independently be oxide semiconductors including a metal oxide including indium (In), gallium (Ga), and zinc (Zn).

[0161] In one embodiment, the lower semiconductor pattern (AB) may include IGZO, and the upper semiconductor pattern (AT) may include a material having a higher mobility than the IGZO of the lower semiconductor pattern (AB). Alternatively, in one embodiment, the upper semiconductor pattern (AT) may include IGZO, and the lower semiconductor pattern (AB) may include a material having a higher mobility than the IGZO of the upper semiconductor pattern (AT).

[0162] The content of indium in the metal oxide included in the lower semiconductor pattern (AB) and the upper semiconductor pattern (AT) may be more than twice the content of gallium.

[0163] Referring to FIGS. 7 to 8B, a lower shielding pattern (BML) may be arranged below a lower semiconductor pattern (AB) of a first transistor (Tr-B). The lower shielding pattern (BML) may be electrically connected to a lower wiring (SL-L) through a contact hole defined in a buffer layer (BFL) and a first insulating layer (10). For example, in one embodiment, the lower wiring (SL-L) may be a wiring to which a constant voltage is applied.

[0164] A first source (SB), a first drain (DB), a first upper electrode (GB), etc. of a first transistor (Tr-B) may be electrically connected to an electrode or a signal wire, etc., through a first contact hole (CH-B), etc., defined in a first insulating layer (10). The first source (SB) may be connected to a first source electrode (SE-B), the first drain (DB) may be electrically connected to a first drain electrode (DE-B), and the first upper electrode (GB) may be electrically connected to a first gate line (SL-GB). The lower wiring (SL-L), the first source electrode (SE-B), the first drain electrode (DE-B), and the first gate line (SL-GB) may be covered with a second insulating layer (20). The upper surface of the second insulating layer (20) may be a flat surface.

[0165] The conductive pattern (SMP) may be disposed between the first transistor (Tr-B) and the second transistor (Tr-T). At least one insulating layer may be disposed between the first transistor (Tr-B) and the conductive pattern (SMP), and at least one insulating layer may be disposed between the conductive pattern (SMP) and the second transistor (Tr-T).

[0166] Referring to FIG. 7, etc., the conductive pattern (SMP) may be disposed on the second insulating layer (20) and covered with a third insulating layer (30). The conductive pattern (SMP) may be spaced apart from the first transistor (Tr-B) in the third direction (DR3) with the second insulating layer (20) therebetween, and the conductive pattern (SMP) may also be spaced apart from the second transistor (Tr-T) in the third direction (DR3) with the third insulating layer (30) therebetween.

[0167] The conductive pattern (SMP) can be electrically connected to the voltage line (SL-P) through a contact hole defined in the third to fifth insulating layers (30, 40, 50). For example, in one embodiment, the voltage line (SL-P) electrically connected to the conductive pattern (SMP) can be a line to which a constant voltage is applied. That is, in one embodiment, the conductive pattern (SMP) can be electrically connected to a constant voltage line. A predetermined DC voltage can be applied to the conductive pattern (SMP) through the voltage line (SL-P).

[0168] The second source (ST), the second drain (DT), and the second upper electrode (G-UP) of the second transistor (Tr-T) may be electrically connected to electrodes or signal lines, etc., through the second contact hole (CH-U) defined in the fifth insulating layer (50). The second source (ST) may be electrically connected to the second source electrode (SE-T), the second drain (DT) may be electrically connected to the second drain electrode (DE-T), and the second upper electrode (G-UP) may be electrically connected to the second gate line (SL-GU). The lower electrode (G-BP) of the second transistor (Tr-T) may be electrically connected to the upper wiring (SL-U) through the contact hole defined in the fourth insulating layer (40) and the fifth insulating layer (50). The upper wiring (SL-U) may be a signal wiring connected to the lower electrode (G-BP). The upper wiring (SL-U) can transmit a signal to the lower electrode (G-BP) of the second transistor (Tr-T). The lower electrode (G-BP) of the second transistor (Tr-T) may be electrically connected to the upper semiconductor pattern (AT). Alternatively, the lower electrode (G-BP) of the second transistor (Tr-T) may be electrically connected to the second upper electrode (G-UP). In addition, the upper connection wiring (UCL) may be connected to the lower wiring (SL-L) through the second to fifth insulating layers (20, 30, 40, 50). The upper connection wiring (UCL) may be electrically connected to the lower wiring (SL-L) and also electrically connected to the lower shielding pattern (BML).

[0169] The voltage wiring (SL-P), the upper wiring (SL-U), the second source electrode (SE-T), the second drain electrode (DE-T), the second gate line (SL-GU), and the upper connection wiring (UCL) may be covered with an upper insulating layer (60).

[0170] The conductive pattern (SMP) may overlap at least a portion of each of the lower semiconductor pattern (AB) and the upper semiconductor pattern (AT). The conductive pattern (SMP) may be positioned between the lower semiconductor pattern (AB) and the upper semiconductor pattern (AT) that overlap each other. The conductive pattern (SMP) may include a metal, a metal oxide, or a transparent conductive material.

[0171] Referring to FIGS. 7 and 8A, the conductive pattern (SMP) may overlap the lower semiconductor pattern (AB) on a plane defined by the first direction axis (DR1) and the second direction axis (DR2). In one embodiment, the conductive pattern (SMP) may cover the entire area of ​​the lower semiconductor pattern (AB). The conductive pattern (SMP) may cover the first transistor (Tr-B).

[0172] Referring to FIGS. 7 to 8b, the conductive pattern (SMP) may overlap the lower semiconductor pattern (AB) and the upper semiconductor pattern (AT) on a plane defined by the first direction axis (DR1) and the second direction axis (DR2). In one embodiment, the upper semiconductor pattern (AT) may completely overlap the lower semiconductor pattern (AB). The channel (CT) of the upper semiconductor pattern (AT) may overlap the channel (CB) of the lower semiconductor pattern (AB).

[0173] Referring to FIGS. 8A and 8B, the conductive pattern (SMP) may be provided to overlap the entire lower semiconductor pattern (AB) and the upper semiconductor pattern (AT). Meanwhile, although the area of ​​the upper semiconductor pattern (AT) is illustrated as being smaller than the area of ​​the lower semiconductor pattern (AB) in FIG. 8B and the like, the embodiment is not limited thereto, and the area of ​​the lower semiconductor pattern (AB) may be larger than illustrated, and in this case, the lower semiconductor pattern (AB) may overlap the conductive pattern (SMP).

[0174] The conductive pattern (SMP) is arranged to overlap with the first semiconductor pattern (AB) and the second semiconductor pattern (AT) to prevent coupling between the first transistor (Tr-B) and the second transistor (Tr-T), thereby enabling the display device to exhibit good electrical characteristics and driving characteristics even when transistors that are controlled and operated differently are aligned in the vertical direction.

[0175] A display panel (100) according to one embodiment may include a first pixel transistor (T1) and a second pixel transistor (T2). Referring to FIG. 6, the first pixel transistor (T1) and the second pixel transistor (T2) may be disposed in a display area (DA). However, the embodiment is not limited thereto, and some of the plurality of pixel transistors may be disposed in a non-display area (NDA).

[0176] The first pixel transistor (T1) may be connected to the light emitting element (ED). In one embodiment, the first pixel transistor (T1) may be a driving transistor. The second pixel transistor (T2) may be electrically connected to the first pixel transistor (T1). The second pixel transistor (T2) may be a switching transistor.

[0177] The first pixel transistor (T1) may include a third semiconductor pattern (A1) and a first gate (G1). The third semiconductor pattern (A1) may be divided into a third source (or a third source region, S1), a third channel (or a third channel region, C1), and a third drain (or a third drain region, D1). A first insulating pattern (GI1) may be disposed between the third semiconductor pattern (A1) and the first gate (G1). The first gate (G1) may be disposed on the first insulating pattern (GI1) and may be spaced apart from the third semiconductor pattern (A1) in a third direction (DR3). The first gate (G1) may overlap the third channel (C1). For example, the width of the third channel (C1) may be determined to correspond to the first gate (G1).

[0178] The third source (S1) and the third drain (D1) of the first pixel transistor (T1) may be connected to electrodes or signal lines, etc., through contact holes, etc. defined in the first insulating layer (10). The third source (S1) may be connected to the third source electrode (SE1), and the third drain (D1) may be connected to the third drain electrode (DE1). Meanwhile, the third source electrode (SE1) may be electrically connected to the lower shielding pattern (BML) through the contact holes defined in the buffer layer (BFL) and the first insulating layer (10). In addition, the third source electrode (SE1) may be electrically connected to the light-emitting element (ED) through the connection electrode (CNE). The third source electrode (SE1) and the third drain electrode (DE1) may be covered with the second insulating layer (20).

[0179] The second pixel transistor (T2) may include a fourth semiconductor pattern (A2) and a second gate (G2). The fourth semiconductor pattern (A2) may be divided into a fourth source (or fourth source region, S2), a fourth channel (or fourth channel region, C2), and a fourth drain (or fourth drain region, D2). A second insulating pattern (GI2) may be disposed between the fourth semiconductor pattern (A2) and the second gate (G2). The second gate (G2) may be disposed on the second insulating pattern (GI2) and may be spaced apart from the fourth semiconductor pattern (A2) in a third direction (DR3). The second gate (G2) may overlap the fourth channel (C2). For example, the width of the fourth channel (C2) may be determined to correspond to the second gate (G2).

[0180] The fourth source (S2) and the fourth drain (D2) of the second pixel transistor (T1) may be connected to electrodes or signal lines through contact holes defined in the first insulating layer (10). The fourth source (S2) may be connected to the fourth source electrode (SE2), and the fourth drain (D2) may be connected to the fourth drain electrode (DE2). Meanwhile, the fourth source electrode (SE2) may be electrically connected to the lower shielding pattern (BML) through contact holes defined in the buffer layer (BFL) and the first insulating layer (10). In addition, the fourth source electrode (SE2) may be electrically connected to the upper signal line (USL) through contact holes defined in the second to fifth insulating layers (20, 30, 40, 50). The fourth source electrode (SE2) and the fourth drain electrode (DE2) may be covered with the second insulating layer (20).

[0181] In one embodiment, the first pixel transistor (T1) and the second pixel transistor (T2) may be disposed on the same layer. However, the embodiment is not limited thereto, and in one embodiment, the semiconductor pattern (A1) of the first pixel transistor (T1) and the semiconductor pattern (A2) of the second pixel transistor (T2) may be disposed on different layers, or in one embodiment, the first pixel transistor (T1) and the second pixel transistor (T2) may be disposed to overlap in the third direction (DR3). In this case, a conductive pattern may be additionally disposed between the first pixel transistor (T1) and the second pixel transistor (T2).

[0182] In one embodiment, a display device can reduce the area for arranging transistors by vertically overlapping a plurality of transistors, and even when the transistors are arranged overlappingly, excellent driving characteristics can be maintained. In addition, when a plurality of circuits for providing driving signals to pixels in one row or one column must be arranged in a corresponding row or column, the transistors constituting the plurality of circuits can be arranged to vertically overlap each other, thereby reducing the spacing between rows or columns for arranging the plurality of transistors, thereby reducing the spacing between the pixels. Accordingly, the display device of one embodiment can implement high resolution.

[0183] Hereinafter, a display panel according to one embodiment and a display device according to one embodiment will be described with reference to FIGS. 9 to 16, etc. In the following description of FIGS. 9 to 16, any content overlapping with that described with reference to FIGS. 1 to 8b, etc. will not be described again, and differences will be primarily described.

[0184] The AA-1 region illustrated in FIG. 9 may correspond to the AA region of FIG. 6. FIG. 9 illustrates a cross-section of a portion of a display panel according to one embodiment. Although FIG. 9 illustrates the source, channel, and drain regions of the semiconductor patterns without distinguishing them, the same content as described in FIG. 6 and FIG. 7 can be applied to the distinction of regions of the semiconductor patterns.

[0185] Referring to FIG. 9, the lower semiconductor pattern (A-Ba) may include two stacked semiconductor pattern layers (A-BB, A-BT). In one embodiment, the first lower semiconductor layer (A-BB) and the second lower semiconductor layer (A-BT) may each be an oxide semiconductor layer. The first lower semiconductor layer (A-BB) and the second lower semiconductor layer (A-BT) may have the same oxide semiconductor material composition or may have oxide semiconductor material compositions of different compositions.

[0186] Additionally, the upper semiconductor pattern (A-Ta) may include two stacked semiconductor pattern layers (A-TB, A-TT). In one embodiment, the first upper semiconductor layer (A-TB) and the second upper semiconductor layer (A-TT) may each be an oxide semiconductor layer. The first upper semiconductor layer (A-TB) and the second upper semiconductor layer (A-TT) may have the same oxide semiconductor material composition or may have oxide semiconductor material compositions having different compositions.

[0187] Meanwhile, in Fig. 9, the first transistor (Tr-B) and the second transistor (Tr-T) each include a semiconductor pattern including two stacked semiconductor layers, but the embodiment is not limited thereto, and either the lower semiconductor pattern (A-Ba) or the upper semiconductor pattern (A-Ta) may have a structure in which multiple semiconductor layers are stacked, and the other may have a structure in which a single layer is stacked. In addition, the first transistor (Tr-B) and the second transistor (Tr-T) may each have a structure in which three or more layers are stacked.

[0188] Since the semiconductor pattern (A-Ba, A-Ta) has a structure in which multiple semiconductor layers are stacked, the electron mobility in the semiconductor pattern (A-Ba, A-Ta) can be increased by the combination of materials of the semiconductor layers.

[0189] Figures 10a and 10b are plan views each showing an embodiment of a conductive pattern. Figures 10a and 10b each show an embodiment of a conductive pattern, and the conductive pattern may have a shape in which an open area portion (HA, OPA) is defined in which a conductive material is not disposed in at least some areas.

[0190] Referring to FIG. 10a, a conductive pattern (SMP-a) according to one embodiment may have a grid pattern including a horizontal line portion (SML-H) extending in one direction on a plane and a vertical line portion (SML-V) intersecting the horizontal line portion (SML-H). An aperture pattern (HA) may be defined according to the intersecting arrangement of the horizontal line portion (SML-H) and the vertical line portion (SML-V).

[0191] Referring to FIG. 10b, at least one hole (OPA) may be defined in a conductive pattern (SMP-b) according to one embodiment. The hole (OPA) may be formed by penetrating the conductive pattern (SMP-B).

[0192] FIGS. 10A and 10B are illustrative examples of one embodiment of a conductive pattern, and the shape of the conductive pattern is not limited to that illustrated. The conductive pattern (SMP-a, SMP-b) according to one embodiment illustrated in FIGS. 10A and 10B corresponds to one in which at least a portion of the area is defined as an open area portion, and accordingly, the possibility of peeling of the conductive pattern can be reduced compared to a case in which the conductive pattern (SMP-a, SMP-b) is provided entirely without an open area. That is, when the conductive pattern (SMP-a, SMP-b) is provided with a thin film thickness, there is a risk of peeling if the provided area is wide, and therefore, when an opening pattern (HA) or a hole (OPA) is defined in the conductive pattern (SMP-a, SMP-b), the stress provided to the conductive pattern (SMP-a, SMP-b) is reduced, and thus the bonding strength attached to the neighboring insulating layer, etc. can be increased.

[0193] FIGS. 11A and 11B are cross-sectional views each showing a portion of a display panel according to one embodiment, and FIGS. 12A and 12B are plan views each showing a portion of a display panel according to one embodiment.

[0194] FIG. 11b is a cross-sectional view showing a case where an upper insulating layer (60) is added to FIG. 11a, and the AA-2a region of FIG. 11a and the AA-2b region of FIG. 11b may correspond to the AA region of FIG. 6, respectively. FIG. 12a and FIG. 12b may be plan views showing a part of a part corresponding to the AA-2b region shown in FIG. 11b. FIG. 12a is an example of a plane in which a first transistor (Tr-B) and a conductive pattern (SMP-b) are arranged on the first transistor (Tr-B), and FIG. 12b is an example of a plane in which a second transistor (Tr-T) is arranged on the stacked structure of the first transistor (Tr-B) and the conductive pattern (SMP-b) of FIG. 12a. In FIG. 12a and FIG. 12b, some of the laminated structure is omitted and illustrated, and the overlapping relationship between the semiconductor pattern of the first transistor (Tr-B), the conductive pattern (SMP-b), and the semiconductor pattern of the second transistor (Tr-T) is illustrated with emphasis.

[0195] A display panel according to one embodiment may include a hole region defined to penetrate two or more insulating layers among stacked insulating layers included in a circuit layer. Referring to FIGS. 11A and 11B , in the display panel according to one embodiment, a hole region (OH) may be defined to penetrate the third to fifth insulating layers (30, 40, 50) and extend to an upper portion of the second insulating layer (20). The hole region (OH) is defined in the insulating layers, and a conductive pattern, a semiconductor pattern, a wiring, or the like may not overlap in the hole region (OH). The hole region (OH) formed by penetrating the insulating layers has a contact hole shape, but a conductive material is not placed in the hole region (OH), and thus, the hole region (OH) may be referred to as a dummy contact hole.

[0196] In FIGS. 11a and 11b, an embodiment in which the hole region (OH) is integrally formed from the second insulating layer (20) to the fifth insulating layer (50) is illustrated, but the embodiment is not limited thereto, and the hole region (OH) may be formed in a form in which it starts from any one of the first to fourth insulating layers (10, 20, 30, 40) and penetrates the upper insulating layers. For example, the hole region (OH) may be defined by penetrating from any one of the first to fourth insulating layers (10, 20, 30, 40) to the fifth insulating layer (50).

[0197] The hole region (OH) can be filled with a material of the upper insulating layer in which the hole region is not defined. Referring to FIG. 11b and the like, in one embodiment, the hole region (OH) can be filled with the upper insulating layer (60).

[0198] In one embodiment, the hole region (OH) may be non-overlapping with the conductive pattern (SMP-b). A hole (OPA) may be defined in the conductive pattern (SMP-b) overlapping the hole region (OH).

[0199] A display device according to one embodiment can allow outgas generated under high temperature conditions or the like in the lower portions of insulating layers or in insulating layers during a display panel manufacturing process to be discharged without being transmitted to transistors or conductive patterns by including a hole region (OH) in a circuit layer that is not covered with a metal or conductive material, such as a conductive pattern or a transistor, and formed by penetrating a plurality of insulating layers, so that outgas can be easily discharged through the hole region (OH) in the circuit layer, such as a conductive pattern or a transistor, so that the reliability of the conductive pattern and the transistor can be secured. Therefore, the display device according to one embodiment can exhibit excellent reliability and driving characteristics.

[0200] Referring to FIGS. 12a and 12b, the conductive pattern (SMP-b) may be provided to overlap the entire lower semiconductor pattern (AB) and the upper semiconductor pattern (AT). Meanwhile, although the area of ​​the upper semiconductor pattern (AT) is illustrated as being smaller than the area of ​​the lower semiconductor pattern (AB) in FIG. 12b and the like, the embodiment is not limited thereto, and the area of ​​the lower semiconductor pattern (AB) may be larger than illustrated, and in this case, the lower semiconductor pattern (AB) may overlap the conductive pattern (SMP-b).

[0201] The conductive pattern (SMP-b) is arranged to overlap the first semiconductor pattern (AB) and the second semiconductor pattern (AT) to prevent the coupling phenomenon of the first transistor (Tr-B) and the second transistor (Tr-T), so that even when transistors that are controlled and operated differently are aligned in the vertical direction, the display device can exhibit good electrical characteristics and driving characteristics. In addition, the conductive pattern (SMP-B) includes a hole (OPA) defined to overlap the entire hole area (OH) formed by penetrating the insulating layers, so that the hole area (OH) is not covered by a conductive layer, etc., so that the lower outgas can be easily discharged through the hole area (OH). Therefore, the display device of one embodiment can exhibit excellent reliability characteristics because the adhesion of the conductive pattern (SMP-b) is increased by the hole (OPA) defined in the conductive pattern (SMP-b), and the discharge of gas generated during the manufacturing process is also facilitated through the hole area (OH) overlapping the hole (OPA).

[0202] Fig. 13 is a cross-sectional view of a display panel according to one embodiment. Area AA-3 of Fig. 13 may correspond to areas AA of Figs. 6 and 7. Referring to Fig. 13, the display panel according to one embodiment has a difference in the shape of electrodes or wires connected to a lower shielding pattern (BML), a first transistor (Tr-B), a second transistor (Tr-T), or a conductive pattern (SMP) through contact holes of insulating layers compared to the display panel of Fig. 7.

[0203] In one embodiment, the conductive pattern (SMP) is connected to a voltage line (SL-Pa) to which a constant voltage is applied, and further, the conductive pattern (SMP) may be electrically connected to at least one of the first semiconductor pattern (AB) and the second semiconductor pattern (AT). Referring to FIG. 13, the voltage line (SL-Pa) may be electrically connected to the conductive pattern (SMP) and the first source electrode (SE-Ba). Therefore, the conductive pattern (SMP) may be electrically connected to the voltage line (SL-Pa), which is a constant voltage line, and may be electrically connected to the first semiconductor pattern (AB). In addition, the second source electrode (SE-Ta) may be electrically connected to the second semiconductor pattern (AT) and the conductive pattern (SMP). Meanwhile, unlike as illustrated in FIG. 13, the conductive pattern (SMP) may be electrically connected to only one of the first semiconductor pattern (AB) and the second semiconductor pattern (AT).

[0204] Even when the conductive pattern (SMP) is electrically connected to at least one of the first semiconductor pattern (AB) and the second semiconductor pattern (AT), a predetermined DC voltage of the conductive pattern (SMP) is applied, and a coupling phenomenon between the first transistor (Tr-B) and the second transistor (Tr-T) can be prevented by the conductive pattern (SMP).

[0205] Fig. 14 is a cross-sectional view of a portion of a display panel according to one embodiment. The display panel (100-1) according to this embodiment illustrated in Fig. 14 differs from the display panel (100) of the embodiment illustrated in Fig. 6 in that it further includes capacitors (CAP1, CAP2).

[0206] In one embodiment of the display panel (100), the circuit layer (DP-CL) may further include a capacitor (CAP1, CAP2) including a first sub-conductive pattern (SMP-S) disposed on the same layer as the conductive pattern (SMP) and including the same material as the conductive pattern (SMP), and a second sub-conductive pattern (BML2, CMP) disposed on or below the first sub-conductive pattern (SMP-S) so as to overlap the first sub-conductive pattern (SMP-S).

[0207] Referring to FIG. 14, one embodiment may include at least one of a first auxiliary capacitor (CAP1) composed of a second-first sub-conductive pattern (BML2) and a first sub-conductive pattern (SMP-S), and a second auxiliary capacitor (CAP2) composed of a second-second sub-conductive pattern (CMP) and a first sub-conductive pattern (SMP-S). Meanwhile, the stacked structure of the second sub-conductive pattern (BML2, CMP) illustrated in FIG. 14 is taken as an example, and the second sub-conductive pattern (BML2, CMP) may be arranged on the same layer as a semiconductor pattern or an upper electrode or a lower electrode.

[0208] That is, the display device of one embodiment further includes a capacitor composed of a first sub-conductive pattern (SMP-S) disposed on the same layer as the conductive pattern (SMP) and a second sub-conductive pattern (BML2, CMP) disposed on the same layer as other conductive layers, wiring, electrode patterns, etc. included in the circuit layer (DP-CL), so that the storage cap (capacitance) can be increased.

[0209] Fig. 15 is a cross-sectional view of a portion of a display panel of one embodiment. Referring to Fig. 15, the display panel (100-2) of one embodiment may include a plurality of sets of transistors arranged to overlap vertically.

[0210] A display panel (100-2) of one embodiment may include a first-first transistor (Tr-B1) and a second-first transistor (Tr-T1) arranged to overlap in a third direction (DR3), and a first-second transistor (Tr-B2) and a second-second transistor (Tr-T2) arranged to overlap in a third direction (DR3). The semiconductor patterns of the first-first transistor (Tr-B1) and the second-first transistor (Tr-T1) may overlap each other, and the semiconductor patterns of the first-second transistor (Tr-B2) and the second-second transistor (Tr-T2) may overlap each other.

[0211] In the display panel (100-2) of one embodiment, the first-first transistor (Tr-B1) and the first-second transistor (Tr-B2) may be disposed on the same layer, and the second-first transistor (Tr-T1) and the second-second transistor (Tr-T2) may be disposed on the same layer. However, the embodiment is not limited thereto, and any laminated structure in which the first-first transistor (Tr-B1) and the second-first transistor (Tr-T1) overlap, and the first-second transistor (Tr-B2) and the second-second transistor (Tr-T2) overlap may be used without limitation.

[0212] A first conductive pattern (SMP1) may be arranged between the first-first transistor (Tr-B1) and the second-first transistor (Tr-T1). The first conductive pattern (SMP1) may overlap the semiconductor pattern of the first-first transistor (Tr-B1) and the semiconductor pattern of the second-first transistor (Tr-T1). The first conductive pattern (SMP1) may be electrically connected to a first voltage line (SL-P1). A predetermined constant voltage may be applied to the first conductive pattern (SMP1) through the first voltage line (SL-P1).

[0213] A second conductive pattern (SMP2) may be arranged between the first-second transistor (Tr-B2) and the second-second transistor (Tr-T2). The second conductive pattern (SMP2) may overlap the semiconductor pattern of the first-second transistor (Tr-B2) and the semiconductor pattern of the second-second transistor (Tr-T2). The second conductive pattern (SMP2) may be electrically connected to a second voltage line (SL-P2). A predetermined constant voltage may be applied to the second conductive pattern (SMP2) through the second voltage line (SL-P2).

[0214] Different constant voltage lines may be electrically connected to the first conductive pattern (SMP1) and the second conductive pattern (SMP2). The DC voltage provided to the first voltage wire (SL-P1) connected to the first conductive pattern (SMP1) and the DC voltage provided to the second voltage wire (SL-P2) connected to the second conductive pattern (SMP2) may have different voltage levels.

[0215] The second conductive pattern (SMP2) may be spaced apart from the first conductive pattern (SMP1) on a plane. The display panel (100-3) of one embodiment may include a plurality of conductive patterns that are distinct from each other, and the plurality of conductive patterns may be arranged to be spaced apart from each other on a plane. Furthermore, in one embodiment, different constant voltage lines may be electrically connected to each of the conductive patterns.

[0216] Fig. 16 is a cross-sectional view of a portion of a display panel of one embodiment. Fig. 16 illustrates a portion of a display area (DA) of the display panel (100-3). Fig. 16 may correspond to the display area of ​​Fig. 6.

[0217] In a display panel (100-3) according to one embodiment, a plurality of transistors constituting a pixel circuit may be arranged to overlap in a third direction (DR3). Referring to FIG. 16, a first pixel transistor (T1) and a second pixel transistor (T2-a) may be arranged to overlap in the third direction (DR3). The first pixel transistor (T1) may be a driving transistor connected to a light-emitting element (ED), and the second pixel transistor (T2-a) may be a switching transistor electrically connected to the first pixel transistor (T1).

[0218] The first pixel transistor (T1) may include a semiconductor pattern (third semiconductor pattern, A1) and a gate (third gate, G1). A first insulating pattern (GI1) may be arranged between the semiconductor pattern (third semiconductor pattern, A1) and the gate (third gate, G1). A source electrode (SE1) and a drain electrode (DE1) may be electrically connected to the semiconductor pattern (A1). The source electrode (SE1) of the first pixel transistor (T1) may be electrically connected to a light-emitting element (ED) via a connection electrode (CNE).

[0219] The second pixel transistor (T2-a) may include a semiconductor pattern (a fourth semiconductor pattern, A2), an upper gate (G2-T), and a lower gate (G2-B). A second insulating pattern (GI2) may be disposed between the semiconductor pattern (the fourth semiconductor pattern, A2) and the upper gate (G2-T). A source electrode (SE2) and a drain electrode (DE2) may be electrically connected to the semiconductor pattern (A2).

[0220] Meanwhile, in one embodiment, at least one semiconductor pattern of the first pixel transistor (T1) and the second pixel transistor (T2) may include a metal oxide. The first pixel transistor (T1) and the second pixel transistor (T2) may include oxide semiconductor patterns having the same composition, or may include oxide semiconductor patterns having different material components or different material ratios.

[0221] The semiconductor pattern (third semiconductor pattern, A1) of the first pixel transistor (T1) may overlap with the semiconductor pattern (fourth semiconductor pattern, A2) of the second pixel transistor (T2-a). A conductive pattern (SMP) may be arranged on the first pixel transistor (T1) and the second pixel transistor (T2-a). The conductive pattern (SMP) may be referred to as a pixel portion conductive pattern. The conductive pattern (SMP) may overlap with the semiconductor pattern (third semiconductor pattern, A1) of the first pixel transistor (T1) and the semiconductor pattern (fourth semiconductor pattern, A2) of the second pixel transistor (T2-a). Although not illustrated in FIG. 16, the conductive pattern (SMP) may be connected to a voltage wiring, and a predetermined constant voltage may be applied to the conductive pattern (SMP).

[0222] Since the conductive pattern (SMP) is arranged to overlap the semiconductor pattern (third semiconductor pattern, A1) of the first pixel transistor (T1) and the semiconductor pattern (fourth semiconductor pattern, A2) of the second pixel transistor (T2-a), even when the first pixel transistor (T1) and the second pixel transistor (T2-a) are arranged to overlap in the vertical direction, a coupling phenomenon does not occur, and thus the display device of one embodiment can exhibit excellent driving characteristics.

[0223] In addition, although only the stacked arrangement of pixel transistors (T1, T2-a) is illustrated in FIG. 16, other transistors than the pixel transistors may also have a structure in which they are arranged vertically overlapping, as described with reference to FIGS. 6 to 15, etc. Accordingly, the display device of one embodiment can exhibit improved display quality and resolution characteristics by arranging the transistors to overlap in the vertical direction, thereby reducing the area for arranging the transistors, thereby increasing the area of ​​the display portion (light-emitting area), and reducing the area of ​​the non-display portion (non-light-emitting area, dead space, etc.).

[0224] A display device of one embodiment may include a lower transistor and an upper transistor arranged to vertically overlap each other, and a conductive pattern arranged between the lower transistor and the upper transistor to overlap both a semiconductor pattern of the lower transistor and a semiconductor pattern of the upper transistor. Accordingly, the display device of one embodiment may reduce a space for arranging transistors to minimize dead space, and may implement high resolution by reducing an arrangement interval between pixels by arranging the transistors in an integrated manner. In addition, by arranging the conductive pattern between the transistors, a coupling phenomenon between the transistors may be prevented, thereby exhibiting excellent electrical characteristics and driving characteristics.

[0225] Fig. 17 is a block diagram of an electronic device according to one embodiment. Referring to Fig. 17, an electronic device (DD) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0226] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0227] The memory (13) may store data information required for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) may process the received signal and output image information through a display screen. The display module (11) may include a display panel that displays an image. In addition, the display module (11) may further include an electronic module that receives image information, sensing information, optical signal information, etc.

[0228] The power module (14) may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device (DD).

[0229] The electronic device (DD) may include a display device that generates and displays an image. The display device may be a part that includes a display module (11). In addition, some of the components or individual modules of the electronic device (DD) described above may be included in the display device, while others may be provided separately from the display device. For example, the display device may include the display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (DD) rather than the display device.

[0230] FIG. 18 is a schematic diagram of an electronic device according to various embodiments.

[0231] Referring to FIG. 18, various electronic devices including a display device according to one embodiment may include not only image display electronic devices such as a smart phone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and vehicle electronic devices (10_3) including display modules such as a CID (Center Information Display) and a room mirror display arranged on a dashboard, center fascia, or car instrument panel. Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims to be described later.

[0232] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0233] The present invention relates to a display device and an electronic device including a lower transistor and an upper transistor arranged to overlap vertically, and a conductive pattern arranged to overlap both the semiconductor pattern of the lower transistor and the semiconductor pattern of the upper transistor. The display device and the electronic device of one embodiment have high industrial applicability because the space for arranging the transistors can be reduced to minimize dead space, and the transistors are arranged in an integrated manner to reduce the arrangement interval between pixels, thereby realizing high resolution.

Claims

1. Base layer; A circuit layer disposed on the base layer, the circuit layer including a first transistor, a second transistor disposed on the first transistor, and a conductive pattern disposed between the first transistor and the second transistor; and A display layer disposed on the circuit layer and including a light-emitting element; The first transistor includes a first semiconductor pattern and a first upper electrode disposed on the first semiconductor pattern, The second transistor includes a second semiconductor pattern, a second upper electrode disposed on the second semiconductor pattern, and a lower electrode disposed below the second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern overlap, A display device in which the above-mentioned challenge pattern overlaps at least a portion of each of the first semiconductor pattern and the second semiconductor pattern.

2. In paragraph 1, A display device wherein at least one of the first semiconductor pattern and the second semiconductor pattern includes an oxide semiconductor.

3. In paragraph 2, The above oxide semiconductor is a display device having a mobility of 20㎠ / Vs or more.

4. In paragraph 2, A display device in which the oxide semiconductor is a metal oxide containing indium, gallium, and zinc, and the content of the indium in the metal oxide is at least twice the content of the gallium.

5. In paragraph 2, A display device comprising a plurality of layers, at least one of the first semiconductor pattern and the second semiconductor pattern being stacked in the thickness direction and having different oxide semiconductor material compositions.

6. In paragraph 1, The above-mentioned conductive pattern is a display device including a metal, a metal oxide, or a transparent conductive material.

7. In paragraph 1, A display device in which the above-mentioned conductive pattern is electrically connected to a constant voltage line, and the lower electrode is electrically connected to the second semiconductor pattern or the second upper electrode.

8. In paragraph 1, The above challenge pattern is a display device including a grid pattern including a horizontal line portion extending in one direction on a plane and a vertical line portion intersecting the horizontal line portion.

9. In paragraph 1, A display device having at least one hole defined in the above challenge pattern.

10. In paragraph 1, A display device, wherein the circuit layer further comprises a first insulating layer covering the first semiconductor pattern, a second insulating layer disposed between the first insulating layer and the conductive pattern, a third insulating layer disposed between the conductive pattern and the lower electrode, a fourth insulating layer covering the lower electrode, a fifth insulating layer covering the second semiconductor pattern, and an upper insulating layer disposed on the fifth insulating layer.

11. In paragraph 10, A display device in which a hole region is defined penetrating from any one of the first to fourth insulating layers to the fifth insulating layer, and the upper insulating layer is filled in the hole region.

12. In paragraph 10, A display device in which at least one of the upper surface of the second insulating layer and the upper surface of the third insulating layer is a flat surface.

13. In paragraph 1, The above challenge patterns are multiple and distinct from each other, A display device in which the above plurality of conductive patterns are spaced apart from each other on a plane, and different constant voltage lines are electrically connected to each of the conductive patterns.

14. In paragraph 1, A display device in which a constant voltage is applied to the conductive pattern, and the conductive pattern is electrically connected to at least one of the first semiconductor pattern and the second semiconductor pattern.

15. In paragraph 1, A display device further comprising a capacitor, wherein the circuit layer comprises a first sub-conductive pattern disposed on the same layer as the conductive pattern and including the same material as the conductive pattern, and a second sub-conductive pattern disposed above or below the first sub-conductive pattern, overlapping the first sub-conductive pattern.

16. It is divided into a display area and a non-display area arranged on at least one side of the display area, base layer; A display layer disposed on the base layer and including a plurality of light-emitting elements disposed corresponding to the display area; and A circuit layer disposed between the base layer and the display layer, and including a plurality of transistors and a plurality of insulating layers; The circuit layer comprises a pixel circuit electrically connected to the light-emitting element; and A gate driving circuit disposed in the non-display area, comprising a lower transistor, an upper transistor disposed on the lower transistor, and a conductive pattern disposed between the lower transistor and the upper transistor; The lower transistor includes a first semiconductor pattern and a first upper electrode disposed on the first semiconductor pattern, The upper transistor includes a second semiconductor pattern, a second upper electrode disposed on the second semiconductor pattern, and a lower electrode disposed below the second semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern overlap, An electronic device in which the above-mentioned challenge pattern overlaps at least a portion of each of the first semiconductor pattern and the second semiconductor pattern.

17. In paragraph 16, An electronic device wherein at least one of the first semiconductor pattern and the second semiconductor pattern comprises a metal oxide including at least one of indium, gallium, zinc, tin, and titanium.

18. In paragraph 16, The pixel circuit includes a driving transistor including a third semiconductor pattern, and a switching transistor including a fourth semiconductor pattern that is distinct from the third semiconductor pattern. An electronic device wherein at least one of the third semiconductor pattern and the fourth semiconductor pattern comprises a metal oxide including at least one of indium, gallium, zinc, tin, and titanium.

19. In paragraph 18, An electronic device in which the third semiconductor pattern and the fourth semiconductor pattern are arranged on the same layer as the first semiconductor pattern.

20. In paragraph 18, The third semiconductor pattern is arranged on the same layer as either the first semiconductor pattern or the second semiconductor pattern, The fourth semiconductor pattern is arranged on the upper or lower side of the third semiconductor pattern, overlapping the third semiconductor pattern. An electronic device wherein the circuit layer further includes a pixel conductive pattern disposed between the third semiconductor pattern and the fourth semiconductor pattern.

Images