Radiation hardened FLIP-flop storage for efpga configuration bits

Abstract

Disclosed herein are various embodiments for radiation-hardened, SEU tolerant configuration FFs for standard cell-based eFPGA fabrics. These various embodiments include a dual-storage-mode (DSM) FF, a dual-modular redundant slave latch (DMR-SL) FF and a HALF-DICE FF. These embodiments assume that a radiation strike is likely to affect only one element of a radiation-hardened FF and provide additional circuitry to introduce an automatic refresh feature into the designs sufficient to recover from an SEU.

Description

Attorney Docket: 8350.2024-294WORADIATION HARDENED FLIP-FLOP STORAGE FOR EFPGA CONFIGURATION BITSRelated Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 683,602, filed August 15, 2024, the contents of which are hereby incorporated herein in their entirety.Background

[0002] Soft embedded FPGA (eFPGA) fabrics are increasingly used in modern heterogeneous system-on-a-chip (SoC) designs as they offer flexibility by accelerating various workloads while providing better energy efficiency than a CPU. Multiple commercial vendors provide radiation hardened versions of their eFPGAs for integration into SoCs. Unlike traditional FPGA fabrics that use SRAM cells for configuration bits, eFPGA fabrics are typically built using standard cells and store configuration bits in flip-flops (FFs).

[0003] The flip-flops used as configuration bits in the eFPGA are susceptible to single event upsets (SEUs) caused by radiation strikes. A single event upset is a temporary change in the state of an integrated circuit caused by energetic particles, such as protons, neutrons, or heavy ions, when they interact with the semiconductor. SEUs are particularly problematic in eFPGAs when they occur in configuration memory. An SEU in the configuration memory canAttorney Docket: 8350.2024-294WO permanently alter the circuit implemented on the eFPGA fabric. Although SEUs are transient, they manifest as permanent errors in the design implemented on the eFPGA until the SEU is corrected by reconfiguration or configuration scrubbing.

[0004] More than 86% of SEUs occur in configuration storage elements. When block RAMs are protected with error correction code (ECC), configuration SEUs represent more than 95% of the SEUs in an eFPGA. Therefore, it is important to protect the configuration memory from SEUs to reduce application failure rates in an eFPGA fabric.

[0005] Techniques such as configuration scrubbing, dual modular redundancy (DMR), and triple modular redundancy (TMR) can be used to reduce the mean time to failure (MTTF) of eFPGA designs according to the requirements of the radiation environment. However, techniques such as TMR typically incur high area (3-4x) and performance overheads. Because eFPGA fabrics can be synthesized from RTL and implemented using standard cells, the eFPGA fabric can be easily modified, unlike commercial SRAM-based FPGAs, which can take many months or years to redesign. The ease of modifying the eFPGA fabric opens new avenues for more efficient hardening of the FPGA fabric.

[0006] Because FFs used to store the eFPGA configuration typically only account for around 30% of the eFPGA area but contribute to most of the SEUs in an eFPGA, hardening the eFPGA configuration cells can significantly reduce softAttorney Docket: 8350.2024-294WO error rates (SER) of eFPGA designs with minimal area overhead. Therefore, it would be desirable to provide designs to harden the FFs specifically used for the configuration cells of the eFPGA.Summary of the Invention

[0007] Disclosed herein are various embodiments for radiation-hardened, SEU tolerant configuration FFs for standard cell-based eFPGA fabrics.

[0008] The configuration FFs of an eFPGA have different characteristics than the regular FFs in the eFPGA. The purpose of a configuration FFs is to hold the configuration bits for millions of cycles until they are reconfigured or updated by a configuration scrubber. Because the configuration FFs store a static value, they are not in the critical path, and their contribution to the dynamic power of the eFPGA is negligible. Therefore, the new designs for the configuration of FFs must focus on minimizing the on-chip area occupied by the FFs and maximizing the SEU resilience.

[0009] Because the eFPGA configuration storage is static, the master latch of the FF is transparent and unused, except when a configuration is loaded. The configuration bits are stored only in the slave latch, and hardening the slave latch is sufficient to provide the required error-tolerance.Attorney Docket: 8350.2024-294WO

[0010] In a first embodiment, a dual-storage-mode (DSM) FF is disclosed that reuses the master and slave latches as redundant storage along with a C-element for error correction.

[0011] In a second embodiment, a dual-modular redundant slave latch (DMR-SL) FF is disclosed as a first modification to a duel-interlocked storage cell (DICE) which duplicates only the slave latch and uses a C-element for error correction.

[0012] In a third embodiment, a HALF-DICE FF is disclosed, wherein only the slave latch is converted to a DICE latch, and the master latch is left unmodified.

[0013] Because a large portion of a typical eFPGA configuration is unused, there is ample potential to drastically reduce area overheads by hardening sections of the configuration with one or more of the different embodiments of hardened FFs disclosed herein and mapping the design to the hardened sections based on the architecture vulnerability factor of the different primitives in the design.Brief Description of the Drawings

[0014] By way of example, specific exemplary embodiments of the disclosed system and method will now be described, with reference to the accompanying drawings, in which:

[0015] FIG. 1 is a schematic of a dual storage mode flip-flop in accordance with a first embodiment of the invention.Attorney Docket: 8350.2024-294WO

[0016] FIG. 2 is a schematic and truth table of the Muller C-element.

[0017] FIG. 3 is a schematic of a prior art master-slave DICE FF.

[0018] FIG. 4 is a schematic of the dual modular slave latch FF in accordance with a second embodiment of the invention.

[0019] FIG. 5 is a schematic of the DMR-LAT-CEL FF and the DMR_LCN FF variants of the DMR-SL FF.

[0020] FIG. 6 is a schematic of the Half-DICE FF in accordance with a third embodiment of the invention.Detailed Description

[0021] Dual Storage Mode FF Embodiment

[0022] In a first embodiment of the invention, a dual-storage-mode FF (DSM-FF) design is disclosed. This design reuses existing storage elements (i.e., the master and slave latches) in a D-FF as redundant storage nodes to increase tolerance to SEUs. A schematic of the DSM-FF is shown in FIG. 1. In a standard D-FF, one of the master or slave latches is always transparent. For a positive edge-triggered D-FF, the master is transparent when CLK = 0 and the slave is transparent when CLK - 1. The D-FF is modified to introduce an additional signal, that can force the master latch from transparent mode to storage mode. In this scenario, redundant master and slave latches can be used to increase the SEU resilience of the DSM-FF by adding an error correction element before the output. A Muller C-element is inserted beforeAttorney Docket: 8350.2024-294WO the output of the DSM-FF and can be used to correct an error in one of the storage nodes.

[0023] A schematic of the C-element as shown in FIG. 2. The C-element outputs 0 when all inputs are 0, and outputs 1 when all inputs are 1. Otherwise, the previous output state is retained. The C-element can be implemented by feeding back the output of a majority gate to one of its inputs. When one of the storage nodes experiences an upset, the feedback tunes the C-element stateful retaining the correct output value. The majority gate performs the same function as the carry cell (AB + BC + CA), and the carry cells in the std- cell library are already well optimized for reducing delay. Therefore, the use of a carry cell to construct the C element can significantly reduce its delay. When replacing the output inverter in a D-FF with a delay-optimized C- element, the impact on the CLK-Q delay can be negligible.

[0024] Radiation-tolerant FFs that use redundant storage cells can experience an SEU due to two different scenarios. First, a multi-bit upset (MBU) can cause two redundant storage nodes to flip simultaneously. It is not possible to correct this error using a C-element or a majority voter. The impact of the MBU can only be reduced by increasing the node spacing between the redundant storage nodes. The second scenario is caused by an accumulation of errors in which the two storage nodes are independently flipped at two different points in time. SEUs due to error accumulation can be avoided if the first storage node experiencing an SEU is restored to the correct value using aAttorney Docket: 8350.2024-294WO refresh mechanism before the second storage node is upset. This refresh mechanism can be performed externally using configuration scrubbing or locally at the cell level. The external configuration scrubbing is typically a slow process, as the entire configuration must be read from an external device or memory and written into the eFPGA configuration cells. Therefore, in the DSM-FF, a local self-refresh is implemented by using the output of a multiplexor (having the C-element output as an input to the multiplexor) as an input of the master latch to recirculate the corrected output from the C- element in the DSM-FF. This provides a periodic automatic refresh of the storage nodes.

[0025] DMR-SL and HALF-DICE Embodiments

[0026] Due to the static nature of the configuration FFs, the configuration bit is always stored in the slave latch (CLK = 0), except for the one cycle when a new configuration bit is loaded into the FF. Therefore, in these embodiments, only the slave latch of the FF is hardened to minimize the area occupied by the FF.

[0027] In a second embodiment of the invention, a dual-modular redundant slave latch (DMR-SL) FF is disclosed. The DMR-SL, shown schematically in FIG. 4, is a modification to a master-slave duel interlocked storage cell (DICE), shown in FIG. 3, in which the slave latch is duplicated (SI and S2) and a C-element is used at the end for error correction to reduce the area overhead compared to, for example, a DMR_CEL FF.Attorney Docket: 8350.2024-294WO

[0028] Two additional variants of the DMR-SL FF are also disclosed and are shown in schematic form in FIG. 5. The first variant is the DMR-LAT-CEL FF, where the D-FF (M and SI latch), the S2 latch, and the C-element are separated into three individual cells on the eFPGA to increase the spacing between the storage nodes. The second variant is called the DMR-LCN, where the S2 latch and the C-element in the DMR-LAT-CEL FF are combined into a single latch plus C-element (LCN cell).

[0029] Self-refresh can be added by the additional of a self-refresh refresh multiplexor to the DMR-SL, and its two variants, as discussed above with respect to the first embodiment.

[0030] In a third embodiment of the invention, shown in FIG. 6, a HALF-DICE FF is disclosed where only the slave latch is implemented as DICE latch, and the master is left unhardened.

[0031] The ability to easily modify and port eFPGAs creates new avenues for exploring radiation-hardened eFPGA designs. Because configuration SEUs cause most of the failures in the FPGA, especially when SRAM memories are protected with ECC, this invention is focused on area-efficient, radiation hardened FFs for hardening that are specifically designed for the configuration cells of the eFPGA.

[0032] As would be realized by one of skill in the art, many variations on implementations discussed herein which fall within the scope of the invention are possible. Specifically, many variations of the components usedAttorney Docket: 8350.2024-294WO and their arrangement could be used to obtain similar results. The invention is not meant to be limited to the particular exemplary embodiments disclosed herein. Moreover, it is to be understood that the features of the various embodiments described herein were not mutually exclusive and can exist in various combinations and permutations, even if such combinations or permutations were not made express herein, without departing from the spirit and scope of the invention. Accordingly, devices disclosed herein are not to be taken as limitations on the invention but as an illustration thereof.

Claims

Attorney Docket: 8350.2024-294WOClaims:

1. A radiation-hardened flip-flop comprising: a master latch having an output; a slave latch having an output and having as input the output from the master latch; and a C-element having as inputs the outputs from the master and slave latches; wherein an output of the C-element is the output of the flip-flop.

2. The flip-flop of claim 1 further comprising: a NOR gate combining a clock and digital signal masking signal input to the master latch.

3. The flip-flop of claim 1 further comprising: a multiplexor controlling input to the master latch to provide automatic refresh of the flip-flop.

4. The flip-flop of claim 3 wherein the output of the C-element is fed back as one input to the multiplexor.

5. A radiation-hardened flip-flop comprising:Attorney Docket: 8350.2024-294WO a master latch having an output; a first slave latch having an output and having as input the output from the master latch; a second slave latch having an output and having as input the output from the first slave latch; and a C-element having as inputs the outputs from the first slave latch and the second slave latch; wherein an output of the C-element is the output of the flip-flop.

6. The flip flop of claim 5 wherein an inverted clock signal is fed to the master latch and a non-inverted clock signal is fed to the first and second slave latches.

7. The flip-flop of claim 5 further comprising: a multiplexor controlling input to the master latch to provide automatic refresh of the flip-flop.

8. The flip-flop of claim 7 wherein the output of the C-element is fed back as one input to the multiplexor.

9. The flip-flop of claim 5 wherein the master latch and the first slave latch, the second slave latch, and the C-element are separated into individual cells to increase the spacingAttorney Docket: 8350.2024-294WO between the storage nodes.

10. The flip-flop of claim 5 wherein the second slave latch and the C-element are combined into a single latch plus C-element cell.

11. A radiation-hardened flip-flop comprising: a standard master latch having an output; and a dual-interlocked storage cell slave latch having an output and having as input the output from the standard master latch; wherein an output of the dual-interlocked storage cell slave latch is the output of the flip-flop.

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