A programmable digitally-controlled oscillator (DCO) and a backscattered software-defined radio (SDR) transmitter system comprising the programmable dco

Abstract

A programmable digitally-controlled oscillator (DCO) for time-domain symbol generation is described in an embodiment. The programmable DCO comprising: an odd number (n) of multi delay cells (MDGs) to form a ring oscillator, the odd number (n) being equal to or more than three, and the odd number (n) of MDCs being adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation, wherein each of the n number of MDCs comprises: two or more multi jitter cells (MJCs), each of the two or more MJCs being adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit of a frequency shift keying (FSK) modulation, wherein each of the two of more MJCs comprises: two or more replica basic delay cells (BDCs) configured to adjust jitter, wherein each of the two or more replica BDC is adapted to provide a predetermined jitter target and comprises: two or more sets of reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the two or more reconfigurable inverter gates being selectable based on a target frequency range. A backscattered software-defined radio (SDR) transmitter system is also described in an embodiment.

Description

[0001] A programmable digitally-controlled oscillator (DCO) and a backscattered software-defined radio (SDR) transmitter system comprising the programmable DCO

[0002] Technical Field

[0003] The present disclosure relates to the field of Complementary Metal-Oxide- Semiconductor (CMOS) solid-state circuits and systems, and more specifically, to a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation and a backscattered software-defined radio (SDR) transmitter system comprising the programmable DCO.

[0004] Wireless transmissions are responsible for a major portion of the very limited power budget of distributed sensor nodes, especially in low-cost mm-sized integrated systems. Aggressive energy reductions in wireless transmitters for pervasive inclusion of edge- to-cloud connectivity in tightly-constrained silicon systems have been recently enabled by 2.4-GHz backscattered transmitters (TX). It is desirable that Internet of Things (loT) systems have very low costs (e.g., using high-volume manufacturing or small areas), small form factors (e.g., single antenna), long lifespan of up to decades (e.g. being embedded into physical objects or deployed in infrastructure), and data-rates from <100 kbps (e.g., Z-Wave, Zigbee) to several Mbps (e.g., WiFi) for most applications.

[0005] Prior backscattered transmitters typically support a single custom protocol or wireless standard, and with some achieving an energy below 10 pJ / bit. To support higher manufacturing volumes and strengthen supply chain resilience and die reuse across applications, dual-standard backscattered transmitters were investigated. However, such multi-standard backscattered transmitters still restrict communications to very few protocols (e.g., 2 - 802.1 1 b and BLE) and hence (i) prohibit over-the-air updates, (ii) require device replacement upon protocol updates or upgrades, (iii) limit device lifespan, and (iv) disallow the deployment of new or proprietary protocols over the device lifecycle. On the other hand, software-defined radios (SDR) offer high levels of flexibility and upgradeability, at the cost of 2-3 orders of magnitude higher energy / bit (e.g., 2.58 nJ / bit). This is generally due to the dominant power of the Digital-to Analog Converter (DAC) used for voltage-domain symbol generation, the Phase-Locked Loop (PLL) used for frequency synthesis, and the power amplifier used.

[0006] It is therefore desirable to provide a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation and a backscattered software-defined radio (SDR) transmitter system comprising the programmable DCO which address the aforementioned problems and / or provide a useful alternative. Further, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.

[0007] Summary

[0008] Aspects of the present application relate to a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation and a backscattered software- defined radio (SDR) transmitter system comprising the programmable DCO.

[0009] In accordance with a first aspect, there is provided a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation, the programmable DCO comprising: an odd number (n) of multi delay cells (MDCs) to form a ring oscillator, the odd number (n) being equal to or more than three, and the odd number (n) of MDCs being adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation, wherein each of the n number of MDCs comprises: two or more multi jitter cells (MJCs), each of the two or more MJCs being adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit of a frequency shift keying (FSK) modulation, wherein each of the two of more MJCs comprises: two or more replica basic delay cells (BDCs) configured to adjust jitter, wherein each of the two or more replica BDC is adapted to provide a predetermined jitter target and comprises: two or more sets of reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the two or more reconfigurable inverter gates being selectable based on a target frequency range.

[0010] By having a four-stage hierarchy for the programmable DCO comprising the multi-delay cells (MDCs), the multi jitter cells (MJCs), the basic delay cells (BDCs) and the reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the programmable DCO is adapted to generate time-domain baseband signals or symbols with a high level of flexibility, covering a wide range of timing requirements from different standards. Particularly, programmable phase (e.g. using the MDCs) and frequency (e.g. using the BDCs) of the time-domain symbols using the programmable DCO can support Phase Shift Keying (PSK) and Frequency Shift Keying (FSK) modulations. The programmable jitter using the MJCs also enable adaptation of power-jitter tradeoff to minimize power consumption for a given standard jitter requirement, or chip process corner.

[0011] The programmable DCO may be programmable using a look-up table (LUT) by an embedded Field Programmable Gate Array (FPGA). By using a LUT, for example to replicate a filter response, energy used by the embedded FPGA can be reduced as compared to traditionally expensive operations for spectral mask compliance such as Gaussian Frequency Shift Keying (GFSK) pulse shaping.

[0012] In accordance with a second aspect, there is provided a backscattered software- defined radio (SDR) transmitter system comprising: a micro-controller configured to generate data packets; an embedded Field Programmable Gate Array (FPGA) configured to read the data packets generated by the micro-controller and execute signal processing for modulating a carrier signal; a programmable digitally-controlled oscillator (DCO) configured to generate time-domain symbols, the programmable DCO comprising: an odd number (n) of multi delay cells (MDCs) to form a ring oscillator, the odd number (n) being equal to or more than three, and the odd number (n) of MDCs being adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation, wherein each of the n number of MDCs comprises: two or more multi jitter cells (MJCs), each of the two or more MJCs being adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit of a frequency shift keying (FSK) modulation, wherein each of the two of more MJCs comprises: two or more replica basic delay cells (BDCs) configured to adjust jitter, wherein each of the two or more replica BDC is adapted to provide a predetermined jitter target and comprises: two or more sets of reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the two or more reconfigurable inverter gates being selectable based on a target frequency range; and a RF switch connected to a transmitter antenna, a RF impedance of the RF switch being modulated using the time-domain symbols for modulating a carrier signal using the transmitter antenna to provide a backscattered signal, wherein the embedded FPGA is configured to provide control signals to the programmable DCO for generating the time-domain symbols to modulate the RF impedance of the RF switch for modulating the carrier signal.

[0013] The embedded FPGA may be configured to program the programmable DCO using a look-up table (LUT).

[0014] The odd number of MDCs may include five MDCs and the five MDCs may be adapted to generate four multiplexed phases as 0°, 90°, 180° and 270°.

[0015] The two or more BDCs may include four replica BDCs to provide four predetermined jitter targets to satisfy jitter requirements in a range of fifty to two hundred picoseconds (PS).

[0016] The two or more sets of reconfigurable inverter gates may include three sets of transistors having three different sets of leakage-dynamic energy-speed tradeoffs to provide the corresponding frequency ranges.

[0017] The RF impedance of the RF switch may be configured to be digitally modulated between two statically assigned RF switch impedances for supporting Amplitude Shift Keying (ASK) modulation.

[0018] The microcontroller may be configured to perform pre-modulation manipulations, including cyclic redundancy check (CRC) manipulation and direct-sequence spread spectrum (DSSS) manipulation, at sub-uW power.

[0019] The backscattered software-defined radio (SDR) transmitter system may comprise an instructable address counter configured to fetch pre-encoded data packet memory associated with the microcontroller for recreating packet bitstream. In this way, efficient recreation of the packet bitstream can be achieved without using e.g. the embedded FPGA memory control which is more power intensive.

[0020] The backscattered software-defined radio (SDR) transmitter system may comprise support peripherals configured to perform coarse tuning and fine tuning of the programmable DCO. The programmable DCO may be configured to be used as a clock source for digital logics in the software-defined backscattered transmitter system.

[0021] It should be appreciated that features relating to one aspect may be applicable to the other aspects.

[0022] Embodiments of the present disclosure provide a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation and a backscattered software- defined radio (SDR) transmitter system comprising the programmable DCO. By having a four-stage hierarchy for the programmable DCO comprising the multi-delay cells (MDCs), the multi jitter cells (MJCs), the basic delay cells (BDCs) and the reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the programmable DCO is adapted to generate time-domain baseband signals or symbols with a high level of flexibility, covering a wide range of timing requirements from different standards. Particularly, programmable phase (e.g. using the MDCs) and frequency (e.g. using the BDCs) of the time-domain symbols using the programmable DCO can support Phase Shift Keying (PSK) and Frequency Shift Keying (FSK) modulations. The programmable jitter using the MJCs also enable adaptation of power-jitter tradeoff to minimize power consumption for a given standard jitter requirement, or chip process corner. The flexibility provided in the present backscattered software-defined radio (SDR) transmitter system means it is also adapted for die reuse across various applications and upgrade over a device lifespan.

[0023] Brief description of the drawings

[0024] Embodiments will now be described, by way of example only, with reference to the following drawings, in which:

[0025] Figure 1 shows a schematic to illustrate trade-offs for a conventional transmitter, a backscattered transmitter, a conventional software-defined radio transmitter and a backscattered software-defined radio transmitter in accordance with an embodiment;

[0026] Figure 2 shows a schematic of a backscattered communication scheme using a backscattered software-defined radio transmitter in accordance with an embodiment;

[0027] Figure 3 is a block diagram of a backscattered software-defined radio (SDR) transmitter system in accordance with an embodiment; Figure 4 is a circuit diagram of a programmable digitally-controlled oscillator (DCO) comprised in the backscattered SDR transmitter system of Figure 3 in accordance with an embodiment;

[0028] Figure 5 is a schematic diagram of a multi-delay cell (MDC) used in the programmable DCO of Figure 4 in accordance with an embodiment;

[0029] Figure 6 is a schematic diagram of a basic delay cell (BDC) used in the programmable DCO of Figure 4 in accordance with an embodiment;

[0030] Figure 7 shows a plot of measured power versus frequency to illustrate powerfrequency programmability of the programmable DCO of Figure 4 in accordance with an embodiment;

[0031] Figure 8 shows a plot of measured power versus jitter to illustrate power-jitter programmability of the programmable DCO of Figure 4 in accordance with an embodiment;

[0032] Figure 9 shows a plot of measured frequency versus temperature to illustrate frequency stability with temperatures of the programmable DCO of Figure 4 in accordance with an embodiment;

[0033] Figure 10 shows a measured spectrum of backscattered 802.1 1 b wireless signals using Complementary Code Keying (CCK) modulation at 1 1 Mbps in accordance with an embodiment;

[0034] Figure 1 1 shows a constellation diagram of Quadrature Phase Shift Keying (QPSK) modulated 802.1 1 b signals using CCK modulation at 1 1 Mbps in accordance with an embodiment;

[0035] Figure 12 shows a constellation diagram of Differential Binary Phase Shift Keying (DBPSK) modulated 802.1 1 b signals using Direct Sequence Spread Spectrum (DSSS) at 1 Mbps in accordance with an embodiment;

[0036] Figure 13 shows a measured spectrum of backscattered ZigBee signals at 20 kbps using Binary Phase Shift Keying (BPSK) modulation in accordance with an embodiment; Figure 14 shows a measured spectrum of backscattered Zigbee signals at 40 kbps using BPSK modulation in accordance with an embodiment;

[0037] Figure 15 shows a constellation diagram of BPSK modulated Zigbee signals at 40 kbps in accordance with an embodiment;

[0038] Figures 16A and 16B show photographs to illustrate reception of WiFi beacon frame transmitted using the backscattered software-defined radio (SDR) transmitter system of Figure 3 in accordance with an embodiment, where Figure 16A shows a photograph of a setup for demonstrating the reception including a tone generator, the backscattered SDR transmitter system and a commodity receiver and Figure 16B shows the WiFi signal obtained on the commodity receiver;

[0039] Figure 17 shows an illustration of a report including packet analysis and correct reception for WiFi beacon frame transmitted to the commodity WiFi receiver in accordance with an embodiment;

[0040] Figure 18 shows an illustration of a report including packet analysis and correct reception for ZigBee beacon frame transmitted to the commodity ZigBee receiver in accordance with an embodiment; and

[0041] Figure 19 is a die micrograph of the backscattered software-defined radio (SDR) transmitter system of Figure 3 in accordance with an embodiment.

[0042] Detailed description

[0043] Exemplary embodiments relate to a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation and a backscattered software-defined radio (SDR) transmitter system comprising the programmable DCO.

[0044] It is appreciated that in the present application, the use of the singular includes the plural unless specifically stated otherwise. It should be noted that, as used in the specification and the appended claims, the singular forms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise. Further, the use of the term “including”, “comprising”, and “having” as well as other forms, such as “include”, “comprise”, “have” are not considered limiting. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] As used herein, the term “comprising” or “including” is to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more features, integers, steps or components, or groups thereof. However, in context with the present disclosure, the term “comprising” or “including” also includes “consisting of”. The variations of the word “comprising”, such as “comprise” and “comprises”, and “including”, such as “include” and “includes”, have correspondingly varied meanings.

[0046] The present disclosure aims to fill a flexibility-energy gap between backscattered and conventional SDR transmitters. Embodiments of the present disclosure present a backscattered software-defined radio (SDR) transmitter system to enable flexible adoption of various standards, as well as to update and upgrade it over the entire device lifespan with ultra-low energy in the few tens of pJ / bit range. Embodiments of the backscattered SDR transmitter system includes a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation at the physical (PHY) layer, eliminating the traditional energy-hungry DAC in SDRs. The architecture of backscattered SDR transmitter system supports all basic modulations (PSK / FSK / ASK) and adjustable jitter-power tradeoffs, so that the energy / bit can be reduced whenever the adopted standard has a relaxed jitter requirement. In an embodiment, an on-chip low-energy embedded FPGA controls the programmable DCO, carries out digital processing for flexible PHY layer implementation, and uniquely supports conventional power-hungry physical-layer capabilities (e.g., filter-less over-sampling for pulse shaping such as GFSK modulation for the BLE standard). As discussed later in a subsequent experimental section, end-to-end demonstration in 180 nm from packet formation to transmission in an existing wireless infrastructure for various protocols is shown, achieving an energy of 34.08 pJ / bit to 58.5 pJ / bit.

[0047] Figure 1 shows a schematic 100 to illustrate trade-offs for a conventional transmitter, a backscattered transmitter, a conventional software-defined radio transmitter and a backscattered software-defined radio transmitter in accordance with an embodiment.

[0048] Conventional transmitter (TX) 102 typically is applicable only to a single standard, for example BLE and 802.11b, with high power usage. To improve from the conventional transmitter, a backscattered transmitter 104 is used which provides low power. Nonetheless, a backscattered transmitter 104 also only supports a single standard and therefore does not provide flexibility. On the other hand, a conventional software- defined radio (SDR) transmitter 106 can be adapted to provide software-defined standards which provide flexibility for the transmitter system, but typically requires use of DACs which translate to a high-power requirement. In the present disclosure, a backscattered SDR transmitter system 108 is presented for filling the flexibility-energy gap between backscattered transmitters 104 and the conventional SDR transmitters 106 which aims to provide flexibility in adapting various standards while maintaining low-power operations.

[0049] Figure 2 shows a schematic of a backscattered communication scheme 200 using a backscattered software-defined radio transmitter (or a backscatter tag in Figure 2) in accordance with an embodiment. The backscattered communication scheme 200 as shown is fully compatible with commodity hardware (e.g. commodity receiver etc.).

[0050] As shown in Figure 2, an incident wave is provided or sent by a tone generator 202 (shared among all radios in the surroundings) with properly shifted carrier frequency. In the present case, a single tone as carrier signals is sent at a frequency of fc-foco for backscattering. A backscattered SDR transmitter or a backscatter tag 204 is configured to modulate and backscatter the carrier signals from the tone generator 202 using an on-chip programmable DCO output at foco based on the modulation protocol by modulating a RF impedance of a RF switch connected to the backscattered transmitter antenna. The modulated backscattered signals are modulated and shifted back to the targeted channel frequency fc by the on-chip programmable DCO oscillator frequency foco in the backscattered SDR transmitter 204. The commodity receiver 206 (e.g. a 802.1 1 b, a BLE5, a ZigBee or a Z-wave receiver) is configured to receive and decode data packets received from the backscattered SDR transmitter 204 accordingly.

[0051] Figure 3 is a block diagram of a backscattered software-defined radio (SDR) transmitter system 300 in accordance with an embodiment.

[0052] The backscattered SDR transmitter system 300 includes a programmable packet generation unit 302, an embedded FPGA 304, a programmable DCO unit 306 having support peripherals which is used to drive or control a RF switch impedance of an antenna switch 308 for modulating an RF impedance of a transmitter antenna 310. The programmable DCO unit 306 having support peripherals and the antenna switch 308 form the physical (PHY) layer of the backscattered SDR transmitter system 300.

[0053] The programmable packet generation unit 302 comprises a microcontroller 312, an instruction memory 314 and a data memory 316. The microcontroller 312 is configured to generate data packets including basic encodings and pre-modulation manipulations (e.g., Cyclic Redundancy Check (CRC) or Direct-Sequence Spread Spectrum (DSSS)) at relaxed performance requirement (sub-pW) as it operates before transmission, and hence, with relaxed timing requirements (e.g. compared to embedded FPGA). The microcontroller 312 includes a 32-bit RISC-V Microcontroller unit (MCU) in the present embodiment. The instruction memory 314 and the data memory 316 are operationally connected to the microcontroller 312. The instruction memory 314 is configured to store and provide instructions for execution to the microcontroller 312. The instruction memory 314 is configured to receive pre-load instructions and payload at 318 and is also connected to an off-chip real-time clock 320 in the present embodiment. The off- chip real-time clock 320 is configured to utilise nW power to keep the overall power usage low in this case. The data memory 316 is adapted to store data packets generated by the microcontroller 312. The backscattered SDR transmitter system 300 also includes an instructable address counter 322 which is configured to be connected to the data memory 316 and is adapted to enable address counting for the embedded FPGA 304 to step through or read data packets from the data memory 316 at precise timing. This allows for efficient recreation of packet bitstream without using power- hungry eFPGA memory control. Particularly, address counting is needed for any modulation, and by having a specific module such as the instructable address counter 322 in the present embodiment configured to perform address counting, energy efficiency and area efficiency can be achieved in place of programming the address counting for each modulation using the power hungry eFPGA memory control.

[0054] The microcontroller 312 is configured to provide data packets and control instructions to the embedded FPGA (eFPGA) 304. The microcontroller 312, in an embodiment, is configured to cover tasks or handle a medium access control (MAC) layer. In the present embodiment, the data packets are read by the eFPGA 304 for every 32 bits. A programmable bit length may be achieved by programming a packet read MUX comprised in the eFPGA 304 as shown in relation to Figure 3. In the present embodiment, the eFPGA 304 is adaptable and can be configured to emulate any digital baseband processor. For example, four architectures each emulating a single baseband is shown in Figure 3. The four example architectures as provided relate to the 802.1 1b standard 324, the BLE5 standard 326, the Z-Wave standard 328 and the ZigBee standard 330. It should be appreciated that other architectures for other desired standards can also be included in the eFPGA 304, and in other combinations. The eFPGA 304 is therefore adaptable to be used with any form of digital baseband standard. In the present embodiment, the embedded FPGA 304 can be adapted to include a full Register-Transfer-Level (RTL) design software stack for flexible physical (PHY) layer support and for peripheral support at full transmission speed. This will allow energy reduction, in contrast to energy utilization in the range of -n J / bit energy if a processor is used. Also shown in Figure 3 are the pre-programming interfaces 332 for the eFPGA 304 which can be used to connect to parts of the programmable packet generation unit 302 and to a FPGA bitstream at 334.

[0055] The eFPGA 304 is adapted to control DCO settings of the programmable DCO unit 306 for modulating a carrier signal using the programmable DCO unit 306. In each cycle, the pre-programmed eFPGA 304 reads packets from the data memory 316, executes signal processing for modulation at the physical (PHY) layer and sets next-cycle control signals of the programmable DCO phase / frequency for time-domain symbol generation (e.g. by setting delays and / or phase for the next cycle).

[0056] The programmable DCO unit 306 includes a programmable DCO 336 which is configured to generate time-domain symbols to drive the antenna switch 308 for backscattering. The programmable DCO unit 306 of the present embodiment includes a flexible frequency-phase-jitter-power programmable DCO meeting wide requirements of different standards. Details of the programmable DCO 336 are discussed in relation to Figures 4 to 6 below.

[0057] Also shown in relation to Figure 3 is that the programmable DCO unit 306 includes support peripherals such as a low dropout (LDO) regulator 338 for coarse frequency tuning using supply voltage, a baseband (BB) regulator 340 for fine tuning using body biasing, a finite state machine (FSM) 342 adapted to provide control logic for the coarse and fine tuning of the programmable DCO 336, and a high frequency clock counter 344. In the present embodiment, a clock divider 346 is provided to divide a baseband clock from an output of the programmable DCO unit 306 so that the programmable DCO 336 is also configured to be used as a clock source for digital logics in the software-defined backscattered transmitter system 300. In the present embodiment, the programmable DCO unit 306 is event-driven regulated and is adapted to ensure correct frequency at all times but to provide power only when needed. The antenna switch 308 in the present embodiment comprises a digital switch strength selection for amplitude modulation (ASK).

[0058] In the present embodiment, the backscattered SDR transmitter system 300 as described can therefore be adapted to eliminate conventional DAC in SDR radios, by enabling purely digital modulation of the RF switch impedance is modulated purely digitally (i.e., in the time domain) using the programmable DCO 336. As will be discussed below, the programmable DCO 336 is configured to directly support Phase Shift Keying (PSK) modulation by simple phase multiplexing and Frequency Shift Keying (FSK) modulation using staged delay setting modulations. The present backscattered SDR transmitter system 300 can also be configured to support Amplitude Shift Keying (ASK) modulation by statically assigning different RF switch impedances of the antenna switch 308 when driven by different selection signals (e.g. 0 / 1 ). For example, a 50 Ohm / OFF is effectively no reflection / fully-reflected wave as required by ASK modulation with 100% modulation index (<50 Ohm for lower index). Further, eFPGA 304 flexibility allows further opportunities to reduce energy in traditionally energy-hungry operations for spectral mask compliance such as Gaussian Frequency Shift Keying (GFSK) pulse shaping. For example, this is the case of >1 Oth- order Gaussian filter in BLE and Z-Wave, where the filter smoothing frequency transitions is replaced by simple look-up tables (LUTs) replicating the filter response for the 8 combinations of triplets of consecutive symbols (Feher approximation used below in BLE, as supported by adequate inter-symbol interference control of the modulation). An example of a LUT for programmable DCO configuration is provided below in Table 1.

[0059]

[0060] Table 1 : Look-up Table (LUT) for programming the programmable DCO using the eFPGA

[0061] Figure 4 is a circuit diagram of a programmable digitally-controlled oscillator (DCO) 400 comprised in the backscattered SDR transmitter system 300 of Figure 3 in accordance with an embodiment. The programmable DCO 400 is adapted to perform time-domain symbol generation and provides a high level of flexibility and frequency-phase-jitter- power programmability as described below. The high level of flexibility and programmability enables the programmable DCO 400 to cover a wide range of timing requirements for different standards (e.g. the 802.11 b, BLE5, Z-Wave and ZigBee standards as illustrated in relation to Figure 3 above), while saving energy in those with relaxed or non-stringent timing targets. As shown in Figure 4, the programmable DCO 400 of the present embodiment includes a multiplexer 402 which is configured to be used for phase selection for PSK modulation. In the present disclosure, an odd number (n) of multi delay cells (MDCs) 404 are provided to form a ring oscillator, where the odd number (n) of MDCs 404 are adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation. More specifically, in the present embodiment, five MDCs 404 are provided and the five MDCs 404 are adapted to generate four multiplexed phases as 0°, 90°, 180° and 270° as provided by the multiplexer 402. The phase selection for PSK modulation can be performed using 2-bits (P0P1) 406 where “00” represents 0°, “01 ” represents 90°, “10” represents 180° and “11 ” represents 270°. As shown in the circuit diagram of the programmable DCO 400, programmable delay cells 408, 410, 412 are provided to program or configure the necessary phase shifts required for the PSK modulation. Each of the programmable delay cells 408, 410, 412 includes an inverter with strength control through baseband fine tuning using body biasing. For example, each of the MDC in the present embodiment is adapted to generate one of four multiplexed basic phases as a multiple of 45° (as appropriate for Mbps and below) and the programmable delay cell 408 is adapted to modulate this phase shift by two times (2x) to output a 90° phase-shift. Another example as shown in relation to the circuit diagram of Figure 4 is that after cumulating four times of 45° phase-shift (i.e. after passing through four MDCs) which results in a combined phase-shift of 180°, the programmable delay cells 410 and 412 (which total to 1.5 times) can be applied to modulate the phase-shift for outputting a phase-shift of 270°.

[0062] The programmable DCO 400 further comprises flip-flops 414, 416 which are configured to store state information and to divide frequencies. The flip-flops 414 and 416 are provided for the phase selection bits (P0P1) 406 and the delay selection bits (T0TIT2T3) 418, respectively. The present programmable DCO 400 is configured to provide on-the- fly update 420 of frequency phase configuration with registers triggered by proper digitally-controlled (DC) phases. Also shown in Figure 4 is that in the event of temperature deviations, a nW-power reference clock 422 (off-chip for simplicity) is activated for calibrating the various delay cells used in the programmable DCO 400. For example, the relative delay of the delay stages (i.e., phases) can be preliminarily calibrated at boot time against the nW reference clock 422. Support peripherals 424 such as the FSM 342 together with the LDO regulator 338 can also be used to for frequency calibration by selecting the appropriate voltage from the programmable LDO regulator 338.

[0063] Figure 5 is a schematic diagram of a multi-delay cell (MDC) 404 used in the programmable DCO 400 of Figure 4 in accordance with an embodiment.

[0064] In the present embodiment, the MDC 404 comprises four multi jitter cells (MJCs) 502, 504, 506, 508. Each of the MJCs 502, 504, 506, 508 is assigned by one of the delay selection bits (T0T1T2T3) 418 and is adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit (e.g. Toor T1 or T2or T3) of a frequency shift keying (FSK) modulation. In the present embodiment, there are therefore four different delays, corresponding to the delay selection bits (T0TIT2T3) 418, for supporting FSK modulations.

[0065] Though not explicitly shown in Figure 5, in the present embodiment, each of the four MJCs 502, 504, 506, 508 includes four replica basic delay cells (BDCs). Each of the BDCs is configured to provide a corresponding predetermined jitter target to satisfy a jitter requirement. The jitter requirement is dependent on a selected baseband which is shown in relation to Figure 8 below. In an embodiment, the jitter targets are adapted to satisfy jitter requirements in a range of fifty to two hundred picoseconds (ps). Each MJCs 502, 504, 506, 508 are therefore adapted to adjust jitter by activating an appropriate BDC.

[0066] Figure 6 is a schematic diagram of a basic delay cell (BDC) 600 used in the programmable DCO 400 of Figure 4 in accordance with an embodiment.

[0067] In the present embodiment, the BDC 600 comprises three reconfigurable inverter gates 602, 604, 606 having different channel lengths and corresponding frequency ranges. Each of the three reconfigurable inverter gates 602, 604, 606 comprises a corresponding set of transistors, where each of the corresponding sets of transistors include different channel lengths for providing a corresponding set of leakage-dynamic energy-speed tradeoffs to deliver the corresponding frequency ranges.

[0068] In the present embodiment, a first reconfigurable inverter gate 602 having transistors with long channel lengths is configured to be activated for low frequency ranges from 0.1 MHz to 3 MHz, a second reconfigurable inverter gate 604 having transistors with moderate channel length is configured to be activated for moderate frequency ranges from 3 MHz to 12 MHz, and a third reconfigurable inverter gate 606 having transistors with short channel length is configured to be activated for high frequency ranges from 12 MHz to 25 MHz. The relevant reconfigurable inverter gate 602, 604, 606 can therefore be selected based on a target frequency range. To enable selection of the appropriate BDC and the appropriate reconfigurable inverter gate, a 7-bit packet n be used where ( are the frequency range selection bits and (jijzjsj^ are the jitter selection bits.

[0069] By implementing the reconfigurable inverter gates 602, 604, 606, a power utilized by the programmable DCO 400 can be minimized across a wide range of foco frequencies (from tens of kHz to tens of MHz), e.g., by selecting the slowest frequency range for low foco targets to avoid an overwhelming consumption of a frequency-divided fast programmable DCO 400 when supporting low data-rates. This also aids to keep the supply voltage of the programmable DCO 400 in a relatively small range (0.8 V to 1 V) for inexpensive power management and low costs. For example, in this case, no voltage domains / level shifters are required to manage at run time, which would otherwise add complexity and energy when adapting to different standards. Further, with the hierarchical structure of the programmable DCO 400 as described above, a wide frequency-phase-jitter-power programmability can be achieved. This is demonstrated in relation to Figures 7 to 9 below.

[0070] Figure 7 shows a plot 700 of measured power versus frequency to illustrate powerfrequency programmability of the programmable DCO 400 of Figure 4 in accordance with an embodiment.

[0071] The plot 700 illustrates measured power-frequency programmability of the programmable DCO 400 to cover a wide range of standards. Particularly, the powerfrequency programmability can be achieved via supply and body bias voltage tuning from the Z-Wave standard 702 at a frequency of 400 kHz to the BLE5 standard 704 at a frequency of 24 MHz. Using the programmable DCO 400, the frequency can be properly set according to each standard to correctly place backscattering images, which varies based on the radio bandwidth and oversampling ratio if applicable (e.g., using GFSK modulation for the BLE5 standard). The demarcations for the low frequency ranges 706, the middle frequency ranges 708 and the high frequency ranges 710 are indicated in the plot 700. Figure 8 shows a plot 800 of measured power versus jitter to illustrate power-jitter programmability of the programmable DCO of Figure 4 in accordance with an embodiment.

[0072] The plot 800 illustrates jitter-power programmability of the programmable DCO 400 to cover a wide range of standards. Jitter-power programmability is embedded in each BSD of the MJC 502, 504, 506, 508 where each digitally-selectable BSD replicas of the MJC has a different strength to cater for a different jitter. For example, a BSD with higher strength leads to lower jitter at higher DCO power. This feature of the programmable DCO 400 enables power saving in standards with a relaxed jitter target. As shown in the plot 800, the programmable DCO 400 widely covers jitter requirements of several standards from the BLE5 standard 802 to the Z-Wave standard 804 with jitter ranging from tens to hundreds of ps with a corresponding power ranging from 12 pW for the BLE5 standard 802 down to 0.44 pW for the Z-Wave standard 804.

[0073] Figure 9 shows a plot 900 of measured frequency versus temperature to illustrate frequency stability with temperatures of the programmable DCO of Figure 4 in accordance with an embodiment.

[0074] Power utilized by the backscattered SDR transmitter system 300 can also be reduced by sacrificing temperature stability for less demanding standards. As shown in the plot 900, frequency stability over temperatures can be relaxed by increasing the maximum temperature deviation allowed without triggering temperature event-driven recalibration against the reference clock, based on the frequency stability requirement (e.g., 35 kHz for ZigBee 902, 60 kHz for WiFi (i.e. 802.1 1b) 904). As a result, a more relaxed frequency stability activates re-calibration less frequently and saves power. The programmable DCO 400 can also be configured to be reused to derive system clocks for the backscattered SDR transmitter system 300, as shown in relation to the clock divider 346 as provided in relation to Figure 3.

[0075] The received spectra of backscattered WiFi (802.11 b, CCK 1 1 Mbps) and ZigBee (40 kbps, BPSK) signals and their corresponding constellation diagrams are shown in relation to Figures 10 to 15 below. Backscattered signals are evaluated at (i) fc= 2.412 GHz (Ch. 1 ) with foco= 11 MHz for WiFi (see e.g. Figure 10), (ii) fc= 868.3 MHz with fDco = 1 -2 MHz for ZigBee (see e.g. Figure 13) and (iii) fc= 906 MHz with fDco = 1.2 MHz for ZigBee (see e.g. Figure 14). Figure 10 shows a measured spectrum 1000 of backscattered 802.11 b wireless signals using Complementary Code Keying (CCK) modulation at 11 Mbps in accordance with an embodiment. The y-axis 1002 of the measured spectrum 1000 is in dBm and the x- axis 1004 of the measured spectrum 1000 is in MHz. As shown in the measured spectrum 1000, the power of the single tone single PtOne is about 10 dBm.

[0076] Figure 1 1 shows a constellation diagram 1100 of Quadrature Phase Shift Keying (QPSK) modulated 802.1 1 b signals using CCK modulation at 1 1 Mbps in accordance with an embodiment. Table 2 below provides extracted Error Vector Magnitude (EVM) values obtained using the constellation diagram 1 100. From Table 2, it is shown that the RMS EVM Mean obtained is 6.44% for the received backscattered WiFi signals (802.1 1 b, CCK 11 Mbps) with a peak EVM (802.1 1 -2007) Maximum of 17.38% which is within the requirement of a peak EVM being less than 35% by the 802.1 1 b standard.

[0077] Table 2: Extracted EVM from the Constellation Diagram 1 100

[0078] Table 3: Characteristic of the received spectrum 1000 Table 3 shows characteristic of the received spectrum 1000 which shows that the header cyclic redundancy check (CRC) on the packet’s header has passed and the received signal is matched with the transmitted packet.

[0079] Figure 12 shows a constellation diagram 1200 of Differential Binary Phase Shift Keying (DBPSK) modulated 802.11 b signals using Direct Sequence Spread Spectrum (DSSS) at 1 Mbps in accordance with an embodiment. Table 4 below provides extracted Error Vector Magnitude (EVM) values obtained using the constellation diagram 1200. From Table 4, it is shown that the RMS EVM Mean obtained is 5.22% for the received backscattered WiFi signals (802.1 1 b, DSSS 1 Mbps) with a peak EVM (802.11 -2007) Maximum of 7.66% which is within the requirement of a peak EVM being less than 35% by the 802.11 b standard.

[0080] Table 4: Extracted EVM from the Constellation Diagram 1200

[0081] Table 5: Characteristic of the DBPSK modulated 802.1 1b signals Table 5 shows characteristic of the DBPSK modulated 802.11 b signals associated with the constellation diagram 1200, which shows that the header cyclic redundancy check (CRC) on the packet’s header has passed and the received signal is matched with the transmitted packet.

[0082] Figure 13 shows a measured spectrum 1300 of backscattered ZigBee signals at 20 kbps using Binary Phase Shift Keying (BPSK) modulation in accordance with an embodiment. The y-axis 1302 of the measured spectrum 1300 is in dBm and the x-axis 1304 of the measured spectrum 1300 is in kHz.

[0083] Figure 14 shows a measured spectrum 1400 of backscattered Zigbee signals at 40 kbps using BPSK modulation in accordance with an embodiment. The y-axis 1402 of the measured spectrum 1400 is in dBm and the x-axis 1404 of the measured spectrum 1400 is in kHz.

[0084] Figure 15 shows a constellation diagram 1500 of BPSK modulated Zigbee signals at 40 kbps in accordance with an embodiment. Table 6 below provides extracted Error Vector Magnitude (EVM) values obtained using the constellation diagram 1500. From Table 6, it is shown that the RMS EVM Mean obtained is about 6.05% for the received backscattered BPSK modulated Zigbee signals at 40 kbps with a Maximum peak EVM of about 13.33% which is within the requirement of a peak EVM being less than 35% by the ZigBee standard.

[0085] Table 6: Extracted EVM from the Constellation Diagram 1500

[0086] Figures 16A and 16B show photographs to illustrate reception of WiFi beacon frame transmitted using the backscattered software-defined radio (SDR) transmitter system of Figure 3 in accordance with an embodiment. Figure 16A shows a photograph 1600 of a setup for demonstrating the reception including a tone generator 1602, the backscattered SDR transmitter system (or SDR backscatter tag) 1604 and a commodity WiFi receiver 1606. Figure 16B shows the WiFi signal received on the commodity WiFi receiver 1606 from the backscattered SDR transmitter system. The WiFi network “Green-IC DEMO” 1610 is used in the present case.

[0087] Figure 17 shows an illustration of a report 1700 including packet analysis and correct reception for WiFi beacon frame transmitted to the commodity WiFi receiver 1606 in accordance with an embodiment. Figure 18 shows an illustration of a report 1800 including packet analysis and correct reception for Zig Bee beacon frame transmitted to a commodity ZigBee receiver in accordance with an embodiment. Correct packet reception / decoding are shown by the reports 1700, 1800 for WiFi and ZigBee signals using a corresponding commodity receiver, respectively. Further, referring to Figures 7 to 9 above, it is also shown that all other requirements such as phase noise and frequency stability are also met for at least these two standards.

[0088] Figure 19 is a die micrograph 1900 of the backscattered software-defined radio (SDR) transmitter system 300 of Figure 3 in accordance with an embodiment, which is used for performing the experiments. The die micrograph 1900 shows various components of the backscattered SDR transmitter system 300 including a microcontroller 1902, an embedded FPGA 1904, memory 1906 associated with the microcontroller 1902, an instructable address counter 1908, a digitally controlled oscillator (DCO) 1910 and RF switches 1912 connected to a transmitter antenna for changing an antenna RF impedance for modulating backscattered signals.

[0089] Table 7 provides power utilization of the backscattered SDR transmitter system for various standards. For the BLE 5.0 standard, a lower energy bit of 28.5 pJ / bit with simpler FSK modulation (i.e. no pulse shaping) can be obtained in place of the 58.5pJ / bit as shown. It is also noted that data rates of the other standards have also been demonstrated and tested and these include: (i) 1 Mbps, 2 Mbps and 5.5 Mpbs for the 802.1 1 b standard, (ii) 125kbps, 500kbps and 2 Mbps for the BLE5 standard, (iii) 100 kbps for the Z-wave standard, and (iv) 20 kbps for the ZigBee standard.

[0090] As shown in Table 7, the energy / bit obtained using the backscattered SDR transmitter system of the present disclosure ranges from 34.08 pJ / bit for the 802.1 1 b standard to 58.5 pJ / bit for the BLE5 standard, which is about 44X lower than that obtained by a state-of-the-art conventional SDR transmitter of Ref. [9].

[0091] Table 7: Power utilization of the backscattered SDR transmitter system for various standards

[0092] Table 8 provides a comparison between the performance obtained by backscattered SDR transmitter system of the present disclosure and the performance of the state-of- the-art as demonstrated using Refs [2], [4], [5], [6], [8], [9] and

[0010] .

[0093] Compared to the recent software-defined backscattered transmitter within BPSK and 2FSK standards in Ref.

[0010] , the energy / bit of the backscattered software-defined radio (SDR) transmitter system of the present disclosure is up to 1 ,100X lower in protocols where energy is a most important concern (data-rates <1 Mbps), and worse by <3X at multi-Mbps data-rates. For fair comparison, Ref.

[0010] did not include packet generation / assembly and did not demonstrate any existing standard. Although the work of Ref.

[0010] attempted to fill the substantial flexibility-energy gap between backscattered and conventional software-defined radio transmitters, its operation frequency (433 MHz) is not compatible with most of adopted wireless communication standards (~2.4 GHz). Also, the modulator was not demonstrated to cover the various modulations (e.g., GFSK, QPSK) and jitter / frequency requirements used in practical wireless standards. Further, the backscattered software-defined radio (SDR) transmitter system of the present disclosure supports 2.2X higher maximum data-rate (11 Mbps), and can support existing / future standards using basic FSK / PSK / ASK modulations.

[0094] (a) Backscattered radios are generally digital-dominated area efficiency better captured by normalizing to the min. feature size F of the process

[0095] (b) Transmission allowed only when other BLE / 802 11 b devices are simultaneously transmitting

[0096] (c) Power / energy not including packet generation / assembly

[0097] Table 8: Performance summary and comparison with state-of-the-art Compared to single-standard backscattered transmitters of Refs. [1]-[6], the energy increase to achieve software-defined functionality is 2.7X-13.6X for WiFi and 3.4X-8.2X for BLE. In spite of the unique inclusion of packet generation for complete transmitter sub-system, the area normalized to the process minimum feature size is comparable to the recent single-standard backscattered transmitters for Refs. [2], [4], [6], and 14.5X smaller than non-backscattered SDR radios of the Ref. [9]. Compared to the dualstandard backscattered SDR transmitter of Ref. [8], the backscattered software-defined radio (SDR) transmitter system of the present disclosure covers a much broader range of protocols yet at 5X higher peak data-rate and 1.3X lower energy / bit. In addition to the unique flexibility, reusability and upgrade-ability, the backscattered software- defined radio (SDR) transmitter system of the present disclosure at <1 Mbps data-rates consumes tens of pWs and down to ~1.5 pW (ZigBee, Z-Wave). This can be delivered by a coin cell battery for >20 years when transmitting continuously, or an off-the-shelf 3x3 mm2solar cell at 500 lux light intensity (as experimentally validated).

[0098] In conclusion, the present disclosure describes a backscattered software-defined radio (SDR) architecture that enables flexible standard adoption, die reuse across applications, update and upgrade over the entire lifespan of the device with energy in the few tens of pJ / bit range. The backscattered software-defined radio (SDR) architecture of the present disclosure includes a programmable digitally-controlled oscillator (DCO) for time-domain symbol generation at the physical (PHY) layer, thereby eliminating a need for the traditional energy-hungry DAC in SDRs. As described above, the DAC-less backscattered SDR transmitter system of the present disclosure supports all basic modulations (e.g. PSK / FSK / ASK modulations) and is capable of adjustable jitter-power programmability to minimize the energy / bit for a given standard jitter requirement. An embedded microcontroller of the backscattered SDR transmitter system is configured to perform packet assembly before transmission and store the packets into its data memory. An on-chip low-energy embedded FPGA of the backscattered SDR transmitter system is then configured to control a frequencyphase-jitter-power programmable DCO, carries out digital processing for flexible PHY layer implementation, and uniquely supports conventional power-hungry physical-layer capabilities (e.g., filter-less over-sampling for pulse shaping). End-to-end demonstration from packet formation to transmission in existing wireless infrastructure for loT wireless communication protocols using commodity wireless infrastructure for the WiFi, BLE5, ZigBee, and Z-Wave standards is also shown and it is demonstrated that the energy consumption using the backscattered SDR transmitter system of the present disclosure ranges from 34.08 pJ / bit to 58.5 pJ / bit, which is at least two orders of magnitude lower than recent state-of-the-art software-defined radios. A 180-nm testchip was used as shown in relation to Figure 19 and it shows 44X lower energy than conventional SDR and up to 1 ,100X lower energy than the recent backscattered software-defined TX, even if the present backscattered SDR transmitter system uniquely includes the entire packet generation and assembly, and demonstrates transmission in actual wireless standards

[0099] The described backscattered SDR transmitter system is useful for applications where extreme-low power / energy consumption and protocol-upgradable radios are needed, such as distributed loT sensor nodes. The described backscattered SDR transmitter system is adapted to enable software-defined radio (SDR) transmitters with pW-range power at Mbps data rate, which greatly extends the battery and the system lifespan thanks to its adaptability to changes in the communication protocol. Further, the described backscattered SDR transmitter system is adapted for aggressive die reuse across applications and upgrade over the system lifespan, thereby enabling fitting of the required wireless communication standard for different geographies and evolving standards using the same die.

[0100] Table 9 provides a summary of features of the system of the present embodiment along with their respective advantages.

[0101] Table 9: Features and Corresponding Advantages.

[0102] Alternative embodiments may include: (i) a programmable DCO having an odd number (n) of MDCs as shown in the example where n is equal to or more than three; (ii) each MDC comprising two or more MJCs; (iii) each MJC comprising two or more BDCs; (iv) each BDCs having two or more sets of reconfigurable inverter gates of different channel lengths and corresponding frequency range; (v) the MDC each introducing a different phase shift, for example, 30° or 60° phase shift; and (vi) use of the MDCs to generate other combinations of multiplexed phases, e.g. 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315°. Although only certain embodiments of the present invention have been described in detail, many variations are possible in accordance with the appended claims. For example, features described in relation to one embodiment may be incorporated into one or more other embodiments and vice versa.

[0103] References

[0001] P. -H. P. Wang, C. Zhang, H. Yang, D. Bharadia, and P. P. Mercier, "A 28pW loT Tag That Can Communicate with Commodity WiFi Transceivers via a Single-Side-Band QPSK Backscatter Communication Technique," 2020 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco (USA), 2020.

[0104] [2] S. -K. Kuo, M. Dunna, H. Lu, A. Agarwal, D. Bharadia, and P. P. Mercier, "An LTE- Harvesting BLE-to-WiFi Backscattering Chip for Single-Device RFID-Like Interrogation," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 320-322.

[0105] [3] K. A. Ahmed, R. Yang, P. Salamani, V. Rajanna, and M. Alioto, "Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 pW Peak Power for Purely- Harvested Green Systems," ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), Lisbon, Portugal, 2023, pp. 49-52.

[0106] [4] Z. Chang, Q. Xiao, C. Chen, W. Wang, X. Hu, C. Yang, Z. Li, Y. Luo, and B. Zhao, "A Passive Crystal-Less Wi-Fi-to-BLE Tag Demonstrating Battery-Free FDD Communication with Smartphones," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 404-406.

[0107] [5] L. Lin, K. A. Ahmed, P. S. Salamani, and M. Alioto, "Battery-Less loT Sensor Node with PLL- Less WiFi Backscattering Communications in a 2.5-pW Peak Power Envelope," 2021 Symposium on VLSI Circuits, Kyoto, Japan, 2021 , pp. 1 -2.

[0108] [6] Z. Chang, Q. Xiao, W. Wang, Y. Luo and, B. Zhao, "A Passive Bidirectional BLE Tag Demonstrating Battery-Free Communication in Tablet / Smartphone-to-Tag, Tag-to- Tablet / Smartphone, and Tag-to-Tag Modes," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 468-470.

[0109] [7] Y. Zhang, R. Luo, J. Xiong, S. Liang, and M. Meng, "A 19pW 200Mb / s loT Tag Demonstrating High-Definition Video Streaming via a Digital-Switch-Based Reconfigurable 16- QAM Backscatter Communication Technique," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 224-226.

[0110] [8] S. -K. Kuo, M. Dunna, D. Bharadia, and P. P. Mercier, "A WiFi and Bluetooth Backscattering Combo Chip Featuring Beam Steering via a Fully-Reflective Phased-Controlled Multi-Antenna Termination Technique Enabling Operation Over 56 Meters," 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1 -3. [9] Z. Liu, Y. Tan, C. Xu. H. Li, H. Jiang, X. Bao, D. Wang, J. Liu, and H. Liao, "A 2.85mm2 RF Transceiver in 40nm CMOS for loT Micro-Hub Applications," 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Republic of, 2021 , pp. 1 -3.

[0111]

[0010] J. Shen, F. Zhu, Y. Liu, B. Liu, C. Shi, L. Huang, L. Xu, X. Tian, and R. Zhang, "A 44pW loT Tag Enabling 1 ps Synchronization Accuracy and OFDMA Concurrent Communication with

[0112] Software-Defined Modulation," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 400-402.

Claims

Claims1. A programmable digitally-controlled oscillator (DCO) for time-domain symbol generation, the programmable DCO comprising: an odd number (n) of multi delay cells (MDCs) to form a ring oscillator, the odd number (n) being equal to or more than three, and the odd number (n) of MDCs being adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation, wherein each of the n number of MDCs comprises: two or more multi jitter cells (MJCs), each of the two or more MJCs being adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit of a frequency shift keying (FSK) modulation, wherein each of the two of more MJCs comprises: two or more replica basic delay cells (BDCs) configured to adjust jitter, wherein each of the two or more replica BDC is adapted to provide a predetermined jitter target and comprises: two or more sets of reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the two or more reconfigurable inverter gates being selectable based on a target frequency range.

2. The programmable DCO of claim 1 , wherein the programmable DCO is programmable using a look-up table (LUT) by an embedded Field Programmable Gate Array (FPGA).

3. The programmable DCO of claim 1 or claim 2, wherein the odd number of MDCs includes five MDCs and the five MDCs are adapted to generate four multiplexed phases as 0°, 90°, 180° and 270°.

4. The programmable DCO of any one of claims 1 to 3, wherein the two or more BDCs includes four replica BDCs to provide four predetermined jitter targets to satisfy jitter requirements in a range of fifty to two hundred picoseconds (ps).

5. The programmable DCO of any one of claims 1 to 4, wherein the two or more sets of reconfigurable inverter gates include three sets of transistors having three different setsof leakage-dynamic energy-speed tradeoffs to provide the corresponding frequency ranges.

6. A backscattered software-defined radio (SDR) transmitter system comprising: a micro-controller configured to generate data packets; an embedded Field Programmable Gate Array (FPGA) configured to read the data packets generated by the micro-controller and execute signal processing for modulating a carrier signal; a programmable digitally-controlled oscillator (DCO) configured to generate time-domain symbols, the programmable DCO comprising: an odd number (n) of multi delay cells (MDCs) to form a ring oscillator, the odd number (n) being equal to or more than three, and the odd number (n) of MDCs being adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation, wherein each of the n number of MDCs comprises: two or more multi jitter cells (MJCs), each of the two or more MJCs being adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit of a frequency shift keying (FSK) modulation, wherein each of the two of more MJCs comprises: two or more replica basic delay cells (BDCs) configured to adjust jitter, wherein each of the two or more replica BDC is adapted to provide a predetermined jitter target and comprises: two or more sets of reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the two or more reconfigurable inverter gates being selectable based on a target frequency range; and a RF switch connected to a transmitter antenna, a RF impedance of the RF switch being modulated using the time-domain symbols for modulating a carrier signal using the transmitter antenna to provide a backscattered signal, wherein the embedded FPGA is configured to provide control signals to the programmable DCO for generating the time-domain symbols to modulate the RF impedance of the RF switch for modulating the carrier signal.

7. The backscattered software-defined radio (SDR) transmitter system of claim 6, wherein the embedded FPGA is configured to program the programmable DCO using a look-up table (LUT).

8. The backscattered software-defined radio (SDR) transmitter system of claim 6 or claim 7, wherein the odd number of MDGs includes five MDGs and the five MDGs are adapted to generate four multiplexed phases as 0°, 90°, 180° and 270°.

9. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 8, wherein the two or more BDCs includes four replica BDCs to provide four predetermined jitter targets to satisfy jitter requirements in a range of fifty to two hundred picoseconds (ps).

10. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 9, wherein the two or more sets of reconfigurable inverter gates include three sets of transistors having three different sets of leakage-dynamic energy-speed tradeoffs to provide the corresponding frequency ranges.1 1. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 10, wherein the RF impedance of the RF switch is configured to be digitally modulated between two statically assigned RF switch impedances for supporting Amplitude Shift Keying (ASK) modulation.

12. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 1 1 , wherein the microcontroller is configured to perform pre-modulation manipulations, including cyclic redundancy check (CRC) manipulation and direct- sequence spread spectrum (DSSS) manipulation, at sub-uW power.

13. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 12, further comprising an instructable address counter configured to fetch pre-encoded data packet memory associated with the microcontroller for recreating packet bitstream.

14. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 13, further comprising support peripherals configured to perform coarse tuning and fine tuning of the programmable DCO.

15. The backscattered software-defined radio (SDR) transmitter system of any one of claims 6 to 14, wherein the programmable DCO is configured to be used as a clock source for digital logics in the software-defined backscattered transmitter system.

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