Thin-film transistor and preparation method therefor, display substrate, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a thin-film transistor and a preparation method therefor, a display substrate, and a display device. The thin-film transistor of the present disclosure comprises: a base substrate, and a first semiconductor active layer, a gate, a source, and a drain that are arranged on the base substrate; the source is connected to a source contact region of the first semiconductor active layer, and the drain is connected to a drain contact region of the first semiconductor active layer; the thin-film transistor further comprises at least one second semiconductor active layer located on the side of the first semiconductor active layer away from the gate, the second semiconductor active layer is electrically connected to the first semiconductor active layer, and the conductivity of the second semiconductor active layer is greater than the conductivity of the first semiconductor active layer.

Description

Thin-film transistors and their fabrication methods, display substrates, and display devices. Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a thin-film transistor and its fabrication method, a display substrate, and a display device. Background Technology

[0002] Currently, amorphous silicon, low-temperature polycrystalline silicon, and indium gallium zinc oxide (IGZO) thin-film transistors have been widely used in active-matrix flat panel displays such as TFT-LCDs, organic light-emitting diode displays (AMOLEDs), and large-area optoelectronic sensing such as FPXDs. However, in these technologies, the on-state current of amorphous silicon and IGZO thin-film transistors is relatively small; for example, the mobility of amorphous silicon is only 0.5 cm⁻¹. 2 At approximately / Vs, the mobility of IGZO-TFTs only reaches 10-30cm. 2 The / Vs ratio limits its application in array substrates with high aperture ratios. Although the mobility of low-temperature polycrystalline silicon thin-film transistors can reach 80-100 cm⁻¹, this limitation restricts their use. 2 / Vs, but its process is complex, the cost is high, and it cannot be applied to large-size back panels.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a thin film transistor and its preparation method, a display substrate, and a display device.

[0005] This disclosure provides a thin-film transistor, comprising: a substrate, a first semiconductor active layer, a gate, a source, and a drain disposed on the substrate; the source is connected to a source contact region of the first semiconductor layer, and the drain is connected to a drain contact region of the first semiconductor layer; wherein...

[0006] The thin-film transistor further includes at least one second semiconductor active layer located on the side of the first semiconductor active layer away from the gate, the second semiconductor active layer being electrically connected to the first semiconductor active layer; and the conductivity of the second semiconductor active layer being greater than the conductivity of the first semiconductor active layer.

[0007] In some examples, the second semiconductor active layer is in contact with the first semiconductor active layer, and the orthographic projection of the second semiconductor active layer on the substrate is located between the orthographic projections of the source contact region and the drain contact region of the first semiconductor active layer on the substrate.

[0008] In some examples, the first semiconductor active layer is located on the side of the gate away from the substrate, and a gate insulating layer is disposed between the first semiconductor active layer and the layer containing the gate.

[0009] In some examples, the source and the drain are located on the side of the first semiconductor active layer away from the substrate, and a passivation layer is disposed between the source and drain layers and the first semiconductor active layer; the source is connected to the source contact area through a first connection via penetrating the passivation layer, and the drain is connected to the drain contact area through a second connection via penetrating the passivation layer.

[0010] Both the first and second connection vias do not overlap with the orthographic projection of the second semiconductor active layer on the substrate.

[0011] In some examples, both the first and second connection vias overlap with the orthographic projection of the gate onto the substrate.

[0012] In some examples, the first semiconductor active layer is located on the side of the gate closer to the substrate, and a gate insulating layer is disposed between the first semiconductor active layer and the layer containing the gate.

[0013] In some examples, the first semiconductor active layer covers the second semiconductor active layer; the source and the drain are located on opposite sides of the first semiconductor active layer and are in contact with the first semiconductor active layer.

[0014] In some examples, the second semiconductor active layer has multiple layers, and the conductivity of the second semiconductor active layer is higher the farther it is from the first semiconductor active layer.

[0015] In some examples, the first semiconductor active layer and the second semiconductor active layer are made of the same material.

[0016] In some examples, the materials of the first semiconductor active layer and the second semiconductor active layer include indium gallium zinc oxide.

[0017] This disclosure provides a method for fabricating a thin-film transistor, comprising: providing a substrate, forming a first semiconductor active layer, a gate, a source, and a drain on the substrate; wherein the source is connected to a source contact region of the first semiconductor layer, and the drain is connected to a drain contact region of the first semiconductor layer; wherein...

[0018] The preparation method further includes: forming at least one second semiconductor active layer on the side of the first semiconductor active layer away from the gate, wherein the second semiconductor active layer is electrically connected to the first semiconductor active layer; and the conductivity of the second semiconductor active layer is greater than the conductivity of the first semiconductor active layer.

[0019] In some examples, both the first and second active semiconductor layers are made of indium gallium zinc oxide, and the atmosphere in which the first and second active semiconductor layers are formed is oxygen and argon. The proportion of oxygen and argon in the first active semiconductor layer is greater than that in the second active semiconductor layer.

[0020] In some examples, the second semiconductor active layer has multiple layers, and the proportion of oxygen and argon is lower when the second semiconductor active layer is formed further away from the first semiconductor active layer.

[0021] This disclosure provides a display substrate comprising a plurality of pixel units, each pixel unit including a pixel driving circuit; at least some transistors in the pixel driving circuit employ any of the thin-film transistors described above.

[0022] In some examples, the display substrate further includes multiple gate lines and multiple data lines, defining the pixel unit at the intersection of the gate lines and the data lines; the gate of the transistor connected to the gate line in the pixel driving circuit is integrally formed with the gate line.

[0023] This disclosure provides a display substrate including a pixel unit, the pixel unit including a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit; wherein, at least the driving transistor in the pixel driving circuit is a thin-film transistor as described above.

[0024] In some examples, the display substrate further includes multiple gate lines and multiple data lines, defining the pixel unit at the intersection of the gate lines and the data lines; the gate of the transistor connected to the gate line in the pixel driving circuit is integrally formed with the gate line.

[0025] This disclosure provides a display device comprising any of the display substrates described above. Attached Figure Description

[0026] Figure 1 is a cross-sectional view of a thin-film transistor according to a first example of an embodiment of this disclosure.

[0027] Figure 2 is a schematic diagram of the working principle of a thin-film transistor according to a first example of an embodiment of this disclosure.

[0028] Figure 3 is a flowchart of a method for fabricating a thin-film transistor according to a first example of an embodiment of this disclosure.

[0029] Figure 4 is a cross-sectional view of a thin-film transistor according to a second example of an embodiment of this disclosure.

[0030] Figure 5 is a flowchart of a method for fabricating a thin-film transistor according to a second example of an embodiment of this disclosure.

[0031] Figure 6 is a cross-sectional view of a thin-film transistor according to a third example of an embodiment of this disclosure.

[0032] Figure 7 is a flowchart of a method for fabricating a thin-film transistor according to a third example of an embodiment of this disclosure.

[0033] Figure 8 is a schematic top view of a display substrate according to an embodiment of the present disclosure.

[0034] Figure 9 is a pixel unit layout of an exemplary display substrate according to an embodiment of the present disclosure.

[0035] Figure 10 is an equivalent circuit diagram of a pixel unit of a display substrate according to another exemplary embodiment of the present disclosure.

[0036] Figure 11 is a timing diagram of the pixel driving circuit shown in Figure 10. Detailed Implementation

[0037] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] This disclosure provides a thin-film transistor, specifically an oxide thin-film transistor, which can be either a top-gate or bottom-gate type. The thin-film transistor in this disclosure may include a substrate, a first semiconductor active layer, a gate, a source, and a drain disposed on the substrate; wherein the source is connected to the source contact region of the first semiconductor active layer, and the drain is connected to the drain contact region of the first semiconductor active layer. Notably, at least one second semiconductor active layer is disposed on the side of the first semiconductor active layer away from the gate, and this second semiconductor active layer is electrically connected to the first conductive active layer; and the conductivity of the second semiconductor active layer is greater than the conductivity of the first semiconductor active layer.

[0040] In the thin-film transistor of this embodiment, since the first semiconductor active layer and the second semiconductor layer with higher conductivity are connected, the doping level of the first semiconductor active layer can be reversibly dynamically controlled when a voltage is applied to the gate, thereby changing the switching characteristics of the thin-film transistor and obtaining a higher on-state current. It should be noted that the second semiconductor active layer is not directly electrically connected to the source and drain, and therefore does not affect the off-state current of the thin-film transistor.

[0041] The structure and fabrication method of the thin-film transistor according to the present disclosure will be described below with reference to specific examples.

[0042] First Example: Figure 1 is a cross-sectional view of a thin-film transistor according to a first example of the present disclosure. As shown in Figure 1, the thin-film transistor in this example is a bottom-gate thin-film transistor, which specifically includes a substrate 1, a gate 2 disposed on the substrate 1, a gate insulating layer 6 disposed on the side of the gate 2 away from the substrate 1, a second semiconductor active layer 8 disposed on the side of the first semiconductor active layer 3 away from the gate insulating layer 6, a passivation layer 7 disposed on the side of the second semiconductor active layer 8 away from the first semiconductor active layer 3, a source electrode 4 and a drain electrode 5 disposed on the side of the passivation layer 7 away from the second semiconductor active layer 8, the source electrode 4 being connected to the source contact region of the first semiconductor active layer 3 through a first connection via 101 penetrating the passivation layer 7, and the drain electrode 5 being connected to the drain contact region of the first semiconductor active layer 3 through a second connection via 102 penetrating the passivation layer 7. In this example, the lower surface of the second active semiconductor layer 8 is in contact with the upper surface of the first active semiconductor layer 3. Specifically, the second active semiconductor layer 8 is located on the channel region of the first active semiconductor layer 3 and is not connected to either the source 4 or the drain 5. The channel region of the first active semiconductor layer 3 is located between its source contact region and its drain 5 contact region. The conductivity of the second active semiconductor layer 8 is greater than the conductivity of the first active semiconductor layer 3.

[0043] It should be noted that, in any embodiment of this disclosure, of the two surfaces of any film layer disposed opposite each other along its thickness direction, the one that is relatively closer to the substrate 1 is called the lower surface, and the one that is relatively farther away from the substrate 1 is called the upper surface.

[0044] Figure 2 is a schematic diagram of the working principle of a thin-film transistor according to a first example of an embodiment of this disclosure. As shown in Figure 2, in this example, by providing a second semiconductor active layer 8 with higher conductivity above the first semiconductor active layer 3, the doping level of the first semiconductor active layer 3 can be reversibly dynamically controlled under the vertical electric field of the gate voltage after applying a gate voltage to the gate 2. Specifically, 1) the thin-film transistor is in the on state: the vertical electric field of the gate voltage can, on the one hand, cause the first semiconductor active layer 3 to form an electron accumulation state near the gate insulating layer, generating a channel region, and on the other hand, it can cause oxygen vacancies in the second semiconductor active layer 8 to migrate to the channel region of the first semiconductor active layer 3 under the action of the vertical electric field, thereby further increasing the electron concentration in the channel region. Therefore, the thin-film transistor of this embodiment can obtain a larger on-state current without significantly changing the oxide mobility. 2) Thin-film transistor in the off state: There is no contact between the second semiconductor active layer 8 and the source and drain 5, that is, there is isolation. The thin-film transistor is still connected to the source 4 and drain 5 through the first semiconductor active layer 3. Therefore, leakage current will not occur due to the increase of the second semiconductor active layer 8 in the off state. Under the action of the vertical electric field, oxygen vacancies reversibly migrate from the channel region of the first semiconductor active layer 3 to the second semiconductor active layer 8 in the reverse direction, reducing the electron concentration in the channel region of the first semiconductor active layer 3. Therefore, a low off-state current can still be maintained.

[0045] In some examples, continuing to refer to Figure 1, to ensure that the source 4 and drain 5 of the thin-film transistor are not in contact with the second semiconductor active layer 8, in this embodiment of the disclosure, the orthographic projections of the second semiconductor active layer 8, the first connection via 101, and the second connection via 102 on the substrate 1 are all overlapping. Furthermore, the second semiconductor active layer 8 is located only in the channel region of the first semiconductor active layer 3, that is, in the channel region of the first semiconductor active layer 3; that is, the lateral width of the second semiconductor active layer 8 is smaller than the lateral width of the first semiconductor active layer 3.

[0046] In some examples, continuing to refer to Figure 1, both the first connection via 101 and the second connection via 102 penetrating the passivation layer 7 overlap with the gate 2 projected onto the substrate 1. This arrangement is because the source 4 is connected to the source contact region of the first semiconductor active layer 3 via the first connection via 101, and the drain 5 is connected to the drain contact region of the first semiconductor active layer 3 via the second connection via 102. In other words, the position of the first connection via 101 corresponds to the location of the source 4, and the position of the second connection via 102 corresponds to the location of the drain 5. Both the first connection via 101 and the second connection via 102 overlap with the gate 2 projected onto the substrate 1, meaning that both the source 4 and the drain 5 overlap with the gate 2 projected onto the substrate 1. This ensures that the entire channel region of the first semiconductor active layer 3 can be controlled by the gate 2.

[0047] In some examples, although the first active semiconductor layer 3 and the second active semiconductor layer 8 in this embodiment have different conductivity, they are both formed using the same material. For example, the materials of the first active semiconductor layer 3 and the second active semiconductor layer 8 include, but are not limited to, indium gallium zinc oxide (IGZO). The following explanation, in conjunction with the fabrication method of thin-film transistors, details the reason why the first active semiconductor layer 3 and the second active semiconductor layer 8 have different conductivity despite using the same material. In this embodiment, only the use of IGZO as the material for the first active semiconductor layer 3 and the second active semiconductor layer 8 is taken as an example.

[0048] The fabrication method of the thin-film transistor in the first example is described below. Figure 3 is a flowchart of the fabrication method of the thin-film transistor in the first example of this disclosure; as shown in Figure 3, the fabrication method of the thin-film transistor may specifically include the following steps:

[0049] S11. Provide a substrate 1.

[0050] In some examples, the substrate 1 includes, but is not limited to, a glass substrate. In this embodiment of the disclosure, only a glass substrate is used as an example for illustration. Step S11 may specifically include providing a substrate 1 and cleaning it using a standard process.

[0051] S12. A pattern including gate 2 is formed through a patterning process.

[0052] In some examples, the gate 2 can be formed from conductive materials such as metals or metal alloys, such as molybdenum, molybdenum-niobium alloys, aluminum, aluminum-neodymium alloys, titanium, or copper.

[0053] In some examples, step S12 may specifically include forming a gate metal thin film on the substrate 1 using any of the following methods: sputtering, thermal evaporation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECR-CVD), and forming a pattern including the gate 2 through a patterning process (film formation, exposure, development, wet etching, or dry etching).

[0054] S13, Forming the gate insulating layer 6.

[0055] In some examples, the gate insulating layer 6 can be a single-layer structure or a stacked structure of multiple sublayers. Specifically, each layer can be formed using silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), or aluminum oxide (AlyOx). In the embodiments of this disclosure, the gate insulating layer 6 adopts a SiNx / SiOx stacked structure; the thickness of SiNx is approximately 100–200 nm, and the thickness of SiOx is approximately 50–100 nm.

[0056] In some examples, step S13 may specifically involve forming the gate insulating layer 6 using methods including, but not limited to, plasma-enhanced chemical vapor deposition.

[0057] S14. A pattern including the first semiconductor active layer 3 is formed by a patterning process.

[0058] In some examples, taking IGZO as the material for the first active semiconductor layer 3, step S14 involves using an IGZO target and introducing a mixed gas containing argon (Ar) and oxygen (O2) for sputtering reaction to form the first IGZO film layer. Subsequently, a pattern including the first active semiconductor layer 3 is formed through a patterning process. The ratio of argon to oxygen in forming the first active semiconductor layer 3 is approximately 100:1 to 200:1.

[0059] S15. A pattern including the second semiconductor active layer 8 is formed through a patterning process.

[0060] The formation of the second semiconductor active layer 8 is roughly the same as the formation of the first semiconductor active layer 3. The only difference is that the ratio of oxygen and argon in the atmosphere in which the second IGZO film is formed is less than the ratio of oxygen and argon in the atmosphere in which the first IGZO film is formed, so that the conductivity of the second IGZO film is greater than that of the first IGZO film.

[0061] S16. A passivation layer 7 is formed, and a first connection via 101 and a second connection via 102 are formed through the passivation layer 7.

[0062] In some examples, the passivation layer 7 can be formed using the same process steps as the gate insulating layer 6. The passivation layer 7 can also be a single-layer structure or a stacked structure of multiple sublayers. Specifically, each layer can be formed using silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), or aluminum oxide (AlyOx). In the embodiments of this disclosure, the gate insulating layer 6 adopts a SiOx / SiNx stacked structure; the thickness of SiOx is about 100-200 nm, and the thickness of SiNx is about 200-300 nm.

[0063] The formation of the first connection via 101 and the second connection via 102 may include, after forming the passivation layer 7, photoresist coating, exposure of the patterns of the first connection via 101 and the second connection via 102, development, post-baking, etching, and photoresist stripping.

[0064] S17. A pattern including source 4 and drain 5 is formed through a patterning process.

[0065] In some examples, the formation of source 4 and drain 5 can be the same as the formation of gate 2. Source 4 and drain 5 can be formed from metals or metal alloys, such as molybdenum, molybdenum-niobium alloys, aluminum, aluminum-neodymium alloys, titanium, or copper, etc., conductive materials. In this embodiment, a molybdenum / aluminum / molybdenum three-layer structure is used as an example, with the thicknesses of the three layers being... about.

[0066] This completes the fabrication of the first example of a thin-film transistor.

[0067] The second example: Figure 4 is a cross-sectional view of a thin-film transistor according to a second example of the present disclosure. As shown in Figure 4, the thin-film transistor in this example is a top-gate thin-film transistor, which specifically includes a substrate 1, a buffer layer 9 disposed on the substrate 1, a source 4 and a drain 5 disposed on the side of the buffer layer 9 away from the substrate 1, a second active semiconductor layer 8 located between the source 4 and the drain 5, a first active semiconductor layer 3 disposed on the side of the source 4 and the drain 5 away from the substrate 1, a gate insulating layer 6 disposed on the side of the first active semiconductor layer 3 away from the second active semiconductor layer 8, and a gate 2 disposed on the side of the gate insulating layer 6 away from the first active semiconductor layer 3. The first active semiconductor layer 3 covers the second active semiconductor layer 8, and the source contact region of the first active semiconductor layer 3 is connected to the source 4, and the drain contact region of the first active semiconductor layer 3 is connected to the drain 5.

[0068] The working principle and effect of the thin-film transistor in this example are the same as in the first example, so they will not be repeated here.

[0069] The thin-film transistor in the second example differs from the thin-film transistor in the first example in that its second semiconductor active layer 8 is disposed on the same layer as the source 4 and the drain 5, and its first semiconductor active layer 3 is directly connected to the source 4 and the drain 5.

[0070] To better illustrate the structure of each film layer in the second example of the thin-film transistor, the following detailed description is provided in conjunction with the fabrication method of the thin-film transistor. Figure 5 is a flowchart of the fabrication method of the second example of the thin-film transistor according to an embodiment of this disclosure; as shown in Figure 5, the fabrication method of the thin-film transistor specifically includes the following steps:

[0071] S21. Provide a substrate 1.

[0072] In some examples, the substrate 1 includes, but is not limited to, a glass substrate. In this embodiment of the disclosure, only the use of a glass substrate as the substrate is described. Step S21 may specifically include providing a substrate 1 and cleaning it using a standard process.

[0073] S22, forming a buffer layer 9.

[0074] In some examples, the buffer layer 9 can be a single-layer structure or a stacked structure of multiple sublayers. Specifically, each layer can be formed using silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), or aluminum oxide (AlyOx). In the embodiments of this disclosure, the buffer layer 9 adopts a SiNx / SiOx stacked structure; the thickness of SiNx is approximately 100–200 nm, and the thickness of SiOx is approximately 50–100 nm.

[0075] S23. A pattern including the second semiconductor active layer 8 is formed through a patterning process.

[0076] In some examples, taking IGZO as the material for the second semiconductor active layer 8, an IGZO target is used, and a mixed gas containing argon (Ar) and oxygen (O2) is introduced for sputtering reaction to form the first IGZO film layer. Then, a pattern including the second semiconductor active layer 8 is formed through a patterning process.

[0077] S24. A pattern including source 4 and drain 5 is formed through a patterning process.

[0078] In some examples, source 4 and drain 5 can be formed from metals or metal alloys, such as molybdenum, molybdenum-niobium alloys, aluminum, aluminum-neodymium alloys, titanium, or copper, etc. In this embodiment, a molybdenum / aluminum / molybdenum three-layer structure is used as an example, with the thicknesses of the three layers being... about.

[0079] In some instances, step S24 may specifically include forming a gate metal thin film using any of the following methods: sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and forming a pattern including the source 4 and the drain 5 through a patterning process (film formation, exposure, development, wet etching, or dry etching).

[0080] S25. A pattern including the first semiconductor active layer 3 is formed by a patterning process.

[0081] In some examples, the formation steps of the first active semiconductor layer 3 and the second active semiconductor layer 8 are largely the same, except that the ratio of oxygen to argon in the atmosphere forming the second IGZO film is higher than that in the atmosphere forming the first IGZO film. This results in the conductivity of the second IGZO film being lower than that of the first IGZO film, meaning the conductivity of the first active semiconductor layer 3 is lower than that of the second active semiconductor layer 8. The argon to oxygen ratio in the formation of the first active semiconductor layer 3 is approximately 100:1 to 200:1.

[0082] S26, Forming the gate insulating layer 6.

[0083] In some examples, the gate insulating layer 6 can be a single-layer structure or a stacked structure of multiple sublayers. Specifically, each layer can be formed using silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), or aluminum oxide (AlyOx). In the embodiments of this disclosure, the gate insulating layer 6 adopts a SiNx / SiOx stacked structure; the thickness of SiNx is approximately 100–200 nm, and the thickness of SiOx is approximately 50–100 nm.

[0084] In some examples, step S26 may specifically involve forming the gate insulating layer 6 using methods including, but not limited to, plasma-enhanced chemical vapor deposition.

[0085] S27. A pattern including gate 2 is formed by a patterning process.

[0086] In some examples, the steps for forming the gate 2 can be the same as those for forming the source 4 and drain 5 described above. The gate 2 can be formed from conductive materials such as metals or metal alloys, such as molybdenum, molybdenum-niobium alloys, aluminum, aluminum-neodymium alloys, titanium, or copper.

[0087] This completes the fabrication of the second example of a thin-film transistor.

[0088] The third example: Figure 6 is a cross-sectional view of a thin-film transistor according to the third example of the present disclosure; as shown in Figure 6, the structure of the thin-film transistor in this example is roughly the same as that of the thin-film transistor in the first example. The difference is that the number of layers of the second semiconductor active layer 8 in this example is multiple. In this example, only two layers of the second semiconductor active layer 8 are taken as an example. The conductivity of the second semiconductor active layer 8 is higher the further away from the first semiconductor active layer 3.

[0089] Specifically, referring to Figure 6, the thin-film transistor in the third example includes: a substrate 1, a gate 2 disposed on the substrate 1, a gate insulating layer 6 disposed on the side of the gate 2 facing away from the substrate 1; two second semiconductor active layers 8 disposed on the side of the first semiconductor active layer 3 facing away from the gate insulating layer 6, a passivation layer 7 disposed on the side of the second semiconductor active layer 8 facing away from the first semiconductor active layer 3, a source electrode 4 and a drain electrode 5 disposed on the side of the passivation layer 7 facing away from the second semiconductor active layer 8, the source electrode 4 being connected to the source contact region of the first semiconductor active layer 3 through a first connection via 101 penetrating the passivation layer 7, and the drain electrode 5 being connected to the drain contact region of the first semiconductor active layer 3 through a second connection via 102 penetrating the passivation layer 7. In this example, the lower surface of the first second active semiconductor layer 8a is in contact with the upper surface of the first active semiconductor layer 3. Specifically, the first second active semiconductor layer 8a is located on the channel region of the first active semiconductor layer 3 and is not connected to either the source 4 or the drain 5. The channel region of the first active semiconductor layer 3 is located between its source contact region and its drain 5 contact region. The conductivity of both second active semiconductor layers 8 is greater than the conductivity of the first active semiconductor layer 3.

[0090] In this example, the thin-film transistor can not only reversibly and dynamically control the doping level of the first semiconductor active layer 3 under the vertical electric field of the gate voltage, thereby changing the switching characteristics of the thin-film transistor and obtaining a higher on-state current, but also, since the thin-film transistor in this example includes two second semiconductor active layers 8, the degree of reversible doping of the channel region of the first semiconductor active layer 3 can be more precisely controlled, thereby regulating the final on-state current and threshold voltage of the thin-film transistor.

[0091] In some examples, two second semiconductor active layers 8 are stacked, and their patterns are approximately identical. To ensure that the source 4 and drain 5 of the thin-film transistor are not in contact with either of the second semiconductor active layers 8, in this embodiment, the orthographic projections of either second semiconductor active layer 8, the first connection via 101, and the second connection via 102 on the substrate 1 overlap. Furthermore, each second semiconductor active layer 8 is located only in the channel region of the first semiconductor active layer 3, that is, in the channel region of the first semiconductor active layer 3. In other words, the lateral width of each second semiconductor active layer 8 is smaller than the lateral width of the first semiconductor active layer 3.

[0092] In some examples, both the first connection via 101 and the second connection via 102 penetrating the passivation layer 7 overlap with the gate 2 projected onto the substrate 1. This arrangement is because the source 4 is connected to the source contact region of the first semiconductor active layer 3 via the first connection via 101, and the drain 5 is connected to the drain contact region of the first semiconductor active layer 3 via the second connection via 102. In other words, the position of the first connection via 101 corresponds to the location of the source 4, and the position of the second connection via 102 corresponds to the location of the drain 5. Both the first connection via 101 and the second connection via 102 overlap with the gate 2 projected onto the substrate 1, meaning that both the source 4 and the drain 5 overlap with the gate 2 projected onto the substrate 1. This ensures that the entire channel region of the first semiconductor active layer 3 can be controlled by the gate 2.

[0093] In some examples, although the first active semiconductor layer 3 and the second active semiconductor layer 8 in this embodiment have different conductivity, they are both formed using the same material. For example, the materials of the first active semiconductor layer 3 and the second active semiconductor layer 8 include, but are not limited to, indium gallium zinc oxide (IGZO). The following explanation, in conjunction with the fabrication method of thin-film transistors, details the reason why the first active semiconductor layer 3 and the second active semiconductor layer 8 have different conductivity despite using the same material. In this embodiment, only the use of IGZO as the material for the first active semiconductor layer 3 and the second active semiconductor layer 8 is taken as an example.

[0094] The fabrication method of the thin-film transistor in the third example is described below. Figure 7 is a flowchart of the fabrication method of the thin-film transistor in the third example of this disclosure; as shown in Figure 7, the fabrication method of the thin-film transistor may specifically include the following steps:

[0095] S31. Provide a substrate 1.

[0096] In some examples, the substrate 1 includes, but is not limited to, a glass substrate. In this embodiment of the disclosure, only the use of a glass substrate as the substrate is described. Step S31 may specifically include providing a substrate 1 and cleaning it using a standard process.

[0097] S32, A pattern including gate 2 is formed by a patterning process.

[0098] In some examples, the gate 2 can be formed from conductive materials such as metals or metal alloys, such as molybdenum, molybdenum-niobium alloys, aluminum, aluminum-neodymium alloys, titanium, or copper.

[0099] In some examples, step S32 may specifically include forming a gate metal thin film on the substrate 1 using any of the following methods: sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and forming a pattern including the gate 2 through a patterning process (film formation, exposure, development, wet etching, or dry etching).

[0100] S33, Forming the gate insulating layer 6.

[0101] In some examples, the gate insulating layer 6 can be a single-layer structure or a stacked structure of multiple sublayers. Specifically, each layer can be formed using silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), or aluminum oxide (AlyOx). In the embodiments of this disclosure, the gate insulating layer 6 adopts a SiNx / SiOx stacked structure; the thickness of SiNx is approximately 100–200 nm, and the thickness of SiOx is approximately 50–100 nm.

[0102] In some examples, step S13 may specifically involve forming the gate insulating layer 6 using methods including, but not limited to, plasma-enhanced chemical vapor deposition.

[0103] S34. A pattern including the first semiconductor active layer 3 is formed by a patterning process.

[0104] In some examples, taking IGZO as the material for the first active semiconductor layer 3, step S34 involves using an IGZO target and introducing a mixed gas containing argon (Ar) and oxygen (O2) for sputtering reaction to form the first IGZO film layer. Subsequently, a pattern including the first active semiconductor layer 3 is formed through a patterning process. The argon to oxygen ratio for forming the first active semiconductor layer 3 is approximately 100:1 to 200:1.

[0105] S35. A pattern including a first layer and a second semiconductor active layer 8a is formed through a patterning process.

[0106] The formation of the second semiconductor active layer 8 is roughly the same as the formation of the first semiconductor active layer 3. The only difference is that the ratio of oxygen and argon in the atmosphere in which the second IGZO film is formed is less than the ratio of oxygen and argon in the atmosphere in which the first IGZO film is formed, so that the conductivity of the second IGZO film is greater than that of the first IGZO film.

[0107] S36. A pattern including the second semiconductor active layer 8b is formed through a patterning process.

[0108] The formation of the second active semiconductor layer 8b is roughly the same as the formation of the first active semiconductor layer 8a. The only difference is that the ratio of oxygen and argon in the atmosphere in which the third IGZO film is formed is less than the ratio of oxygen and argon in the atmosphere in which the second IGZO film is formed, so that the conductivity of the third IGZO film is greater than that of the second IGZO film.

[0109] S37. A passivation layer 7 is formed, and a first connection via 101 and a second connection via 102 are formed through the passivation layer 7.

[0110] In some examples, the passivation layer 7 can be formed using the same process steps as the gate insulating layer 6. The passivation layer 7 can also be a single-layer structure or a stacked structure of multiple sublayers. Specifically, each layer can be formed using silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), or aluminum oxide (AlyOx). In the embodiments of this disclosure, the gate insulating layer 6 adopts a SiOx / SiNx stacked structure; the thickness of SiOx is about 100-200 nm, and the thickness of SiNx is about 200-300 nm.

[0111] The formation of the first connection via 101 and the second connection via 102 may include, after forming the passivation layer 7, photoresist coating, exposure of the patterns of the first connection via 101 and the second connection via 102, development, post-baking, etching, and photoresist stripping.

[0112] S38. A pattern including source 4 and drain 5 is formed through a patterning process.

[0113] In some examples, the formation of source 4 and drain 5 can be the same as the formation of gate 2. Source 4 and drain 5 can be formed from metals or metal alloys, such as molybdenum, molybdenum-niobium alloys, aluminum, aluminum-neodymium alloys, titanium, or copper, etc., conductive materials. In this embodiment, a molybdenum / aluminum / molybdenum three-layer structure is used as an example, with the thicknesses of the three layers being... about.

[0114] This completes the fabrication of the third example of a thin-film transistor.

[0115] This disclosure also provides a display substrate including the aforementioned thin-film transistors. The display substrate can be an array substrate in a liquid crystal display or an OLED substrate used in an organic light-emitting diode (OLED) display. The following provides a detailed description of these two types of display substrates.

[0116] In one example, FIG9 is an exemplary pixel unit 100 layout of a display substrate according to an embodiment of the present disclosure. As shown in FIG9, when the display substrate is applied to a liquid crystal display, the display substrate specifically includes multiple gate lines S1 and multiple data lines D, which are intersected to define multiple pixel units 100. Each pixel unit 100 includes a thin film transistor, a pixel electrode 300, and a common electrode 200. The drain 5 of the thin film transistor is connected to the pixel electrode 300. The substrate 1 of each thin film transistor is formed as a single structure. In this embodiment of the present disclosure, the common electrode 200 is positioned closer to the substrate 1 than the pixel electrode 300. In this case, the common electrode 200 is a plate electrode, and the pixel electrode 300 is a slit electrode. Of course, the pixel electrode 300 and the common electrode 200 can also be located on the same layer, with the two spaced apart. Alternatively, only the pixel electrode 300 can be disposed on the display substrate, and the common electrode 200 can be disposed on the cell substrate of the liquid crystal display. These are not listed here.

[0117] In some examples, continuing to refer to Figure 9, an interlayer insulating layer is also provided between the layer containing the pixel electrode 300 and the layer containing the drain 5 of the thin-film transistor. In this case, the pixel electrode 300 needs to be connected to the thin-film transistor through a third connection via 103 penetrating the interlayer insulating layer. For each thin-film transistor, the gate 2 and the gate line S1 connected thereto are integrally formed structures, and the source 4 and the data line D connected thereto are integrally formed structures. For example, a portion of the gate line S1 is used as the gate 2 of the thin-film transistor. Furthermore, the gate line S1 has a first notch. The orthographic projection of the third connection via connecting the pixel electrode 200 and the drain 5 of the thin-film transistor onto the substrate 1 is located within the orthographic projection of the first notch onto the substrate 1. This reduces the pixel size, thereby improving the achievement of high resolution.

[0118] In another example, the display substrate is an OLED substrate, specifically including multiple gate lines S1 and multiple data lines D, which are intersected to define multiple pixel units 100. Each pixel unit 100 includes a pixel driving circuit and a light-emitting device, i.e., an OLED, electrically connected to the pixel driving circuit. At least a portion of the pixel driving circuit employs the aforementioned thin-film transistors. In particular, employing the aforementioned thin-film transistors in the driving transistors of the pixel driving circuit can significantly improve driving capability and increase pixel aperture ratio.

[0119] In some examples, the entire pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 10 is an equivalent circuit diagram of a pixel unit of a display substrate according to another exemplary embodiment of the present disclosure; as shown in Figure 10, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C, and the pixel driving circuit is connected to seven signal lines (data line D, gate line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS).

[0120] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0121] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0122] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initial voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0123] The control electrode of the second transistor T2 is connected to the gate line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction level scan signal is applied to the gate line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0124] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0125] The control electrode of the fourth transistor T4 is connected to the gate line S1, the first electrode of the fourth transistor T4 is connected to the data line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction level scanning signal is applied to the gate line S1, the fourth transistor T4 causes the data voltage of the data line D to be input to the pixel driving circuit.

[0126] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0127] The control electrode of the seventh transistor T7 is connected to the gate line S1, the second electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the first electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scanning signal is applied to the gate line S1, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0128] Figure 11 is a timing diagram of the pixel driving circuit shown in Figure 10. The following describes an exemplary embodiment of the present disclosure through the operation of the pixel driving circuit exemplified in Figure 10. The pixel driving circuit in Figure 10 includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data line D, gate line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS). All 7 transistors are P-type transistors.

[0129] In an exemplary embodiment, taking OLED as an example, the operation of the pixel driving circuit may include:

[0130] In the first stage, A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the gate line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage within it. The high signals on the gate line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0131] The second stage, A2, is called the data writing stage or threshold compensation stage. The signal on gate line S1 is low, while the signals on the second scan signal line S2 and the light emission signal line E are high. Data line D outputs a data voltage. During this stage, because the second terminal of storage capacitor C is low, the third transistor T3 is turned on. The low signal on gate line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from data line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from data line D and the threshold voltage of the third transistor T3 is charged into storage capacitor C. The voltage at the second terminal of storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from data line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0132] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the gate line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0133] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0134] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data line D, and Vdd is the power supply voltage output by the first power line VDD.

[0135] In the exemplary pixel driving circuit provided above, the third transistor T3 is the driving transistor in the pixel driving circuit. This transistor adopts the thin-film transistor in the example above, which can greatly improve the driving capability of the pixel driving circuit and increase the pixel aperture ratio.

[0136] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0137] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A thin-film transistor, comprising: A substrate, comprising a first semiconductor active layer, a gate, a source, and a drain disposed on the substrate; The source electrode is connected to the source contact region of the first semiconductor layer, and the drain electrode is connected to the drain contact region of the first semiconductor layer; wherein... The thin-film transistor further includes at least one second semiconductor active layer located on the side of the first semiconductor active layer opposite to the gate, the second semiconductor active layer being electrically connected to the first semiconductor active layer; and the conductivity of the second semiconductor active layer being greater than the conductivity of the first semiconductor active layer.

2. The thin-film transistor according to claim 1, wherein, The second semiconductor active layer is in contact with the first semiconductor active layer, and the orthographic projection of the second semiconductor active layer on the substrate is located between the orthographic projections of the source contact region and the drain contact region of the first semiconductor active layer on the substrate.

3. The thin-film transistor according to claim 1, wherein, The first semiconductor active layer is located on the side of the gate away from the substrate, and a gate insulating layer is disposed between the first semiconductor active layer and the layer containing the gate.

4. The thin-film transistor according to claim 3, wherein, The source and the drain are located on the side of the first semiconductor active layer away from the substrate, and a passivation layer is provided between the source and drain layers and the first semiconductor active layer; the source is connected to the source contact area through a first connection via penetrating the passivation layer, and the drain is connected to the drain contact area through a second connection via penetrating the passivation layer. Both the first and second connection vias do not overlap with the orthographic projection of the second semiconductor active layer on the substrate.

5. The thin-film transistor according to claim 4, wherein, Both the first and second connection vias overlap with the orthographic projection of the gate on the substrate.

6. The thin-film transistor according to claim 1, wherein, The first semiconductor active layer is located on the side of the gate near the substrate, and a gate insulating layer is disposed between the first semiconductor active layer and the gate layer.

7. The thin-film transistor according to claim 5, wherein, The first active semiconductor layer covers the second active semiconductor layer; the source and the drain are respectively disposed on both sides of the first active semiconductor layer and are in contact with the first active semiconductor layer.

8. The thin-film transistor according to any one of claims 1-7, wherein, The second semiconductor active layer has multiple layers, and the conductivity of the second semiconductor active layer is higher the farther it is from the first semiconductor active layer.

9. The thin-film transistor according to any one of claims 1-7, wherein, The first semiconductor active layer and the second semiconductor active layer are made of the same material.

10. The thin-film transistor according to claim 8, wherein, The materials of the first semiconductor active layer and the second semiconductor active layer include indium gallium zinc oxide.

11. A method for fabricating a thin-film transistor, comprising: A substrate is provided, on which a first semiconductor active layer, a gate, a source, and a drain are formed; The source electrode is connected to the source contact region of the first semiconductor layer, and the drain electrode is connected to the drain contact region of the first semiconductor layer; wherein... The preparation method further includes: forming at least one second semiconductor active layer on the side of the first semiconductor active layer away from the gate, wherein the second semiconductor active layer is electrically connected to the first semiconductor active layer; and the conductivity of the second semiconductor active layer is greater than the conductivity of the first semiconductor active layer.

12. The method for fabricating a thin-film transistor according to claim 11, wherein, The materials for both the first semiconductor active layer and the second semiconductor active layer are indium gallium zinc oxide, and the atmospheres for forming the first semiconductor active layer and the second semiconductor active layer are oxygen and argon. The ratio of oxygen and argon forming the first semiconductor active layer is greater than the ratio of oxygen and argon forming the second semiconductor active layer.

13. The method for fabricating a thin-film transistor according to claim 12, wherein, The second semiconductor active layer has multiple layers, and the ratio of oxygen and argon is lower when the second semiconductor active layer is formed, the farther away from the first semiconductor active layer.

14. A display substrate comprising a plurality of pixel units, each pixel unit comprising a pixel driving circuit; wherein at least a portion of the transistors in the pixel driving circuit employ thin-film transistors as described in any one of claims 1-10.

15. The display substrate according to claim 14, wherein, It also includes multiple gate lines and multiple data lines, defining the pixel unit at the intersection of the gate lines and the data lines; the gate of the transistor connected to the gate line in the pixel driving circuit is integrally formed with the gate line.

16. A display substrate comprising pixel units, each pixel unit including a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit; wherein, The pixel driving circuit uses at least one thin-film transistor as described in any one of claims 1-10 as the driving transistor.

17. The display substrate according to claim 16, wherein, It also includes multiple gate lines and multiple data lines, defining the pixel unit at the intersection of the gate lines and the data lines; the gate of the transistor connected to the gate line in the pixel driving circuit is integrally formed with the gate line.

18. A display device comprising a display substrate according to any one of claims 14-17.

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