Source driving circuit, display panel, display apparatus and driving method

Abstract

The present disclosure relates to the technical field of display. Disclosed are a source driving circuit, a display panel, a display apparatus and a driving method. The source driving circuit comprises: a first input sub-circuit (101), a second input sub-circuit (102), a node control sub-circuit (103), and an output sub-circuit (104). In response to an active voltage signal among signals of a first control signal terminal, the first input sub-circuit (101) provides to a first node and a second node a scan start signal among signals of a second control signal terminal, wherein within one frame display time period, the signals of the first control signal terminal comprise one active voltage signal, and the signals of the second control signal terminal comprise the scan start signal and a data voltage signal, which appear in sequence; the second input sub-circuit (102) provides a signal of a first reference signal terminal to a third node; the node control sub-circuit (103) controls signals of a pull-up node and a pull-down node; and the output sub-circuit (104) provides a signal of a second reference signal terminal to a drive output terminal, or provides the signal of the first reference signal terminal to the drive output terminal. The configuration of the source driving circuit can achieve local refresh of some of the columns in display panels, thereby saving power consumption.

Description

A source drive circuit, a display panel, a display device, and a driving method. Technical Field

[0001] This disclosure relates to the field of display technology, and provides a source driving circuit, a display panel, a display device, and a driving method. Background Technology

[0002] Currently, existing display panels need to initialize and write the data voltage of all pixels within one frame when updating the screen. However, in certain special screen conditions (such as static screens, screens with infrequent updates, and screens that only require updating a few columns), the data voltage of most pixels on the screen does not need to be updated. In this case, the original display brightness can be maintained by low-leakage transistors. Repeatedly writing and updating these pixels results in some wasted power consumption.

[0003] Summary of the Invention

[0004] This disclosure provides a source drive circuit, a display panel, a display device, and a driving method to reduce the power consumption of the display panel during the display process.

[0005] The specific technical solution provided in this disclosure is as follows:

[0006] In a first aspect, embodiments of this disclosure provide a source drive circuit, including: a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit;

[0007] The first input sub-circuit is configured to provide a scan start signal from the second control signal terminal to the first node and the second node in response to an effective voltage signal in the signal of the first control signal terminal. The signal of the first control signal terminal includes an effective voltage signal during one frame display time, and the signal of the second control signal terminal includes a scan start signal and a data voltage signal that appear sequentially.

[0008] The second input sub-circuit is configured to provide the signal from the first reference signal terminal to the third node in response to the signal from the first clock signal terminal.

[0009] The node control sub-circuit is configured to control the signals of the pull-up and pull-down nodes based on the signals of the first node, the second node, and the third node;

[0010] The output sub-circuit is configured to provide the signal of the second reference signal terminal to the drive output terminal in response to the signal of the pull-up node; and to provide the signal of the first reference signal terminal to the drive output terminal in response to the signal of the pull-down node.

[0011] In some possible implementations provided in this disclosure, the first input sub-circuit includes: a first transistor and a second transistor;

[0012] The control terminal of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the second control signal terminal, and the second terminal of the first transistor is coupled to the first node.

[0013] The control terminal of the second transistor is coupled to the first control signal terminal, the first terminal of the second transistor is coupled to the second control signal terminal, and the second terminal of the second transistor is coupled to the second node.

[0014] In some possible implementations provided in this disclosure, the second input sub-circuit includes: a third transistor;

[0015] The control terminal of the third transistor is coupled to the first clock signal terminal, the first terminal of the third transistor is coupled to the first reference signal terminal, and the second terminal of the third transistor is coupled to the third node.

[0016] In some possible implementations provided in this disclosure, the node control sub-circuit includes: a first control sub-unit, a second control sub-unit, and a third control sub-unit;

[0017] The first control subunit is coupled to the first node, the second node, the fourth node, the first reference signal terminal, and the pull-down node. The first control subunit is configured to provide the signal of the first node to the pull-down node in response to the signal of the first reference signal terminal, and to provide the signal of the second node to the fourth node in response to the signal of the first reference signal terminal, and to provide the signal of the fourth node to the pull-down node in response to the signal of the fourth node.

[0018] The second control subunit is coupled to the first node, the third node, the second reference signal terminal, the first clock signal terminal, the second clock signal terminal, and the fourth node. The second control subunit is configured to provide the signal of the first clock signal terminal to the third node in response to a signal from the first node; to provide the signal of the second reference signal terminal to the fifth node in response to a signal from the third node; and to provide the signal of the second clock signal terminal to the fifth node in response to a signal from the fourth node.

[0019] The third control subunit is coupled to the first node, the third node, the first reference signal terminal, the second clock signal terminal, the second reference signal terminal, and the pull-up node. The third control subunit is configured to provide the signal of the second clock signal terminal to the pull-up node in response to the signals of the first reference signal terminal, the third node, and the second clock signal terminal; and to provide the signal of the second reference signal terminal to the pull-up node in response to the signal of the first node.

[0020] In some possible implementations provided in this disclosure, the first control subunit includes: a fourth transistor, a fifth transistor, and a sixth transistor;

[0021] The control terminal of the fourth transistor is coupled to the first reference signal terminal, the first terminal of the fourth transistor is coupled to the first node, and the second terminal of the fourth transistor is coupled to the pull-down node.

[0022] The control terminal of the fifth transistor is coupled to the first reference signal terminal, the first terminal of the fifth transistor is coupled to the second node, and the second terminal of the fifth transistor is coupled to the fourth node.

[0023] The control terminal of the sixth transistor is coupled to the fourth node, the first terminal of the sixth transistor is coupled to the fourth node, and the second terminal of the sixth transistor is coupled to the pull-down node.

[0024] In some possible implementations provided in this disclosure, the second control subunit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor;

[0025] The control terminal of the seventh transistor is coupled to the first node, the first terminal of the seventh transistor is coupled to the first clock signal terminal, and the second terminal of the seventh transistor is coupled to the third node.

[0026] The control terminal of the eighth transistor is coupled to the third node, the first terminal of the eighth transistor is coupled to the fifth node, and the second terminal of the eighth transistor is coupled to the second reference signal terminal.

[0027] The control terminal of the ninth transistor is coupled to the fourth node, and the first terminal of the ninth transistor is coupled to the second clock signal terminal;

[0028] The first terminal of the first capacitor is coupled to the fourth node, and the second terminal of the first capacitor is coupled to the fifth node.

[0029] In some possible implementations provided in this disclosure, the third control subunit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor;

[0030] The control terminal of the tenth transistor is coupled to the first reference voltage signal terminal, the first terminal of the tenth transistor is coupled to the third node, and the second terminal of the tenth transistor is coupled to the first terminal of the second capacitor.

[0031] The control terminal of the eleventh transistor is coupled to the first terminal of the second capacitor, the first terminal of the eleventh transistor is coupled to the second terminal of the second capacitor, and the second terminal of the eleventh transistor is coupled to the second clock signal terminal.

[0032] The control terminal of the twelfth transistor is coupled to the second clock signal terminal, the first terminal of the twelfth transistor is coupled to the second terminal of the second capacitor, and the second terminal of the twelfth transistor is coupled to the pull-up node.

[0033] The control terminal of the thirteenth transistor is coupled to the first node, the first terminal of the thirteenth transistor is coupled to the second reference signal terminal, and the second terminal of the thirteenth transistor is coupled to the pull-up node.

[0034] In some possible implementations provided in this disclosure, the output sub-circuit includes: a fourteenth transistor, a third capacitor, and a fifteenth transistor;

[0035] The control terminal of the fourteenth transistor is coupled to the pull-down node, the first terminal of the fourteenth transistor is coupled to the first reference signal terminal, and the second terminal of the fourteenth transistor is coupled to the drive output terminal.

[0036] The first terminal of the third capacitor is coupled to the pull-up node, and the second terminal of the third capacitor is coupled to the second reference signal terminal.

[0037] The control terminal of the fifteenth transistor is coupled to the pull-up node, the first terminal of the fifteenth transistor is coupled to the drive output terminal, and the second terminal of the fifteenth transistor is coupled to the second reference signal terminal.

[0038] In some possible implementations provided in this disclosure, a first pull-down control sub-circuit is also included;

[0039] The first pull-down control subcircuit is configured to provide a signal from the first reference signal terminal to the fourth node in response to a signal from the pull-down node, the first node, or the second node.

[0040] In some possible implementations provided in this disclosure, the first pull-down control subcircuit includes: a sixteenth transistor;

[0041] The control terminal of the sixteenth transistor is coupled to the pull-down node, the first node, or the second node. The first terminal of the sixteenth transistor is coupled to the first reference signal terminal, and the second terminal of the sixteenth transistor is coupled to the fourth node.

[0042] In some possible implementations provided in this disclosure, a second pull-down control subcircuit is also included;

[0043] The first pull-down control sub-circuit is coupled to the first reference signal terminal via the second pull-down control sub-circuit. The second pull-down control sub-circuit is configured to provide the signal from the first reference signal terminal to the first pull-down control sub-circuit in response to the signal from the drive output terminal.

[0044] In some possible implementations provided in this disclosure, the second pull-down control sub-circuit includes: a seventeenth transistor;

[0045] The control terminal of the seventeenth transistor is coupled to the drive output terminal, the first terminal of the seventeenth transistor is coupled to the first pull-down control sub-circuit, and the second terminal of the seventeenth transistor is coupled to the first reference signal terminal.

[0046] In some possible implementations provided in this disclosure, a reset sub-circuit is also included;

[0047] The reset sub-circuit is configured to provide a signal from the second reference signal terminal to the first node in response to a signal from the node control signal terminal.

[0048] In some possible implementations provided in this disclosure, the reset sub-circuit includes: an eighteenth transistor;

[0049] The control terminal of the eighteenth transistor is coupled to the node control signal terminal, the first terminal of the eighteenth transistor is coupled to the first node, and the second terminal of the eighteenth transistor is coupled to the second reference signal terminal.

[0050] In some possible implementations provided in this disclosure, the first reference signal terminal includes a first sub-reference signal terminal and a second sub-reference signal terminal;

[0051] The second reference signal terminal includes a first reference sub-signal terminal and a second reference sub-signal terminal.

[0052] In some possible implementations provided in this disclosure, the voltage value of the first sub-reference signal terminal is greater than or equal to the voltage value of the second sub-reference signal terminal.

[0053] In some possible implementations provided in this disclosure, the voltage value of the second reference sub-signal terminal is greater than or equal to the voltage value of the first reference sub-signal terminal.

[0054] Secondly, embodiments of this disclosure also provide a display panel, including:

[0055] The display area includes multiple sub-pixels, multiple column refresh lines, and multiple data lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit connected to the light-emitting device. A column refresh line is connected to the pixel driving circuit of at least some of the sub-pixels in a column of sub-pixels, and a data line is connected to the pixel driving circuit of at least some of the sub-pixels in a column of sub-pixels.

[0056] The non-display area includes multiple source control lines and multiple source drive circuits as described above. The drive output terminal of one of the multiple source drive circuits is connected to one of the multiple column refresh lines. The second control signal terminal of one of the multiple source drive circuits is connected to one of the multiple data lines. The first control signal terminal of one of the multiple source drive circuits is connected to one of the multiple source control lines.

[0057] In some possible implementations provided in this disclosure, the pixel driving circuit includes: a first write transistor and a second write transistor, wherein the first write transistor and the second write transistor are of different types;

[0058] The control terminal of the first write transistor is coupled to the second scan signal terminal connected to the sub-pixel, the first terminal of the first write transistor is coupled to the first reference signal terminal, and the second terminal of the first write transistor is coupled to the first terminal of the second write transistor.

[0059] The control terminal of the second write transistor is coupled to the second scan signal terminal connected to the sub-pixel. The first terminal of the second write transistor is coupled to the control terminal of the turn-on control transistor. The second terminal of the second write transistor is coupled to the first scan signal terminal connected to the sub-pixel. The first terminal of the turn-on control transistor is coupled to the control terminal of the drive transistor. The second terminal of the turn-on control transistor is coupled to the first terminal of the drive transistor. The first scan signal terminal is coupled to the column refresh line connected to the sub-pixel.

[0060] Thirdly, embodiments of this disclosure also provide a display device, including: a display panel as described above and at least one source chip;

[0061] The source chip is coupled to at least some of the data lines and at least some of the source control lines of the display panel. The source chip is configured to sequentially output a scan start signal and a data voltage signal to the data lines connected to it during one frame of display time, and to output an effective voltage signal to the source control line.

[0062] Fourthly, embodiments of this disclosure also provide a first driving method applied to the source driving circuit of any of the above claims, comprising:

[0063] Input phase: The first input sub-circuit responds to the effective voltage signal in the signal of the first control signal terminal and provides the scan start signal in the signal of the second control signal terminal to the first node and the second node; the second input sub-circuit is configured to respond to the signal of the first clock signal terminal and provide the signal of the first reference signal terminal to the third node; the node control sub-circuit controls the signals of the pull-up node and the pull-down node to be in a sustaining state according to the signals of the first node, the second node and the third node;

[0064] Output phase: The first input sub-circuit responds to the invalid voltage signal in the signal of the first control signal terminal, maintaining the first node and the second node at an invalid level; the second input sub-circuit responds to the first clock signal terminal, maintaining the third node at an active level; the node control sub-circuit controls the signal of the pull-up node to be active based on the signals of the first node, the second node and the third node; and the output sub-circuit is configured to provide the signal of the second reference signal terminal to the drive output terminal in response to the signal of the pull-up node.

[0065] Fifthly, embodiments of this disclosure also provide a second driving method applied to the source drive circuit of any of the above claims, comprising:

[0066] Signal input phase: The first input sub-circuit responds to the effective voltage signal in the signal of the first control signal terminal and provides the scan start signal in the signal of the second control signal terminal to the first node and the second node; the second input sub-circuit is configured to respond to the signal of the first clock signal terminal and provide the signal of the first reference signal terminal to the third node; the node control sub-circuit controls the signal of the pull-down node to be in an effective state according to the signals of the first node, the second node and the third node;

[0067] Signal output stage: The node control sub-circuit controls the signal of the pull-up node to be in an invalid state and controls the signal of the pull-down node to be in an active state according to the signals of the first node, the second node and the third node; and the output sub-circuit is configured to provide the signal of the first reference signal terminal to the drive output terminal in response to the signal of the pull-down node.

[0068] The beneficial effects of this disclosure are as follows:

[0069] In summary, this disclosure provides a source driving circuit, a display panel, a display device, and a driving method. The source driving circuit includes a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit. The first input sub-circuit is configured to provide a scan start signal from the second control signal to a first node and a second node in response to an effective voltage signal in the signal of a first control signal terminal. Within one frame of display time, the signal of the first control signal terminal includes an effective voltage signal, and the signal of the second control signal terminal includes a scan start signal and a data voltage signal appearing sequentially. The second input sub-circuit is configured to provide a signal from a first reference signal terminal to a third node in response to a signal of a first clock signal terminal. The node control sub-circuit is configured to control the signals of a pull-up node and a pull-down node based on the signals of the first node, the second node, and the third node. The output sub-circuit is configured to provide a signal from the second reference signal terminal to a drive output terminal in response to a signal from a pull-up node, and to provide a signal from the first reference signal terminal to a drive output terminal in response to a signal from a pull-down node. Through the above-described source driving circuit configuration, partial refresh of some columns in the display panel can be achieved, thereby saving power consumption while ensuring display quality.

[0070] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0071] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0072] Figure 1 is a circuit connection diagram of the first pixel driving circuit in the related technology;

[0073] Figure 2 is a circuit connection diagram of the second type of pixel driving circuit in the related technology;

[0074] Figure 3 is a circuit connection diagram of the third type of pixel driving circuit in the related technology;

[0075] Figure 4 is a circuit connection diagram of the fourth pixel driving circuit in the related technology;

[0076] Figure 5 is a circuit connection diagram of the fifth pixel driving circuit in the related technology;

[0077] Figure 6 is a circuit connection diagram of the sixth pixel driving circuit in the related technology;

[0078] Figure 7 is a circuit connection diagram of the seventh pixel driving circuit in the related technology;

[0079] Figure 8 is a circuit connection diagram of the eighth pixel driving circuit in the related technology;

[0080] Figure 9 is a connection diagram of the first source drive circuit in the embodiment of this disclosure;

[0081] Figure 10 is a connection diagram of the second type of source drive circuit in an embodiment of this disclosure;

[0082] Figure 11 is a circuit connection diagram of the first source drive circuit in the embodiment of this disclosure;

[0083] Figure 12 is a connection diagram of the third type of source drive circuit in the embodiment of this disclosure;

[0084] Figure 13 is a circuit connection diagram of the second source drive circuit in the embodiments of this disclosure;

[0085] Figure 14 is a connection diagram of the fourth source drive circuit in the embodiments of this disclosure;

[0086] Figure 15 is a circuit connection diagram of the third source drive circuit in the embodiments of this disclosure;

[0087] Figure 16 is a connection diagram of the fifth source drive circuit in the embodiments of this disclosure;

[0088] Figure 17 is a circuit connection diagram of the fourth source drive circuit in the embodiments of this disclosure;

[0089] Figure 18 is a circuit connection diagram of the fifth source drive circuit in the embodiments of this disclosure;

[0090] Figure 19 is a circuit connection diagram of the sixth source drive circuit in the embodiments of this disclosure;

[0091] Figure 20 is a circuit connection diagram of the seventh source drive circuit in the embodiments of this disclosure;

[0092] Figure 21 is a circuit connection diagram of the eighth source drive circuit in the embodiments of this disclosure;

[0093] Figure 22 is a timing diagram of a source drive circuit according to an embodiment of this disclosure;

[0094] Figure 23 is a schematic diagram of the connection of a display panel according to an embodiment of the present disclosure;

[0095] Figure 24 is a connection diagram of a display device according to an embodiment of the present disclosure;

[0096] Figure 25 is a connection diagram of a display device according to an embodiment of the present disclosure;

[0097] Figure 26 is a flowchart of a first driving method for a source drive circuit in an embodiment of the present disclosure;

[0098] Figure 27 is a first simulation waveform diagram of a source drive circuit according to an embodiment of the present disclosure;

[0099] Figure 28 is a flowchart of a second driving method for a source drive circuit in an embodiment of this disclosure;

[0100] Figure 29 is a second simulation waveform diagram of a source drive circuit in an embodiment of this disclosure. Detailed Implementation

[0101] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0102] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0103] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0104] In related technologies, when a display panel updates its image, it needs to initialize and write the data voltage of all pixels within one frame. However, in certain special image conditions (e.g., static images, images with infrequent updates, and images that only require updating a few columns), the data voltage of most pixels on the screen does not need to be updated. In this case, the original display brightness can be maintained by low-leakage transistors. Repeatedly writing and updating these pixels results in some wasted power consumption.

[0105] The following describes a pixel driving circuit adapted to the source driving circuit in the embodiments of this disclosure. Unlike the pixel driving circuit of related technologies, the data writing sub-circuit of the adapted pixel driving circuit includes at least two switching transistors, which control whether the data voltage is written to the control terminal of the driving transistor.

[0106] For example, the pixel driving circuit adapted to the source driving circuit in the embodiments of this disclosure includes: a driving transistor, a light-emitting device, a data writing sub-circuit, and a light-emitting control sub-circuit.

[0107] The data writing sub-circuit is coupled to the control terminal of the driving transistor and is configured to provide the data voltage of the data signal terminal to the control terminal of the driving transistor in response to the signal at the scan signal terminal.

[0108] During implementation, when the signal at the scanning signal terminal is at an effective level, the data writing sub-circuit is turned on, and the data voltage at the data signal terminal is provided to the control terminal of the driving transistor through the turned-on data writing sub-circuit.

[0109] In the first case, two switching transistors are connected in series to write the data voltage. Referring to Figures 1 and 2, the data writing sub-circuit includes a first switching transistor M1 and a second switching transistor M2, wherein the scan signal terminals include a first scan signal terminal C_Gate and a second scan signal terminal N_Gate.

[0110] The control terminal of the first switching transistor M1 is coupled to the first scan signal terminal C_Gate, the first terminal of the first switching transistor M1 is coupled to the second terminal of the driving transistor, and the second terminal of the first switching transistor M1 is coupled to the first terminal of the second switching transistor M2.

[0111] During implementation, when the signal at the first scan signal terminal C_Gate is at an effective level, the first switching transistor M1 is turned on, and the second terminal of the driving transistor is connected to the first terminal of the second switching transistor M2 through the turned-on first switching transistor M1.

[0112] The control terminal of the second switching transistor M2 is coupled to the second scan signal terminal N_Gate, and the second terminal of the second switching transistor M2 is coupled to the control terminal of the driving transistor.

[0113] During implementation, when the signal at the second scan signal terminal N_Gate is at an effective level, the second switching transistor M2 is turned on, and the control terminal of the driving transistor is connected to the second terminal of the first switching transistor M1 through the turned-on second switching transistor M2.

[0114] It should be noted that when the display panel needs to refresh the image, it is necessary to simultaneously control the first switching transistor M1 and the second switching transistor M2 to be turned on, so as to write the data voltage into the driving transistor of the pixel driving circuit corresponding to the sub-pixel.

[0115] However, when the display panel does not need to refresh the image, at least one of the first switching transistor M1 and the second switching transistor M2 can be turned off, thereby preventing the data voltage from being written into the driving transistor of the pixel driving circuit corresponding to the sub-pixel.

[0116] In the second case, two switching transistors are connected in series to write the data voltage. As shown in Figures 3 and 4, the data writing sub-circuit includes a third switching transistor M3 and a fourth switching transistor M4. The scan signal terminals include a first scan signal terminal C_Gate and a second scan signal terminal N_Gate.

[0117] The control terminal of the third switching transistor M3 is coupled to the first scan signal terminal C_Gate, the first terminal of the third switching transistor M3 is coupled to the control terminal of the driving transistor, and the second terminal of the third switching transistor M3 is coupled to the first terminal of the fourth switching transistor M4.

[0118] During implementation, when the signal at the first scan signal terminal C_Gate is at an effective level, the third switching transistor M3 is turned on, and the control terminal of the driving transistor is connected to the first terminal of the fourth switching transistor M4 through the turned-on third switching transistor M3.

[0119] The control terminal of the fourth switching transistor M4 is coupled to the second scan signal terminal N_Gate, and the second terminal of the fourth switching transistor M4 is coupled to the second terminal of the driving transistor.

[0120] During implementation, when the signal at the second scan signal terminal N_Gate is at an effective level, the fourth switching transistor M4 is turned on, and the second terminal of the driving transistor is connected to the second terminal of the third switching transistor M3 through the turned-on fourth switching transistor M4.

[0121] It should be noted that when the display panel needs to refresh the image, both the third switching transistor M3 and the fourth switching transistor M4 need to be turned on simultaneously, so as to write the data voltage into the driving transistor of the pixel driving circuit corresponding to the sub-pixel.

[0122] However, when the display panel does not need to refresh the image, at least one of the third switching transistor M3 and the fourth switching transistor M4 can be turned off, thereby preventing the data voltage from being written into the driving transistor of the pixel driving circuit corresponding to the sub-pixel.

[0123] In the third scenario, three switching transistors work together to write the data voltage. As shown in Figures 5 and 6, the data writing sub-circuit includes: the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7. The scan signal terminals include the first scan signal terminal C_Gate and the second scan signal terminal N_Gate.

[0124] The control terminal of the fifth switching transistor M5 is coupled to the first scan signal terminal C_Gate, the first terminal of the fifth switching transistor M5 is coupled to the second scan signal terminal N_Gate, and the second terminal of the fifth switching transistor M5 is coupled to the first terminal of the sixth switching transistor M6.

[0125] During implementation, when the signal at the first scan signal terminal C_Gate is at an effective level, the fifth switching transistor M5 is turned on, and the second scan signal terminal N_Gate is connected to the first terminal of the sixth switching transistor M6 via the turned-on fifth switching transistor M5.

[0126] The control terminal of the sixth switching transistor M6 is coupled to the first scan signal terminal C_Gate, and the second terminal of the sixth switching transistor M6 is coupled to the first voltage signal terminal.

[0127] During implementation, when the signal at the first scan signal terminal C_Gate is at an active level, the sixth switching transistor M6 is turned on, and the first voltage signal terminal is connected to the second terminal of the fifth switching transistor M5 via the turned-on sixth switching transistor M6. The fifth switching transistor M5 and the sixth switching transistor M6 are of different types; that is, the active levels of the control terminals of the fifth switching transistor M5 and the sixth switching transistor M6 are opposite. Therefore, the fifth switching transistor M5 and the sixth switching transistor M6 will not be turned on simultaneously.

[0128] The control terminal of the seventh switching transistor M7 is coupled to the first terminal of the sixth switching transistor M6, the first terminal of the seventh switching transistor M7 is coupled to the control terminal of the driving transistor, and the second terminal of the seventh switching transistor M7 is coupled to the second terminal of the driving transistor.

[0129] During implementation, when the signal at the first terminal of the sixth switching transistor M6 is at an effective level, the seventh switching transistor M7 is turned on, and the second terminal of the seventh switching transistor M7 is connected to the control terminal of the driving transistor through the turned-on seventh switching transistor M7.

[0130] It should be noted that when the display panel needs to refresh the image, the seventh switch transistor M7 is turned on by selecting the fifth switch transistor M5 and the sixth switch transistor M6, thereby writing the data voltage into the driving transistor of the pixel driving circuit corresponding to the sub-pixel.

[0131] However, when the display panel does not need to refresh the image, the seventh switch transistor M7 is turned off by selecting the fifth switch transistor M5 and the sixth switch transistor M6, thereby preventing the data voltage from being written into the driving transistor of the pixel driving circuit corresponding to the sub-pixel.

[0132] In the fourth case, three switching transistors work together to write the data voltage. As shown in Figures 7 and 8, the data writing sub-circuit includes: the eighth switching transistor M8, the ninth switching transistor M9, and the tenth switching transistor M10. The scan signal terminals include the first scan signal terminal C_Gate and the second scan signal terminal N_Gate.

[0133] The control terminal of the eighth switching transistor M8 is coupled to the second scan signal terminal N_Gate, the first terminal of the eighth switching transistor M8 is coupled to the first scan signal terminal C_Gate, and the second terminal of the eighth switching transistor M8 is coupled to the first terminal of the ninth switching transistor M9.

[0134] During implementation, when the signal at the second scan signal terminal N_Gate is at an effective level, the eighth switch transistor M8 is turned on, and the first scan signal terminal C_Gate is connected to the first terminal of the ninth switch transistor M9 via the turned-on eighth switch transistor M8.

[0135] The control terminal of the ninth switching transistor M9 is coupled to the second scan signal terminal N_Gate, and the second terminal of the ninth switching transistor M9 is coupled to the first voltage signal terminal.

[0136] During implementation, when the signal at the second scan signal terminal N_Gate is at an active level, the ninth switching transistor M9 is turned on, and the first voltage signal terminal is connected to the second terminal of the eighth switching transistor M8 via the turned-on ninth switching transistor M9. The eighth switching transistor M8 and the ninth switching transistor M9 are of different types; that is, the active levels of the control terminals of the eighth switching transistor M8 and the ninth switching transistor M9 are opposite. Therefore, the eighth switching transistor M8 and the ninth switching transistor M9 will not be turned on simultaneously.

[0137] The control terminal of the tenth switching transistor M10 is coupled to the first terminal of the ninth switching transistor M9, the first terminal of the tenth switching transistor M10 is coupled to the control terminal of the driving transistor, and the second terminal of the tenth switching transistor M10 is coupled to the second terminal of the driving transistor.

[0138] During implementation, when the signal at the first terminal of the ninth switching transistor M9 is at an effective level, the tenth switching transistor M10 is turned on, and the control terminal of the driving transistor is connected to the second terminal of the driving transistor through the turned-on tenth switching transistor M10.

[0139] After writing data voltage to the driving transistor in the pixel driving circuit using the first, second, third, or fourth method described above, the driving transistor is configured to generate driving current based on the data voltage.

[0140] During implementation, when the data voltage is written to the control terminal of the driving transistor, the driving transistor can generate a driving current according to the data voltage, thereby realizing the update of the data voltage of the corresponding sub-pixel.

[0141] The driving transistor is coupled to the light-emitting device through a light-emitting control sub-circuit, which is configured to provide the driving current generated by the driving transistor to the light-emitting device.

[0142] During implementation, when the light-emitting control sub-circuit is turned on, the driving transistor can connect with the light-emitting device through the light-emitting control sub-circuit, thereby providing the driving current generated by the driving transistor to the light-emitting device, thereby causing the light-emitting device corresponding to the above-mentioned sub-pixel to emit light and display, thus realizing the refresh of the screen.

[0143] It should also be noted that if certain columns of the display screen do not need to be refreshed, the sub-pixels of the relevant columns can be controlled not to update the data voltage. In the specific implementation process, by controlling the on / off state of at least two switching transistors included in the data writing sub-circuit of the pixel driving circuit mentioned above, the data voltage is not written to the control terminal of the driving transistor during the display time of this frame.

[0144] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0145] Referring to Figures 9 and 10, a source drive circuit proposed in this application embodiment includes: a first input sub-circuit 101, a second input sub-circuit 102, a node control sub-circuit 103, and an output sub-circuit 104.

[0146] The first input sub-circuit 101 is configured to provide the scan start signal in the second control signal terminal Datain to the first node N1 and the second node N2 in response to the effective voltage signal in the signal of the first control signal terminal HSW. The signal of the first control signal terminal HSW includes an effective voltage signal during one frame display time, and the signal of the second control signal terminal Datain includes the scan start signal and the data voltage signal that appear sequentially.

[0147] During implementation, when the effective voltage signal in the signal of the first control signal terminal HSW is input, the first input sub-circuit 101 is turned on, and the scan start signal in the signal of the second control signal terminal Datain is provided to the first node N1 and the second node N2 through the turned-on first input sub-circuit 101.

[0148] In order to achieve partial refresh of the display panel in the column direction, in this embodiment of the present disclosure, before writing data voltage to the data line, the effective voltage signal and the scan start signal are used to control whether to refresh the column. Therefore, within one frame display time, the signal of the first control signal terminal HSW includes only one effective voltage signal. That is, when the column needs to be refreshed, the effective voltage signal provided by the first control signal terminal HSW is input to the first input sub-circuit 101, and then the scan start signal provided by the second control signal terminal Datain is written to the first node N1 and the second node N2.

[0149] It should be noted that the signals of the second control signal terminal Datain include the scan start signal and the data voltage signal that appear sequentially. However, when the second control signal terminal Datain provides the data voltage signal, the signal of the first control signal terminal HSW will correspond to a signal other than the effective voltage signal. That is, when the signal of the first control signal terminal HSW is a signal other than the effective voltage signal, the signal of the second control signal terminal Datain is the data voltage signal. In other words, the source drive circuit of the above-mentioned circuit shields the response of the data voltage signal and controls whether the column is refreshed only according to the scan start signal before the data voltage signal appears.

[0150] For example, referring to FIG11, the first input sub-circuit 101 includes: a first transistor T1 and a second transistor T2.

[0151] The control terminal of the first transistor T1 is coupled to the first control signal terminal HSW, the first terminal of the first transistor T1 is coupled to the second control signal terminal Datain, and the second terminal of the first transistor T1 is coupled to the first node N1.

[0152] For example, the first transistor T1 can be turned on under the control of the active level of the first control signal terminal HSW, and can be turned off under the control of the inactive level of the first control signal terminal HSW. For example, if the first transistor T1 is set as an N-type transistor, then the active level of the signal at the first control signal terminal HSW is a high level, and the inactive level of the signal at the first control signal terminal HSW is a low level. Alternatively, if the first transistor T1 is set as a P-type transistor, then the active level of the signal at the first control signal terminal HSW is a low level, and the inactive level of the signal at the first control signal terminal HSW is a high level.

[0153] Referring to Figure 11, the first transistor T1 is a P-type transistor. When the signal at the first control signal terminal HSW is low, the first transistor T1 is turned on, and the second control signal terminal Datain is connected to the first node N1 through the turned-on first transistor T1.

[0154] The control terminal of the second transistor T2 is coupled to the first control signal terminal HSW, the first terminal of the second transistor T2 is coupled to the second control signal terminal Datain, and the second terminal of the second transistor T2 is coupled to the second node N2.

[0155] For example, the second transistor T2 can be turned on under the control of the active level of the first control signal terminal HSW, and can be turned off under the control of the inactive level of the first control signal terminal HSW. For example, if the second transistor T2 is set as an N-type transistor, then the active level of the signal at the first control signal terminal HSW is a high level, and the inactive level of the signal at the first control signal terminal HSW is a low level. Alternatively, if the second transistor T2 is set as a P-type transistor, then the active level of the signal at the first control signal terminal HSW is a low level, and the inactive level of the signal at the first control signal terminal HSW is a high level.

[0156] Referring to Figure 11, the second transistor T2 is a P-type transistor. When the signal at the first control signal terminal HSW is low, the second transistor T2 is turned on, and the second control signal terminal Datain is connected to the second node N2 through the turned-on second transistor T2.

[0157] The second input sub-circuit 102 is configured to provide the signal of the first reference signal terminal VGL to the third node N3 in response to the signal of the first clock signal terminal CK.

[0158] During implementation, when the signal at the first clock signal terminal CK is valid, the second input sub-circuit 102 is turned on, and the signal at the first reference signal terminal VGL is provided to the third node N3 through the turned-on second input sub-circuit 102.

[0159] For example, referring to FIG11, the second input sub-circuit 102 includes a third transistor T3.

[0160] The control terminal of the third transistor T3 is coupled to the first clock signal terminal CK, the first terminal of the third transistor T3 is coupled to the first reference signal terminal VGL, and the second terminal of the third transistor T3 is coupled to the third node N3.

[0161] For example, the third transistor T3 can be turned on under the control of the active level of the first clock signal terminal CK, and can be turned off under the control of the inactive level of the first clock signal terminal CK. For example, if the third transistor T3 is set as an N-type transistor, then the active level of the signal at the first clock signal terminal CK is high, and the inactive level of the signal at the first clock signal terminal CK is low. Alternatively, if the third transistor T3 is set as a P-type transistor, then the active level of the signal at the first clock signal terminal CK is low, and the inactive level of the signal at the first clock signal terminal CK is high.

[0162] Referring to Figure 11, the third transistor T3 is a P-type transistor. When the signal at the first clock signal terminal CK is low, the third transistor T3 is turned on, and the first reference signal terminal VGL is connected to the third node N3 through the turned-on third transistor T3.

[0163] The node control sub-circuit 103 is configured to control the signals of pull-up node N8 and pull-down node N9 based on the signals of the first node N1, the second node N2 and the third node N3.

[0164] During implementation, the node control sub-circuit 103 controls the pull-up node N8 to an active level based on the signals from the first node N1, the second node N2, and the third node N3, thereby causing the output sub-circuit 104 to output the signal from the second reference signal terminal VGH. Alternatively, the node control sub-circuit 103 controls the pull-down node N9 to an active level based on the signals from the first node N1, the second node N2, and the third node N3, thereby causing the output sub-circuit 104 to output the signal from the first reference signal terminal VGL.

[0165] During implementation, when the signal of pull-up node N8 is at an active level, output sub-circuit 104 is turned on, and the signal of the second reference signal terminal VGH is provided to the drive output terminal HOUT through the turned-on output sub-circuit 104. Alternatively, when the signal of pull-down node N9 is at an active level, output sub-circuit 104 is turned on, and the signal of the first reference signal terminal VGL is provided to the drive output terminal HOUT through the turned-on output sub-circuit 104.

[0166] For example, referring to FIG11, the node control sub-circuit 103 includes: a first control sub-unit 1031, a second control sub-unit 1032 and a third control sub-unit 1033.

[0167] The first control subunit 1031 is coupled to the first node N1, the second node N2, the fourth node N4, the first reference signal terminal VGL, and the pull-down node N9. The first control subunit 1031 is configured to provide the signal of the first node N1 to the pull-down node N9 in response to the signal of the first reference signal terminal VGL, provide the signal of the second node N2 to the fourth node N4 in response to the signal of the first reference signal terminal VGL, and provide the signal of the fourth node N4 to the pull-down node N9 in response to the signal of the fourth node N4.

[0168] For example, referring to FIG11, the first control subunit 1031 includes: a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0169] The control terminal of the fourth transistor T4 is coupled to the first reference signal terminal VGL, the first terminal of the fourth transistor T4 is coupled to the first node N1, and the second terminal of the fourth transistor T4 is coupled to the pull-down node N9.

[0170] For example, the fourth transistor T4 can be turned on under the control of the active level of the first reference signal terminal VGL, and can be turned off under the control of the inactive level of the first reference signal terminal VGL. For example, if the fourth transistor T4 is set as an N-type transistor, then the active level of the signal at the first reference signal terminal VGL is a high level, and the inactive level of the signal at the first reference signal terminal VGL is a low level. Alternatively, if the fourth transistor T4 is set as a P-type transistor, then the active level of the signal at the first reference signal terminal VGL is a low level, and the inactive level of the signal at the first reference signal terminal VGL is a high level.

[0171] Referring to Figure 11, the fourth transistor T4 is a P-type transistor. When the signal at the first reference signal terminal VGL is low, the fourth transistor T4 is turned on, and the first node N1 is connected to the pull-down node N9 through the turned-on fourth transistor T4.

[0172] The control terminal of the fifth transistor T5 is coupled to the first reference signal terminal VGL, the first terminal of the fifth transistor T5 is coupled to the second node N2, and the second terminal of the fifth transistor T5 is coupled to the fourth node N4.

[0173] For example, the fifth transistor T5 can be turned on under the control of the active level of the first reference signal terminal VGL, and can be turned off under the control of the inactive level of the first reference signal terminal VGL. For example, if the fifth transistor T5 is set as an N-type transistor, then the active level of the signal at the first reference signal terminal VGL is a high level, and the inactive level of the signal at the first reference signal terminal VGL is a low level. Alternatively, if the fifth transistor T5 is set as a P-type transistor, then the active level of the signal at the first reference signal terminal VGL is a low level, and the inactive level of the signal at the first reference signal terminal VGL is a high level.

[0174] Referring to Figure 11, the fifth transistor T5 is a P-type transistor. When the signal at the first reference signal terminal VGL is low, the fifth transistor T5 is turned on, and the second node N2 is connected to the fourth node N4 through the turned-on fifth transistor T5.

[0175] The control terminal of the sixth transistor T6 is coupled to the fourth node N4, the first terminal of the sixth transistor T6 is coupled to the fourth node N4, and the second terminal of the sixth transistor T6 is coupled to the pull-down node N9.

[0176] For example, the sixth transistor T6 can be turned on under the control of the active level of the fourth node N4, and turned off under the control of the inactive level of the fourth node N4. For example, if the sixth transistor T6 is set as an N-type transistor, then the active level of the signal at the fourth node N4 is high, and the inactive level of the signal at the fourth node N4 is low. Alternatively, if the sixth transistor T6 is set as a P-type transistor, then the active level of the signal at the fourth node N4 is low, and the inactive level of the signal at the fourth node N4 is high.

[0177] Referring to Figure 11, the sixth transistor T6 is a P-type transistor. When the signal of the fourth node N4 is low, the sixth transistor T6 is turned on, and the fourth node N4 is connected to the pull-down node N9 through the turned-on sixth transistor T6.

[0178] The second control subunit 1032 is coupled to the first node N1, the third node N3, the second reference signal terminal VGH, the first clock signal terminal CK, the second clock signal terminal CB, and the fourth node N4. The second control subunit 1032 is configured to provide the signal of the first clock signal terminal CK to the third node N3 in response to the signal of the first node N1; to provide the signal of the second reference signal terminal VGH to the fifth node N5 in response to the signal of the third node N3; and to provide the signal of the second clock signal terminal CB to the fifth node N5 in response to the signal of the fourth node N4.

[0179] For example, referring to FIG11, the second control subunit 1032 includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a first capacitor C1.

[0180] The control terminal of the seventh transistor T7 is coupled to the first node N1, the first terminal of the seventh transistor T7 is coupled to the first clock signal terminal CK, and the second terminal of the seventh transistor T7 is coupled to the third node N3.

[0181] For example, the seventh transistor T7 can be turned on under the control of the active level of the first node N1 and turned off under the control of the inactive level of the first node N1. For example, if the seventh transistor T7 is set as an N-type transistor, then the active level of the signal of the first node N1 is a high level, and the inactive level of the signal of the first node N1 is a low level. Alternatively, if the seventh transistor T7 is set as a P-type transistor, then the active level of the signal of the first node N1 is a low level, and the inactive level of the signal of the first node N1 is a high level.

[0182] Referring to Figure 11, the seventh transistor T7 is a P-type transistor. When the signal at the first node N1 is low, the seventh transistor T7 is turned on, and the first clock signal terminal CK is connected to the third node N3 through the turned-on seventh transistor T7.

[0183] The control terminal of the eighth transistor T8 is coupled to the third node N3, the first terminal of the eighth transistor T8 is coupled to the fifth node N5, and the second terminal of the eighth transistor T8 is coupled to the second reference signal terminal VGH.

[0184] For example, the eighth transistor T8 can be turned on under the control of the active level of the third node N3, and can be turned off under the control of the inactive level of the third node N3. For example, if the eighth transistor T8 is set as an N-type transistor, then the active level of the signal of the third node N3 is a high level, and the inactive level of the signal of the third node N3 is a low level. Alternatively, if the eighth transistor T8 is set as a P-type transistor, then the active level of the signal of the third node N3 is a low level, and the inactive level of the signal of the third node N3 is a high level.

[0185] Referring to Figure 11, the eighth transistor T8 is a P-type transistor. When the signal at the third node N3 is low, the eighth transistor T8 is turned on, and the fifth node N5 is connected to the second reference signal terminal VGH through the turned-on eighth transistor T8.

[0186] The control terminal of the ninth transistor T9 is coupled to the fourth node N4, and the first terminal of the ninth transistor T9 is coupled to the second clock signal terminal CB.

[0187] For example, the ninth transistor T9 can be turned on under the control of the active level of the fourth node N4, and turned off under the control of the inactive level of the fourth node N4. For example, if the ninth transistor T9 is set as an N-type transistor, then the active level of the signal at the fourth node N4 is a high level, and the inactive level of the signal at the fourth node N4 is a low level. Alternatively, if the ninth transistor T9 is set as a P-type transistor, then the active level of the signal at the fourth node N4 is a low level, and the inactive level of the signal at the fourth node N4 is a high level.

[0188] Referring to Figure 11, the ninth transistor T9 is a P-type transistor. When the signal at the fourth node N4 is low, the ninth transistor T9 is turned on, and the fifth node N5 is connected to the second clock signal terminal CB through the turned-on ninth transistor T9.

[0189] The first terminal of the first capacitor C1 is coupled to the fourth node N4, and the second terminal of the first capacitor C1 is coupled to the fifth node N5.

[0190] The third control subunit 1033 is coupled to the first node N1, the third node N3, the first reference signal terminal VGL, the second clock signal terminal CB, the second reference signal terminal VGH, and the pull-up node N8. The third control subunit 1033 is configured to provide the signal of the second clock signal terminal CB to the pull-up node N8 in response to the signals of the first reference signal terminal VGL, the third node N3, and the second clock signal terminal CB, and to provide the signal of the second reference signal terminal VGH to the pull-up node N8 in response to the signal of the first node N1.

[0191] For example, referring to FIG11, the third control subunit 1033 includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a second capacitor C2.

[0192] The control terminal of the tenth transistor T10 is coupled to the first reference voltage signal terminal, the first terminal of the tenth transistor T10 is coupled to the third node N3, and the second terminal of the tenth transistor T10 is coupled to the first terminal of the second capacitor C2.

[0193] For example, the tenth transistor T10 can be turned on under the control of the effective level of the first reference voltage signal terminal, and can be turned off under the control of the ineffective level of the first reference voltage signal terminal. For example, if the tenth transistor T10 is set as an N-type transistor, then the effective level of the signal at the first reference voltage signal terminal is a high level, and the ineffective level of the signal at the first reference voltage signal terminal is a low level. Alternatively, if the tenth transistor T10 is set as a P-type transistor, then the effective level of the signal at the first reference voltage signal terminal is a low level, and the ineffective level of the signal at the first reference voltage signal terminal is a high level.

[0194] Referring to Figure 11, the tenth transistor T10 is a P-type transistor. When the signal at the first reference voltage signal terminal is low, the tenth transistor T10 is turned on, and the third node N3 is connected to the first terminal of the second capacitor C2 through the turned-on tenth transistor T10.

[0195] The control terminal of the eleventh transistor T11 is coupled to the first terminal of the second capacitor C2, the first terminal of the eleventh transistor T11 is coupled to the second terminal of the second capacitor C2, and the second terminal of the eleventh transistor T11 is coupled to the second clock signal terminal CB.

[0196] For example, the eleventh transistor T11 can be turned on under the control of the effective level of the first terminal of the second capacitor C2, and can be turned off under the control of the ineffective level of the first terminal of the second capacitor C2. For example, if the eleventh transistor T11 is set as an N-type transistor, then the effective level of the signal at the first terminal of the second capacitor C2 is a high level, and the ineffective level of the signal at the first terminal of the second capacitor C2 is a low level. Alternatively, if the eleventh transistor T11 is set as a P-type transistor, then the effective level of the signal at the first terminal of the second capacitor C2 is a low level, and the ineffective level of the signal at the first terminal of the second capacitor C2 is a high level.

[0197] Referring to Figure 11, the eleventh transistor T11 is a P-type transistor. When the signal at the first terminal of the second capacitor C2 is low, the eleventh transistor T11 is turned on, and the second terminal of the second capacitor C2 is connected to the second clock signal terminal CB through the turned-on eleventh transistor T11.

[0198] The control terminal of the twelfth transistor T12 is coupled to the second clock signal terminal CB, the first terminal of the twelfth transistor T12 is coupled to the second terminal of the second capacitor C2, and the second terminal of the twelfth transistor T12 is coupled to the pull-up node N8.

[0199] For example, the twelfth transistor T12 can be turned on under the control of the active level of the second clock signal terminal CB, and can be turned off under the control of the inactive level of the second clock signal terminal CB. For example, if the twelfth transistor T12 is set as an N-type transistor, then the active level of the signal at the second clock signal terminal CB is a high level, and the inactive level of the signal at the second clock signal terminal CB is a low level. Alternatively, if the twelfth transistor T12 is set as a P-type transistor, then the active level of the signal at the second clock signal terminal CB is a low level, and the inactive level of the signal at the second clock signal terminal CB is a high level.

[0200] Referring to Figure 11, the twelfth transistor T12 is a P-type transistor. When the signal at the second clock signal terminal CB is low, the twelfth transistor T12 is turned on, and the second terminal of the second capacitor C2 is connected to the pull-up node N8 through the turned-on twelfth transistor T12.

[0201] The control terminal of the thirteenth transistor T13 is coupled to the first node N1, the first terminal of the thirteenth transistor T13 is coupled to the second reference signal terminal VGH, and the second terminal of the thirteenth transistor T13 is coupled to the pull-up node N8.

[0202] For example, the thirteenth transistor T13 can be turned on under the control of the effective level of the first node N1, and can be turned off under the control of the ineffective level of the first node N1. For example, if the thirteenth transistor T13 is set as an N-type transistor, then the effective level of the signal of the first node N1 is a high level, and the ineffective level of the signal of the first node N1 is a low level. Alternatively, if the thirteenth transistor T13 is set as a P-type transistor, then the effective level of the signal of the first node N1 is a low level, and the ineffective level of the signal of the first node N1 is a high level.

[0203] Referring to Figure 11, the thirteenth transistor T13 is a P-type transistor. When the signal at the first node N1 is low, the thirteenth transistor T13 is turned on, and the second reference signal terminal VGH is connected to the pull-up node N8 through the turned-on thirteenth transistor T13.

[0204] The output sub-circuit 104 is configured to provide the signal of the second reference signal terminal VGH to the drive output terminal HOUT in response to the signal of the pull-up node N8, and to provide the signal of the first reference signal terminal VGL to the drive output terminal HOUT in response to the signal of the pull-down node N9.

[0205] For example, referring to FIG11, the output sub-circuit 104 includes: a fourteenth transistor T14, a third capacitor C3 and a fifteenth transistor T15.

[0206] The control terminal of the fourteenth transistor T14 is coupled to the pull-down node N9, the first terminal of the fourteenth transistor T14 is coupled to the first reference signal terminal VGL, and the second terminal of the fourteenth transistor T14 is coupled to the drive output terminal HOUT.

[0207] For example, the fourteenth transistor T14 can be turned on under the control of the active level of the pull-down node N9, and can be turned off under the control of the inactive level of the pull-down node N9. For example, if the fourteenth transistor T14 is set as an N-type transistor, then the active level of the signal of the pull-down node N9 is a high level, and the inactive level of the signal of the pull-down node N9 is a low level. Alternatively, if the fourteenth transistor T14 is set as a P-type transistor, then the active level of the signal of the pull-down node N9 is a low level, and the inactive level of the signal of the pull-down node N9 is a high level.

[0208] Referring to Figure 11, the fourteenth transistor T14 is a P-type transistor. When the signal of the pull-down node N9 is low, the fourteenth transistor T14 is turned on, and the first reference signal terminal VGL is connected to the drive output terminal HOUT through the turned-on fourteenth transistor T14.

[0209] The first terminal of the third capacitor C3 is coupled to the pull-up node N8, and the second terminal of the third capacitor C3 is coupled to the second reference signal terminal VGH.

[0210] The control terminal of the fifteenth transistor T15 is coupled to the pull-up node N8, the first terminal of the fifteenth transistor T15 is coupled to the drive output terminal HOUT, and the second terminal of the fifteenth transistor T15 is coupled to the second reference signal terminal VGH.

[0211] For example, the fifteenth transistor T15 can be turned on under the control of the active level of pull-up node N8, and can be turned off under the control of the inactive level of pull-up node N8. For example, if the fifteenth transistor T15 is set as an N-type transistor, then the active level of the signal of pull-up node N8 is a high level, and the inactive level of the signal of pull-up node N8 is a low level. Alternatively, if the fifteenth transistor T15 is set as a P-type transistor, then the active level of the signal of pull-up node N8 is a low level, and the inactive level of the signal of pull-up node N8 is a high level.

[0212] Referring to Figure 11, the fifteenth transistor T15 is a P-type transistor. When the signal of the pull-up node N8 is low, the fifteenth transistor T15 is turned on, and the second reference signal terminal VGH is connected to the drive output terminal HOUT through the turned-on fifteenth transistor T15.

[0213] Furthermore, as exemplarily shown in Figures 12 and 13, the aforementioned source drive circuit also includes a first pull-down control sub-circuit 105.

[0214] The first pull-down control sub-circuit 105 is configured to provide the signal of the first reference signal terminal VGL to the fourth node N4 in response to the signal of the pull-down node N9, the first node N1, or the second node N2.

[0215] During implementation, the first pull-down control sub-circuit 105 is turned on according to the signals of pull-down node N9, first node N1 or second node N2, and the signal of the first reference signal terminal VGL is provided to the fourth node N4 through the turned-on first pull-down control sub-circuit 105.

[0216] For example, referring to Figures 13, 15 and 17, the first pull-down control sub-circuit 105 includes a sixteenth transistor T16.

[0217] The control terminal of the sixteenth transistor T16 is coupled to the pull-down node N9, the first node N1, or the second node N2. The first terminal of the sixteenth transistor T16 is coupled to the first reference signal terminal VGL. The second terminal of the sixteenth transistor T16 is coupled to the fourth node N4.

[0218] (1) For example, the sixteenth transistor T16 can be turned on under the control of the active level of the pull-down node N9, and can be turned off under the control of the inactive level of the pull-down node N9. For example, if the sixteenth transistor T16 is set as an N-type transistor, then the active level of the signal of the pull-down node N9 is a high level, and the inactive level of the signal of the pull-down node N9 is a low level. Alternatively, if the sixteenth transistor T16 is set as a P-type transistor, then the active level of the signal of the pull-down node N9 is a low level, and the inactive level of the signal of the pull-down node N9 is a high level.

[0219] Referring to Figure 13, the sixteenth transistor T16 is a P-type transistor. When the signal of the pull-down node N9 is low, the sixteenth transistor T16 is turned on, and the signal of the first reference signal terminal VGL is provided to the fourth node N4 through the turned-on sixteenth transistor T16.

[0220] (2) For example, the sixteenth transistor T16 can be turned on under the control of the effective level of the first node N1, and can be turned off under the control of the ineffective level of the first node N1. For example, if the sixteenth transistor T16 is set as an N-type transistor, then the effective level of the signal of the first node N1 is a high level, and the ineffective level of the signal of the first node N1 is a low level. Alternatively, if the sixteenth transistor T16 is set as a P-type transistor, then the effective level of the signal of the first node N1 is a low level, and the ineffective level of the signal of the first node N1 is a high level.

[0221] Referring to Figure 13, the sixteenth transistor T16 is a P-type transistor. When the signal at the first node N1 is low, the sixteenth transistor T16 is turned on. The sixteenth transistor T16, which is turned on by the first reference signal terminal VGL, provides the signal to the fourth node N4.

[0222] (3) For example, the sixteenth transistor T16 can be turned on under the control of the effective level of the second node N2, and can be turned off under the control of the ineffective level of the second node N2. For example, if the sixteenth transistor T16 is set as an N-type transistor, then the effective level of the signal of the second node N2 is a high level, and the ineffective level of the signal of the second node N2 is a low level. Alternatively, if the sixteenth transistor T16 is set as a P-type transistor, then the effective level of the signal of the second node N2 is a low level, and the ineffective level of the signal of the second node N2 is a high level.

[0223] Referring to Figure 14, the sixteenth transistor T16 is a P-type transistor. When the signal at the second node N2 is low, the sixteenth transistor T16 is turned on, and the signal at the first reference signal terminal VGL is provided to the fourth node N4 through the turned-on sixteenth transistor T16.

[0224] Furthermore, as exemplarily shown in Figures 14 and 15, the aforementioned source drive circuit also includes a second pull-down control sub-circuit 106.

[0225] The first pull-down control sub-circuit 105 is coupled to the first reference signal terminal VGL via the second pull-down control sub-circuit 106. The second pull-down control sub-circuit 106 is configured to provide the signal of the first reference signal terminal VGL to the first pull-down control sub-circuit 105 in response to the signal of the drive output terminal HOUT.

[0226] During implementation, when the signal of the drive output terminal HOUT is valid, the first pull-down control sub-circuit 105 is connected to the first reference signal terminal VGL via the second pull-down control sub-circuit 106, and the signal of the first reference signal terminal VGL is provided to the first pull-down control sub-circuit 105 via the activated second pull-down control sub-circuit 106.

[0227] For example, referring to FIG15, the second pull-down control sub-circuit 106 includes: a seventeenth transistor T17.

[0228] The control terminal of the seventeenth transistor T17 is coupled to the drive output terminal HOUT, the first terminal of the seventeenth transistor T17 is coupled to the first pull-down control sub-circuit, and the second terminal of the seventeenth transistor T17 is coupled to the first reference signal terminal VGL.

[0229] For example, the seventeenth transistor T17 can be turned on under the control of the effective level of the drive output terminal HOUT, and can be turned off under the control of the ineffective level of the drive output terminal HOUT. For example, if the seventeenth transistor T17 is set as an N-type transistor, then the effective level of the signal at the drive output terminal HOUT is a high level, and the ineffective level of the signal at the drive output terminal HOUT is a low level. Alternatively, if the seventeenth transistor T17 is set as a P-type transistor, then the effective level of the signal at the drive output terminal HOUT is a low level, and the ineffective level of the signal at the drive output terminal HOUT is a high level.

[0230] Referring to Figure 15, the seventeenth transistor T17 is a P-type transistor. When the signal at the drive output terminal HOUT is low, the seventeenth transistor T17 is turned on. The first terminal of the first pull-down control sub-circuit 105, i.e. the sixteenth transistor T16, is connected to the first reference signal terminal VGL through the turned-on seventeenth transistor T17.

[0231] As exemplarily shown in Figures 16 and 17, the above-described source drive circuit also includes a reset sub-circuit 107.

[0232] The reset circuit 107 is configured to provide the signal of the second reference signal terminal VGH to the first node N1 in response to the signal of the node control signal terminal HCX.

[0233] During implementation, when the signal at the node control signal terminal HCX is valid, the reset sub-circuit 107 is turned on, and the signal at the second reference signal terminal VGH is provided to the first node N1 through the turned-on reset sub-circuit 107.

[0234] For example, referring to Figures 17, 18 and 19, the reset sub-circuit 107 includes an eighteenth transistor T18.

[0235] The control terminal of the eighteenth transistor T18 is coupled to the node control signal terminal HCX, the first terminal of the eighteenth transistor T18 is coupled to the first node N1, and the second terminal of the eighteenth transistor T18 is coupled to the second reference signal terminal VGH.

[0236] For example, the eighteenth transistor T18 can be turned on under the control of the active level of the node control signal terminal HCX, and can be turned off under the control of the inactive level of the node control signal terminal HCX. For example, if the eighteenth transistor T18 is set as an N-type transistor, then the active level of the signal at the node control signal terminal HCX is a high level, and the inactive level of the signal at the node control signal terminal HCX is a low level. Alternatively, if the eighteenth transistor T18 is set as a P-type transistor, then the active level of the signal at the node control signal terminal HCX is a low level, and the inactive level of the signal at the node control signal terminal HCX is a high level.

[0237] Referring to Figure 17, the eighteenth transistor T18 is a P-type transistor. When the signal at the node control signal terminal HCX is low, the eighteenth transistor T18 is turned on, and the first node N1 is connected to the second reference signal terminal VGH through the turned-on eighteenth transistor T18. In this case, the first node N1 is at a high level, thereby resetting the first node N1.

[0238] For example, referring to Figures 20 and 21, the first reference signal terminal includes a first sub-reference signal terminal VGL1 and a second sub-reference signal terminal VGL; the second reference signal terminal includes a first reference sub-signal terminal VGH1 and a second reference sub-signal terminal VGH.

[0239] The above-mentioned multiple reference signal terminals enable more independent setting of reference voltage, realizing a scheme where different reference signal terminals provide voltage to different transistors, thereby improving circuit stability.

[0240] In one implementation, the voltage value of the first sub-reference signal terminal VGL1 is greater than or equal to the voltage value of the second sub-reference signal terminal VGL.

[0241] During implementation, setting the voltage values ​​of the first sub-reference signal terminal VGL1 and the second sub-reference signal terminal VGL to different values ​​can save some power consumption. On the other hand, setting the voltage value of the first sub-reference signal terminal VGL1 to be greater than or equal to the voltage value of the second sub-reference signal terminal VGL can enhance the output capability of the circuit.

[0242] That is, the voltage value acting on the first sub-reference signal terminal VGL1 of the output sub-circuit 104 is greater than or equal to the voltage value acting on the second sub-reference signal terminal VGL of the second input sub-circuit 102 and the node control sub-circuit 103. In this way, the noise between the second input sub-circuit 102, the node control sub-circuit 103 and the output sub-circuit 104 can be better isolated. After the second input sub-circuit 102 inputs the signal of the second sub-reference signal terminal VGL, the node control sub-circuit 103 can better control the signals of the pull-up node N8 and the pull-down node N9. At the same time, the output sub-circuit 104 can better output the voltage value of the first sub-reference signal terminal VGL1, thereby enhancing the output capability of the circuit.

[0243] Similarly, the voltage value of the second reference sub-signal terminal VGH is greater than or equal to the voltage value of the first reference sub-signal terminal VGH1.

[0244] That is, the voltage value of the second reference sub-signal terminal VGH acting on the node control sub-circuit 103 is greater than or equal to the voltage value of the first reference sub-signal terminal VGH1 acting on the output sub-circuit 104. In this way, the noise between the node control sub-circuit 103 and the output sub-circuit 104 can be better isolated, the node control sub-circuit 103 can better control the signals of the pull-up node N8 and the pull-down node N9, and at the same time, the output sub-circuit 104 can better output the voltage value of the first reference sub-signal terminal VGH1.

[0245] Referring to Figures 11 and 22, the main working process of the source drive circuit will be described below with reference to the timing diagram.

[0246] In this context, 0 represents a low signal level, and 1 represents a high signal level.

[0247] Timing T1 stage: HSW=0, CK=0, CB=1, Datain=1, HOUT=0

[0248] When the effective voltage signal in the first control signal terminal HSW is low, the first transistor T1 and the second transistor T2 are turned on. The scan start signal in the second control signal terminal Datain is provided to the first node N1 and the second node N2. Since the scan start signal is high, the first node N1 and the second node N2 are also high. The low level of the signal in the first reference signal terminal VGL turns on the fourth transistor T4 and the fifth transistor T5. Thus, the fourth node N4 and the ninth node N9 are high. The high level of the ninth node N9 turns off the fourteenth transistor T14. The high level of the fourth node N4 turns off the sixth transistor T6 and the ninth transistor T9. When the first clock signal terminal CK is low, the third transistor T3 is turned on. When the first reference signal terminal VGL is low, the tenth transistor T10 is turned on. The third node N3 and the sixth node N6 are both low. When the second clock signal terminal CB is high, the twelfth transistor T12 is turned off. The eighth node, which is also the pull-up node N8, remains at its previous high level. The fifteenth transistor T15 is turned off. The drive output terminal HOUT remains at its previous low output state.

[0249] Timing T2 stage: HSW=1, HOUT=1

[0250] When the effective voltage signal in the first control signal terminal HSW is low, the first transistor T1 and the second transistor T2 are cut off, and the data voltage signal appearing after the scan start signal will not affect the circuit state. When the signal in the first clock signal terminal CK is high, the third transistor T3 is cut off, the first node N1 remains high, the seventh transistor T7 is cut off, the third node N3 and the sixth node N6 both remain low, maintaining a low voltage, the eleventh transistor T11 is turned on, the second clock signal terminal CB is low, the second clock signal terminal CB makes the seventh node N7 low, the second clock signal terminal CB is low, the twelfth transistor T12 is turned on, the eighth node, which is also the pull-up node N8, is at a low potential, the fifteenth transistor T15 is turned on, the signal in the second reference signal terminal VGH is provided to the drive output terminal HOUT, making the drive output terminal HOUT output a high level.

[0251] Timing T3 stage: HSW=0, CK=0, CB=1, Datain=0, HOUT=0

[0252] When the effective voltage signal in the first control signal terminal HSW is low, the first transistor T1 and the second transistor T2 are turned on. The scan start signal in the second control signal terminal Datain is provided to the first node N1 and the second node N2. Since the scan start signal is low, the first node N1 and the second node N2 are also low. The low level of the first reference signal terminal VGL turns on the fourth transistor T4 and the fifth transistor T5. Thus, the fourth node N4 and the ninth node N9 are low. The low level of the ninth node N9 turns on the fourteenth transistor T14. The low level of the fourth node N4 turns on the sixth transistor T6. The signal in the first clock signal terminal CK is low, and the third transistor T3 is turned on. The low level of the first reference signal terminal VGL turns on the tenth transistor T10. The third node N3 and the sixth node N6 are both low. The second clock signal terminal CB is high, and the twelfth transistor T12 is turned off. The eighth node, which is also the pull-up node N8, remains at its previous high level, and the fifteenth transistor T15 is turned off. Simultaneously, the low level of the third node N3 turns on the eighth transistor T8, and the high level of the signal at the second reference signal terminal VGH, via the eighth transistor T8, makes the fifth node N5 high. This high level at the fifth node N5 causes the fourteenth transistor T14 to not turn on sufficiently, preventing the drive output terminal HOUT from fully outputting the low-level signal at the first reference signal terminal VGL.

[0253] Timing T4 stage: HSW=1, HOUT=0

[0254] When the effective voltage signal in the first control signal terminal HSW is low, the first transistor T1 and the second transistor T2 are off, and the data voltage signal appearing after the scan start signal will not affect the circuit state. When the signal in the first clock signal terminal CK is high, the third transistor T3 is off, the low level of the first node N1 turns on the seventh transistor T7, the second clock signal terminal CB is high, and the turned-on seventh transistor T7 turns on the third node N3, which in turn turns on the sixth node N6, and the eleventh transistor T11 is off. The low level of the first node N1 turns on the thirteenth transistor T13, the third clock signal terminal is low, and the high level of the second reference signal terminal VGH turns on the eighth node, which is also the pull-up node N8, high through the turned-on thirteenth transistor T13, and the fifteenth transistor T15 is off. The high level of the first clock signal terminal CK turns off the eighth transistor T8 via the conducting seventh transistor T7, the fourth node N4 is at a low level, the ninth transistor T9 is turned on, the low level of the third clock signal terminal causes the fifth node N5 to be at a low level via the ninth transistor T9, and the level of the fourth node N4 is pulled low through the coupling effect of the first capacitor C1, the sixth transistor T6 is turned on, and further pulls the level of the ninth node N9 low, the fourteenth transistor T14 is fully turned on, and the output terminal HOUT outputs a stable low level.

[0255] Based on the same inventive concept, referring to Figure 23, this disclosure provides a display panel, including: a display area, including multiple sub-pixels, multiple column refresh lines and multiple data lines, each sub-pixel including a light-emitting device and a pixel driving circuit connected to the light-emitting device, a column refresh line connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels, and a data line connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels.

[0256] In this embodiment, to achieve partial refresh of the display panel along the column direction, a matching column refresh line is provided for each data line in the display area, and this column refresh line is arranged parallel to the data line. Simultaneously, the pixel driving circuit included in each sub-pixel is connected to the column refresh line and the data line.

[0257] The non-display area includes multiple source control lines and multiple source drive circuits as described above. The drive output terminal HOUT of one of the multiple source drive circuits is connected to one of the multiple column refresh lines. The second control signal terminal Datain of one of the multiple source drive circuits is connected to one of the multiple data lines. The first control signal terminal HSW of one of the multiple source drive circuits is connected to one of the multiple source control lines.

[0258] To connect the source driver circuit and the source chip, in this embodiment, multiple source control lines are provided in the non-display area of ​​the display panel, i.e., one source control line is provided for each source driver circuit. The source chip sends a signal to the first control signal terminal HSW of the source driver circuit through the aforementioned source control lines. Simultaneously, the source chip also sends a sequentially occurring scan start signal and data voltage signal to the aforementioned data lines. These sequentially occurring scan start signal and data voltage signal are sent to the source driver circuit, allowing the second control signal terminal Datain of the source driver circuit to receive them. After the drive output terminal HOUT of the source driver circuit generates a signal, it sends the signal from the drive output terminal HOUT to the pixel driver circuit through the column refresh line. For example, the control terminals of the first switching transistor shown in Figure 1, the third switching transistor shown in Figure 3, the fifth and sixth switching transistors shown in Figure 5, and the eighth switching transistor shown in Figure 7, etc., thereby updating the data voltage of the pixel driver circuit and thus refreshing the display of the connected data lines.

[0259] For example, referring to FIG7, the pixel driving circuit includes: a first write transistor M9 and a second write transistor M8, wherein the first write transistor M9 and the second write transistor M8 are of different types.

[0260] Referring to Figure 7, the control terminal of the first write transistor M9 is coupled to the second scan signal terminal N_Gate connected to the sub-pixel, the first terminal of the first write transistor M9 is coupled to the first reference signal terminal VGL, and the second terminal of the first write transistor M9 is coupled to the first terminal of the second write transistor M8.

[0261] During implementation, when the signal of the second scan signal terminal N_Gate is high, the first write transistor M9 is turned on. The signal of the first reference signal terminal VGL is provided to the control terminal of the conduction control transistor M10 through the turned-on first write transistor M9, causing the conduction control transistor M10 to be turned off. This results in the control terminal of the driving transistor M3 being in an open circuit state with the first terminal of the driving transistor M3, preventing the data voltage from being written to the control terminal of the driving transistor M3, and preventing the corresponding sub-pixel from being refreshed.

[0262] Referring to Figure 7, the control terminal of the second write transistor M8 is coupled to the second scan signal terminal N_Gate connected to the sub-pixel, the first terminal of the second write transistor M8 is coupled to the control terminal of the conduction control transistor M10, and the second terminal of the second write transistor M8 is coupled to the first scan signal terminal C_Gate connected to the sub-pixel. The first terminal of the conduction control transistor M10 is coupled to the control terminal of the driving transistor M3, and the second terminal of the conduction control transistor M10 is coupled to the first terminal of the driving transistor M3.

[0263] During implementation, when the signal of the second scan signal terminal N_Gate is low, the second write transistor M8 is turned on. The signal of the first scan signal terminal C_Gate is provided to the control terminal of the conduction control transistor M10 through the turned-on second write transistor M8, so that the conduction control transistor M10 is turned on, thereby making the control terminal of the driving transistor M3 and the first terminal of the driving transistor M3 in a conducting state. The data voltage is written to the control terminal of the driving transistor M3, and the corresponding sub-pixel is refreshed.

[0264] It should also be noted that the first scan signal terminal C_Gate is coupled to the column refresh line connected to the sub-pixel. That is, after the source drive circuit generates a signal, it will send the signal of the drive output terminal HOUT to the first scan signal terminal C_Gate in the pixel drive circuit through the column refresh line, so as to control whether the corresponding sub-pixel is updated with data voltage.

[0265] Based on the same inventive concept, referring to Figures 24 and 25, an embodiment of this disclosure provides a display device, including a display panel as described above and at least one source chip.

[0266] The source chip is coupled to at least some of the data lines and at least some of the source control lines of the display panel. The source chip is configured to sequentially output a scan start signal and a data voltage signal to the data lines connected to it during one frame of display time, and to output an effective voltage signal to the source control line.

[0267] In this embodiment of the present disclosure, the source chip is connected to the display panel, and the source chip and the display panel are used in conjunction to enable the display panel to refresh in the column direction.

[0268] During implementation, within one frame of display time on the display panel, the source chip sequentially outputs a scan start signal and a data voltage signal to the data line connected to it. After being sent to the data line, these sequentially output scan start signal and data voltage signal are further sent to the aforementioned source drive circuit. In addition, the source chip also outputs an effective voltage signal to the source control line, and this effective voltage signal is then supplied to the source drive circuit via the source control line, thereby enabling the source drive circuit to operate.

[0269] It should be noted that the HCT pulse shown in Figure 25 is the scan start signal mentioned above, and the low level of the HCT pulse is the effective level of the scan start signal.

[0270] The display device provided in the embodiments of this disclosure can be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0271] Based on the same inventive concept, referring to Figure 26, this disclosure provides a first driving method for a source driving circuit applied to any of the above claims, including:

[0272] Step 201: Input Phase: In response to the effective voltage signal in the signal of the first control signal terminal HSW, the first input sub-circuit 101 provides the scan start signal in the signal of the second control signal terminal Datain to the first node N1 and the second node N2. The second input sub-circuit 102 is configured to provide the signal of the first reference signal terminal VGL to the third node N3 in response to the signal of the first clock signal terminal CK. The node control sub-circuit 103 controls the signals of the pull-up node N8 and the pull-down node N9 to maintain a holding state based on the signals of the first node N1, the second node N2 and the third node N3.

[0273] During implementation, when a valid voltage signal is input to the first control signal terminal HSW, the first input sub-circuit 101 is turned on. The scan start signal in the second control signal terminal Datain is provided to the first node N1 and the second node N2 via the turned-on first input sub-circuit 101. When the first clock signal terminal CK is at a valid level, the second input sub-circuit 102 is turned on. The signal of the first reference signal terminal VGL is provided to the third node N3 via the turned-on second input sub-circuit 102. Thus, the node control sub-circuit 103 controls the signals of the pull-up node N8 and the pull-down node N9 to maintain a holding state based on the signals of the first node N1, the second node N2, and the third node N3.

[0274] Step 202: Output Stage: The first input sub-circuit 101, in response to an invalid voltage signal in the first control signal terminal HSW, maintains the first node N1 and the second node N2 at an invalid level. The second input sub-circuit 102, in response to the first clock signal terminal CK, maintains the third node N3 at an active level. The node control sub-circuit 103, based on the signals of the first node N1, the second node N2, and the third node N3, controls the signal of the pull-up node N8 to be active. The output sub-circuit 104 is configured to, in response to the signal of the pull-up node N8, provide the signal of the second reference signal terminal VGH to the drive output terminal HOUT.

[0275] During implementation, when an invalid voltage signal is input to the first control signal terminal HSW, i.e., during any period other than when an valid voltage signal appears within a frame display time, the first input sub-circuit 101 is disconnected, and the first node N1 and the second node N2 remain at an invalid level. When the signal of the first clock signal terminal CK is at an invalid level, the second input sub-circuit 102 is disconnected, and the third node N3 remains at an valid level. Thus, the node control sub-circuit 103 controls the signal of the pull-up node N8 to be in a valid state based on the signals of the first node N1, the second node N2, and the third node N3. The output sub-circuit 104 is configured to provide the signal of the second reference signal terminal VGH to the drive output terminal HOUT in response to the signal of the pull-up node N8. Referring to Figure 27, the drive output terminal HOUT outputs a high-level signal.

[0276] Based on the same inventive concept, referring to Figure 28, this disclosure provides a second driving method for a source drive circuit applied to any of the above claims, including:

[0277] Step 301: Signal Input Stage: In response to the valid voltage signal in the signal of the first control signal terminal HSW, the first input sub-circuit 101 provides the scan start signal in the signal of the second control signal terminal Datain to the first node N1 and the second node N2. The second input sub-circuit 102 is configured to provide the signal of the first reference signal terminal VGL to the third node N3 in response to the signal of the first clock signal terminal CK. The node control sub-circuit 103 controls the signal of the pull-down node N9 to be in an active state according to the signals of the first node N1, the second node N2 and the third node N3.

[0278] During implementation, when a valid voltage signal is input to the first control signal terminal HSW, the first input sub-circuit 101 is turned on. The scan start signal in the second control signal terminal Datain is provided to the first node N1 and the second node N2 via the turned-on first input sub-circuit 101. When the signal of the first clock signal terminal CK is at a valid level, the second input sub-circuit 102 is turned on. The signal of the first reference signal terminal VGL is provided to the third node N3 via the turned-on second input sub-circuit 102. Thus, the node control sub-circuit 103 controls the signal of the pull-down node N9 to be in a valid state based on the signals of the first node N1, the second node N2, and the third node N3.

[0279] Step 302: Signal Output Stage: Node control sub-circuit 103 controls the signal of pull-up node N8 to be in an invalid state and controls the signal of pull-down node N9 to be in an active state based on the signals of the first node N1, the second node N2, and the third node N3. Output sub-circuit 104 is configured to provide the signal of the first reference signal terminal VGL to the drive output terminal HOUT in response to the signal of pull-down node N9.

[0280] During implementation, the node control sub-circuit 103 controls the signal of pull-up node N8 to be in an invalid state and controls the signal of pull-down node N9 to be in an active state based on the signals of the first node N1, the second node N2, and the third node N3. Simultaneously, the node control sub-circuit 103 can further pull down the level of pull-down node N9. Thus, the output sub-circuit 104, responding to the signal of pull-down node N9, can fully provide the signal of the first reference signal terminal VGL to the drive output terminal HOUT. Referring to Figure 29, the drive output terminal HOUT outputs a low-level signal.

[0281] In summary, the present disclosure provides a source driving circuit, a display panel, a display device, and a driving method. The source driving circuit includes a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit. The first input sub-circuit is configured to provide a scan start signal from the second control signal to a first node and a second node in response to an effective voltage signal in the signal of a first control signal terminal. Within one frame of display time, the signal of the first control signal terminal includes an effective voltage signal, and the signal of the second control signal terminal includes a scan start signal and a data voltage signal appearing sequentially. The second input sub-circuit is configured to provide a signal from a first reference signal terminal to a third node in response to a signal of a first clock signal terminal. The node control sub-circuit is configured to control the signals of a pull-up node and a pull-down node based on the signals of the first node, the second node, and the third node. The output sub-circuit is configured to provide a signal from the second reference signal terminal to a drive output terminal in response to a signal from a pull-up node, and to provide a signal from the first reference signal terminal to a drive output terminal in response to a signal from a pull-down node. Through the above-described source driving circuit configuration, partial refresh of some columns in the display panel can be achieved, thereby saving power consumption while ensuring display quality.

[0282] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0283] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0284] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0285] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0286] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A source drive circuit, wherein, include: The circuit consists of a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit. The first input sub-circuit is configured to provide a scan start signal from the second control signal to the first node and the second node in response to an effective voltage signal in the signal of the first control signal terminal, wherein the signal of the first control signal terminal includes one effective voltage signal within one frame display time, and the signal of the second control signal terminal includes a scan start signal and a data voltage signal that appear sequentially. The second input sub-circuit is configured to provide the signal from the first reference signal terminal to the third node in response to the signal from the first clock signal terminal; The node control subcircuit is configured to control the signals of the pull-up node and the pull-down node based on the signals of the first node, the second node and the third node; The output sub-circuit is configured to provide a signal from the second reference signal terminal to the drive output terminal in response to a signal from the pull-up node. In response to the signal from the pull-down node, the signal from the first reference signal terminal is provided to the drive output terminal.

2. The source drive circuit as described in claim 1, wherein, The first input sub-circuit includes: a first transistor and a second transistor; The control terminal of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the second control signal terminal, and the second terminal of the first transistor is coupled to the first node. The control terminal of the second transistor is coupled to the first control signal terminal, the first terminal of the second transistor is coupled to the second control signal terminal, and the second terminal of the second transistor is coupled to the second node.

3. The source drive circuit as described in claim 1, wherein, The second input sub-circuit includes: a third transistor; The control terminal of the third transistor is coupled to the first clock signal terminal. The first terminal of the transistor is coupled to the first reference signal terminal, and the second terminal of the third transistor is coupled to the third node.

4. The source drive circuit as described in claim 1, wherein, The node control sub-circuit includes: a first control sub-unit, a second control sub-unit, and a third control sub-unit; The first control subunit is coupled to the first node, the second node, the fourth node, the first reference signal terminal and the pull-down node. The first control subunit is configured to provide the signal of the first node to the pull-down node in response to the signal of the first reference signal terminal, and to provide the signal of the second node to the fourth node in response to the signal of the first reference signal terminal, and to provide the signal of the fourth node to the pull-down node in response to the signal of the fourth node. The second control subunit is coupled to the first node, the third node, the second reference signal terminal, the first clock signal terminal, the second clock signal terminal, and the fourth node. The second control subunit is configured to provide the signal of the first clock signal terminal to the third node in response to a signal from the first node; to provide the signal of the second reference signal terminal to the fifth node in response to a signal from the third node; and to provide the signal of the second clock signal terminal to the fifth node in response to a signal from the fourth node. The third control subunit is coupled to the first node, the third node, the first reference signal terminal, the second clock signal terminal, the second reference signal terminal, and the pull-up node. The third control subunit is configured to provide the signal of the second clock signal terminal to the pull-up node in response to the signals of the first reference signal terminal, the third node, and the second clock signal terminal; and to provide the signal of the second reference signal terminal to the pull-up node in response to the signal of the first node.

5. The source drive circuit as described in claim 4, wherein, The first control subunit includes: a fourth transistor, a fifth transistor, and a sixth transistor; The control terminal of the fourth transistor is coupled to the first reference signal terminal, the first terminal of the fourth transistor is coupled to the first node, and the second terminal of the fourth transistor is coupled to the pull-down node. The control terminal of the fifth transistor is coupled to the first reference signal terminal. The first end of the fifth transistor is coupled to the second node, and the second end of the fifth transistor is coupled to the fourth node. The control terminal of the sixth transistor is coupled to the fourth node, the first terminal of the sixth transistor is coupled to the fourth node, and the second terminal of the sixth transistor is coupled to the pull-down node.

6. The source drive circuit as described in claim 4, wherein, The second control subunit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a first capacitor; The control terminal of the seventh transistor is coupled to the first node, the first terminal of the seventh transistor is coupled to the first clock signal terminal, and the second terminal of the seventh transistor is coupled to the third node. The control terminal of the eighth transistor is coupled to the third node, the first terminal of the eighth transistor is coupled to the fifth node, and the second terminal of the eighth transistor is coupled to the second reference signal terminal. The control terminal of the ninth transistor is coupled to the fourth node, and the first terminal of the ninth transistor is coupled to the second clock signal terminal; The first end of the first capacitor is coupled to the fourth node, and the second end of the first capacitor is coupled to the fifth node.

7. The source drive circuit as described in claim 4, wherein, The third control subunit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor; The control terminal of the tenth transistor is coupled to the first reference voltage signal terminal, the first terminal of the tenth transistor is coupled to the third node, and the second terminal of the tenth transistor is coupled to the first terminal of the second capacitor. The control terminal of the eleventh transistor is coupled to the first terminal of the second capacitor, the first terminal of the eleventh transistor is coupled to the second terminal of the second capacitor, and the second terminal of the eleventh transistor is coupled to the second clock signal terminal. The control terminal of the twelfth transistor is coupled to the second clock signal terminal, the first terminal of the twelfth transistor is coupled to the second terminal of the second capacitor, and the second terminal of the twelfth transistor is coupled to the pull-up node. The control terminal of the thirteenth transistor is coupled to the first node, the first terminal of the thirteenth transistor is coupled to the second reference signal terminal, and the second terminal of the thirteenth transistor is coupled to the pull-up terminal. Node coupling.

8. The source drive circuit as described in any one of claims 1 to 7, wherein, The output sub-circuit includes: a fourteenth transistor, a third capacitor, and a fifteenth transistor; The control terminal of the fourteenth transistor is coupled to the pull-down node, the first terminal of the fourteenth transistor is coupled to the first reference signal terminal, and the second terminal of the fourteenth transistor is coupled to the drive output terminal. The first terminal of the third capacitor is coupled to the pull-up node, and the second terminal of the third capacitor is coupled to the second reference signal terminal. The control terminal of the fifteenth transistor is coupled to the pull-up node, the first terminal of the fifteenth transistor is coupled to the drive output terminal, and the second terminal of the fifteenth transistor is coupled to the second reference signal terminal.

9. The source drive circuit as described in any one of claims 4 to 7, wherein, It also includes the first pull-down control sub-circuit; The first pull-down control subcircuit is configured to provide a signal from the first reference signal terminal to the fourth node in response to a signal from the pull-down node, the first node, or the second node.

10. The source drive circuit as described in claim 9, wherein, The first pull-down control sub-circuit includes: a sixteenth transistor; The control terminal of the sixteenth transistor is coupled to the pull-down node, the first node, or the second node; the first terminal of the sixteenth transistor is coupled to the first reference signal terminal; and the second terminal of the sixteenth transistor is coupled to the fourth node.

11. The source drive circuit as described in claim 9, wherein, It also includes a second pull-down control sub-circuit; The first pull-down control sub-circuit is coupled to the first reference signal terminal via the second pull-down control sub-circuit. The second pull-down control sub-circuit is configured to provide the signal of the first reference signal terminal to the first pull-down control sub-circuit in response to the signal of the drive output terminal.

12. The source drive circuit as described in claim 11, wherein, The second pull-down control sub-circuit includes: a seventeenth transistor; The control terminal of the seventeenth transistor is coupled to the drive output terminal, the first terminal of the seventeenth transistor is coupled to the first pull-down control sub-circuit, and the second terminal of the seventeenth transistor is coupled to the first reference signal terminal.

13. The source drive circuit according to any one of claims 1 to 12, wherein, It also includes a reset circuit; The reset sub-circuit is configured to provide a signal from the second reference signal terminal to the first node in response to a signal from the node control signal terminal.

14. The source drive circuit as described in claim 13, wherein, The reset sub-circuit includes: an eighteenth transistor; The control terminal of the eighteenth transistor is coupled to the node control signal terminal, the first terminal of the eighteenth transistor is coupled to the first node, and the second terminal of the eighteenth transistor is coupled to the second reference signal terminal.

15. The source drive circuit as described in any one of claims 1 to 14, wherein, The first reference signal terminal includes a first sub-reference signal terminal and a second sub-reference signal terminal; The second reference signal terminal includes a first reference sub-signal terminal and a second reference sub-signal terminal.

16. The source drive circuit as described in claim 15, wherein, The voltage value at the first sub-reference signal terminal is greater than or equal to the voltage value at the second sub-reference signal terminal.

17. The source drive circuit as described in claim 15, wherein, The voltage value at the second reference sub-signal terminal is greater than or equal to the voltage value at the first reference sub-signal terminal.

18. A display panel, wherein, include: The display area includes multiple sub-pixels, multiple column refresh lines, and multiple data lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit connected to the light-emitting device. One column refresh line is connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels, and one data line is connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels. The non-display area includes multiple source control lines and multiple source drive circuits as described in any one of claims 1 to 17, wherein the drive output of one of the multiple source drive circuits is... The output terminal is connected to one of the column refresh lines, the second control signal terminal of one of the multiple source drive circuits is connected to one of the multiple data lines, and the first control signal terminal of one of the multiple source drive circuits is connected to one of the multiple source control lines.

19. The display panel as claimed in claim 18, wherein, The pixel driving circuit includes: a first write transistor and a second write transistor, wherein the first write transistor and the second write transistor are of different types; The control terminal of the first write transistor is coupled to the second scan signal terminal connected to the sub-pixel, the first terminal of the first write transistor is coupled to the first reference signal terminal, and the second terminal of the first write transistor is coupled to the first terminal of the second write transistor. The control terminal of the second write transistor is coupled to the second scan signal terminal connected to the sub-pixel. The first terminal of the second write transistor is coupled to the control terminal of the turn-on control transistor. The second terminal of the second write transistor is coupled to the first scan signal terminal connected to the sub-pixel. The first terminal of the turn-on control transistor is coupled to the control terminal of the drive transistor. The second terminal of the turn-on control transistor is coupled to the first terminal of the drive transistor. The first scan signal terminal is coupled to the column refresh line connected to the sub-pixel.

20. A display device, wherein, include: The display panel and at least one source chip as described in claim 18; The source chip is coupled to at least a portion of the data lines and at least a portion of the source control lines of the display panel. The source chip is configured to sequentially output a scan start signal and a data voltage signal to the data lines connected to it within one frame display time, and to output an effective voltage signal to the source control lines.

21. A first driving method applied to a driving circuit as described in any one of claims 1 to 17, wherein, include: Input Phase: In response to the effective voltage signal in the signal at the first control signal terminal, the first input sub-circuit provides the scan start signal in the signal at the second control signal terminal to the first node and the second node; the second input sub-circuit is configured to respond to the signal at the first clock signal terminal. The signal from the first reference signal terminal is provided to the third node; the node control sub-circuit controls the signals of the pull-up node and the pull-down node to maintain a state based on the signals from the first node, the second node and the third node. Output phase: The first input sub-circuit responds to the invalid voltage signal in the signal of the first control signal terminal, and maintains the first node and the second node at invalid potentials; the second input sub-circuit responds to the first clock signal terminal, and maintains the third node at an effective potential. The node control subcircuit controls the signal of the pull-up node to be in an active state based on the signals of the first node, the second node, and the third node; and the output subcircuit is configured to provide the signal of the second reference signal terminal to the drive output terminal in response to the signal of the pull-up node.

22. A second driving method applied to a driving circuit as described in any one of claims 1 to 17, wherein, include: Signal input phase: The first input sub-circuit responds to the effective voltage signal in the signal of the first control signal terminal and provides the scan start signal in the signal of the second control signal terminal to the first node and the second node; the second input sub-circuit is configured to respond to the signal of the first clock signal terminal and provide the signal of the first reference signal terminal to the third node; The node control sub-circuit controls the signal of the pull-down node to be in an active state based on the signals of the first node, the second node, and the third node. Signal output stage: The node control sub-circuit controls the signal of the pull-up node to be in an invalid state and controls the pull-down node to be in an active state according to the signals of the first node, the second node and the third node; and the output sub-circuit is configured to provide the signal of the first reference signal terminal to the drive output terminal in response to the signal of the pull-down node.

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